1/* 2 This file is provided under a dual BSD/GPLv2 license. When using or 3 redistributing this file, you may do so under either license. 4 5 GPL LICENSE SUMMARY 6 Copyright(c) 2014 Intel Corporation. 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of version 2 of the GNU General Public License as 9 published by the Free Software Foundation. 10 11 This program is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 Contact Information: 17 qat-linux@intel.com 18 19 BSD LICENSE 20 Copyright(c) 2014 Intel Corporation. 21 Redistribution and use in source and binary forms, with or without 22 modification, are permitted provided that the following conditions 23 are met: 24 25 * Redistributions of source code must retain the above copyright 26 notice, this list of conditions and the following disclaimer. 27 * Redistributions in binary form must reproduce the above copyright 28 notice, this list of conditions and the following disclaimer in 29 the documentation and/or other materials provided with the 30 distribution. 31 * Neither the name of Intel Corporation nor the names of its 32 contributors may be used to endorse or promote products derived 33 from this software without specific prior written permission. 34 35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 46*/ 47#ifndef ADF_ACCEL_DEVICES_H_ 48#define ADF_ACCEL_DEVICES_H_ 49#include <linux/module.h> 50#include <linux/atomic.h> 51#include <linux/list.h> 52#include <linux/proc_fs.h> 53#include <linux/io.h> 54#include "adf_cfg_common.h" 55 56#define PCI_VENDOR_ID_INTEL 0x8086 57#define ADF_DH895XCC_DEVICE_NAME "dh895xcc" 58#define ADF_DH895XCC_PCI_DEVICE_ID 0x435 59#define ADF_DH895XCC_PMISC_BAR 1 60#define ADF_DH895XCC_ETR_BAR 2 61#define ADF_PCI_MAX_BARS 3 62#define ADF_DEVICE_NAME_LENGTH 32 63#define ADF_ETR_MAX_RINGS_PER_BANK 16 64#define ADF_MAX_MSIX_VECTOR_NAME 16 65#define ADF_DEVICE_NAME_PREFIX "qat_" 66 67enum adf_accel_capabilities { 68 ADF_ACCEL_CAPABILITIES_NULL = 0, 69 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1, 70 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2, 71 ADF_ACCEL_CAPABILITIES_CIPHER = 4, 72 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8, 73 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32, 74 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64, 75 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128 76}; 77 78struct adf_bar { 79 resource_size_t base_addr; 80 void __iomem *virt_addr; 81 resource_size_t size; 82} __packed; 83 84struct adf_accel_msix { 85 struct msix_entry *entries; 86 char **names; 87} __packed; 88 89struct adf_accel_pci { 90 struct pci_dev *pci_dev; 91 struct adf_accel_msix msix_entries; 92 struct adf_bar pci_bars[ADF_PCI_MAX_BARS]; 93 uint8_t revid; 94 uint8_t sku; 95} __packed; 96 97enum dev_state { 98 DEV_DOWN = 0, 99 DEV_UP 100}; 101 102enum dev_sku_info { 103 DEV_SKU_1 = 0, 104 DEV_SKU_2, 105 DEV_SKU_3, 106 DEV_SKU_4, 107 DEV_SKU_UNKNOWN, 108}; 109 110static inline const char *get_sku_info(enum dev_sku_info info) 111{ 112 switch (info) { 113 case DEV_SKU_1: 114 return "SKU1"; 115 case DEV_SKU_2: 116 return "SKU2"; 117 case DEV_SKU_3: 118 return "SKU3"; 119 case DEV_SKU_4: 120 return "SKU4"; 121 case DEV_SKU_UNKNOWN: 122 default: 123 break; 124 } 125 return "Unknown SKU"; 126} 127 128struct adf_hw_device_class { 129 const char *name; 130 const enum adf_device_type type; 131 uint32_t instances; 132} __packed; 133 134struct adf_cfg_device_data; 135struct adf_accel_dev; 136struct adf_etr_data; 137struct adf_etr_ring_data; 138 139struct adf_hw_device_data { 140 struct adf_hw_device_class *dev_class; 141 uint32_t (*get_accel_mask)(uint32_t fuse); 142 uint32_t (*get_ae_mask)(uint32_t fuse); 143 uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self); 144 uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self); 145 uint32_t (*get_num_aes)(struct adf_hw_device_data *self); 146 uint32_t (*get_num_accels)(struct adf_hw_device_data *self); 147 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); 148 void (*hw_arb_ring_enable)(struct adf_etr_ring_data *ring); 149 void (*hw_arb_ring_disable)(struct adf_etr_ring_data *ring); 150 int (*alloc_irq)(struct adf_accel_dev *accel_dev); 151 void (*free_irq)(struct adf_accel_dev *accel_dev); 152 void (*enable_error_correction)(struct adf_accel_dev *accel_dev); 153 const char *fw_name; 154 uint32_t pci_dev_id; 155 uint32_t fuses; 156 uint32_t accel_capabilities_mask; 157 uint16_t accel_mask; 158 uint16_t ae_mask; 159 uint16_t tx_rings_mask; 160 uint8_t tx_rx_gap; 161 uint8_t instance_id; 162 uint8_t num_banks; 163 uint8_t num_accel; 164 uint8_t num_logical_accel; 165 uint8_t num_engines; 166} __packed; 167 168/* CSR write macro */ 169#define ADF_CSR_WR(csr_base, csr_offset, val) \ 170 __raw_writel(val, csr_base + csr_offset) 171 172/* CSR read macro */ 173#define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) 174 175#define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev) 176#define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars) 177#define GET_HW_DATA(accel_dev) (accel_dev->hw_device) 178#define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks) 179#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines) 180#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev 181 182struct adf_admin_comms; 183struct icp_qat_fw_loader_handle; 184struct adf_fw_loader_data { 185 struct icp_qat_fw_loader_handle *fw_loader; 186 const struct firmware *uof_fw; 187}; 188 189struct adf_accel_dev { 190 struct adf_etr_data *transport; 191 struct adf_hw_device_data *hw_device; 192 struct adf_cfg_device_data *cfg; 193 struct adf_fw_loader_data *fw_loader; 194 struct adf_admin_comms *admin; 195 struct list_head crypto_list; 196 unsigned long status; 197 atomic_t ref_count; 198 struct dentry *debugfs_dir; 199 struct list_head list; 200 struct module *owner; 201 struct adf_accel_pci accel_pci_dev; 202 uint8_t accel_id; 203} __packed; 204#endif 205