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1/* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
2 *
3 *  This program is free software; you can redistribute it and/or
4 *  modify it under the terms of the GNU General Public License
5 *  as published by the Free Software Foundation; either version
6 *  2 of the License, or (at your option) any later version.
7 *
8 * This driver supports ATM cards based on the Efficient "Lanai"
9 * chipset such as the Speedstream 3010 and the ENI-25p.  The
10 * Speedstream 3060 is currently not supported since we don't
11 * have the code to drive the on-board Alcatel DSL chipset (yet).
12 *
13 * Thanks to Efficient for supporting this project with hardware,
14 * documentation, and by answering my questions.
15 *
16 * Things not working yet:
17 *
18 * o  We don't support the Speedstream 3060 yet - this card has
19 *    an on-board DSL modem chip by Alcatel and the driver will
20 *    need some extra code added to handle it
21 *
22 * o  Note that due to limitations of the Lanai only one VCC can be
23 *    in CBR at once
24 *
25 * o We don't currently parse the EEPROM at all.  The code is all
26 *   there as per the spec, but it doesn't actually work.  I think
27 *   there may be some issues with the docs.  Anyway, do NOT
28 *   enable it yet - bugs in that code may actually damage your
29 *   hardware!  Because of this you should hardware an ESI before
30 *   trying to use this in a LANE or MPOA environment.
31 *
32 * o  AAL0 is stubbed in but the actual rx/tx path isn't written yet:
33 *	vcc_tx_aal0() needs to send or queue a SKB
34 *	vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
35 *	vcc_rx_aal0() needs to handle AAL0 interrupts
36 *    This isn't too much work - I just wanted to get other things
37 *    done first.
38 *
39 * o  lanai_change_qos() isn't written yet
40 *
41 * o  There aren't any ioctl's yet -- I'd like to eventually support
42 *    setting loopback and LED modes that way.
43 *
44 * o  If the segmentation engine or DMA gets shut down we should restart
45 *    card as per section 17.0i.  (see lanai_reset)
46 *
47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the
48 *   API says it isn't exactly commonly implemented)
49 */
50
51/* Version history:
52 *   v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
53 *   v.0.02 -- 11-JAN-2000 -- Endian fixes
54 *   v.0.01 -- 30-NOV-1999 -- Initial release
55 */
56
57#include <linux/module.h>
58#include <linux/slab.h>
59#include <linux/mm.h>
60#include <linux/atmdev.h>
61#include <asm/io.h>
62#include <asm/byteorder.h>
63#include <linux/spinlock.h>
64#include <linux/pci.h>
65#include <linux/dma-mapping.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/interrupt.h>
69
70/* -------------------- TUNABLE PARAMATERS: */
71
72/*
73 * Maximum number of VCIs per card.  Setting it lower could theoretically
74 * save some memory, but since we allocate our vcc list with get_free_pages,
75 * it's not really likely for most architectures
76 */
77#define NUM_VCI			(1024)
78
79/*
80 * Enable extra debugging
81 */
82#define DEBUG
83/*
84 * Debug _all_ register operations with card, except the memory test.
85 * Also disables the timed poll to prevent extra chattiness.  This
86 * isn't for normal use
87 */
88#undef DEBUG_RW
89
90/*
91 * The programming guide specifies a full test of the on-board SRAM
92 * at initialization time.  Undefine to remove this
93 */
94#define FULL_MEMORY_TEST
95
96/*
97 * This is the number of (4 byte) service entries that we will
98 * try to allocate at startup.  Note that we will end up with
99 * one PAGE_SIZE's worth regardless of what this is set to
100 */
101#define SERVICE_ENTRIES		(1024)
102/* TODO: make above a module load-time option */
103
104/*
105 * We normally read the onboard EEPROM in order to discover our MAC
106 * address.  Undefine to _not_ do this
107 */
108/* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
109/* TODO: make above a module load-time option (also) */
110
111/*
112 * Depth of TX fifo (in 128 byte units; range 2-31)
113 * Smaller numbers are better for network latency
114 * Larger numbers are better for PCI latency
115 * I'm really sure where the best tradeoff is, but the BSD driver uses
116 * 7 and it seems to work ok.
117 */
118#define TX_FIFO_DEPTH		(7)
119/* TODO: make above a module load-time option */
120
121/*
122 * How often (in jiffies) we will try to unstick stuck connections -
123 * shouldn't need to happen much
124 */
125#define LANAI_POLL_PERIOD	(10*HZ)
126/* TODO: make above a module load-time option */
127
128/*
129 * When allocating an AAL5 receiving buffer, try to make it at least
130 * large enough to hold this many max_sdu sized PDUs
131 */
132#define AAL5_RX_MULTIPLIER	(3)
133/* TODO: make above a module load-time option */
134
135/*
136 * Same for transmitting buffer
137 */
138#define AAL5_TX_MULTIPLIER	(3)
139/* TODO: make above a module load-time option */
140
141/*
142 * When allocating an AAL0 transmiting buffer, how many cells should fit.
143 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
144 * really critical
145 */
146#define AAL0_TX_MULTIPLIER	(40)
147/* TODO: make above a module load-time option */
148
149/*
150 * How large should we make the AAL0 receiving buffer.  Remember that this
151 * is shared between all AAL0 VC's
152 */
153#define AAL0_RX_BUFFER_SIZE	(PAGE_SIZE)
154/* TODO: make above a module load-time option */
155
156/*
157 * Should we use Lanai's "powerdown" feature when no vcc's are bound?
158 */
159/* #define USE_POWERDOWN */
160/* TODO: make above a module load-time option (also) */
161
162/* -------------------- DEBUGGING AIDS: */
163
164#define DEV_LABEL "lanai"
165
166#ifdef DEBUG
167
168#define DPRINTK(format, args...) \
169	printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
170#define APRINTK(truth, format, args...) \
171	do { \
172		if (unlikely(!(truth))) \
173			printk(KERN_ERR DEV_LABEL ": " format, ##args); \
174	} while (0)
175
176#else /* !DEBUG */
177
178#define DPRINTK(format, args...)
179#define APRINTK(truth, format, args...)
180
181#endif /* DEBUG */
182
183#ifdef DEBUG_RW
184#define RWDEBUG(format, args...) \
185	printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
186#else /* !DEBUG_RW */
187#define RWDEBUG(format, args...)
188#endif
189
190/* -------------------- DATA DEFINITIONS: */
191
192#define LANAI_MAPPING_SIZE	(0x40000)
193#define LANAI_EEPROM_SIZE	(128)
194
195typedef int vci_t;
196typedef void __iomem *bus_addr_t;
197
198/* DMA buffer in host memory for TX, RX, or service list. */
199struct lanai_buffer {
200	u32 *start;	/* From get_free_pages */
201	u32 *end;	/* One past last byte */
202	u32 *ptr;	/* Pointer to current host location */
203	dma_addr_t dmaaddr;
204};
205
206struct lanai_vcc_stats {
207	unsigned rx_nomem;
208	union {
209		struct {
210			unsigned rx_badlen;
211			unsigned service_trash;
212			unsigned service_stream;
213			unsigned service_rxcrc;
214		} aal5;
215		struct {
216		} aal0;
217	} x;
218};
219
220struct lanai_dev;			/* Forward declaration */
221
222/*
223 * This is the card-specific per-vcc data.  Note that unlike some other
224 * drivers there is NOT a 1-to-1 correspondance between these and
225 * atm_vcc's - each one of these represents an actual 2-way vcc, but
226 * an atm_vcc can be 1-way and share with a 1-way vcc in the other
227 * direction.  To make it weirder, there can even be 0-way vccs
228 * bound to us, waiting to do a change_qos
229 */
230struct lanai_vcc {
231	bus_addr_t vbase;		/* Base of VCC's registers */
232	struct lanai_vcc_stats stats;
233	int nref;			/* # of atm_vcc's who reference us */
234	vci_t vci;
235	struct {
236		struct lanai_buffer buf;
237		struct atm_vcc *atmvcc;	/* atm_vcc who is receiver */
238	} rx;
239	struct {
240		struct lanai_buffer buf;
241		struct atm_vcc *atmvcc;	/* atm_vcc who is transmitter */
242		int endptr;		/* last endptr from service entry */
243		struct sk_buff_head backlog;
244		void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
245	} tx;
246};
247
248enum lanai_type {
249	lanai2	= PCI_DEVICE_ID_EF_ATM_LANAI2,
250	lanaihb	= PCI_DEVICE_ID_EF_ATM_LANAIHB
251};
252
253struct lanai_dev_stats {
254	unsigned ovfl_trash;	/* # of cells dropped - buffer overflow */
255	unsigned vci_trash;	/* # of cells dropped - closed vci */
256	unsigned hec_err;	/* # of cells dropped - bad HEC */
257	unsigned atm_ovfl;	/* # of cells dropped - rx fifo overflow */
258	unsigned pcierr_parity_detect;
259	unsigned pcierr_serr_set;
260	unsigned pcierr_master_abort;
261	unsigned pcierr_m_target_abort;
262	unsigned pcierr_s_target_abort;
263	unsigned pcierr_master_parity;
264	unsigned service_notx;
265	unsigned service_norx;
266	unsigned service_rxnotaal5;
267	unsigned dma_reenable;
268	unsigned card_reset;
269};
270
271struct lanai_dev {
272	bus_addr_t base;
273	struct lanai_dev_stats stats;
274	struct lanai_buffer service;
275	struct lanai_vcc **vccs;
276#ifdef USE_POWERDOWN
277	int nbound;			/* number of bound vccs */
278#endif
279	enum lanai_type type;
280	vci_t num_vci;			/* Currently just NUM_VCI */
281	u8 eeprom[LANAI_EEPROM_SIZE];
282	u32 serialno, magicno;
283	struct pci_dev *pci;
284	DECLARE_BITMAP(backlog_vccs, NUM_VCI);   /* VCCs with tx backlog */
285	DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
286	struct timer_list timer;
287	int naal0;
288	struct lanai_buffer aal0buf;	/* AAL0 RX buffers */
289	u32 conf1, conf2;		/* CONFIG[12] registers */
290	u32 status;			/* STATUS register */
291	spinlock_t endtxlock;
292	spinlock_t servicelock;
293	struct atm_vcc *cbrvcc;
294	int number;
295	int board_rev;
296/* TODO - look at race conditions with maintence of conf1/conf2 */
297/* TODO - transmit locking: should we use _irq not _irqsave? */
298/* TODO - organize above in some rational fashion (see <asm/cache.h>) */
299};
300
301/*
302 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
303 * This function iterates one of these, calling a given function for each
304 * vci with their bit set
305 */
306static void vci_bitfield_iterate(struct lanai_dev *lanai,
307	const unsigned long *lp,
308	void (*func)(struct lanai_dev *,vci_t vci))
309{
310	vci_t vci;
311
312	for_each_set_bit(vci, lp, NUM_VCI)
313		func(lanai, vci);
314}
315
316/* -------------------- BUFFER  UTILITIES: */
317
318/*
319 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
320 * usually any page allocation will do.  Just to be safe in case
321 * PAGE_SIZE is insanely tiny, though...
322 */
323#define LANAI_PAGE_SIZE   ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
324
325/*
326 * Allocate a buffer in host RAM for service list, RX, or TX
327 * Returns buf->start==NULL if no memory
328 * Note that the size will be rounded up 2^n bytes, and
329 * if we can't allocate that we'll settle for something smaller
330 * until minbytes
331 */
332static void lanai_buf_allocate(struct lanai_buffer *buf,
333	size_t bytes, size_t minbytes, struct pci_dev *pci)
334{
335	int size;
336
337	if (bytes > (128 * 1024))	/* max lanai buffer size */
338		bytes = 128 * 1024;
339	for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
340		;
341	if (minbytes < LANAI_PAGE_SIZE)
342		minbytes = LANAI_PAGE_SIZE;
343	do {
344		/*
345		 * Technically we could use non-consistent mappings for
346		 * everything, but the way the lanai uses DMA memory would
347		 * make that a terrific pain.  This is much simpler.
348		 */
349		buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr);
350		if (buf->start != NULL) {	/* Success */
351			/* Lanai requires 256-byte alignment of DMA bufs */
352			APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
353			    "bad dmaaddr: 0x%lx\n",
354			    (unsigned long) buf->dmaaddr);
355			buf->ptr = buf->start;
356			buf->end = (u32 *)
357			    (&((unsigned char *) buf->start)[size]);
358			memset(buf->start, 0, size);
359			break;
360		}
361		size /= 2;
362	} while (size >= minbytes);
363}
364
365/* size of buffer in bytes */
366static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
367{
368	return ((unsigned long) buf->end) - ((unsigned long) buf->start);
369}
370
371static void lanai_buf_deallocate(struct lanai_buffer *buf,
372	struct pci_dev *pci)
373{
374	if (buf->start != NULL) {
375		pci_free_consistent(pci, lanai_buf_size(buf),
376		    buf->start, buf->dmaaddr);
377		buf->start = buf->end = buf->ptr = NULL;
378	}
379}
380
381/* size of buffer as "card order" (0=1k .. 7=128k) */
382static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
383{
384	int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
385
386	/* This can only happen if PAGE_SIZE is gigantic, but just in case */
387	if (order > 7)
388		order = 7;
389	return order;
390}
391
392/* -------------------- PORT I/O UTILITIES: */
393
394/* Registers (and their bit-fields) */
395enum lanai_register {
396	Reset_Reg		= 0x00,	/* Reset; read for chip type; bits: */
397#define   RESET_GET_BOARD_REV(x)    (((x)>> 0)&0x03)	/* Board revision */
398#define   RESET_GET_BOARD_ID(x)	    (((x)>> 2)&0x03)	/* Board ID */
399#define     BOARD_ID_LANAI256		(0)	/* 25.6M adapter card */
400	Endian_Reg		= 0x04,	/* Endian setting */
401	IntStatus_Reg		= 0x08,	/* Interrupt status */
402	IntStatusMasked_Reg	= 0x0C,	/* Interrupt status (masked) */
403	IntAck_Reg		= 0x10,	/* Interrupt acknowledge */
404	IntAckMasked_Reg	= 0x14,	/* Interrupt acknowledge (masked) */
405	IntStatusSet_Reg	= 0x18,	/* Get status + enable/disable */
406	IntStatusSetMasked_Reg	= 0x1C,	/* Get status + en/di (masked) */
407	IntControlEna_Reg	= 0x20,	/* Interrupt control enable */
408	IntControlDis_Reg	= 0x24,	/* Interrupt control disable */
409	Status_Reg		= 0x28,	/* Status */
410#define   STATUS_PROMDATA	 (0x00000001)	/* PROM_DATA pin */
411#define   STATUS_WAITING	 (0x00000002)	/* Interrupt being delayed */
412#define	  STATUS_SOOL		 (0x00000004)	/* SOOL alarm */
413#define   STATUS_LOCD		 (0x00000008)	/* LOCD alarm */
414#define	  STATUS_LED		 (0x00000010)	/* LED (HAPPI) output */
415#define   STATUS_GPIN		 (0x00000020)	/* GPIN pin */
416#define   STATUS_BUTTBUSY	 (0x00000040)	/* Butt register is pending */
417	Config1_Reg		= 0x2C,	/* Config word 1; bits: */
418#define   CONFIG1_PROMDATA	 (0x00000001)	/* PROM_DATA pin */
419#define   CONFIG1_PROMCLK	 (0x00000002)	/* PROM_CLK pin */
420#define   CONFIG1_SET_READMODE(x) ((x)*0x004)	/* PCI BM reads; values: */
421#define     READMODE_PLAIN	    (0)		/*   Plain memory read */
422#define     READMODE_LINE	    (2)		/*   Memory read line */
423#define     READMODE_MULTIPLE	    (3)		/*   Memory read multiple */
424#define   CONFIG1_DMA_ENABLE	 (0x00000010)	/* Turn on DMA */
425#define   CONFIG1_POWERDOWN	 (0x00000020)	/* Turn off clocks */
426#define   CONFIG1_SET_LOOPMODE(x) ((x)*0x080)	/* Clock&loop mode; values: */
427#define     LOOPMODE_NORMAL	    (0)		/*   Normal - no loop */
428#define     LOOPMODE_TIME	    (1)
429#define     LOOPMODE_DIAG	    (2)
430#define     LOOPMODE_LINE	    (3)
431#define   CONFIG1_MASK_LOOPMODE  (0x00000180)
432#define   CONFIG1_SET_LEDMODE(x) ((x)*0x0200)	/* Mode of LED; values: */
433#define     LEDMODE_NOT_SOOL	    (0)		/*   !SOOL */
434#define	    LEDMODE_OFF		    (1)		/*   0     */
435#define	    LEDMODE_ON		    (2)		/*   1     */
436#define	    LEDMODE_NOT_LOCD	    (3)		/*   !LOCD */
437#define	    LEDMORE_GPIN	    (4)		/*   GPIN  */
438#define     LEDMODE_NOT_GPIN	    (7)		/*   !GPIN */
439#define   CONFIG1_MASK_LEDMODE	 (0x00000E00)
440#define   CONFIG1_GPOUT1	 (0x00001000)	/* Toggle for reset */
441#define   CONFIG1_GPOUT2	 (0x00002000)	/* Loopback PHY */
442#define   CONFIG1_GPOUT3	 (0x00004000)	/* Loopback lanai */
443	Config2_Reg		= 0x30,	/* Config word 2; bits: */
444#define   CONFIG2_HOWMANY	 (0x00000001)	/* >512 VCIs? */
445#define   CONFIG2_PTI7_MODE	 (0x00000002)	/* Make PTI=7 RM, not OAM */
446#define   CONFIG2_VPI_CHK_DIS	 (0x00000004)	/* Ignore RX VPI value */
447#define   CONFIG2_HEC_DROP	 (0x00000008)	/* Drop cells w/ HEC errors */
448#define   CONFIG2_VCI0_NORMAL	 (0x00000010)	/* Treat VCI=0 normally */
449#define   CONFIG2_CBR_ENABLE	 (0x00000020)	/* Deal with CBR traffic */
450#define   CONFIG2_TRASH_ALL	 (0x00000040)	/* Trashing incoming cells */
451#define   CONFIG2_TX_DISABLE	 (0x00000080)	/* Trashing outgoing cells */
452#define   CONFIG2_SET_TRASH	 (0x00000100)	/* Turn trashing on */
453	Statistics_Reg		= 0x34,	/* Statistics; bits: */
454#define   STATS_GET_FIFO_OVFL(x)    (((x)>> 0)&0xFF)	/* FIFO overflowed */
455#define   STATS_GET_HEC_ERR(x)      (((x)>> 8)&0xFF)	/* HEC was bad */
456#define   STATS_GET_BAD_VCI(x)      (((x)>>16)&0xFF)	/* VCI not open */
457#define   STATS_GET_BUF_OVFL(x)     (((x)>>24)&0xFF)	/* VCC buffer full */
458	ServiceStuff_Reg	= 0x38,	/* Service stuff; bits: */
459#define   SSTUFF_SET_SIZE(x) ((x)*0x20000000)	/* size of service buffer */
460#define   SSTUFF_SET_ADDR(x)	    ((x)>>8)	/* set address of buffer */
461	ServWrite_Reg		= 0x3C,	/* ServWrite Pointer */
462	ServRead_Reg		= 0x40,	/* ServRead Pointer */
463	TxDepth_Reg		= 0x44,	/* FIFO Transmit Depth */
464	Butt_Reg		= 0x48,	/* Butt register */
465	CBR_ICG_Reg		= 0x50,
466	CBR_PTR_Reg		= 0x54,
467	PingCount_Reg		= 0x58,	/* Ping count */
468	DMA_Addr_Reg		= 0x5C	/* DMA address */
469};
470
471static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
472	enum lanai_register reg)
473{
474	return lanai->base + reg;
475}
476
477static inline u32 reg_read(const struct lanai_dev *lanai,
478	enum lanai_register reg)
479{
480	u32 t;
481	t = readl(reg_addr(lanai, reg));
482	RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
483	    (int) reg, t);
484	return t;
485}
486
487static inline void reg_write(const struct lanai_dev *lanai, u32 val,
488	enum lanai_register reg)
489{
490	RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
491	    (int) reg, val);
492	writel(val, reg_addr(lanai, reg));
493}
494
495static inline void conf1_write(const struct lanai_dev *lanai)
496{
497	reg_write(lanai, lanai->conf1, Config1_Reg);
498}
499
500static inline void conf2_write(const struct lanai_dev *lanai)
501{
502	reg_write(lanai, lanai->conf2, Config2_Reg);
503}
504
505/* Same as conf2_write(), but defers I/O if we're powered down */
506static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
507{
508#ifdef USE_POWERDOWN
509	if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
510		return;
511#endif /* USE_POWERDOWN */
512	conf2_write(lanai);
513}
514
515static inline void reset_board(const struct lanai_dev *lanai)
516{
517	DPRINTK("about to reset board\n");
518	reg_write(lanai, 0, Reset_Reg);
519	/*
520	 * If we don't delay a little while here then we can end up
521	 * leaving the card in a VERY weird state and lock up the
522	 * PCI bus.  This isn't documented anywhere but I've convinced
523	 * myself after a lot of painful experimentation
524	 */
525	udelay(5);
526}
527
528/* -------------------- CARD SRAM UTILITIES: */
529
530/* The SRAM is mapped into normal PCI memory space - the only catch is
531 * that it is only 16-bits wide but must be accessed as 32-bit.  The
532 * 16 high bits will be zero.  We don't hide this, since they get
533 * programmed mostly like discrete registers anyway
534 */
535#define SRAM_START (0x20000)
536#define SRAM_BYTES (0x20000)	/* Again, half don't really exist */
537
538static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
539{
540	return lanai->base + SRAM_START + offset;
541}
542
543static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
544{
545	return readl(sram_addr(lanai, offset));
546}
547
548static inline void sram_write(const struct lanai_dev *lanai,
549	u32 val, int offset)
550{
551	writel(val, sram_addr(lanai, offset));
552}
553
554static int sram_test_word(const struct lanai_dev *lanai, int offset,
555			  u32 pattern)
556{
557	u32 readback;
558	sram_write(lanai, pattern, offset);
559	readback = sram_read(lanai, offset);
560	if (likely(readback == pattern))
561		return 0;
562	printk(KERN_ERR DEV_LABEL
563	    "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
564	    lanai->number, offset,
565	    (unsigned int) pattern, (unsigned int) readback);
566	return -EIO;
567}
568
569static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
570{
571	int offset, result = 0;
572	for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
573		result = sram_test_word(lanai, offset, pattern);
574	return result;
575}
576
577static int sram_test_and_clear(const struct lanai_dev *lanai)
578{
579#ifdef FULL_MEMORY_TEST
580	int result;
581	DPRINTK("testing SRAM\n");
582	if ((result = sram_test_pass(lanai, 0x5555)) != 0)
583		return result;
584	if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
585		return result;
586#endif
587	DPRINTK("clearing SRAM\n");
588	return sram_test_pass(lanai, 0x0000);
589}
590
591/* -------------------- CARD-BASED VCC TABLE UTILITIES: */
592
593/* vcc table */
594enum lanai_vcc_offset {
595	vcc_rxaddr1		= 0x00,	/* Location1, plus bits: */
596#define   RXADDR1_SET_SIZE(x) ((x)*0x0000100)	/* size of RX buffer */
597#define   RXADDR1_SET_RMMODE(x) ((x)*0x00800)	/* RM cell action; values: */
598#define     RMMODE_TRASH	  (0)		/*   discard */
599#define     RMMODE_PRESERVE	  (1)		/*   input as AAL0 */
600#define     RMMODE_PIPE		  (2)		/*   pipe to coscheduler */
601#define     RMMODE_PIPEALL	  (3)		/*   pipe non-RM too */
602#define   RXADDR1_OAM_PRESERVE	 (0x00002000)	/* Input OAM cells as AAL0 */
603#define   RXADDR1_SET_MODE(x) ((x)*0x0004000)	/* Reassembly mode */
604#define     RXMODE_TRASH	  (0)		/*   discard */
605#define     RXMODE_AAL0		  (1)		/*   non-AAL5 mode */
606#define     RXMODE_AAL5		  (2)		/*   AAL5, intr. each PDU */
607#define     RXMODE_AAL5_STREAM	  (3)		/*   AAL5 w/o per-PDU intr */
608	vcc_rxaddr2		= 0x04,	/* Location2 */
609	vcc_rxcrc1		= 0x08,	/* RX CRC claculation space */
610	vcc_rxcrc2		= 0x0C,
611	vcc_rxwriteptr		= 0x10, /* RX writeptr, plus bits: */
612#define   RXWRITEPTR_LASTEFCI	 (0x00002000)	/* Last PDU had EFCI bit */
613#define   RXWRITEPTR_DROPPING	 (0x00004000)	/* Had error, dropping */
614#define   RXWRITEPTR_TRASHING	 (0x00008000)	/* Trashing */
615	vcc_rxbufstart		= 0x14,	/* RX bufstart, plus bits: */
616#define   RXBUFSTART_CLP	 (0x00004000)
617#define   RXBUFSTART_CI		 (0x00008000)
618	vcc_rxreadptr		= 0x18,	/* RX readptr */
619	vcc_txicg		= 0x1C, /* TX ICG */
620	vcc_txaddr1		= 0x20,	/* Location1, plus bits: */
621#define   TXADDR1_SET_SIZE(x) ((x)*0x0000100)	/* size of TX buffer */
622#define   TXADDR1_ABR		 (0x00008000)	/* use ABR (doesn't work) */
623	vcc_txaddr2		= 0x24,	/* Location2 */
624	vcc_txcrc1		= 0x28,	/* TX CRC claculation space */
625	vcc_txcrc2		= 0x2C,
626	vcc_txreadptr		= 0x30, /* TX Readptr, plus bits: */
627#define   TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
628#define   TXREADPTR_MASK_DELTA	(0x0000E000)	/* ? */
629	vcc_txendptr		= 0x34, /* TX Endptr, plus bits: */
630#define   TXENDPTR_CLP		(0x00002000)
631#define   TXENDPTR_MASK_PDUMODE	(0x0000C000)	/* PDU mode; values: */
632#define     PDUMODE_AAL0	 (0*0x04000)
633#define     PDUMODE_AAL5	 (2*0x04000)
634#define     PDUMODE_AAL5STREAM	 (3*0x04000)
635	vcc_txwriteptr		= 0x38,	/* TX Writeptr */
636#define   TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
637	vcc_txcbr_next		= 0x3C	/* # of next CBR VCI in ring */
638#define   TXCBR_NEXT_BOZO	(0x00008000)	/* "bozo bit" */
639};
640
641#define CARDVCC_SIZE	(0x40)
642
643static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
644	vci_t vci)
645{
646	return sram_addr(lanai, vci * CARDVCC_SIZE);
647}
648
649static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
650	enum lanai_vcc_offset offset)
651{
652	u32 val;
653	APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
654	val= readl(lvcc->vbase + offset);
655	RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
656	    lvcc->vci, (int) offset, val);
657	return val;
658}
659
660static inline void cardvcc_write(const struct lanai_vcc *lvcc,
661	u32 val, enum lanai_vcc_offset offset)
662{
663	APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
664	APRINTK((val & ~0xFFFF) == 0,
665	    "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
666	    (unsigned int) val, lvcc->vci, (unsigned int) offset);
667	RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
668	    lvcc->vci, (unsigned int) offset, (unsigned int) val);
669	writel(val, lvcc->vbase + offset);
670}
671
672/* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
673
674/* How many bytes will an AAL5 PDU take to transmit - remember that:
675 *   o  we need to add 8 bytes for length, CPI, UU, and CRC
676 *   o  we need to round up to 48 bytes for cells
677 */
678static inline int aal5_size(int size)
679{
680	int cells = (size + 8 + 47) / 48;
681	return cells * 48;
682}
683
684/* How many bytes can we send if we have "space" space, assuming we have
685 * to send full cells
686 */
687static inline int aal5_spacefor(int space)
688{
689	int cells = space / 48;
690	return cells * 48;
691}
692
693/* -------------------- FREE AN ATM SKB: */
694
695static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
696{
697	if (atmvcc->pop != NULL)
698		atmvcc->pop(atmvcc, skb);
699	else
700		dev_kfree_skb_any(skb);
701}
702
703/* -------------------- TURN VCCS ON AND OFF: */
704
705static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
706{
707	u32 addr1;
708	if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
709		dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
710		cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
711		cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
712		cardvcc_write(lvcc, 0, vcc_rxwriteptr);
713		cardvcc_write(lvcc, 0, vcc_rxbufstart);
714		cardvcc_write(lvcc, 0, vcc_rxreadptr);
715		cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
716		addr1 = ((dmaaddr >> 8) & 0xFF) |
717		    RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
718		    RXADDR1_SET_RMMODE(RMMODE_TRASH) |	/* ??? */
719		 /* RXADDR1_OAM_PRESERVE |	--- no OAM support yet */
720		    RXADDR1_SET_MODE(RXMODE_AAL5);
721	} else
722		addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
723		    RXADDR1_OAM_PRESERVE |		      /* ??? */
724		    RXADDR1_SET_MODE(RXMODE_AAL0);
725	/* This one must be last! */
726	cardvcc_write(lvcc, addr1, vcc_rxaddr1);
727}
728
729static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
730{
731	dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
732	cardvcc_write(lvcc, 0, vcc_txicg);
733	cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
734	cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
735	cardvcc_write(lvcc, 0, vcc_txreadptr);
736	cardvcc_write(lvcc, 0, vcc_txendptr);
737	cardvcc_write(lvcc, 0, vcc_txwriteptr);
738	cardvcc_write(lvcc,
739		(lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
740		TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
741	cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
742	cardvcc_write(lvcc,
743	    ((dmaaddr >> 8) & 0xFF) |
744	    TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
745	    vcc_txaddr1);
746}
747
748/* Shutdown receiving on card */
749static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
750{
751	if (lvcc->vbase == NULL)	/* We were never bound to a VCI */
752		return;
753	/* 15.1.1 - set to trashing, wait one cell time (15us) */
754	cardvcc_write(lvcc,
755	    RXADDR1_SET_RMMODE(RMMODE_TRASH) |
756	    RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
757	udelay(15);
758	/* 15.1.2 - clear rest of entries */
759	cardvcc_write(lvcc, 0, vcc_rxaddr2);
760	cardvcc_write(lvcc, 0, vcc_rxcrc1);
761	cardvcc_write(lvcc, 0, vcc_rxcrc2);
762	cardvcc_write(lvcc, 0, vcc_rxwriteptr);
763	cardvcc_write(lvcc, 0, vcc_rxbufstart);
764	cardvcc_write(lvcc, 0, vcc_rxreadptr);
765}
766
767/* Shutdown transmitting on card.
768 * Unfortunately the lanai needs us to wait until all the data
769 * drains out of the buffer before we can dealloc it, so this
770 * can take awhile -- up to 370ms for a full 128KB buffer
771 * assuming everone else is quiet.  In theory the time is
772 * boundless if there's a CBR VCC holding things up.
773 */
774static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
775	struct lanai_vcc *lvcc)
776{
777	struct sk_buff *skb;
778	unsigned long flags, timeout;
779	int read, write, lastread = -1;
780	APRINTK(!in_interrupt(),
781	    "lanai_shutdown_tx_vci called w/o process context!\n");
782	if (lvcc->vbase == NULL)	/* We were never bound to a VCI */
783		return;
784	/* 15.2.1 - wait for queue to drain */
785	while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
786		lanai_free_skb(lvcc->tx.atmvcc, skb);
787	read_lock_irqsave(&vcc_sklist_lock, flags);
788	__clear_bit(lvcc->vci, lanai->backlog_vccs);
789	read_unlock_irqrestore(&vcc_sklist_lock, flags);
790	/*
791	 * We need to wait for the VCC to drain but don't wait forever.  We
792	 * give each 1K of buffer size 1/128th of a second to clear out.
793	 * TODO: maybe disable CBR if we're about to timeout?
794	 */
795	timeout = jiffies +
796	    (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
797	write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
798	for (;;) {
799		read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
800		if (read == write &&	   /* Is TX buffer empty? */
801		    (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
802		    (cardvcc_read(lvcc, vcc_txcbr_next) &
803		    TXCBR_NEXT_BOZO) == 0))
804			break;
805		if (read != lastread) {	   /* Has there been any progress? */
806			lastread = read;
807			timeout += HZ / 10;
808		}
809		if (unlikely(time_after(jiffies, timeout))) {
810			printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
811			    "backlog closing vci %d\n",
812			    lvcc->tx.atmvcc->dev->number, lvcc->vci);
813			DPRINTK("read, write = %d, %d\n", read, write);
814			break;
815		}
816		msleep(40);
817	}
818	/* 15.2.2 - clear out all tx registers */
819	cardvcc_write(lvcc, 0, vcc_txreadptr);
820	cardvcc_write(lvcc, 0, vcc_txwriteptr);
821	cardvcc_write(lvcc, 0, vcc_txendptr);
822	cardvcc_write(lvcc, 0, vcc_txcrc1);
823	cardvcc_write(lvcc, 0, vcc_txcrc2);
824	cardvcc_write(lvcc, 0, vcc_txaddr2);
825	cardvcc_write(lvcc, 0, vcc_txaddr1);
826}
827
828/* -------------------- MANAGING AAL0 RX BUFFER: */
829
830static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
831{
832	DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
833	lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
834			   lanai->pci);
835	return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
836}
837
838static inline void aal0_buffer_free(struct lanai_dev *lanai)
839{
840	DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
841	lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
842}
843
844/* -------------------- EEPROM UTILITIES: */
845
846/* Offsets of data in the EEPROM */
847#define EEPROM_COPYRIGHT	(0)
848#define EEPROM_COPYRIGHT_LEN	(44)
849#define EEPROM_CHECKSUM		(62)
850#define EEPROM_CHECKSUM_REV	(63)
851#define EEPROM_MAC		(64)
852#define EEPROM_MAC_REV		(70)
853#define EEPROM_SERIAL		(112)
854#define EEPROM_SERIAL_REV	(116)
855#define EEPROM_MAGIC		(120)
856#define EEPROM_MAGIC_REV	(124)
857
858#define EEPROM_MAGIC_VALUE	(0x5AB478D2)
859
860#ifndef READ_EEPROM
861
862/* Stub functions to use if EEPROM reading is disabled */
863static int eeprom_read(struct lanai_dev *lanai)
864{
865	printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
866	    lanai->number);
867	memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
868	return 0;
869}
870
871static int eeprom_validate(struct lanai_dev *lanai)
872{
873	lanai->serialno = 0;
874	lanai->magicno = EEPROM_MAGIC_VALUE;
875	return 0;
876}
877
878#else /* READ_EEPROM */
879
880static int eeprom_read(struct lanai_dev *lanai)
881{
882	int i, address;
883	u8 data;
884	u32 tmp;
885#define set_config1(x)   do { lanai->conf1 = x; conf1_write(lanai); \
886			    } while (0)
887#define clock_h()	 set_config1(lanai->conf1 | CONFIG1_PROMCLK)
888#define clock_l()	 set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
889#define data_h()	 set_config1(lanai->conf1 | CONFIG1_PROMDATA)
890#define data_l()	 set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
891#define pre_read()	 do { data_h(); clock_h(); udelay(5); } while (0)
892#define read_pin()	 (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
893#define send_stop()	 do { data_l(); udelay(5); clock_h(); udelay(5); \
894			      data_h(); udelay(5); } while (0)
895	/* start with both clock and data high */
896	data_h(); clock_h(); udelay(5);
897	for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
898		data = (address << 1) | 1;	/* Command=read + address */
899		/* send start bit */
900		data_l(); udelay(5);
901		clock_l(); udelay(5);
902		for (i = 128; i != 0; i >>= 1) {   /* write command out */
903			tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
904			    ((data & i) ? CONFIG1_PROMDATA : 0);
905			if (lanai->conf1 != tmp) {
906				set_config1(tmp);
907				udelay(5);	/* Let new data settle */
908			}
909			clock_h(); udelay(5); clock_l(); udelay(5);
910		}
911		/* look for ack */
912		data_h(); clock_h(); udelay(5);
913		if (read_pin() != 0)
914			goto error;	/* No ack seen */
915		clock_l(); udelay(5);
916		/* read back result */
917		for (data = 0, i = 7; i >= 0; i--) {
918			data_h(); clock_h(); udelay(5);
919			data = (data << 1) | !!read_pin();
920			clock_l(); udelay(5);
921		}
922		/* look again for ack */
923		data_h(); clock_h(); udelay(5);
924		if (read_pin() == 0)
925			goto error;	/* Spurious ack */
926		clock_l(); udelay(5);
927		send_stop();
928		lanai->eeprom[address] = data;
929		DPRINTK("EEPROM 0x%04X %02X\n",
930		    (unsigned int) address, (unsigned int) data);
931	}
932	return 0;
933    error:
934	clock_l(); udelay(5);		/* finish read */
935	send_stop();
936	printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
937	    lanai->number, address);
938	return -EIO;
939#undef set_config1
940#undef clock_h
941#undef clock_l
942#undef data_h
943#undef data_l
944#undef pre_read
945#undef read_pin
946#undef send_stop
947}
948
949/* read a big-endian 4-byte value out of eeprom */
950static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
951{
952	return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
953}
954
955/* Checksum/validate EEPROM contents */
956static int eeprom_validate(struct lanai_dev *lanai)
957{
958	int i, s;
959	u32 v;
960	const u8 *e = lanai->eeprom;
961#ifdef DEBUG
962	/* First, see if we can get an ASCIIZ string out of the copyright */
963	for (i = EEPROM_COPYRIGHT;
964	    i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
965		if (e[i] < 0x20 || e[i] > 0x7E)
966			break;
967	if ( i != EEPROM_COPYRIGHT &&
968	    i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
969		DPRINTK("eeprom: copyright = \"%s\"\n",
970		    (char *) &e[EEPROM_COPYRIGHT]);
971	else
972		DPRINTK("eeprom: copyright not found\n");
973#endif
974	/* Validate checksum */
975	for (i = s = 0; i < EEPROM_CHECKSUM; i++)
976		s += e[i];
977	s &= 0xFF;
978	if (s != e[EEPROM_CHECKSUM]) {
979		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
980		    "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
981		    (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
982		return -EIO;
983	}
984	s ^= 0xFF;
985	if (s != e[EEPROM_CHECKSUM_REV]) {
986		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
987		    "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
988		    (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
989		return -EIO;
990	}
991	/* Verify MAC address */
992	for (i = 0; i < 6; i++)
993		if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
994			printk(KERN_ERR DEV_LABEL
995			    "(itf %d) : EEPROM MAC addresses don't match "
996			    "(0x%02X, inverse 0x%02X)\n", lanai->number,
997			    (unsigned int) e[EEPROM_MAC + i],
998			    (unsigned int) e[EEPROM_MAC_REV + i]);
999			return -EIO;
1000		}
1001	DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]);
1002	/* Verify serial number */
1003	lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
1004	v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
1005	if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
1006		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
1007		    "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1008		    (unsigned int) lanai->serialno, (unsigned int) v);
1009		return -EIO;
1010	}
1011	DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1012	/* Verify magic number */
1013	lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1014	v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1015	if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1016		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
1017		    "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1018		    lanai->magicno, v);
1019		return -EIO;
1020	}
1021	DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1022	if (lanai->magicno != EEPROM_MAGIC_VALUE)
1023		printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
1024		    "magic not what expected (got 0x%08X, not 0x%08X)\n",
1025		    lanai->number, (unsigned int) lanai->magicno,
1026		    (unsigned int) EEPROM_MAGIC_VALUE);
1027	return 0;
1028}
1029
1030#endif /* READ_EEPROM */
1031
1032static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1033{
1034	return &lanai->eeprom[EEPROM_MAC];
1035}
1036
1037/* -------------------- INTERRUPT HANDLING UTILITIES: */
1038
1039/* Interrupt types */
1040#define INT_STATS	(0x00000002)	/* Statistics counter overflow */
1041#define INT_SOOL	(0x00000004)	/* SOOL changed state */
1042#define INT_LOCD	(0x00000008)	/* LOCD changed state */
1043#define INT_LED		(0x00000010)	/* LED (HAPPI) changed state */
1044#define INT_GPIN	(0x00000020)	/* GPIN changed state */
1045#define INT_PING	(0x00000040)	/* PING_COUNT fulfilled */
1046#define INT_WAKE	(0x00000080)	/* Lanai wants bus */
1047#define INT_CBR0	(0x00000100)	/* CBR sched hit VCI 0 */
1048#define INT_LOCK	(0x00000200)	/* Service list overflow */
1049#define INT_MISMATCH	(0x00000400)	/* TX magic list mismatch */
1050#define INT_AAL0_STR	(0x00000800)	/* Non-AAL5 buffer half filled */
1051#define INT_AAL0	(0x00001000)	/* Non-AAL5 data available */
1052#define INT_SERVICE	(0x00002000)	/* Service list entries available */
1053#define INT_TABORTSENT	(0x00004000)	/* Target abort sent by lanai */
1054#define INT_TABORTBM	(0x00008000)	/* Abort rcv'd as bus master */
1055#define INT_TIMEOUTBM	(0x00010000)	/* No response to bus master */
1056#define INT_PCIPARITY	(0x00020000)	/* Parity error on PCI */
1057
1058/* Sets of the above */
1059#define INT_ALL		(0x0003FFFE)	/* All interrupts */
1060#define INT_STATUS	(0x0000003C)	/* Some status pin changed */
1061#define INT_DMASHUT	(0x00038000)	/* DMA engine got shut down */
1062#define INT_SEGSHUT	(0x00000700)	/* Segmentation got shut down */
1063
1064static inline u32 intr_pending(const struct lanai_dev *lanai)
1065{
1066	return reg_read(lanai, IntStatusMasked_Reg);
1067}
1068
1069static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1070{
1071	reg_write(lanai, i, IntControlEna_Reg);
1072}
1073
1074static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1075{
1076	reg_write(lanai, i, IntControlDis_Reg);
1077}
1078
1079/* -------------------- CARD/PCI STATUS: */
1080
1081static void status_message(int itf, const char *name, int status)
1082{
1083	static const char *onoff[2] = { "off to on", "on to off" };
1084	printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
1085	    itf, name, onoff[!status]);
1086}
1087
1088static void lanai_check_status(struct lanai_dev *lanai)
1089{
1090	u32 new = reg_read(lanai, Status_Reg);
1091	u32 changes = new ^ lanai->status;
1092	lanai->status = new;
1093#define e(flag, name) \
1094		if (changes & flag) \
1095			status_message(lanai->number, name, new & flag)
1096	e(STATUS_SOOL, "SOOL");
1097	e(STATUS_LOCD, "LOCD");
1098	e(STATUS_LED, "LED");
1099	e(STATUS_GPIN, "GPIN");
1100#undef e
1101}
1102
1103static void pcistatus_got(int itf, const char *name)
1104{
1105	printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
1106}
1107
1108static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1109{
1110	u16 s;
1111	int result;
1112	result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1113	if (result != PCIBIOS_SUCCESSFUL) {
1114		printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
1115		    "%d\n", lanai->number, result);
1116		return;
1117	}
1118	s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
1119	    PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
1120	    PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
1121	if (s == 0)
1122		return;
1123	result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1124	if (result != PCIBIOS_SUCCESSFUL)
1125		printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
1126		    "%d\n", lanai->number, result);
1127	if (clearonly)
1128		return;
1129#define e(flag, name, stat) \
1130		if (s & flag) { \
1131			pcistatus_got(lanai->number, name); \
1132			++lanai->stats.pcierr_##stat; \
1133		}
1134	e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
1135	e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
1136	e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
1137	e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
1138	e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
1139	e(PCI_STATUS_PARITY, "master parity", master_parity);
1140#undef e
1141}
1142
1143/* -------------------- VCC TX BUFFER UTILITIES: */
1144
1145/* space left in tx buffer in bytes */
1146static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
1147{
1148	int r;
1149	r = endptr * 16;
1150	r -= ((unsigned long) lvcc->tx.buf.ptr) -
1151	    ((unsigned long) lvcc->tx.buf.start);
1152	r -= 16;	/* Leave "bubble" - if start==end it looks empty */
1153	if (r < 0)
1154		r += lanai_buf_size(&lvcc->tx.buf);
1155	return r;
1156}
1157
1158/* test if VCC is currently backlogged */
1159static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
1160{
1161	return !skb_queue_empty(&lvcc->tx.backlog);
1162}
1163
1164/* Bit fields in the segmentation buffer descriptor */
1165#define DESCRIPTOR_MAGIC	(0xD0000000)
1166#define DESCRIPTOR_AAL5		(0x00008000)
1167#define DESCRIPTOR_AAL5_STREAM	(0x00004000)
1168#define DESCRIPTOR_CLP		(0x00002000)
1169
1170/* Add 32-bit descriptor with its padding */
1171static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
1172	u32 flags, int len)
1173{
1174	int pos;
1175	APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
1176	    "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
1177	lvcc->tx.buf.ptr += 4;	/* Hope the values REALLY don't matter */
1178	pos = ((unsigned char *) lvcc->tx.buf.ptr) -
1179	    (unsigned char *) lvcc->tx.buf.start;
1180	APRINTK((pos & ~0x0001FFF0) == 0,
1181	    "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
1182	    "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1183	    lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1184	pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
1185	APRINTK((pos & ~0x0001FFF0) == 0,
1186	    "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
1187	    "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1188	    lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1189	lvcc->tx.buf.ptr[-1] =
1190	    cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
1191	    ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
1192	    DESCRIPTOR_CLP : 0) | flags | pos >> 4);
1193	if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1194		lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1195}
1196
1197/* Add 32-bit AAL5 trailer and leave room for its CRC */
1198static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
1199	int len, int cpi, int uu)
1200{
1201	APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
1202	    "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
1203	lvcc->tx.buf.ptr += 2;
1204	lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
1205	if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1206		lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1207}
1208
1209static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
1210	const unsigned char *src, int n)
1211{
1212	unsigned char *e;
1213	int m;
1214	e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1215	m = e - (unsigned char *) lvcc->tx.buf.end;
1216	if (m < 0)
1217		m = 0;
1218	memcpy(lvcc->tx.buf.ptr, src, n - m);
1219	if (m != 0) {
1220		memcpy(lvcc->tx.buf.start, src + n - m, m);
1221		e = ((unsigned char *) lvcc->tx.buf.start) + m;
1222	}
1223	lvcc->tx.buf.ptr = (u32 *) e;
1224}
1225
1226static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
1227{
1228	unsigned char *e;
1229	int m;
1230	if (n == 0)
1231		return;
1232	e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1233	m = e - (unsigned char *) lvcc->tx.buf.end;
1234	if (m < 0)
1235		m = 0;
1236	memset(lvcc->tx.buf.ptr, 0, n - m);
1237	if (m != 0) {
1238		memset(lvcc->tx.buf.start, 0, m);
1239		e = ((unsigned char *) lvcc->tx.buf.start) + m;
1240	}
1241	lvcc->tx.buf.ptr = (u32 *) e;
1242}
1243
1244/* Update "butt" register to specify new WritePtr */
1245static inline void lanai_endtx(struct lanai_dev *lanai,
1246	const struct lanai_vcc *lvcc)
1247{
1248	int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
1249	    (unsigned char *) lvcc->tx.buf.start;
1250	APRINTK((ptr & ~0x0001FFF0) == 0,
1251	    "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
1252	    ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
1253	    lvcc->tx.buf.end);
1254
1255	/*
1256	 * Since the "butt register" is a shared resounce on the card we
1257	 * serialize all accesses to it through this spinlock.  This is
1258	 * mostly just paranoia since the register is rarely "busy" anyway
1259	 * but is needed for correctness.
1260	 */
1261	spin_lock(&lanai->endtxlock);
1262	/*
1263	 * We need to check if the "butt busy" bit is set before
1264	 * updating the butt register.  In theory this should
1265	 * never happen because the ATM card is plenty fast at
1266	 * updating the register.  Still, we should make sure
1267	 */
1268	for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1269		if (unlikely(i > 50)) {
1270			printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
1271			    "always busy!\n", lanai->number);
1272			break;
1273		}
1274		udelay(5);
1275	}
1276	/*
1277	 * Before we tall the card to start work we need to be sure 100% of
1278	 * the info in the service buffer has been written before we tell
1279	 * the card about it
1280	 */
1281	wmb();
1282	reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1283	spin_unlock(&lanai->endtxlock);
1284}
1285
1286/*
1287 * Add one AAL5 PDU to lvcc's transmit buffer.  Caller garauntees there's
1288 * space available.  "pdusize" is the number of bytes the PDU will take
1289 */
1290static void lanai_send_one_aal5(struct lanai_dev *lanai,
1291	struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
1292{
1293	int pad;
1294	APRINTK(pdusize == aal5_size(skb->len),
1295	    "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
1296	    pdusize, aal5_size(skb->len));
1297	vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
1298	pad = pdusize - skb->len - 8;
1299	APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
1300	APRINTK(pad < 48, "pad is too big (%d)\n", pad);
1301	vcc_tx_memcpy(lvcc, skb->data, skb->len);
1302	vcc_tx_memzero(lvcc, pad);
1303	vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
1304	lanai_endtx(lanai, lvcc);
1305	lanai_free_skb(lvcc->tx.atmvcc, skb);
1306	atomic_inc(&lvcc->tx.atmvcc->stats->tx);
1307}
1308
1309/* Try to fill the buffer - don't call unless there is backlog */
1310static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1311	struct lanai_vcc *lvcc, int endptr)
1312{
1313	int n;
1314	struct sk_buff *skb;
1315	int space = vcc_tx_space(lvcc, endptr);
1316	APRINTK(vcc_is_backlogged(lvcc),
1317	    "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
1318	    lvcc->vci);
1319	while (space >= 64) {
1320		skb = skb_dequeue(&lvcc->tx.backlog);
1321		if (skb == NULL)
1322			goto no_backlog;
1323		n = aal5_size(skb->len);
1324		if (n + 16 > space) {
1325			/* No room for this packet - put it back on queue */
1326			skb_queue_head(&lvcc->tx.backlog, skb);
1327			return;
1328		}
1329		lanai_send_one_aal5(lanai, lvcc, skb, n);
1330		space -= n + 16;
1331	}
1332	if (!vcc_is_backlogged(lvcc)) {
1333	    no_backlog:
1334		__clear_bit(lvcc->vci, lanai->backlog_vccs);
1335	}
1336}
1337
1338/* Given an skb that we want to transmit either send it now or queue */
1339static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1340	struct sk_buff *skb)
1341{
1342	int space, n;
1343	if (vcc_is_backlogged(lvcc))		/* Already backlogged */
1344		goto queue_it;
1345	space = vcc_tx_space(lvcc,
1346		    TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
1347	n = aal5_size(skb->len);
1348	APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
1349	if (space < n + 16) {			/* No space for this PDU */
1350		__set_bit(lvcc->vci, lanai->backlog_vccs);
1351	    queue_it:
1352		skb_queue_tail(&lvcc->tx.backlog, skb);
1353		return;
1354	}
1355	lanai_send_one_aal5(lanai, lvcc, skb, n);
1356}
1357
1358static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1359	struct lanai_vcc *lvcc, int endptr)
1360{
1361	printk(KERN_INFO DEV_LABEL
1362	    ": vcc_tx_unqueue_aal0: not implemented\n");
1363}
1364
1365static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1366	struct sk_buff *skb)
1367{
1368	printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
1369	/* Remember to increment lvcc->tx.atmvcc->stats->tx */
1370	lanai_free_skb(lvcc->tx.atmvcc, skb);
1371}
1372
1373/* -------------------- VCC RX BUFFER UTILITIES: */
1374
1375/* unlike the _tx_ cousins, this doesn't update ptr */
1376static inline void vcc_rx_memcpy(unsigned char *dest,
1377	const struct lanai_vcc *lvcc, int n)
1378{
1379	int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
1380	    ((const unsigned char *) (lvcc->rx.buf.end));
1381	if (m < 0)
1382		m = 0;
1383	memcpy(dest, lvcc->rx.buf.ptr, n - m);
1384	memcpy(dest + n - m, lvcc->rx.buf.start, m);
1385	/* Make sure that these copies don't get reordered */
1386	barrier();
1387}
1388
1389/* Receive AAL5 data on a VCC with a particular endptr */
1390static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
1391{
1392	int size;
1393	struct sk_buff *skb;
1394	const u32 *x;
1395	u32 *end = &lvcc->rx.buf.start[endptr * 4];
1396	int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
1397	if (n < 0)
1398		n += lanai_buf_size(&lvcc->rx.buf);
1399	APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
1400	    "vcc_rx_aal5: n out of range (%d/%Zu)\n",
1401	    n, lanai_buf_size(&lvcc->rx.buf));
1402	/* Recover the second-to-last word to get true pdu length */
1403	if ((x = &end[-2]) < lvcc->rx.buf.start)
1404		x = &lvcc->rx.buf.end[-2];
1405	/*
1406	 * Before we actually read from the buffer, make sure the memory
1407	 * changes have arrived
1408	 */
1409	rmb();
1410	size = be32_to_cpup(x) & 0xffff;
1411	if (unlikely(n != aal5_size(size))) {
1412		/* Make sure size matches padding */
1413		printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
1414		    "on vci=%d - size=%d n=%d\n",
1415		    lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
1416		lvcc->stats.x.aal5.rx_badlen++;
1417		goto out;
1418	}
1419	skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
1420	if (unlikely(skb == NULL)) {
1421		lvcc->stats.rx_nomem++;
1422		goto out;
1423	}
1424	skb_put(skb, size);
1425	vcc_rx_memcpy(skb->data, lvcc, size);
1426	ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
1427	__net_timestamp(skb);
1428	lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
1429	atomic_inc(&lvcc->rx.atmvcc->stats->rx);
1430    out:
1431	lvcc->rx.buf.ptr = end;
1432	cardvcc_write(lvcc, endptr, vcc_rxreadptr);
1433}
1434
1435static void vcc_rx_aal0(struct lanai_dev *lanai)
1436{
1437	printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
1438	/* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
1439	/* Remember to increment lvcc->rx.atmvcc->stats->rx */
1440}
1441
1442/* -------------------- MANAGING HOST-BASED VCC TABLE: */
1443
1444/* Decide whether to use vmalloc or get_zeroed_page for VCC table */
1445#if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
1446#define VCCTABLE_GETFREEPAGE
1447#else
1448#include <linux/vmalloc.h>
1449#endif
1450
1451static int vcc_table_allocate(struct lanai_dev *lanai)
1452{
1453#ifdef VCCTABLE_GETFREEPAGE
1454	APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1455	    "vcc table > PAGE_SIZE!");
1456	lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1457	return (lanai->vccs == NULL) ? -ENOMEM : 0;
1458#else
1459	int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1460	lanai->vccs = vzalloc(bytes);
1461	if (unlikely(lanai->vccs == NULL))
1462		return -ENOMEM;
1463	return 0;
1464#endif
1465}
1466
1467static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1468{
1469#ifdef VCCTABLE_GETFREEPAGE
1470	free_page((unsigned long) lanai->vccs);
1471#else
1472	vfree(lanai->vccs);
1473#endif
1474}
1475
1476/* Allocate a fresh lanai_vcc, with the appropriate things cleared */
1477static inline struct lanai_vcc *new_lanai_vcc(void)
1478{
1479	struct lanai_vcc *lvcc;
1480	lvcc =  kzalloc(sizeof(*lvcc), GFP_KERNEL);
1481	if (likely(lvcc != NULL)) {
1482		skb_queue_head_init(&lvcc->tx.backlog);
1483#ifdef DEBUG
1484		lvcc->vci = -1;
1485#endif
1486	}
1487	return lvcc;
1488}
1489
1490static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1491	struct lanai_buffer *buf, int max_sdu, int multiplier,
1492	const char *name)
1493{
1494	int size;
1495	if (unlikely(max_sdu < 1))
1496		max_sdu = 1;
1497	max_sdu = aal5_size(max_sdu);
1498	size = (max_sdu + 16) * multiplier + 16;
1499	lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1500	if (unlikely(buf->start == NULL))
1501		return -ENOMEM;
1502	if (unlikely(lanai_buf_size(buf) < size))
1503		printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
1504		    "for %s buffer, got only %Zu\n", lanai->number, size,
1505		    name, lanai_buf_size(buf));
1506	DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name);
1507	return 0;
1508}
1509
1510/* Setup a RX buffer for a currently unbound AAL5 vci */
1511static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1512	struct lanai_vcc *lvcc, const struct atm_qos *qos)
1513{
1514	return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1515	    qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
1516}
1517
1518/* Setup a TX buffer for a currently unbound AAL5 vci */
1519static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1520	const struct atm_qos *qos)
1521{
1522	int max_sdu, multiplier;
1523	if (qos->aal == ATM_AAL0) {
1524		lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
1525		max_sdu = ATM_CELL_SIZE - 1;
1526		multiplier = AAL0_TX_MULTIPLIER;
1527	} else {
1528		lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
1529		max_sdu = qos->txtp.max_sdu;
1530		multiplier = AAL5_TX_MULTIPLIER;
1531	}
1532	return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1533	    multiplier, "TX");
1534}
1535
1536static inline void host_vcc_bind(struct lanai_dev *lanai,
1537	struct lanai_vcc *lvcc, vci_t vci)
1538{
1539	if (lvcc->vbase != NULL)
1540		return;    /* We already were bound in the other direction */
1541	DPRINTK("Binding vci %d\n", vci);
1542#ifdef USE_POWERDOWN
1543	if (lanai->nbound++ == 0) {
1544		DPRINTK("Coming out of powerdown\n");
1545		lanai->conf1 &= ~CONFIG1_POWERDOWN;
1546		conf1_write(lanai);
1547		conf2_write(lanai);
1548	}
1549#endif
1550	lvcc->vbase = cardvcc_addr(lanai, vci);
1551	lanai->vccs[lvcc->vci = vci] = lvcc;
1552}
1553
1554static inline void host_vcc_unbind(struct lanai_dev *lanai,
1555	struct lanai_vcc *lvcc)
1556{
1557	if (lvcc->vbase == NULL)
1558		return;	/* This vcc was never bound */
1559	DPRINTK("Unbinding vci %d\n", lvcc->vci);
1560	lvcc->vbase = NULL;
1561	lanai->vccs[lvcc->vci] = NULL;
1562#ifdef USE_POWERDOWN
1563	if (--lanai->nbound == 0) {
1564		DPRINTK("Going into powerdown\n");
1565		lanai->conf1 |= CONFIG1_POWERDOWN;
1566		conf1_write(lanai);
1567	}
1568#endif
1569}
1570
1571/* -------------------- RESET CARD: */
1572
1573static void lanai_reset(struct lanai_dev *lanai)
1574{
1575	printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* resetting - not "
1576	    "implemented\n", lanai->number);
1577	/* TODO */
1578	/* The following is just a hack until we write the real
1579	 * resetter - at least ack whatever interrupt sent us
1580	 * here
1581	 */
1582	reg_write(lanai, INT_ALL, IntAck_Reg);
1583	lanai->stats.card_reset++;
1584}
1585
1586/* -------------------- SERVICE LIST UTILITIES: */
1587
1588/*
1589 * Allocate service buffer and tell card about it
1590 */
1591static int service_buffer_allocate(struct lanai_dev *lanai)
1592{
1593	lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1594	    lanai->pci);
1595	if (unlikely(lanai->service.start == NULL))
1596		return -ENOMEM;
1597	DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n",
1598	    (unsigned long) lanai->service.start,
1599	    lanai_buf_size(&lanai->service),
1600	    lanai_buf_size_cardorder(&lanai->service));
1601	/* Clear ServWrite register to be safe */
1602	reg_write(lanai, 0, ServWrite_Reg);
1603	/* ServiceStuff register contains size and address of buffer */
1604	reg_write(lanai,
1605	    SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1606	    SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1607	    ServiceStuff_Reg);
1608	return 0;
1609}
1610
1611static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1612{
1613	lanai_buf_deallocate(&lanai->service, lanai->pci);
1614}
1615
1616/* Bitfields in service list */
1617#define SERVICE_TX	(0x80000000)	/* Was from transmission */
1618#define SERVICE_TRASH	(0x40000000)	/* RXed PDU was trashed */
1619#define SERVICE_CRCERR	(0x20000000)	/* RXed PDU had CRC error */
1620#define SERVICE_CI	(0x10000000)	/* RXed PDU had CI set */
1621#define SERVICE_CLP	(0x08000000)	/* RXed PDU had CLP set */
1622#define SERVICE_STREAM	(0x04000000)	/* RX Stream mode */
1623#define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
1624#define SERVICE_GET_END(x) ((x)&0x1FFF)
1625
1626/* Handle one thing from the service list - returns true if it marked a
1627 * VCC ready for xmit
1628 */
1629static int handle_service(struct lanai_dev *lanai, u32 s)
1630{
1631	vci_t vci = SERVICE_GET_VCI(s);
1632	struct lanai_vcc *lvcc;
1633	read_lock(&vcc_sklist_lock);
1634	lvcc = lanai->vccs[vci];
1635	if (unlikely(lvcc == NULL)) {
1636		read_unlock(&vcc_sklist_lock);
1637		DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
1638		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1639		if (s & SERVICE_TX)
1640			lanai->stats.service_notx++;
1641		else
1642			lanai->stats.service_norx++;
1643		return 0;
1644	}
1645	if (s & SERVICE_TX) {			/* segmentation interrupt */
1646		if (unlikely(lvcc->tx.atmvcc == NULL)) {
1647			read_unlock(&vcc_sklist_lock);
1648			DPRINTK("(itf %d) got service entry 0x%X for non-TX "
1649			    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1650			lanai->stats.service_notx++;
1651			return 0;
1652		}
1653		__set_bit(vci, lanai->transmit_ready);
1654		lvcc->tx.endptr = SERVICE_GET_END(s);
1655		read_unlock(&vcc_sklist_lock);
1656		return 1;
1657	}
1658	if (unlikely(lvcc->rx.atmvcc == NULL)) {
1659		read_unlock(&vcc_sklist_lock);
1660		DPRINTK("(itf %d) got service entry 0x%X for non-RX "
1661		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1662		lanai->stats.service_norx++;
1663		return 0;
1664	}
1665	if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
1666		read_unlock(&vcc_sklist_lock);
1667		DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
1668		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1669		lanai->stats.service_rxnotaal5++;
1670		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1671		return 0;
1672	}
1673	if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
1674		vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
1675		read_unlock(&vcc_sklist_lock);
1676		return 0;
1677	}
1678	if (s & SERVICE_TRASH) {
1679		int bytes;
1680		read_unlock(&vcc_sklist_lock);
1681		DPRINTK("got trashed rx pdu on vci %d\n", vci);
1682		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1683		lvcc->stats.x.aal5.service_trash++;
1684		bytes = (SERVICE_GET_END(s) * 16) -
1685		    (((unsigned long) lvcc->rx.buf.ptr) -
1686		    ((unsigned long) lvcc->rx.buf.start)) + 47;
1687		if (bytes < 0)
1688			bytes += lanai_buf_size(&lvcc->rx.buf);
1689		lanai->stats.ovfl_trash += (bytes / 48);
1690		return 0;
1691	}
1692	if (s & SERVICE_STREAM) {
1693		read_unlock(&vcc_sklist_lock);
1694		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1695		lvcc->stats.x.aal5.service_stream++;
1696		printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
1697		    "PDU on VCI %d!\n", lanai->number, vci);
1698		lanai_reset(lanai);
1699		return 0;
1700	}
1701	DPRINTK("got rx crc error on vci %d\n", vci);
1702	atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1703	lvcc->stats.x.aal5.service_rxcrc++;
1704	lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
1705	cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
1706	read_unlock(&vcc_sklist_lock);
1707	return 0;
1708}
1709
1710/* Try transmitting on all VCIs that we marked ready to serve */
1711static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1712{
1713	struct lanai_vcc *lvcc = lanai->vccs[vci];
1714	if (vcc_is_backlogged(lvcc))
1715		lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1716}
1717
1718/* Run service queue -- called from interrupt context or with
1719 * interrupts otherwise disabled and with the lanai->servicelock
1720 * lock held
1721 */
1722static void run_service(struct lanai_dev *lanai)
1723{
1724	int ntx = 0;
1725	u32 wreg = reg_read(lanai, ServWrite_Reg);
1726	const u32 *end = lanai->service.start + wreg;
1727	while (lanai->service.ptr != end) {
1728		ntx += handle_service(lanai,
1729		    le32_to_cpup(lanai->service.ptr++));
1730		if (lanai->service.ptr >= lanai->service.end)
1731			lanai->service.ptr = lanai->service.start;
1732	}
1733	reg_write(lanai, wreg, ServRead_Reg);
1734	if (ntx != 0) {
1735		read_lock(&vcc_sklist_lock);
1736		vci_bitfield_iterate(lanai, lanai->transmit_ready,
1737		    iter_transmit);
1738		bitmap_zero(lanai->transmit_ready, NUM_VCI);
1739		read_unlock(&vcc_sklist_lock);
1740	}
1741}
1742
1743/* -------------------- GATHER STATISTICS: */
1744
1745static void get_statistics(struct lanai_dev *lanai)
1746{
1747	u32 statreg = reg_read(lanai, Statistics_Reg);
1748	lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1749	lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1750	lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1751	lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1752}
1753
1754/* -------------------- POLLING TIMER: */
1755
1756#ifndef DEBUG_RW
1757/* Try to undequeue 1 backlogged vcc */
1758static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1759{
1760	struct lanai_vcc *lvcc = lanai->vccs[vci];
1761	int endptr;
1762	if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
1763	    !vcc_is_backlogged(lvcc)) {
1764		__clear_bit(vci, lanai->backlog_vccs);
1765		return;
1766	}
1767	endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
1768	lvcc->tx.unqueue(lanai, lvcc, endptr);
1769}
1770#endif /* !DEBUG_RW */
1771
1772static void lanai_timed_poll(unsigned long arg)
1773{
1774	struct lanai_dev *lanai = (struct lanai_dev *) arg;
1775#ifndef DEBUG_RW
1776	unsigned long flags;
1777#ifdef USE_POWERDOWN
1778	if (lanai->conf1 & CONFIG1_POWERDOWN)
1779		return;
1780#endif /* USE_POWERDOWN */
1781	local_irq_save(flags);
1782	/* If we can grab the spinlock, check if any services need to be run */
1783	if (spin_trylock(&lanai->servicelock)) {
1784		run_service(lanai);
1785		spin_unlock(&lanai->servicelock);
1786	}
1787	/* ...and see if any backlogged VCs can make progress */
1788	/* unfortunately linux has no read_trylock() currently */
1789	read_lock(&vcc_sklist_lock);
1790	vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1791	read_unlock(&vcc_sklist_lock);
1792	local_irq_restore(flags);
1793
1794	get_statistics(lanai);
1795#endif /* !DEBUG_RW */
1796	mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1797}
1798
1799static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1800{
1801	init_timer(&lanai->timer);
1802	lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1803	lanai->timer.data = (unsigned long) lanai;
1804	lanai->timer.function = lanai_timed_poll;
1805	add_timer(&lanai->timer);
1806}
1807
1808static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1809{
1810	del_timer_sync(&lanai->timer);
1811}
1812
1813/* -------------------- INTERRUPT SERVICE: */
1814
1815static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1816{
1817	u32 ack = 0;
1818	if (reason & INT_SERVICE) {
1819		ack = INT_SERVICE;
1820		spin_lock(&lanai->servicelock);
1821		run_service(lanai);
1822		spin_unlock(&lanai->servicelock);
1823	}
1824	if (reason & (INT_AAL0_STR | INT_AAL0)) {
1825		ack |= reason & (INT_AAL0_STR | INT_AAL0);
1826		vcc_rx_aal0(lanai);
1827	}
1828	/* The rest of the interrupts are pretty rare */
1829	if (ack == reason)
1830		goto done;
1831	if (reason & INT_STATS) {
1832		reason &= ~INT_STATS;	/* No need to ack */
1833		get_statistics(lanai);
1834	}
1835	if (reason & INT_STATUS) {
1836		ack |= reason & INT_STATUS;
1837		lanai_check_status(lanai);
1838	}
1839	if (unlikely(reason & INT_DMASHUT)) {
1840		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
1841		    "shutdown, reason=0x%08X, address=0x%08X\n",
1842		    lanai->number, (unsigned int) (reason & INT_DMASHUT),
1843		    (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1844		if (reason & INT_TABORTBM) {
1845			lanai_reset(lanai);
1846			return;
1847		}
1848		ack |= (reason & INT_DMASHUT);
1849		printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
1850		    lanai->number);
1851		conf1_write(lanai);
1852		lanai->stats.dma_reenable++;
1853		pcistatus_check(lanai, 0);
1854	}
1855	if (unlikely(reason & INT_TABORTSENT)) {
1856		ack |= (reason & INT_TABORTSENT);
1857		printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
1858		    lanai->number);
1859		pcistatus_check(lanai, 0);
1860	}
1861	if (unlikely(reason & INT_SEGSHUT)) {
1862		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1863		    "segmentation shutdown, reason=0x%08X\n", lanai->number,
1864		    (unsigned int) (reason & INT_SEGSHUT));
1865		lanai_reset(lanai);
1866		return;
1867	}
1868	if (unlikely(reason & (INT_PING | INT_WAKE))) {
1869		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1870		    "unexpected interrupt 0x%08X, resetting\n",
1871		    lanai->number,
1872		    (unsigned int) (reason & (INT_PING | INT_WAKE)));
1873		lanai_reset(lanai);
1874		return;
1875	}
1876#ifdef DEBUG
1877	if (unlikely(ack != reason)) {
1878		DPRINTK("unacked ints: 0x%08X\n",
1879		    (unsigned int) (reason & ~ack));
1880		ack = reason;
1881	}
1882#endif
1883   done:
1884	if (ack != 0)
1885		reg_write(lanai, ack, IntAck_Reg);
1886}
1887
1888static irqreturn_t lanai_int(int irq, void *devid)
1889{
1890	struct lanai_dev *lanai = devid;
1891	u32 reason;
1892
1893#ifdef USE_POWERDOWN
1894	/*
1895	 * If we're powered down we shouldn't be generating any interrupts -
1896	 * so assume that this is a shared interrupt line and it's for someone
1897	 * else
1898	 */
1899	if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1900		return IRQ_NONE;
1901#endif
1902
1903	reason = intr_pending(lanai);
1904	if (reason == 0)
1905		return IRQ_NONE;	/* Must be for someone else */
1906
1907	do {
1908		if (unlikely(reason == 0xFFFFFFFF))
1909			break;		/* Maybe we've been unplugged? */
1910		lanai_int_1(lanai, reason);
1911		reason = intr_pending(lanai);
1912	} while (reason != 0);
1913
1914	return IRQ_HANDLED;
1915}
1916
1917/* TODO - it would be nice if we could use the "delayed interrupt" system
1918 *   to some advantage
1919 */
1920
1921/* -------------------- CHECK BOARD ID/REV: */
1922
1923/*
1924 * The board id and revision are stored both in the reset register and
1925 * in the PCI configuration space - the documentation says to check
1926 * each of them.  If revp!=NULL we store the revision there
1927 */
1928static int check_board_id_and_rev(const char *name, u32 val, int *revp)
1929{
1930	DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
1931		(int) RESET_GET_BOARD_ID(val),
1932		(int) RESET_GET_BOARD_REV(val));
1933	if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
1934		printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
1935		    "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
1936		return -ENODEV;
1937	}
1938	if (revp != NULL)
1939		*revp = RESET_GET_BOARD_REV(val);
1940	return 0;
1941}
1942
1943/* -------------------- PCI INITIALIZATION/SHUTDOWN: */
1944
1945static int lanai_pci_start(struct lanai_dev *lanai)
1946{
1947	struct pci_dev *pci = lanai->pci;
1948	int result;
1949
1950	if (pci_enable_device(pci) != 0) {
1951		printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
1952		    "PCI device", lanai->number);
1953		return -ENXIO;
1954	}
1955	pci_set_master(pci);
1956	if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1957		printk(KERN_WARNING DEV_LABEL
1958		    "(itf %d): No suitable DMA available.\n", lanai->number);
1959		return -EBUSY;
1960	}
1961	if (pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1962		printk(KERN_WARNING DEV_LABEL
1963		    "(itf %d): No suitable DMA available.\n", lanai->number);
1964		return -EBUSY;
1965	}
1966	result = check_board_id_and_rev("PCI", pci->subsystem_device, NULL);
1967	if (result != 0)
1968		return result;
1969	/* Set latency timer to zero as per lanai docs */
1970	result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
1971	if (result != PCIBIOS_SUCCESSFUL) {
1972		printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
1973		    "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1974		return -EINVAL;
1975	}
1976	pcistatus_check(lanai, 1);
1977	pcistatus_check(lanai, 0);
1978	return 0;
1979}
1980
1981/* -------------------- VPI/VCI ALLOCATION: */
1982
1983/*
1984 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
1985 * get a CBRZERO interrupt), and we can use it only if no one is receiving
1986 * AAL0 traffic (since they will use the same queue) - according to the
1987 * docs we shouldn't even use it for AAL0 traffic
1988 */
1989static inline int vci0_is_ok(struct lanai_dev *lanai,
1990	const struct atm_qos *qos)
1991{
1992	if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
1993		return 0;
1994	if (qos->rxtp.traffic_class != ATM_NONE) {
1995		if (lanai->naal0 != 0)
1996			return 0;
1997		lanai->conf2 |= CONFIG2_VCI0_NORMAL;
1998		conf2_write_if_powerup(lanai);
1999	}
2000	return 1;
2001}
2002
2003/* return true if vci is currently unused, or if requested qos is
2004 * compatible
2005 */
2006static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
2007	const struct atm_vcc *atmvcc)
2008{
2009	const struct atm_qos *qos = &atmvcc->qos;
2010	const struct lanai_vcc *lvcc = lanai->vccs[vci];
2011	if (vci == 0 && !vci0_is_ok(lanai, qos))
2012		return 0;
2013	if (unlikely(lvcc != NULL)) {
2014		if (qos->rxtp.traffic_class != ATM_NONE &&
2015		    lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
2016			return 0;
2017		if (qos->txtp.traffic_class != ATM_NONE &&
2018		    lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
2019			return 0;
2020		if (qos->txtp.traffic_class == ATM_CBR &&
2021		    lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2022			return 0;
2023	}
2024	if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2025	    qos->rxtp.traffic_class != ATM_NONE) {
2026		const struct lanai_vcc *vci0 = lanai->vccs[0];
2027		if (vci0 != NULL && vci0->rx.atmvcc != NULL)
2028			return 0;
2029		lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2030		conf2_write_if_powerup(lanai);
2031	}
2032	return 1;
2033}
2034
2035static int lanai_normalize_ci(struct lanai_dev *lanai,
2036	const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
2037{
2038	switch (*vpip) {
2039		case ATM_VPI_ANY:
2040			*vpip = 0;
2041			/* FALLTHROUGH */
2042		case 0:
2043			break;
2044		default:
2045			return -EADDRINUSE;
2046	}
2047	switch (*vcip) {
2048		case ATM_VCI_ANY:
2049			for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2050			    (*vcip)++)
2051				if (vci_is_ok(lanai, *vcip, atmvcc))
2052					return 0;
2053			return -EADDRINUSE;
2054		default:
2055			if (*vcip >= lanai->num_vci || *vcip < 0 ||
2056			    !vci_is_ok(lanai, *vcip, atmvcc))
2057				return -EADDRINUSE;
2058	}
2059	return 0;
2060}
2061
2062/* -------------------- MANAGE CBR: */
2063
2064/*
2065 * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2066 * Note that storing a number greater than 2046.0 will result in
2067 * incorrect shaping
2068 */
2069#define CBRICG_FRAC_BITS	(4)
2070#define CBRICG_MAX		(2046 << CBRICG_FRAC_BITS)
2071
2072/*
2073 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
2074 * where MAXPCR is (according to the docs) 25600000/(54*8),
2075 * which is equal to (3125<<9)/27.
2076 *
2077 * Solving for ICG, we get:
2078 *    ICG = MAXPCR/PCR - 1
2079 *    ICG = (3125<<9)/(27*PCR) - 1
2080 *    ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
2081 *
2082 * The end result is supposed to be a fixed-point number with FRAC_BITS
2083 * bits of a fractional part, so we keep everything in the numerator
2084 * shifted by that much as we compute
2085 *
2086 */
2087static int pcr_to_cbricg(const struct atm_qos *qos)
2088{
2089	int rounddown = 0;	/* 1 = Round PCR down, i.e. round ICG _up_ */
2090	int x, icg, pcr = atm_pcr_goal(&qos->txtp);
2091	if (pcr == 0)		/* Use maximum bandwidth */
2092		return 0;
2093	if (pcr < 0) {
2094		rounddown = 1;
2095		pcr = -pcr;
2096	}
2097	x = pcr * 27;
2098	icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
2099	if (rounddown)
2100		icg += x - 1;
2101	icg /= x;
2102	if (icg > CBRICG_MAX)
2103		icg = CBRICG_MAX;
2104	DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
2105	    pcr, rounddown ? 'Y' : 'N', icg);
2106	return icg;
2107}
2108
2109static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2110{
2111	reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2112	reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2113	lanai->conf2 |= CONFIG2_CBR_ENABLE;
2114	conf2_write(lanai);
2115}
2116
2117static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2118{
2119	lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2120	conf2_write(lanai);
2121}
2122
2123/* -------------------- OPERATIONS: */
2124
2125/* setup a newly detected device */
2126static int lanai_dev_open(struct atm_dev *atmdev)
2127{
2128	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2129	unsigned long raw_base;
2130	int result;
2131
2132	DPRINTK("In lanai_dev_open()\n");
2133	/* Basic device fields */
2134	lanai->number = atmdev->number;
2135	lanai->num_vci = NUM_VCI;
2136	bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2137	bitmap_zero(lanai->transmit_ready, NUM_VCI);
2138	lanai->naal0 = 0;
2139#ifdef USE_POWERDOWN
2140	lanai->nbound = 0;
2141#endif
2142	lanai->cbrvcc = NULL;
2143	memset(&lanai->stats, 0, sizeof lanai->stats);
2144	spin_lock_init(&lanai->endtxlock);
2145	spin_lock_init(&lanai->servicelock);
2146	atmdev->ci_range.vpi_bits = 0;
2147	atmdev->ci_range.vci_bits = 0;
2148	while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2149		atmdev->ci_range.vci_bits++;
2150	atmdev->link_rate = ATM_25_PCR;
2151
2152	/* 3.2: PCI initialization */
2153	if ((result = lanai_pci_start(lanai)) != 0)
2154		goto error;
2155	raw_base = lanai->pci->resource[0].start;
2156	lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2157	if (lanai->base == NULL) {
2158		printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
2159		goto error_pci;
2160	}
2161	/* 3.3: Reset lanai and PHY */
2162	reset_board(lanai);
2163	lanai->conf1 = reg_read(lanai, Config1_Reg);
2164	lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2165	    CONFIG1_MASK_LEDMODE);
2166	lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2167	reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2168	udelay(1000);
2169	conf1_write(lanai);
2170
2171	/*
2172	 * 3.4: Turn on endian mode for big-endian hardware
2173	 *   We don't actually want to do this - the actual bit fields
2174	 *   in the endian register are not documented anywhere.
2175	 *   Instead we do the bit-flipping ourselves on big-endian
2176	 *   hardware.
2177	 *
2178	 * 3.5: get the board ID/rev by reading the reset register
2179	 */
2180	result = check_board_id_and_rev("register",
2181	    reg_read(lanai, Reset_Reg), &lanai->board_rev);
2182	if (result != 0)
2183		goto error_unmap;
2184
2185	/* 3.6: read EEPROM */
2186	if ((result = eeprom_read(lanai)) != 0)
2187		goto error_unmap;
2188	if ((result = eeprom_validate(lanai)) != 0)
2189		goto error_unmap;
2190
2191	/* 3.7: re-reset PHY, do loopback tests, setup PHY */
2192	reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2193	udelay(1000);
2194	conf1_write(lanai);
2195	/* TODO - loopback tests */
2196	lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2197	conf1_write(lanai);
2198
2199	/* 3.8/3.9: test and initialize card SRAM */
2200	if ((result = sram_test_and_clear(lanai)) != 0)
2201		goto error_unmap;
2202
2203	/* 3.10: initialize lanai registers */
2204	lanai->conf1 |= CONFIG1_DMA_ENABLE;
2205	conf1_write(lanai);
2206	if ((result = service_buffer_allocate(lanai)) != 0)
2207		goto error_unmap;
2208	if ((result = vcc_table_allocate(lanai)) != 0)
2209		goto error_service;
2210	lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2211	    CONFIG2_HEC_DROP |	/* ??? */ CONFIG2_PTI7_MODE;
2212	conf2_write(lanai);
2213	reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2214	reg_write(lanai, 0, CBR_ICG_Reg);	/* CBR defaults to no limit */
2215	if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2216	    DEV_LABEL, lanai)) != 0) {
2217		printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
2218		goto error_vcctable;
2219	}
2220	mb();				/* Make sure that all that made it */
2221	intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2222	/* 3.11: initialize loop mode (i.e. turn looping off) */
2223	lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2224	    CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
2225	    CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
2226	conf1_write(lanai);
2227	lanai->status = reg_read(lanai, Status_Reg);
2228	/* We're now done initializing this card */
2229#ifdef USE_POWERDOWN
2230	lanai->conf1 |= CONFIG1_POWERDOWN;
2231	conf1_write(lanai);
2232#endif
2233	memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2234	lanai_timed_poll_start(lanai);
2235	printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
2236		"(%pMF)\n", lanai->number, (int) lanai->pci->revision,
2237		(unsigned long) lanai->base, lanai->pci->irq, atmdev->esi);
2238	printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
2239	    "board_rev=%d\n", lanai->number,
2240	    lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2241	    (unsigned int) lanai->serialno, lanai->board_rev);
2242	return 0;
2243
2244    error_vcctable:
2245	vcc_table_deallocate(lanai);
2246    error_service:
2247	service_buffer_deallocate(lanai);
2248    error_unmap:
2249	reset_board(lanai);
2250#ifdef USE_POWERDOWN
2251	lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2252	conf1_write(lanai);
2253#endif
2254	iounmap(lanai->base);
2255    error_pci:
2256	pci_disable_device(lanai->pci);
2257    error:
2258	return result;
2259}
2260
2261/* called when device is being shutdown, and all vcc's are gone - higher
2262 * levels will deallocate the atm device for us
2263 */
2264static void lanai_dev_close(struct atm_dev *atmdev)
2265{
2266	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2267	printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
2268	    lanai->number);
2269	lanai_timed_poll_stop(lanai);
2270#ifdef USE_POWERDOWN
2271	lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2272	conf1_write(lanai);
2273#endif
2274	intr_disable(lanai, INT_ALL);
2275	free_irq(lanai->pci->irq, lanai);
2276	reset_board(lanai);
2277#ifdef USE_POWERDOWN
2278	lanai->conf1 |= CONFIG1_POWERDOWN;
2279	conf1_write(lanai);
2280#endif
2281	pci_disable_device(lanai->pci);
2282	vcc_table_deallocate(lanai);
2283	service_buffer_deallocate(lanai);
2284	iounmap(lanai->base);
2285	kfree(lanai);
2286}
2287
2288/* close a vcc */
2289static void lanai_close(struct atm_vcc *atmvcc)
2290{
2291	struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2292	struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2293	if (lvcc == NULL)
2294		return;
2295	clear_bit(ATM_VF_READY, &atmvcc->flags);
2296	clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
2297	if (lvcc->rx.atmvcc == atmvcc) {
2298		lanai_shutdown_rx_vci(lvcc);
2299		if (atmvcc->qos.aal == ATM_AAL0) {
2300			if (--lanai->naal0 <= 0)
2301				aal0_buffer_free(lanai);
2302		} else
2303			lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2304		lvcc->rx.atmvcc = NULL;
2305	}
2306	if (lvcc->tx.atmvcc == atmvcc) {
2307		if (atmvcc == lanai->cbrvcc) {
2308			if (lvcc->vbase != NULL)
2309				lanai_cbr_shutdown(lanai);
2310			lanai->cbrvcc = NULL;
2311		}
2312		lanai_shutdown_tx_vci(lanai, lvcc);
2313		lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2314		lvcc->tx.atmvcc = NULL;
2315	}
2316	if (--lvcc->nref == 0) {
2317		host_vcc_unbind(lanai, lvcc);
2318		kfree(lvcc);
2319	}
2320	atmvcc->dev_data = NULL;
2321	clear_bit(ATM_VF_ADDR, &atmvcc->flags);
2322}
2323
2324/* open a vcc on the card to vpi/vci */
2325static int lanai_open(struct atm_vcc *atmvcc)
2326{
2327	struct lanai_dev *lanai;
2328	struct lanai_vcc *lvcc;
2329	int result = 0;
2330	int vci = atmvcc->vci;
2331	short vpi = atmvcc->vpi;
2332	/* we don't support partial open - it's not really useful anyway */
2333	if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
2334	    (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
2335		return -EINVAL;
2336	lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2337	result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2338	if (unlikely(result != 0))
2339		goto out;
2340	set_bit(ATM_VF_ADDR, &atmvcc->flags);
2341	if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
2342		return -EINVAL;
2343	DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2344	    (int) vpi, vci);
2345	lvcc = lanai->vccs[vci];
2346	if (lvcc == NULL) {
2347		lvcc = new_lanai_vcc();
2348		if (unlikely(lvcc == NULL))
2349			return -ENOMEM;
2350		atmvcc->dev_data = lvcc;
2351	}
2352	lvcc->nref++;
2353	if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
2354		APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
2355		    vci);
2356		if (atmvcc->qos.aal == ATM_AAL0) {
2357			if (lanai->naal0 == 0)
2358				result = aal0_buffer_allocate(lanai);
2359		} else
2360			result = lanai_setup_rx_vci_aal5(
2361			    lanai, lvcc, &atmvcc->qos);
2362		if (unlikely(result != 0))
2363			goto out_free;
2364		lvcc->rx.atmvcc = atmvcc;
2365		lvcc->stats.rx_nomem = 0;
2366		lvcc->stats.x.aal5.rx_badlen = 0;
2367		lvcc->stats.x.aal5.service_trash = 0;
2368		lvcc->stats.x.aal5.service_stream = 0;
2369		lvcc->stats.x.aal5.service_rxcrc = 0;
2370		if (atmvcc->qos.aal == ATM_AAL0)
2371			lanai->naal0++;
2372	}
2373	if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
2374		APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
2375		    vci);
2376		result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2377		if (unlikely(result != 0))
2378			goto out_free;
2379		lvcc->tx.atmvcc = atmvcc;
2380		if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
2381			APRINTK(lanai->cbrvcc == NULL,
2382			    "cbrvcc!=NULL, vci=%d\n", vci);
2383			lanai->cbrvcc = atmvcc;
2384		}
2385	}
2386	host_vcc_bind(lanai, lvcc, vci);
2387	/*
2388	 * Make sure everything made it to RAM before we tell the card about
2389	 * the VCC
2390	 */
2391	wmb();
2392	if (atmvcc == lvcc->rx.atmvcc)
2393		host_vcc_start_rx(lvcc);
2394	if (atmvcc == lvcc->tx.atmvcc) {
2395		host_vcc_start_tx(lvcc);
2396		if (lanai->cbrvcc == atmvcc)
2397			lanai_cbr_setup(lanai);
2398	}
2399	set_bit(ATM_VF_READY, &atmvcc->flags);
2400	return 0;
2401    out_free:
2402	lanai_close(atmvcc);
2403    out:
2404	return result;
2405}
2406
2407static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
2408{
2409	struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2410	struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2411	unsigned long flags;
2412	if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
2413	      lvcc->tx.atmvcc != atmvcc))
2414		goto einval;
2415#ifdef DEBUG
2416	if (unlikely(skb == NULL)) {
2417		DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
2418		goto einval;
2419	}
2420	if (unlikely(lanai == NULL)) {
2421		DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2422		goto einval;
2423	}
2424#endif
2425	ATM_SKB(skb)->vcc = atmvcc;
2426	switch (atmvcc->qos.aal) {
2427		case ATM_AAL5:
2428			read_lock_irqsave(&vcc_sklist_lock, flags);
2429			vcc_tx_aal5(lanai, lvcc, skb);
2430			read_unlock_irqrestore(&vcc_sklist_lock, flags);
2431			return 0;
2432		case ATM_AAL0:
2433			if (unlikely(skb->len != ATM_CELL_SIZE-1))
2434				goto einval;
2435  /* NOTE - this next line is technically invalid - we haven't unshared skb */
2436			cpu_to_be32s((u32 *) skb->data);
2437			read_lock_irqsave(&vcc_sklist_lock, flags);
2438			vcc_tx_aal0(lanai, lvcc, skb);
2439			read_unlock_irqrestore(&vcc_sklist_lock, flags);
2440			return 0;
2441	}
2442	DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
2443	    atmvcc->vci);
2444    einval:
2445	lanai_free_skb(atmvcc, skb);
2446	return -EINVAL;
2447}
2448
2449static int lanai_change_qos(struct atm_vcc *atmvcc,
2450	/*const*/ struct atm_qos *qos, int flags)
2451{
2452	return -EBUSY;		/* TODO: need to write this */
2453}
2454
2455#ifndef CONFIG_PROC_FS
2456#define lanai_proc_read NULL
2457#else
2458static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
2459{
2460	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2461	loff_t left = *pos;
2462	struct lanai_vcc *lvcc;
2463	if (left-- == 0)
2464		return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
2465		    "serial=%u, magic=0x%08X, num_vci=%d\n",
2466		    atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2467		    (unsigned int) lanai->serialno,
2468		    (unsigned int) lanai->magicno, lanai->num_vci);
2469	if (left-- == 0)
2470		return sprintf(page, "revision: board=%d, pci_if=%d\n",
2471		    lanai->board_rev, (int) lanai->pci->revision);
2472	if (left-- == 0)
2473		return sprintf(page, "EEPROM ESI: %pM\n",
2474		    &lanai->eeprom[EEPROM_MAC]);
2475	if (left-- == 0)
2476		return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
2477		    "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2478		    (lanai->status & STATUS_LOCD) ? 1 : 0,
2479		    (lanai->status & STATUS_LED) ? 1 : 0,
2480		    (lanai->status & STATUS_GPIN) ? 1 : 0);
2481	if (left-- == 0)
2482		return sprintf(page, "global buffer sizes: service=%Zu, "
2483		    "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2484		    lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2485	if (left-- == 0) {
2486		get_statistics(lanai);
2487		return sprintf(page, "cells in error: overflow=%u, "
2488		    "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
2489		    lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2490		    lanai->stats.hec_err, lanai->stats.atm_ovfl);
2491	}
2492	if (left-- == 0)
2493		return sprintf(page, "PCI errors: parity_detect=%u, "
2494		    "master_abort=%u, master_target_abort=%u,\n",
2495		    lanai->stats.pcierr_parity_detect,
2496		    lanai->stats.pcierr_serr_set,
2497		    lanai->stats.pcierr_m_target_abort);
2498	if (left-- == 0)
2499		return sprintf(page, "            slave_target_abort=%u, "
2500		    "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2501		    lanai->stats.pcierr_master_parity);
2502	if (left-- == 0)
2503		return sprintf(page, "                     no_tx=%u, "
2504		    "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2505		    lanai->stats.service_notx,
2506		    lanai->stats.service_rxnotaal5);
2507	if (left-- == 0)
2508		return sprintf(page, "resets: dma=%u, card=%u\n",
2509		    lanai->stats.dma_reenable, lanai->stats.card_reset);
2510	/* At this point, "left" should be the VCI we're looking for */
2511	read_lock(&vcc_sklist_lock);
2512	for (; ; left++) {
2513		if (left >= NUM_VCI) {
2514			left = 0;
2515			goto out;
2516		}
2517		if ((lvcc = lanai->vccs[left]) != NULL)
2518			break;
2519		(*pos)++;
2520	}
2521	/* Note that we re-use "left" here since we're done with it */
2522	left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u",  (vci_t) left,
2523	    lvcc->nref, lvcc->stats.rx_nomem);
2524	if (lvcc->rx.atmvcc != NULL) {
2525		left += sprintf(&page[left], ",\n          rx_AAL=%d",
2526		    lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
2527		if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
2528			left += sprintf(&page[left], ", rx_buf_size=%Zu, "
2529			    "rx_bad_len=%u,\n          rx_service_trash=%u, "
2530			    "rx_service_stream=%u, rx_bad_crc=%u",
2531			    lanai_buf_size(&lvcc->rx.buf),
2532			    lvcc->stats.x.aal5.rx_badlen,
2533			    lvcc->stats.x.aal5.service_trash,
2534			    lvcc->stats.x.aal5.service_stream,
2535			    lvcc->stats.x.aal5.service_rxcrc);
2536	}
2537	if (lvcc->tx.atmvcc != NULL)
2538		left += sprintf(&page[left], ",\n          tx_AAL=%d, "
2539		    "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c",
2540		    lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
2541		    lanai_buf_size(&lvcc->tx.buf),
2542		    lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2543		    vcc_is_backlogged(lvcc) ? 'Y' : 'N');
2544	page[left++] = '\n';
2545	page[left] = '\0';
2546    out:
2547	read_unlock(&vcc_sklist_lock);
2548	return left;
2549}
2550#endif /* CONFIG_PROC_FS */
2551
2552/* -------------------- HOOKS: */
2553
2554static const struct atmdev_ops ops = {
2555	.dev_close	= lanai_dev_close,
2556	.open		= lanai_open,
2557	.close		= lanai_close,
2558	.getsockopt	= NULL,
2559	.setsockopt	= NULL,
2560	.send		= lanai_send,
2561	.phy_put	= NULL,
2562	.phy_get	= NULL,
2563	.change_qos	= lanai_change_qos,
2564	.proc_read	= lanai_proc_read,
2565	.owner		= THIS_MODULE
2566};
2567
2568/* initialize one probed card */
2569static int lanai_init_one(struct pci_dev *pci,
2570			  const struct pci_device_id *ident)
2571{
2572	struct lanai_dev *lanai;
2573	struct atm_dev *atmdev;
2574	int result;
2575
2576	lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
2577	if (lanai == NULL) {
2578		printk(KERN_ERR DEV_LABEL
2579		       ": couldn't allocate dev_data structure!\n");
2580		return -ENOMEM;
2581	}
2582
2583	atmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL);
2584	if (atmdev == NULL) {
2585		printk(KERN_ERR DEV_LABEL
2586		    ": couldn't register atm device!\n");
2587		kfree(lanai);
2588		return -EBUSY;
2589	}
2590
2591	atmdev->dev_data = lanai;
2592	lanai->pci = pci;
2593	lanai->type = (enum lanai_type) ident->device;
2594
2595	result = lanai_dev_open(atmdev);
2596	if (result != 0) {
2597		DPRINTK("lanai_start() failed, err=%d\n", -result);
2598		atm_dev_deregister(atmdev);
2599		kfree(lanai);
2600	}
2601	return result;
2602}
2603
2604static struct pci_device_id lanai_pci_tbl[] = {
2605	{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
2606	{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
2607	{ 0, }	/* terminal entry */
2608};
2609MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
2610
2611static struct pci_driver lanai_driver = {
2612	.name     = DEV_LABEL,
2613	.id_table = lanai_pci_tbl,
2614	.probe    = lanai_init_one,
2615};
2616
2617module_pci_driver(lanai_driver);
2618
2619MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
2620MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
2621MODULE_LICENSE("GPL");
2622