[go: nahoru, domu]

1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef TEGRA_DC_H
11#define TEGRA_DC_H 1
12
13#define DC_CMD_GENERAL_INCR_SYNCPT		0x000
14#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL	0x001
15#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR	0x002
16#define DC_CMD_WIN_A_INCR_SYNCPT		0x008
17#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL		0x009
18#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR		0x00a
19#define DC_CMD_WIN_B_INCR_SYNCPT		0x010
20#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL		0x011
21#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR		0x012
22#define DC_CMD_WIN_C_INCR_SYNCPT		0x018
23#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL		0x019
24#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR		0x01a
25#define DC_CMD_CONT_SYNCPT_VSYNC		0x028
26#define DC_CMD_DISPLAY_COMMAND_OPTION0		0x031
27#define DC_CMD_DISPLAY_COMMAND			0x032
28#define DISP_CTRL_MODE_STOP (0 << 5)
29#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
30#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
31#define DISP_CTRL_MODE_MASK (3 << 5)
32#define DC_CMD_SIGNAL_RAISE			0x033
33#define DC_CMD_DISPLAY_POWER_CONTROL		0x036
34#define PW0_ENABLE (1 <<  0)
35#define PW1_ENABLE (1 <<  2)
36#define PW2_ENABLE (1 <<  4)
37#define PW3_ENABLE (1 <<  6)
38#define PW4_ENABLE (1 <<  8)
39#define PM0_ENABLE (1 << 16)
40#define PM1_ENABLE (1 << 18)
41
42#define DC_CMD_INT_STATUS			0x037
43#define DC_CMD_INT_MASK				0x038
44#define DC_CMD_INT_ENABLE			0x039
45#define DC_CMD_INT_TYPE				0x03a
46#define DC_CMD_INT_POLARITY			0x03b
47#define CTXSW_INT     (1 << 0)
48#define FRAME_END_INT (1 << 1)
49#define VBLANK_INT    (1 << 2)
50#define WIN_A_UF_INT  (1 << 8)
51#define WIN_B_UF_INT  (1 << 9)
52#define WIN_C_UF_INT  (1 << 10)
53#define WIN_A_OF_INT  (1 << 14)
54#define WIN_B_OF_INT  (1 << 15)
55#define WIN_C_OF_INT  (1 << 16)
56
57#define DC_CMD_SIGNAL_RAISE1			0x03c
58#define DC_CMD_SIGNAL_RAISE2			0x03d
59#define DC_CMD_SIGNAL_RAISE3			0x03e
60
61#define DC_CMD_STATE_ACCESS			0x040
62#define READ_MUX  (1 << 0)
63#define WRITE_MUX (1 << 2)
64
65#define DC_CMD_STATE_CONTROL			0x041
66#define GENERAL_ACT_REQ (1 <<  0)
67#define WIN_A_ACT_REQ   (1 <<  1)
68#define WIN_B_ACT_REQ   (1 <<  2)
69#define WIN_C_ACT_REQ   (1 <<  3)
70#define CURSOR_ACT_REQ  (1 <<  7)
71#define GENERAL_UPDATE  (1 <<  8)
72#define WIN_A_UPDATE    (1 <<  9)
73#define WIN_B_UPDATE    (1 << 10)
74#define WIN_C_UPDATE    (1 << 11)
75#define CURSOR_UPDATE   (1 << 15)
76#define NC_HOST_TRIG    (1 << 24)
77
78#define DC_CMD_DISPLAY_WINDOW_HEADER		0x042
79#define WINDOW_A_SELECT (1 << 4)
80#define WINDOW_B_SELECT (1 << 5)
81#define WINDOW_C_SELECT (1 << 6)
82
83#define DC_CMD_REG_ACT_CONTROL			0x043
84
85#define DC_COM_CRC_CONTROL			0x300
86#define DC_COM_CRC_CHECKSUM			0x301
87#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
88#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
89#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
90#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
91#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
92#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
93#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
94#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
95
96#define DC_COM_PIN_MISC_CONTROL			0x31b
97#define DC_COM_PIN_PM0_CONTROL			0x31c
98#define DC_COM_PIN_PM0_DUTY_CYCLE		0x31d
99#define DC_COM_PIN_PM1_CONTROL			0x31e
100#define DC_COM_PIN_PM1_DUTY_CYCLE		0x31f
101
102#define DC_COM_SPI_CONTROL			0x320
103#define DC_COM_SPI_START_BYTE			0x321
104#define DC_COM_HSPI_WRITE_DATA_AB		0x322
105#define DC_COM_HSPI_WRITE_DATA_CD		0x323
106#define DC_COM_HSPI_CS_DC			0x324
107#define DC_COM_SCRATCH_REGISTER_A		0x325
108#define DC_COM_SCRATCH_REGISTER_B		0x326
109#define DC_COM_GPIO_CTRL			0x327
110#define DC_COM_GPIO_DEBOUNCE_COUNTER		0x328
111#define DC_COM_CRC_CHECKSUM_LATCHED		0x329
112
113#define DC_DISP_DISP_SIGNAL_OPTIONS0		0x400
114#define H_PULSE_0_ENABLE (1 <<  8)
115#define H_PULSE_1_ENABLE (1 << 10)
116#define H_PULSE_2_ENABLE (1 << 12)
117
118#define DC_DISP_DISP_SIGNAL_OPTIONS1		0x401
119
120#define DC_DISP_DISP_WIN_OPTIONS		0x402
121#define HDMI_ENABLE	(1 << 30)
122#define DSI_ENABLE	(1 << 29)
123#define SOR_ENABLE	(1 << 25)
124#define CURSOR_ENABLE	(1 << 16)
125
126#define DC_DISP_DISP_MEM_HIGH_PRIORITY		0x403
127#define CURSOR_THRESHOLD(x)   (((x) & 0x03) << 24)
128#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
129#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) <<  8)
130#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) <<  0)
131
132#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER	0x404
133#define CURSOR_DELAY(x)   (((x) & 0x3f) << 24)
134#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
135#define WINDOW_B_DELAY(x) (((x) & 0x3f) <<  8)
136#define WINDOW_C_DELAY(x) (((x) & 0x3f) <<  0)
137
138#define DC_DISP_DISP_TIMING_OPTIONS		0x405
139#define VSYNC_H_POSITION(x) ((x) & 0xfff)
140
141#define DC_DISP_REF_TO_SYNC			0x406
142#define DC_DISP_SYNC_WIDTH			0x407
143#define DC_DISP_BACK_PORCH			0x408
144#define DC_DISP_ACTIVE				0x409
145#define DC_DISP_FRONT_PORCH			0x40a
146#define DC_DISP_H_PULSE0_CONTROL		0x40b
147#define DC_DISP_H_PULSE0_POSITION_A		0x40c
148#define DC_DISP_H_PULSE0_POSITION_B		0x40d
149#define DC_DISP_H_PULSE0_POSITION_C		0x40e
150#define DC_DISP_H_PULSE0_POSITION_D		0x40f
151#define DC_DISP_H_PULSE1_CONTROL		0x410
152#define DC_DISP_H_PULSE1_POSITION_A		0x411
153#define DC_DISP_H_PULSE1_POSITION_B		0x412
154#define DC_DISP_H_PULSE1_POSITION_C		0x413
155#define DC_DISP_H_PULSE1_POSITION_D		0x414
156#define DC_DISP_H_PULSE2_CONTROL		0x415
157#define DC_DISP_H_PULSE2_POSITION_A		0x416
158#define DC_DISP_H_PULSE2_POSITION_B		0x417
159#define DC_DISP_H_PULSE2_POSITION_C		0x418
160#define DC_DISP_H_PULSE2_POSITION_D		0x419
161#define DC_DISP_V_PULSE0_CONTROL		0x41a
162#define DC_DISP_V_PULSE0_POSITION_A		0x41b
163#define DC_DISP_V_PULSE0_POSITION_B		0x41c
164#define DC_DISP_V_PULSE0_POSITION_C		0x41d
165#define DC_DISP_V_PULSE1_CONTROL		0x41e
166#define DC_DISP_V_PULSE1_POSITION_A		0x41f
167#define DC_DISP_V_PULSE1_POSITION_B		0x420
168#define DC_DISP_V_PULSE1_POSITION_C		0x421
169#define DC_DISP_V_PULSE2_CONTROL		0x422
170#define DC_DISP_V_PULSE2_POSITION_A		0x423
171#define DC_DISP_V_PULSE3_CONTROL		0x424
172#define DC_DISP_V_PULSE3_POSITION_A		0x425
173#define DC_DISP_M0_CONTROL			0x426
174#define DC_DISP_M1_CONTROL			0x427
175#define DC_DISP_DI_CONTROL			0x428
176#define DC_DISP_PP_CONTROL			0x429
177#define DC_DISP_PP_SELECT_A			0x42a
178#define DC_DISP_PP_SELECT_B			0x42b
179#define DC_DISP_PP_SELECT_C			0x42c
180#define DC_DISP_PP_SELECT_D			0x42d
181
182#define PULSE_MODE_NORMAL    (0 << 3)
183#define PULSE_MODE_ONE_CLOCK (1 << 3)
184#define PULSE_POLARITY_HIGH  (0 << 4)
185#define PULSE_POLARITY_LOW   (1 << 4)
186#define PULSE_QUAL_ALWAYS    (0 << 6)
187#define PULSE_QUAL_VACTIVE   (2 << 6)
188#define PULSE_QUAL_VACTIVE1  (3 << 6)
189#define PULSE_LAST_START_A   (0 << 8)
190#define PULSE_LAST_END_A     (1 << 8)
191#define PULSE_LAST_START_B   (2 << 8)
192#define PULSE_LAST_END_B     (3 << 8)
193#define PULSE_LAST_START_C   (4 << 8)
194#define PULSE_LAST_END_C     (5 << 8)
195#define PULSE_LAST_START_D   (6 << 8)
196#define PULSE_LAST_END_D     (7 << 8)
197
198#define PULSE_START(x) (((x) & 0xfff) <<  0)
199#define PULSE_END(x)   (((x) & 0xfff) << 16)
200
201#define DC_DISP_DISP_CLOCK_CONTROL		0x42e
202#define PIXEL_CLK_DIVIDER_PCD1  (0 << 8)
203#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
204#define PIXEL_CLK_DIVIDER_PCD2  (2 << 8)
205#define PIXEL_CLK_DIVIDER_PCD3  (3 << 8)
206#define PIXEL_CLK_DIVIDER_PCD4  (4 << 8)
207#define PIXEL_CLK_DIVIDER_PCD6  (5 << 8)
208#define PIXEL_CLK_DIVIDER_PCD8  (6 << 8)
209#define PIXEL_CLK_DIVIDER_PCD9  (7 << 8)
210#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
211#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
212#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
213#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
214#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
215#define SHIFT_CLK_DIVIDER(x)    ((x) & 0xff)
216
217#define DC_DISP_DISP_INTERFACE_CONTROL		0x42f
218#define DISP_DATA_FORMAT_DF1P1C    (0 << 0)
219#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
220#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
221#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
222#define DISP_DATA_FORMAT_DF2S      (4 << 0)
223#define DISP_DATA_FORMAT_DF3S      (5 << 0)
224#define DISP_DATA_FORMAT_DFSPI     (6 << 0)
225#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
226#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
227#define DISP_ALIGNMENT_MSB         (0 << 8)
228#define DISP_ALIGNMENT_LSB         (1 << 8)
229#define DISP_ORDER_RED_BLUE        (0 << 9)
230#define DISP_ORDER_BLUE_RED        (1 << 9)
231
232#define DC_DISP_DISP_COLOR_CONTROL		0x430
233#define BASE_COLOR_SIZE666     (0 << 0)
234#define BASE_COLOR_SIZE111     (1 << 0)
235#define BASE_COLOR_SIZE222     (2 << 0)
236#define BASE_COLOR_SIZE333     (3 << 0)
237#define BASE_COLOR_SIZE444     (4 << 0)
238#define BASE_COLOR_SIZE555     (5 << 0)
239#define BASE_COLOR_SIZE565     (6 << 0)
240#define BASE_COLOR_SIZE332     (7 << 0)
241#define BASE_COLOR_SIZE888     (8 << 0)
242#define DITHER_CONTROL_DISABLE (0 << 8)
243#define DITHER_CONTROL_ORDERED (2 << 8)
244#define DITHER_CONTROL_ERRDIFF (3 << 8)
245
246#define DC_DISP_SHIFT_CLOCK_OPTIONS		0x431
247#define  SC1_H_QUALIFIER_NONE	(1 << 16)
248#define  SC0_H_QUALIFIER_NONE	(1 <<  0)
249
250#define DC_DISP_DATA_ENABLE_OPTIONS		0x432
251#define DE_SELECT_ACTIVE_BLANK  (0 << 0)
252#define DE_SELECT_ACTIVE        (1 << 0)
253#define DE_SELECT_ACTIVE_IS     (2 << 0)
254#define DE_CONTROL_ONECLK       (0 << 2)
255#define DE_CONTROL_NORMAL       (1 << 2)
256#define DE_CONTROL_EARLY_EXT    (2 << 2)
257#define DE_CONTROL_EARLY        (3 << 2)
258#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
259
260#define DC_DISP_SERIAL_INTERFACE_OPTIONS	0x433
261#define DC_DISP_LCD_SPI_OPTIONS			0x434
262#define DC_DISP_BORDER_COLOR			0x435
263#define DC_DISP_COLOR_KEY0_LOWER		0x436
264#define DC_DISP_COLOR_KEY0_UPPER		0x437
265#define DC_DISP_COLOR_KEY1_LOWER		0x438
266#define DC_DISP_COLOR_KEY1_UPPER		0x439
267
268#define DC_DISP_CURSOR_FOREGROUND		0x43c
269#define DC_DISP_CURSOR_BACKGROUND		0x43d
270
271#define DC_DISP_CURSOR_START_ADDR		0x43e
272#define CURSOR_CLIP_DISPLAY	(0 << 28)
273#define CURSOR_CLIP_WIN_A	(1 << 28)
274#define CURSOR_CLIP_WIN_B	(2 << 28)
275#define CURSOR_CLIP_WIN_C	(3 << 28)
276#define CURSOR_SIZE_32x32	(0 << 24)
277#define CURSOR_SIZE_64x64	(1 << 24)
278#define CURSOR_SIZE_128x128	(2 << 24)
279#define CURSOR_SIZE_256x256	(3 << 24)
280#define DC_DISP_CURSOR_START_ADDR_NS		0x43f
281
282#define DC_DISP_CURSOR_POSITION			0x440
283#define DC_DISP_CURSOR_POSITION_NS		0x441
284
285#define DC_DISP_INIT_SEQ_CONTROL		0x442
286#define DC_DISP_SPI_INIT_SEQ_DATA_A		0x443
287#define DC_DISP_SPI_INIT_SEQ_DATA_B		0x444
288#define DC_DISP_SPI_INIT_SEQ_DATA_C		0x445
289#define DC_DISP_SPI_INIT_SEQ_DATA_D		0x446
290
291#define DC_DISP_DC_MCCIF_FIFOCTRL		0x480
292#define DC_DISP_MCCIF_DISPLAY0A_HYST		0x481
293#define DC_DISP_MCCIF_DISPLAY0B_HYST		0x482
294#define DC_DISP_MCCIF_DISPLAY1A_HYST		0x483
295#define DC_DISP_MCCIF_DISPLAY1B_HYST		0x484
296
297#define DC_DISP_DAC_CRT_CTRL			0x4c0
298#define DC_DISP_DISP_MISC_CONTROL		0x4c1
299#define DC_DISP_SD_CONTROL			0x4c2
300#define DC_DISP_SD_CSC_COEFF			0x4c3
301#define DC_DISP_SD_LUT(x)			(0x4c4 + (x))
302#define DC_DISP_SD_FLICKER_CONTROL		0x4cd
303#define DC_DISP_DC_PIXEL_COUNT			0x4ce
304#define DC_DISP_SD_HISTOGRAM(x)			(0x4cf + (x))
305#define DC_DISP_SD_BL_PARAMETERS		0x4d7
306#define DC_DISP_SD_BL_TF(x)			(0x4d8 + (x))
307#define DC_DISP_SD_BL_CONTROL			0x4dc
308#define DC_DISP_SD_HW_K_VALUES			0x4dd
309#define DC_DISP_SD_MAN_K_VALUES			0x4de
310
311#define DC_DISP_INTERLACE_CONTROL		0x4e5
312#define  INTERLACE_STATUS (1 << 2)
313#define  INTERLACE_START  (1 << 1)
314#define  INTERLACE_ENABLE (1 << 0)
315
316#define DC_DISP_CURSOR_START_ADDR_HI		0x4ec
317#define DC_DISP_BLEND_CURSOR_CONTROL		0x4f1
318#define CURSOR_MODE_LEGACY			(0 << 24)
319#define CURSOR_MODE_NORMAL			(1 << 24)
320#define CURSOR_DST_BLEND_ZERO			(0 << 16)
321#define CURSOR_DST_BLEND_K1			(1 << 16)
322#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC	(2 << 16)
323#define CURSOR_DST_BLEND_MASK			(3 << 16)
324#define CURSOR_SRC_BLEND_K1			(0 << 8)
325#define CURSOR_SRC_BLEND_K1_TIMES_SRC		(1 << 8)
326#define CURSOR_SRC_BLEND_MASK			(3 << 8)
327#define CURSOR_ALPHA				0xff
328
329#define DC_WIN_CSC_YOF				0x611
330#define DC_WIN_CSC_KYRGB			0x612
331#define DC_WIN_CSC_KUR				0x613
332#define DC_WIN_CSC_KVR				0x614
333#define DC_WIN_CSC_KUG				0x615
334#define DC_WIN_CSC_KVG				0x616
335#define DC_WIN_CSC_KUB				0x617
336#define DC_WIN_CSC_KVB				0x618
337
338#define DC_WIN_WIN_OPTIONS			0x700
339#define H_DIRECTION  (1 <<  0)
340#define V_DIRECTION  (1 <<  2)
341#define COLOR_EXPAND (1 <<  6)
342#define CSC_ENABLE   (1 << 18)
343#define WIN_ENABLE   (1 << 30)
344
345#define DC_WIN_BYTE_SWAP			0x701
346#define BYTE_SWAP_NOSWAP  (0 << 0)
347#define BYTE_SWAP_SWAP2   (1 << 0)
348#define BYTE_SWAP_SWAP4   (2 << 0)
349#define BYTE_SWAP_SWAP4HW (3 << 0)
350
351#define DC_WIN_BUFFER_CONTROL			0x702
352#define BUFFER_CONTROL_HOST  (0 << 0)
353#define BUFFER_CONTROL_VI    (1 << 0)
354#define BUFFER_CONTROL_EPP   (2 << 0)
355#define BUFFER_CONTROL_MPEGE (3 << 0)
356#define BUFFER_CONTROL_SB2D  (4 << 0)
357
358#define DC_WIN_COLOR_DEPTH			0x703
359#define WIN_COLOR_DEPTH_P1              0
360#define WIN_COLOR_DEPTH_P2              1
361#define WIN_COLOR_DEPTH_P4              2
362#define WIN_COLOR_DEPTH_P8              3
363#define WIN_COLOR_DEPTH_B4G4R4A4        4
364#define WIN_COLOR_DEPTH_B5G5R5A         5
365#define WIN_COLOR_DEPTH_B5G6R5          6
366#define WIN_COLOR_DEPTH_AB5G5R5         7
367#define WIN_COLOR_DEPTH_B8G8R8A8       12
368#define WIN_COLOR_DEPTH_R8G8B8A8       13
369#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
370#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
371#define WIN_COLOR_DEPTH_YCbCr422       16
372#define WIN_COLOR_DEPTH_YUV422         17
373#define WIN_COLOR_DEPTH_YCbCr420P      18
374#define WIN_COLOR_DEPTH_YUV420P        19
375#define WIN_COLOR_DEPTH_YCbCr422P      20
376#define WIN_COLOR_DEPTH_YUV422P        21
377#define WIN_COLOR_DEPTH_YCbCr422R      22
378#define WIN_COLOR_DEPTH_YUV422R        23
379#define WIN_COLOR_DEPTH_YCbCr422RA     24
380#define WIN_COLOR_DEPTH_YUV422RA       25
381
382#define DC_WIN_POSITION				0x704
383#define H_POSITION(x) (((x) & 0x1fff) <<  0)
384#define V_POSITION(x) (((x) & 0x1fff) << 16)
385
386#define DC_WIN_SIZE				0x705
387#define H_SIZE(x) (((x) & 0x1fff) <<  0)
388#define V_SIZE(x) (((x) & 0x1fff) << 16)
389
390#define DC_WIN_PRESCALED_SIZE			0x706
391#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) <<  0)
392#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
393
394#define DC_WIN_H_INITIAL_DDA			0x707
395#define DC_WIN_V_INITIAL_DDA			0x708
396#define DC_WIN_DDA_INC				0x709
397#define H_DDA_INC(x) (((x) & 0xffff) <<  0)
398#define V_DDA_INC(x) (((x) & 0xffff) << 16)
399
400#define DC_WIN_LINE_STRIDE			0x70a
401#define DC_WIN_BUF_STRIDE			0x70b
402#define DC_WIN_UV_BUF_STRIDE			0x70c
403#define DC_WIN_BUFFER_ADDR_MODE			0x70d
404#define DC_WIN_BUFFER_ADDR_MODE_LINEAR		(0 <<  0)
405#define DC_WIN_BUFFER_ADDR_MODE_TILE		(1 <<  0)
406#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV	(0 << 16)
407#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV		(1 << 16)
408#define DC_WIN_DV_CONTROL			0x70e
409
410#define DC_WIN_BLEND_NOKEY			0x70f
411#define DC_WIN_BLEND_1WIN			0x710
412#define DC_WIN_BLEND_2WIN_X			0x711
413#define DC_WIN_BLEND_2WIN_Y			0x712
414#define DC_WIN_BLEND_3WIN_XY			0x713
415
416#define DC_WIN_HP_FETCH_CONTROL			0x714
417
418#define DC_WINBUF_START_ADDR			0x800
419#define DC_WINBUF_START_ADDR_NS			0x801
420#define DC_WINBUF_START_ADDR_U			0x802
421#define DC_WINBUF_START_ADDR_U_NS		0x803
422#define DC_WINBUF_START_ADDR_V			0x804
423#define DC_WINBUF_START_ADDR_V_NS		0x805
424
425#define DC_WINBUF_ADDR_H_OFFSET			0x806
426#define DC_WINBUF_ADDR_H_OFFSET_NS		0x807
427#define DC_WINBUF_ADDR_V_OFFSET			0x808
428#define DC_WINBUF_ADDR_V_OFFSET_NS		0x809
429
430#define DC_WINBUF_UFLOW_STATUS			0x80a
431#define DC_WINBUF_SURFACE_KIND			0x80b
432#define DC_WINBUF_SURFACE_KIND_PITCH	(0 << 0)
433#define DC_WINBUF_SURFACE_KIND_TILED	(1 << 0)
434#define DC_WINBUF_SURFACE_KIND_BLOCK	(2 << 0)
435#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
436
437#define DC_WINBUF_AD_UFLOW_STATUS		0xbca
438#define DC_WINBUF_BD_UFLOW_STATUS		0xdca
439#define DC_WINBUF_CD_UFLOW_STATUS		0xfca
440
441/* synchronization points */
442#define SYNCPT_VBLANK0 26
443#define SYNCPT_VBLANK1 27
444
445#endif /* TEGRA_DC_H */
446