drm_edid.c revision 3cf70dafd7bbbc91df0a9ecb081d46f9f3d867f6
1/* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30#include <linux/kernel.h> 31#include <linux/slab.h> 32#include <linux/hdmi.h> 33#include <linux/i2c.h> 34#include <linux/module.h> 35#include <drm/drmP.h> 36#include <drm/drm_edid.h> 37 38#define version_greater(edid, maj, min) \ 39 (((edid)->version > (maj)) || \ 40 ((edid)->version == (maj) && (edid)->revision > (min))) 41 42#define EDID_EST_TIMINGS 16 43#define EDID_STD_TIMINGS 8 44#define EDID_DETAILED_TIMINGS 4 45 46/* 47 * EDID blocks out in the wild have a variety of bugs, try to collect 48 * them here (note that userspace may work around broken monitors first, 49 * but fixes should make their way here so that the kernel "just works" 50 * on as many displays as possible). 51 */ 52 53/* First detailed mode wrong, use largest 60Hz mode */ 54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 55/* Reported 135MHz pixel clock is too high, needs adjustment */ 56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 57/* Prefer the largest mode at 75 Hz */ 58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 59/* Detail timing is in cm not mm */ 60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 61/* Detailed timing descriptors have bogus size values, so just take the 62 * maximum size and use that. 63 */ 64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 65/* Monitor forgot to set the first detailed is preferred bit. */ 66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 67/* use +hsync +vsync for detailed mode */ 68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 69/* Force reduced-blanking timings for detailed modes */ 70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 71 72struct detailed_mode_closure { 73 struct drm_connector *connector; 74 struct edid *edid; 75 bool preferred; 76 u32 quirks; 77 int modes; 78}; 79 80#define LEVEL_DMT 0 81#define LEVEL_GTF 1 82#define LEVEL_GTF2 2 83#define LEVEL_CVT 3 84 85static struct edid_quirk { 86 char vendor[4]; 87 int product_id; 88 u32 quirks; 89} edid_quirk_list[] = { 90 /* Acer AL1706 */ 91 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 92 /* Acer F51 */ 93 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Unknown Acer */ 95 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 96 97 /* Belinea 10 15 55 */ 98 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 99 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 100 101 /* Envision Peripherals, Inc. EN-7100e */ 102 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 103 /* Envision EN2028 */ 104 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Funai Electronics PM36B */ 107 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 108 EDID_QUIRK_DETAILED_IN_CM }, 109 110 /* LG Philips LCD LP154W01-A5 */ 111 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 112 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 113 114 /* Philips 107p5 CRT */ 115 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 116 117 /* Proview AY765C */ 118 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 119 120 /* Samsung SyncMaster 205BW. Note: irony */ 121 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 122 /* Samsung SyncMaster 22[5-6]BW */ 123 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 124 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 125 126 /* ViewSonic VA2026w */ 127 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 128 129 /* Medion MD 30217 PG */ 130 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 131}; 132 133/* 134 * Autogenerated from the DMT spec. 135 * This table is copied from xfree86/modes/xf86EdidModes.c. 136 */ 137static const struct drm_display_mode drm_dmt_modes[] = { 138 /* 640x350@85Hz */ 139 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 140 736, 832, 0, 350, 382, 385, 445, 0, 141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 142 /* 640x400@85Hz */ 143 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 144 736, 832, 0, 400, 401, 404, 445, 0, 145 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 146 /* 720x400@85Hz */ 147 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 148 828, 936, 0, 400, 401, 404, 446, 0, 149 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 150 /* 640x480@60Hz */ 151 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 152 752, 800, 0, 480, 489, 492, 525, 0, 153 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 154 /* 640x480@72Hz */ 155 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 156 704, 832, 0, 480, 489, 492, 520, 0, 157 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 158 /* 640x480@75Hz */ 159 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 160 720, 840, 0, 480, 481, 484, 500, 0, 161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 162 /* 640x480@85Hz */ 163 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 164 752, 832, 0, 480, 481, 484, 509, 0, 165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 166 /* 800x600@56Hz */ 167 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 168 896, 1024, 0, 600, 601, 603, 625, 0, 169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 170 /* 800x600@60Hz */ 171 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 172 968, 1056, 0, 600, 601, 605, 628, 0, 173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 174 /* 800x600@72Hz */ 175 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 176 976, 1040, 0, 600, 637, 643, 666, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 178 /* 800x600@75Hz */ 179 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 180 896, 1056, 0, 600, 601, 604, 625, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 182 /* 800x600@85Hz */ 183 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 184 896, 1048, 0, 600, 601, 604, 631, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 186 /* 800x600@120Hz RB */ 187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 188 880, 960, 0, 600, 603, 607, 636, 0, 189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 190 /* 848x480@60Hz */ 191 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 192 976, 1088, 0, 480, 486, 494, 517, 0, 193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 194 /* 1024x768@43Hz, interlace */ 195 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 196 1208, 1264, 0, 768, 768, 772, 817, 0, 197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 198 DRM_MODE_FLAG_INTERLACE) }, 199 /* 1024x768@60Hz */ 200 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 201 1184, 1344, 0, 768, 771, 777, 806, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 203 /* 1024x768@70Hz */ 204 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 205 1184, 1328, 0, 768, 771, 777, 806, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 207 /* 1024x768@75Hz */ 208 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 209 1136, 1312, 0, 768, 769, 772, 800, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 1024x768@85Hz */ 212 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 213 1168, 1376, 0, 768, 769, 772, 808, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 1024x768@120Hz RB */ 216 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 217 1104, 1184, 0, 768, 771, 775, 813, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 1152x864@75Hz */ 220 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 221 1344, 1600, 0, 864, 865, 868, 900, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 1280x768@60Hz RB */ 224 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 225 1360, 1440, 0, 768, 771, 778, 790, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 1280x768@60Hz */ 228 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 229 1472, 1664, 0, 768, 771, 778, 798, 0, 230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 231 /* 1280x768@75Hz */ 232 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 233 1488, 1696, 0, 768, 771, 778, 805, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 235 /* 1280x768@85Hz */ 236 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 237 1496, 1712, 0, 768, 771, 778, 809, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 239 /* 1280x768@120Hz RB */ 240 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 241 1360, 1440, 0, 768, 771, 778, 813, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 243 /* 1280x800@60Hz RB */ 244 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 245 1360, 1440, 0, 800, 803, 809, 823, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 247 /* 1280x800@60Hz */ 248 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 249 1480, 1680, 0, 800, 803, 809, 831, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 1280x800@75Hz */ 252 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 253 1488, 1696, 0, 800, 803, 809, 838, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 255 /* 1280x800@85Hz */ 256 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 257 1496, 1712, 0, 800, 803, 809, 843, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 259 /* 1280x800@120Hz RB */ 260 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 261 1360, 1440, 0, 800, 803, 809, 847, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 263 /* 1280x960@60Hz */ 264 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 265 1488, 1800, 0, 960, 961, 964, 1000, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 1280x960@85Hz */ 268 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 269 1504, 1728, 0, 960, 961, 964, 1011, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 1280x960@120Hz RB */ 272 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 273 1360, 1440, 0, 960, 963, 967, 1017, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 275 /* 1280x1024@60Hz */ 276 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 277 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 1280x1024@75Hz */ 280 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 281 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 1280x1024@85Hz */ 284 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 285 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 287 /* 1280x1024@120Hz RB */ 288 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 289 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 291 /* 1360x768@60Hz */ 292 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 293 1536, 1792, 0, 768, 771, 777, 795, 0, 294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 1360x768@120Hz RB */ 296 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 297 1440, 1520, 0, 768, 771, 776, 813, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 299 /* 1400x1050@60Hz RB */ 300 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 301 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 303 /* 1400x1050@60Hz */ 304 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 305 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 307 /* 1400x1050@75Hz */ 308 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 309 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 1400x1050@85Hz */ 312 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 313 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 315 /* 1400x1050@120Hz RB */ 316 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 317 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 319 /* 1440x900@60Hz RB */ 320 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 321 1520, 1600, 0, 900, 903, 909, 926, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 323 /* 1440x900@60Hz */ 324 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 325 1672, 1904, 0, 900, 903, 909, 934, 0, 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 1440x900@75Hz */ 328 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 329 1688, 1936, 0, 900, 903, 909, 942, 0, 330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 1440x900@85Hz */ 332 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 333 1696, 1952, 0, 900, 903, 909, 948, 0, 334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 335 /* 1440x900@120Hz RB */ 336 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 337 1520, 1600, 0, 900, 903, 909, 953, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 339 /* 1600x1200@60Hz */ 340 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 341 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 1600x1200@65Hz */ 344 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 345 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 1600x1200@70Hz */ 348 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 349 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 351 /* 1600x1200@75Hz */ 352 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 353 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 1600x1200@85Hz */ 356 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 357 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 1600x1200@120Hz RB */ 360 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 361 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 363 /* 1680x1050@60Hz RB */ 364 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 365 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 367 /* 1680x1050@60Hz */ 368 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 369 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 1680x1050@75Hz */ 372 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 373 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 1680x1050@85Hz */ 376 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 377 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 1680x1050@120Hz RB */ 380 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 381 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 383 /* 1792x1344@60Hz */ 384 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 385 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 1792x1344@75Hz */ 388 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 389 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 1792x1344@120Hz RB */ 392 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 393 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 395 /* 1856x1392@60Hz */ 396 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 397 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 1856x1392@75Hz */ 400 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 401 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 403 /* 1856x1392@120Hz RB */ 404 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 405 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 407 /* 1920x1200@60Hz RB */ 408 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 409 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 411 /* 1920x1200@60Hz */ 412 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 413 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 1920x1200@75Hz */ 416 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 417 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 419 /* 1920x1200@85Hz */ 420 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 421 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 1920x1200@120Hz RB */ 424 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 425 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 427 /* 1920x1440@60Hz */ 428 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 429 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 1920x1440@75Hz */ 432 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 433 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 1920x1440@120Hz RB */ 436 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 437 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 2560x1600@60Hz RB */ 440 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 441 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 443 /* 2560x1600@60Hz */ 444 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 445 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 2560x1600@75HZ */ 448 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 449 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 451 /* 2560x1600@85HZ */ 452 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 453 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 2560x1600@120Hz RB */ 456 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 457 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 459}; 460 461/* 462 * These more or less come from the DMT spec. The 720x400 modes are 463 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 464 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 465 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 466 * mode. 467 * 468 * The DMT modes have been fact-checked; the rest are mild guesses. 469 */ 470static const struct drm_display_mode edid_est_modes[] = { 471 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 472 968, 1056, 0, 600, 601, 605, 628, 0, 473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 474 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 475 896, 1024, 0, 600, 601, 603, 625, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 477 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 478 720, 840, 0, 480, 481, 484, 500, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 480 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 481 704, 832, 0, 480, 489, 491, 520, 0, 482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 483 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 484 768, 864, 0, 480, 483, 486, 525, 0, 485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 486 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 487 752, 800, 0, 480, 490, 492, 525, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 489 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 490 846, 900, 0, 400, 421, 423, 449, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 492 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 493 846, 900, 0, 400, 412, 414, 449, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 495 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 496 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 498 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 499 1136, 1312, 0, 768, 769, 772, 800, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 501 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 502 1184, 1328, 0, 768, 771, 777, 806, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 504 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 505 1184, 1344, 0, 768, 771, 777, 806, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 507 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 508 1208, 1264, 0, 768, 768, 776, 817, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 510 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 511 928, 1152, 0, 624, 625, 628, 667, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 513 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 514 896, 1056, 0, 600, 601, 604, 625, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 516 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 517 976, 1040, 0, 600, 637, 643, 666, 0, 518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 519 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 520 1344, 1600, 0, 864, 865, 868, 900, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 522}; 523 524struct minimode { 525 short w; 526 short h; 527 short r; 528 short rb; 529}; 530 531static const struct minimode est3_modes[] = { 532 /* byte 6 */ 533 { 640, 350, 85, 0 }, 534 { 640, 400, 85, 0 }, 535 { 720, 400, 85, 0 }, 536 { 640, 480, 85, 0 }, 537 { 848, 480, 60, 0 }, 538 { 800, 600, 85, 0 }, 539 { 1024, 768, 85, 0 }, 540 { 1152, 864, 75, 0 }, 541 /* byte 7 */ 542 { 1280, 768, 60, 1 }, 543 { 1280, 768, 60, 0 }, 544 { 1280, 768, 75, 0 }, 545 { 1280, 768, 85, 0 }, 546 { 1280, 960, 60, 0 }, 547 { 1280, 960, 85, 0 }, 548 { 1280, 1024, 60, 0 }, 549 { 1280, 1024, 85, 0 }, 550 /* byte 8 */ 551 { 1360, 768, 60, 0 }, 552 { 1440, 900, 60, 1 }, 553 { 1440, 900, 60, 0 }, 554 { 1440, 900, 75, 0 }, 555 { 1440, 900, 85, 0 }, 556 { 1400, 1050, 60, 1 }, 557 { 1400, 1050, 60, 0 }, 558 { 1400, 1050, 75, 0 }, 559 /* byte 9 */ 560 { 1400, 1050, 85, 0 }, 561 { 1680, 1050, 60, 1 }, 562 { 1680, 1050, 60, 0 }, 563 { 1680, 1050, 75, 0 }, 564 { 1680, 1050, 85, 0 }, 565 { 1600, 1200, 60, 0 }, 566 { 1600, 1200, 65, 0 }, 567 { 1600, 1200, 70, 0 }, 568 /* byte 10 */ 569 { 1600, 1200, 75, 0 }, 570 { 1600, 1200, 85, 0 }, 571 { 1792, 1344, 60, 0 }, 572 { 1792, 1344, 75, 0 }, 573 { 1856, 1392, 60, 0 }, 574 { 1856, 1392, 75, 0 }, 575 { 1920, 1200, 60, 1 }, 576 { 1920, 1200, 60, 0 }, 577 /* byte 11 */ 578 { 1920, 1200, 75, 0 }, 579 { 1920, 1200, 85, 0 }, 580 { 1920, 1440, 60, 0 }, 581 { 1920, 1440, 75, 0 }, 582}; 583 584static const struct minimode extra_modes[] = { 585 { 1024, 576, 60, 0 }, 586 { 1366, 768, 60, 0 }, 587 { 1600, 900, 60, 0 }, 588 { 1680, 945, 60, 0 }, 589 { 1920, 1080, 60, 0 }, 590 { 2048, 1152, 60, 0 }, 591 { 2048, 1536, 60, 0 }, 592}; 593 594/* 595 * Probably taken from CEA-861 spec. 596 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 597 */ 598static const struct drm_display_mode edid_cea_modes[] = { 599 /* 1 - 640x480@60Hz */ 600 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 601 752, 800, 0, 480, 490, 492, 525, 0, 602 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 603 .vrefresh = 60, }, 604 /* 2 - 720x480@60Hz */ 605 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 606 798, 858, 0, 480, 489, 495, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 608 .vrefresh = 60, }, 609 /* 3 - 720x480@60Hz */ 610 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 611 798, 858, 0, 480, 489, 495, 525, 0, 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 613 .vrefresh = 60, }, 614 /* 4 - 1280x720@60Hz */ 615 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 616 1430, 1650, 0, 720, 725, 730, 750, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 60, }, 619 /* 5 - 1920x1080i@60Hz */ 620 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 621 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 623 DRM_MODE_FLAG_INTERLACE), 624 .vrefresh = 60, }, 625 /* 6 - 1440x480i@60Hz */ 626 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 627 1602, 1716, 0, 480, 488, 494, 525, 0, 628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 629 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 630 .vrefresh = 60, }, 631 /* 7 - 1440x480i@60Hz */ 632 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 633 1602, 1716, 0, 480, 488, 494, 525, 0, 634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 635 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 636 .vrefresh = 60, }, 637 /* 8 - 1440x240@60Hz */ 638 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 639 1602, 1716, 0, 240, 244, 247, 262, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 641 DRM_MODE_FLAG_DBLCLK), 642 .vrefresh = 60, }, 643 /* 9 - 1440x240@60Hz */ 644 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 645 1602, 1716, 0, 240, 244, 247, 262, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 647 DRM_MODE_FLAG_DBLCLK), 648 .vrefresh = 60, }, 649 /* 10 - 2880x480i@60Hz */ 650 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 651 3204, 3432, 0, 480, 488, 494, 525, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 653 DRM_MODE_FLAG_INTERLACE), 654 .vrefresh = 60, }, 655 /* 11 - 2880x480i@60Hz */ 656 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 657 3204, 3432, 0, 480, 488, 494, 525, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 659 DRM_MODE_FLAG_INTERLACE), 660 .vrefresh = 60, }, 661 /* 12 - 2880x240@60Hz */ 662 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 663 3204, 3432, 0, 240, 244, 247, 262, 0, 664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 665 .vrefresh = 60, }, 666 /* 13 - 2880x240@60Hz */ 667 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 668 3204, 3432, 0, 240, 244, 247, 262, 0, 669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 670 .vrefresh = 60, }, 671 /* 14 - 1440x480@60Hz */ 672 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 673 1596, 1716, 0, 480, 489, 495, 525, 0, 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 675 .vrefresh = 60, }, 676 /* 15 - 1440x480@60Hz */ 677 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 678 1596, 1716, 0, 480, 489, 495, 525, 0, 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 680 .vrefresh = 60, }, 681 /* 16 - 1920x1080@60Hz */ 682 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 683 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 60, }, 686 /* 17 - 720x576@50Hz */ 687 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 688 796, 864, 0, 576, 581, 586, 625, 0, 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 690 .vrefresh = 50, }, 691 /* 18 - 720x576@50Hz */ 692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 693 796, 864, 0, 576, 581, 586, 625, 0, 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 695 .vrefresh = 50, }, 696 /* 19 - 1280x720@50Hz */ 697 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 698 1760, 1980, 0, 720, 725, 730, 750, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 50, }, 701 /* 20 - 1920x1080i@50Hz */ 702 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 703 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 705 DRM_MODE_FLAG_INTERLACE), 706 .vrefresh = 50, }, 707 /* 21 - 1440x576i@50Hz */ 708 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 709 1590, 1728, 0, 576, 580, 586, 625, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 711 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 712 .vrefresh = 50, }, 713 /* 22 - 1440x576i@50Hz */ 714 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 715 1590, 1728, 0, 576, 580, 586, 625, 0, 716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 717 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 718 .vrefresh = 50, }, 719 /* 23 - 1440x288@50Hz */ 720 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 721 1590, 1728, 0, 288, 290, 293, 312, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 723 DRM_MODE_FLAG_DBLCLK), 724 .vrefresh = 50, }, 725 /* 24 - 1440x288@50Hz */ 726 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 727 1590, 1728, 0, 288, 290, 293, 312, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 729 DRM_MODE_FLAG_DBLCLK), 730 .vrefresh = 50, }, 731 /* 25 - 2880x576i@50Hz */ 732 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 733 3180, 3456, 0, 576, 580, 586, 625, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 735 DRM_MODE_FLAG_INTERLACE), 736 .vrefresh = 50, }, 737 /* 26 - 2880x576i@50Hz */ 738 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 739 3180, 3456, 0, 576, 580, 586, 625, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 741 DRM_MODE_FLAG_INTERLACE), 742 .vrefresh = 50, }, 743 /* 27 - 2880x288@50Hz */ 744 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 745 3180, 3456, 0, 288, 290, 293, 312, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 747 .vrefresh = 50, }, 748 /* 28 - 2880x288@50Hz */ 749 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 750 3180, 3456, 0, 288, 290, 293, 312, 0, 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 752 .vrefresh = 50, }, 753 /* 29 - 1440x576@50Hz */ 754 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 755 1592, 1728, 0, 576, 581, 586, 625, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 757 .vrefresh = 50, }, 758 /* 30 - 1440x576@50Hz */ 759 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 760 1592, 1728, 0, 576, 581, 586, 625, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 762 .vrefresh = 50, }, 763 /* 31 - 1920x1080@50Hz */ 764 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 765 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 767 .vrefresh = 50, }, 768 /* 32 - 1920x1080@24Hz */ 769 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 770 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 772 .vrefresh = 24, }, 773 /* 33 - 1920x1080@25Hz */ 774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 775 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 777 .vrefresh = 25, }, 778 /* 34 - 1920x1080@30Hz */ 779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 780 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 782 .vrefresh = 30, }, 783 /* 35 - 2880x480@60Hz */ 784 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 785 3192, 3432, 0, 480, 489, 495, 525, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 787 .vrefresh = 60, }, 788 /* 36 - 2880x480@60Hz */ 789 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 790 3192, 3432, 0, 480, 489, 495, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 60, }, 793 /* 37 - 2880x576@50Hz */ 794 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 795 3184, 3456, 0, 576, 581, 586, 625, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 50, }, 798 /* 38 - 2880x576@50Hz */ 799 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 800 3184, 3456, 0, 576, 581, 586, 625, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 50, }, 803 /* 39 - 1920x1080i@50Hz */ 804 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 805 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 807 DRM_MODE_FLAG_INTERLACE), 808 .vrefresh = 50, }, 809 /* 40 - 1920x1080i@100Hz */ 810 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 811 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 813 DRM_MODE_FLAG_INTERLACE), 814 .vrefresh = 100, }, 815 /* 41 - 1280x720@100Hz */ 816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 817 1760, 1980, 0, 720, 725, 730, 750, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 819 .vrefresh = 100, }, 820 /* 42 - 720x576@100Hz */ 821 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 822 796, 864, 0, 576, 581, 586, 625, 0, 823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 824 .vrefresh = 100, }, 825 /* 43 - 720x576@100Hz */ 826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 827 796, 864, 0, 576, 581, 586, 625, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 829 .vrefresh = 100, }, 830 /* 44 - 1440x576i@100Hz */ 831 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 832 1590, 1728, 0, 576, 580, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 834 DRM_MODE_FLAG_DBLCLK), 835 .vrefresh = 100, }, 836 /* 45 - 1440x576i@100Hz */ 837 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 838 1590, 1728, 0, 576, 580, 586, 625, 0, 839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 840 DRM_MODE_FLAG_DBLCLK), 841 .vrefresh = 100, }, 842 /* 46 - 1920x1080i@120Hz */ 843 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 844 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 846 DRM_MODE_FLAG_INTERLACE), 847 .vrefresh = 120, }, 848 /* 47 - 1280x720@120Hz */ 849 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 850 1430, 1650, 0, 720, 725, 730, 750, 0, 851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 852 .vrefresh = 120, }, 853 /* 48 - 720x480@120Hz */ 854 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 855 798, 858, 0, 480, 489, 495, 525, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 120, }, 858 /* 49 - 720x480@120Hz */ 859 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 860 798, 858, 0, 480, 489, 495, 525, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 862 .vrefresh = 120, }, 863 /* 50 - 1440x480i@120Hz */ 864 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 865 1602, 1716, 0, 480, 488, 494, 525, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 867 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 868 .vrefresh = 120, }, 869 /* 51 - 1440x480i@120Hz */ 870 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 871 1602, 1716, 0, 480, 488, 494, 525, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 873 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 874 .vrefresh = 120, }, 875 /* 52 - 720x576@200Hz */ 876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 877 796, 864, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 200, }, 880 /* 53 - 720x576@200Hz */ 881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 882 796, 864, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 200, }, 885 /* 54 - 1440x576i@200Hz */ 886 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 887 1590, 1728, 0, 576, 580, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 889 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 890 .vrefresh = 200, }, 891 /* 55 - 1440x576i@200Hz */ 892 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 893 1590, 1728, 0, 576, 580, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 896 .vrefresh = 200, }, 897 /* 56 - 720x480@240Hz */ 898 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 899 798, 858, 0, 480, 489, 495, 525, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 901 .vrefresh = 240, }, 902 /* 57 - 720x480@240Hz */ 903 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 904 798, 858, 0, 480, 489, 495, 525, 0, 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 906 .vrefresh = 240, }, 907 /* 58 - 1440x480i@240 */ 908 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 909 1602, 1716, 0, 480, 488, 494, 525, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 911 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 912 .vrefresh = 240, }, 913 /* 59 - 1440x480i@240 */ 914 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 915 1602, 1716, 0, 480, 488, 494, 525, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 917 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 918 .vrefresh = 240, }, 919 /* 60 - 1280x720@24Hz */ 920 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 921 3080, 3300, 0, 720, 725, 730, 750, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 24, }, 924 /* 61 - 1280x720@25Hz */ 925 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 926 3740, 3960, 0, 720, 725, 730, 750, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 25, }, 929 /* 62 - 1280x720@30Hz */ 930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 931 3080, 3300, 0, 720, 725, 730, 750, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 30, }, 934 /* 63 - 1920x1080@120Hz */ 935 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 936 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 120, }, 939 /* 64 - 1920x1080@100Hz */ 940 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 941 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, }, 944}; 945 946/* 947 * HDMI 1.4 4k modes. 948 */ 949static const struct drm_display_mode edid_4k_modes[] = { 950 /* 1 - 3840x2160@30Hz */ 951 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 952 3840, 4016, 4104, 4400, 0, 953 2160, 2168, 2178, 2250, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .vrefresh = 30, }, 956 /* 2 - 3840x2160@25Hz */ 957 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 958 3840, 4896, 4984, 5280, 0, 959 2160, 2168, 2178, 2250, 0, 960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 961 .vrefresh = 25, }, 962 /* 3 - 3840x2160@24Hz */ 963 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 964 3840, 5116, 5204, 5500, 0, 965 2160, 2168, 2178, 2250, 0, 966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 967 .vrefresh = 24, }, 968 /* 4 - 4096x2160@24Hz (SMPTE) */ 969 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 970 4096, 5116, 5204, 5500, 0, 971 2160, 2168, 2178, 2250, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .vrefresh = 24, }, 974}; 975 976/*** DDC fetch and block validation ***/ 977 978static const u8 edid_header[] = { 979 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 980}; 981 982 /* 983 * Sanity check the header of the base EDID block. Return 8 if the header 984 * is perfect, down to 0 if it's totally wrong. 985 */ 986int drm_edid_header_is_valid(const u8 *raw_edid) 987{ 988 int i, score = 0; 989 990 for (i = 0; i < sizeof(edid_header); i++) 991 if (raw_edid[i] == edid_header[i]) 992 score++; 993 994 return score; 995} 996EXPORT_SYMBOL(drm_edid_header_is_valid); 997 998static int edid_fixup __read_mostly = 6; 999module_param_named(edid_fixup, edid_fixup, int, 0400); 1000MODULE_PARM_DESC(edid_fixup, 1001 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1002 1003/* 1004 * Sanity check the EDID block (base or extension). Return 0 if the block 1005 * doesn't check out, or 1 if it's valid. 1006 */ 1007bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 1008{ 1009 int i; 1010 u8 csum = 0; 1011 struct edid *edid = (struct edid *)raw_edid; 1012 1013 if (WARN_ON(!raw_edid)) 1014 return false; 1015 1016 if (edid_fixup > 8 || edid_fixup < 0) 1017 edid_fixup = 6; 1018 1019 if (block == 0) { 1020 int score = drm_edid_header_is_valid(raw_edid); 1021 if (score == 8) ; 1022 else if (score >= edid_fixup) { 1023 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1024 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1025 } else { 1026 goto bad; 1027 } 1028 } 1029 1030 for (i = 0; i < EDID_LENGTH; i++) 1031 csum += raw_edid[i]; 1032 if (csum) { 1033 if (print_bad_edid) { 1034 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1035 } 1036 1037 /* allow CEA to slide through, switches mangle this */ 1038 if (raw_edid[0] != 0x02) 1039 goto bad; 1040 } 1041 1042 /* per-block-type checks */ 1043 switch (raw_edid[0]) { 1044 case 0: /* base */ 1045 if (edid->version != 1) { 1046 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1047 goto bad; 1048 } 1049 1050 if (edid->revision > 4) 1051 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1052 break; 1053 1054 default: 1055 break; 1056 } 1057 1058 return true; 1059 1060bad: 1061 if (print_bad_edid) { 1062 printk(KERN_ERR "Raw EDID:\n"); 1063 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1064 raw_edid, EDID_LENGTH, false); 1065 } 1066 return false; 1067} 1068EXPORT_SYMBOL(drm_edid_block_valid); 1069 1070/** 1071 * drm_edid_is_valid - sanity check EDID data 1072 * @edid: EDID data 1073 * 1074 * Sanity-check an entire EDID record (including extensions) 1075 */ 1076bool drm_edid_is_valid(struct edid *edid) 1077{ 1078 int i; 1079 u8 *raw = (u8 *)edid; 1080 1081 if (!edid) 1082 return false; 1083 1084 for (i = 0; i <= edid->extensions; i++) 1085 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1086 return false; 1087 1088 return true; 1089} 1090EXPORT_SYMBOL(drm_edid_is_valid); 1091 1092#define DDC_SEGMENT_ADDR 0x30 1093/** 1094 * Get EDID information via I2C. 1095 * 1096 * \param adapter : i2c device adaptor 1097 * \param buf : EDID data buffer to be filled 1098 * \param len : EDID data buffer length 1099 * \return 0 on success or -1 on failure. 1100 * 1101 * Try to fetch EDID information by calling i2c driver function. 1102 */ 1103static int 1104drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, 1105 int block, int len) 1106{ 1107 unsigned char start = block * EDID_LENGTH; 1108 unsigned char segment = block >> 1; 1109 unsigned char xfers = segment ? 3 : 2; 1110 int ret, retries = 5; 1111 1112 /* The core i2c driver will automatically retry the transfer if the 1113 * adapter reports EAGAIN. However, we find that bit-banging transfers 1114 * are susceptible to errors under a heavily loaded machine and 1115 * generate spurious NAKs and timeouts. Retrying the transfer 1116 * of the individual block a few times seems to overcome this. 1117 */ 1118 do { 1119 struct i2c_msg msgs[] = { 1120 { 1121 .addr = DDC_SEGMENT_ADDR, 1122 .flags = 0, 1123 .len = 1, 1124 .buf = &segment, 1125 }, { 1126 .addr = DDC_ADDR, 1127 .flags = 0, 1128 .len = 1, 1129 .buf = &start, 1130 }, { 1131 .addr = DDC_ADDR, 1132 .flags = I2C_M_RD, 1133 .len = len, 1134 .buf = buf, 1135 } 1136 }; 1137 1138 /* 1139 * Avoid sending the segment addr to not upset non-compliant ddc 1140 * monitors. 1141 */ 1142 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1143 1144 if (ret == -ENXIO) { 1145 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1146 adapter->name); 1147 break; 1148 } 1149 } while (ret != xfers && --retries); 1150 1151 return ret == xfers ? 0 : -1; 1152} 1153 1154static bool drm_edid_is_zero(u8 *in_edid, int length) 1155{ 1156 if (memchr_inv(in_edid, 0, length)) 1157 return false; 1158 1159 return true; 1160} 1161 1162static u8 * 1163drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 1164{ 1165 int i, j = 0, valid_extensions = 0; 1166 u8 *block, *new; 1167 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1168 1169 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1170 return NULL; 1171 1172 /* base block fetch */ 1173 for (i = 0; i < 4; i++) { 1174 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) 1175 goto out; 1176 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1177 break; 1178 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1179 connector->null_edid_counter++; 1180 goto carp; 1181 } 1182 } 1183 if (i == 4) 1184 goto carp; 1185 1186 /* if there's no extensions, we're done */ 1187 if (block[0x7e] == 0) 1188 return block; 1189 1190 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1191 if (!new) 1192 goto out; 1193 block = new; 1194 1195 for (j = 1; j <= block[0x7e]; j++) { 1196 for (i = 0; i < 4; i++) { 1197 if (drm_do_probe_ddc_edid(adapter, 1198 block + (valid_extensions + 1) * EDID_LENGTH, 1199 j, EDID_LENGTH)) 1200 goto out; 1201 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1202 valid_extensions++; 1203 break; 1204 } 1205 } 1206 1207 if (i == 4 && print_bad_edid) { 1208 dev_warn(connector->dev->dev, 1209 "%s: Ignoring invalid EDID block %d.\n", 1210 drm_get_connector_name(connector), j); 1211 1212 connector->bad_edid_counter++; 1213 } 1214 } 1215 1216 if (valid_extensions != block[0x7e]) { 1217 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1218 block[0x7e] = valid_extensions; 1219 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1220 if (!new) 1221 goto out; 1222 block = new; 1223 } 1224 1225 return block; 1226 1227carp: 1228 if (print_bad_edid) { 1229 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1230 drm_get_connector_name(connector), j); 1231 } 1232 connector->bad_edid_counter++; 1233 1234out: 1235 kfree(block); 1236 return NULL; 1237} 1238 1239/** 1240 * Probe DDC presence. 1241 * 1242 * \param adapter : i2c device adaptor 1243 * \return 1 on success 1244 */ 1245bool 1246drm_probe_ddc(struct i2c_adapter *adapter) 1247{ 1248 unsigned char out; 1249 1250 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1251} 1252EXPORT_SYMBOL(drm_probe_ddc); 1253 1254/** 1255 * drm_get_edid - get EDID data, if available 1256 * @connector: connector we're probing 1257 * @adapter: i2c adapter to use for DDC 1258 * 1259 * Poke the given i2c channel to grab EDID data if possible. If found, 1260 * attach it to the connector. 1261 * 1262 * Return edid data or NULL if we couldn't find any. 1263 */ 1264struct edid *drm_get_edid(struct drm_connector *connector, 1265 struct i2c_adapter *adapter) 1266{ 1267 struct edid *edid = NULL; 1268 1269 if (drm_probe_ddc(adapter)) 1270 edid = (struct edid *)drm_do_get_edid(connector, adapter); 1271 1272 return edid; 1273} 1274EXPORT_SYMBOL(drm_get_edid); 1275 1276/** 1277 * drm_edid_duplicate - duplicate an EDID and the extensions 1278 * @edid: EDID to duplicate 1279 * 1280 * Return duplicate edid or NULL on allocation failure. 1281 */ 1282struct edid *drm_edid_duplicate(const struct edid *edid) 1283{ 1284 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1285} 1286EXPORT_SYMBOL(drm_edid_duplicate); 1287 1288/*** EDID parsing ***/ 1289 1290/** 1291 * edid_vendor - match a string against EDID's obfuscated vendor field 1292 * @edid: EDID to match 1293 * @vendor: vendor string 1294 * 1295 * Returns true if @vendor is in @edid, false otherwise 1296 */ 1297static bool edid_vendor(struct edid *edid, char *vendor) 1298{ 1299 char edid_vendor[3]; 1300 1301 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1302 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1303 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1304 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1305 1306 return !strncmp(edid_vendor, vendor, 3); 1307} 1308 1309/** 1310 * edid_get_quirks - return quirk flags for a given EDID 1311 * @edid: EDID to process 1312 * 1313 * This tells subsequent routines what fixes they need to apply. 1314 */ 1315static u32 edid_get_quirks(struct edid *edid) 1316{ 1317 struct edid_quirk *quirk; 1318 int i; 1319 1320 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1321 quirk = &edid_quirk_list[i]; 1322 1323 if (edid_vendor(edid, quirk->vendor) && 1324 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1325 return quirk->quirks; 1326 } 1327 1328 return 0; 1329} 1330 1331#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1332#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) 1333 1334/** 1335 * edid_fixup_preferred - set preferred modes based on quirk list 1336 * @connector: has mode list to fix up 1337 * @quirks: quirks list 1338 * 1339 * Walk the mode list for @connector, clearing the preferred status 1340 * on existing modes and setting it anew for the right mode ala @quirks. 1341 */ 1342static void edid_fixup_preferred(struct drm_connector *connector, 1343 u32 quirks) 1344{ 1345 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1346 int target_refresh = 0; 1347 1348 if (list_empty(&connector->probed_modes)) 1349 return; 1350 1351 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1352 target_refresh = 60; 1353 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1354 target_refresh = 75; 1355 1356 preferred_mode = list_first_entry(&connector->probed_modes, 1357 struct drm_display_mode, head); 1358 1359 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1360 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1361 1362 if (cur_mode == preferred_mode) 1363 continue; 1364 1365 /* Largest mode is preferred */ 1366 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1367 preferred_mode = cur_mode; 1368 1369 /* At a given size, try to get closest to target refresh */ 1370 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1371 MODE_REFRESH_DIFF(cur_mode, target_refresh) < 1372 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) { 1373 preferred_mode = cur_mode; 1374 } 1375 } 1376 1377 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1378} 1379 1380static bool 1381mode_is_rb(const struct drm_display_mode *mode) 1382{ 1383 return (mode->htotal - mode->hdisplay == 160) && 1384 (mode->hsync_end - mode->hdisplay == 80) && 1385 (mode->hsync_end - mode->hsync_start == 32) && 1386 (mode->vsync_start - mode->vdisplay == 3); 1387} 1388 1389/* 1390 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1391 * @dev: Device to duplicate against 1392 * @hsize: Mode width 1393 * @vsize: Mode height 1394 * @fresh: Mode refresh rate 1395 * @rb: Mode reduced-blanking-ness 1396 * 1397 * Walk the DMT mode list looking for a match for the given parameters. 1398 * Return a newly allocated copy of the mode, or NULL if not found. 1399 */ 1400struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1401 int hsize, int vsize, int fresh, 1402 bool rb) 1403{ 1404 int i; 1405 1406 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1407 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1408 if (hsize != ptr->hdisplay) 1409 continue; 1410 if (vsize != ptr->vdisplay) 1411 continue; 1412 if (fresh != drm_mode_vrefresh(ptr)) 1413 continue; 1414 if (rb != mode_is_rb(ptr)) 1415 continue; 1416 1417 return drm_mode_duplicate(dev, ptr); 1418 } 1419 1420 return NULL; 1421} 1422EXPORT_SYMBOL(drm_mode_find_dmt); 1423 1424typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1425 1426static void 1427cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1428{ 1429 int i, n = 0; 1430 u8 d = ext[0x02]; 1431 u8 *det_base = ext + d; 1432 1433 n = (127 - d) / 18; 1434 for (i = 0; i < n; i++) 1435 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1436} 1437 1438static void 1439vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1440{ 1441 unsigned int i, n = min((int)ext[0x02], 6); 1442 u8 *det_base = ext + 5; 1443 1444 if (ext[0x01] != 1) 1445 return; /* unknown version */ 1446 1447 for (i = 0; i < n; i++) 1448 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1449} 1450 1451static void 1452drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1453{ 1454 int i; 1455 struct edid *edid = (struct edid *)raw_edid; 1456 1457 if (edid == NULL) 1458 return; 1459 1460 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1461 cb(&(edid->detailed_timings[i]), closure); 1462 1463 for (i = 1; i <= raw_edid[0x7e]; i++) { 1464 u8 *ext = raw_edid + (i * EDID_LENGTH); 1465 switch (*ext) { 1466 case CEA_EXT: 1467 cea_for_each_detailed_block(ext, cb, closure); 1468 break; 1469 case VTB_EXT: 1470 vtb_for_each_detailed_block(ext, cb, closure); 1471 break; 1472 default: 1473 break; 1474 } 1475 } 1476} 1477 1478static void 1479is_rb(struct detailed_timing *t, void *data) 1480{ 1481 u8 *r = (u8 *)t; 1482 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1483 if (r[15] & 0x10) 1484 *(bool *)data = true; 1485} 1486 1487/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1488static bool 1489drm_monitor_supports_rb(struct edid *edid) 1490{ 1491 if (edid->revision >= 4) { 1492 bool ret = false; 1493 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1494 return ret; 1495 } 1496 1497 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1498} 1499 1500static void 1501find_gtf2(struct detailed_timing *t, void *data) 1502{ 1503 u8 *r = (u8 *)t; 1504 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1505 *(u8 **)data = r; 1506} 1507 1508/* Secondary GTF curve kicks in above some break frequency */ 1509static int 1510drm_gtf2_hbreak(struct edid *edid) 1511{ 1512 u8 *r = NULL; 1513 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1514 return r ? (r[12] * 2) : 0; 1515} 1516 1517static int 1518drm_gtf2_2c(struct edid *edid) 1519{ 1520 u8 *r = NULL; 1521 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1522 return r ? r[13] : 0; 1523} 1524 1525static int 1526drm_gtf2_m(struct edid *edid) 1527{ 1528 u8 *r = NULL; 1529 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1530 return r ? (r[15] << 8) + r[14] : 0; 1531} 1532 1533static int 1534drm_gtf2_k(struct edid *edid) 1535{ 1536 u8 *r = NULL; 1537 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1538 return r ? r[16] : 0; 1539} 1540 1541static int 1542drm_gtf2_2j(struct edid *edid) 1543{ 1544 u8 *r = NULL; 1545 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1546 return r ? r[17] : 0; 1547} 1548 1549/** 1550 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1551 * @edid: EDID block to scan 1552 */ 1553static int standard_timing_level(struct edid *edid) 1554{ 1555 if (edid->revision >= 2) { 1556 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1557 return LEVEL_CVT; 1558 if (drm_gtf2_hbreak(edid)) 1559 return LEVEL_GTF2; 1560 return LEVEL_GTF; 1561 } 1562 return LEVEL_DMT; 1563} 1564 1565/* 1566 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1567 * monitors fill with ascii space (0x20) instead. 1568 */ 1569static int 1570bad_std_timing(u8 a, u8 b) 1571{ 1572 return (a == 0x00 && b == 0x00) || 1573 (a == 0x01 && b == 0x01) || 1574 (a == 0x20 && b == 0x20); 1575} 1576 1577/** 1578 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1579 * @t: standard timing params 1580 * @timing_level: standard timing level 1581 * 1582 * Take the standard timing params (in this case width, aspect, and refresh) 1583 * and convert them into a real mode using CVT/GTF/DMT. 1584 */ 1585static struct drm_display_mode * 1586drm_mode_std(struct drm_connector *connector, struct edid *edid, 1587 struct std_timing *t, int revision) 1588{ 1589 struct drm_device *dev = connector->dev; 1590 struct drm_display_mode *m, *mode = NULL; 1591 int hsize, vsize; 1592 int vrefresh_rate; 1593 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1594 >> EDID_TIMING_ASPECT_SHIFT; 1595 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1596 >> EDID_TIMING_VFREQ_SHIFT; 1597 int timing_level = standard_timing_level(edid); 1598 1599 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1600 return NULL; 1601 1602 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1603 hsize = t->hsize * 8 + 248; 1604 /* vrefresh_rate = vfreq + 60 */ 1605 vrefresh_rate = vfreq + 60; 1606 /* the vdisplay is calculated based on the aspect ratio */ 1607 if (aspect_ratio == 0) { 1608 if (revision < 3) 1609 vsize = hsize; 1610 else 1611 vsize = (hsize * 10) / 16; 1612 } else if (aspect_ratio == 1) 1613 vsize = (hsize * 3) / 4; 1614 else if (aspect_ratio == 2) 1615 vsize = (hsize * 4) / 5; 1616 else 1617 vsize = (hsize * 9) / 16; 1618 1619 /* HDTV hack, part 1 */ 1620 if (vrefresh_rate == 60 && 1621 ((hsize == 1360 && vsize == 765) || 1622 (hsize == 1368 && vsize == 769))) { 1623 hsize = 1366; 1624 vsize = 768; 1625 } 1626 1627 /* 1628 * If this connector already has a mode for this size and refresh 1629 * rate (because it came from detailed or CVT info), use that 1630 * instead. This way we don't have to guess at interlace or 1631 * reduced blanking. 1632 */ 1633 list_for_each_entry(m, &connector->probed_modes, head) 1634 if (m->hdisplay == hsize && m->vdisplay == vsize && 1635 drm_mode_vrefresh(m) == vrefresh_rate) 1636 return NULL; 1637 1638 /* HDTV hack, part 2 */ 1639 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1640 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1641 false); 1642 mode->hdisplay = 1366; 1643 mode->hsync_start = mode->hsync_start - 1; 1644 mode->hsync_end = mode->hsync_end - 1; 1645 return mode; 1646 } 1647 1648 /* check whether it can be found in default mode table */ 1649 if (drm_monitor_supports_rb(edid)) { 1650 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1651 true); 1652 if (mode) 1653 return mode; 1654 } 1655 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1656 if (mode) 1657 return mode; 1658 1659 /* okay, generate it */ 1660 switch (timing_level) { 1661 case LEVEL_DMT: 1662 break; 1663 case LEVEL_GTF: 1664 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1665 break; 1666 case LEVEL_GTF2: 1667 /* 1668 * This is potentially wrong if there's ever a monitor with 1669 * more than one ranges section, each claiming a different 1670 * secondary GTF curve. Please don't do that. 1671 */ 1672 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1673 if (!mode) 1674 return NULL; 1675 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1676 drm_mode_destroy(dev, mode); 1677 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1678 vrefresh_rate, 0, 0, 1679 drm_gtf2_m(edid), 1680 drm_gtf2_2c(edid), 1681 drm_gtf2_k(edid), 1682 drm_gtf2_2j(edid)); 1683 } 1684 break; 1685 case LEVEL_CVT: 1686 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1687 false); 1688 break; 1689 } 1690 return mode; 1691} 1692 1693/* 1694 * EDID is delightfully ambiguous about how interlaced modes are to be 1695 * encoded. Our internal representation is of frame height, but some 1696 * HDTV detailed timings are encoded as field height. 1697 * 1698 * The format list here is from CEA, in frame size. Technically we 1699 * should be checking refresh rate too. Whatever. 1700 */ 1701static void 1702drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1703 struct detailed_pixel_timing *pt) 1704{ 1705 int i; 1706 static const struct { 1707 int w, h; 1708 } cea_interlaced[] = { 1709 { 1920, 1080 }, 1710 { 720, 480 }, 1711 { 1440, 480 }, 1712 { 2880, 480 }, 1713 { 720, 576 }, 1714 { 1440, 576 }, 1715 { 2880, 576 }, 1716 }; 1717 1718 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1719 return; 1720 1721 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1722 if ((mode->hdisplay == cea_interlaced[i].w) && 1723 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1724 mode->vdisplay *= 2; 1725 mode->vsync_start *= 2; 1726 mode->vsync_end *= 2; 1727 mode->vtotal *= 2; 1728 mode->vtotal |= 1; 1729 } 1730 } 1731 1732 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1733} 1734 1735/** 1736 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1737 * @dev: DRM device (needed to create new mode) 1738 * @edid: EDID block 1739 * @timing: EDID detailed timing info 1740 * @quirks: quirks to apply 1741 * 1742 * An EDID detailed timing block contains enough info for us to create and 1743 * return a new struct drm_display_mode. 1744 */ 1745static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1746 struct edid *edid, 1747 struct detailed_timing *timing, 1748 u32 quirks) 1749{ 1750 struct drm_display_mode *mode; 1751 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1752 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1753 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1754 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1755 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1756 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1757 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1758 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1759 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1760 1761 /* ignore tiny modes */ 1762 if (hactive < 64 || vactive < 64) 1763 return NULL; 1764 1765 if (pt->misc & DRM_EDID_PT_STEREO) { 1766 DRM_DEBUG_KMS("stereo mode not supported\n"); 1767 return NULL; 1768 } 1769 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1770 DRM_DEBUG_KMS("composite sync not supported\n"); 1771 } 1772 1773 /* it is incorrect if hsync/vsync width is zero */ 1774 if (!hsync_pulse_width || !vsync_pulse_width) { 1775 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1776 "Wrong Hsync/Vsync pulse width\n"); 1777 return NULL; 1778 } 1779 1780 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1781 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1782 if (!mode) 1783 return NULL; 1784 1785 goto set_size; 1786 } 1787 1788 mode = drm_mode_create(dev); 1789 if (!mode) 1790 return NULL; 1791 1792 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1793 timing->pixel_clock = cpu_to_le16(1088); 1794 1795 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1796 1797 mode->hdisplay = hactive; 1798 mode->hsync_start = mode->hdisplay + hsync_offset; 1799 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1800 mode->htotal = mode->hdisplay + hblank; 1801 1802 mode->vdisplay = vactive; 1803 mode->vsync_start = mode->vdisplay + vsync_offset; 1804 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1805 mode->vtotal = mode->vdisplay + vblank; 1806 1807 /* Some EDIDs have bogus h/vtotal values */ 1808 if (mode->hsync_end > mode->htotal) 1809 mode->htotal = mode->hsync_end + 1; 1810 if (mode->vsync_end > mode->vtotal) 1811 mode->vtotal = mode->vsync_end + 1; 1812 1813 drm_mode_do_interlace_quirk(mode, pt); 1814 1815 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1816 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1817 } 1818 1819 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1820 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1821 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1822 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1823 1824set_size: 1825 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1826 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1827 1828 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1829 mode->width_mm *= 10; 1830 mode->height_mm *= 10; 1831 } 1832 1833 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1834 mode->width_mm = edid->width_cm * 10; 1835 mode->height_mm = edid->height_cm * 10; 1836 } 1837 1838 mode->type = DRM_MODE_TYPE_DRIVER; 1839 mode->vrefresh = drm_mode_vrefresh(mode); 1840 drm_mode_set_name(mode); 1841 1842 return mode; 1843} 1844 1845static bool 1846mode_in_hsync_range(const struct drm_display_mode *mode, 1847 struct edid *edid, u8 *t) 1848{ 1849 int hsync, hmin, hmax; 1850 1851 hmin = t[7]; 1852 if (edid->revision >= 4) 1853 hmin += ((t[4] & 0x04) ? 255 : 0); 1854 hmax = t[8]; 1855 if (edid->revision >= 4) 1856 hmax += ((t[4] & 0x08) ? 255 : 0); 1857 hsync = drm_mode_hsync(mode); 1858 1859 return (hsync <= hmax && hsync >= hmin); 1860} 1861 1862static bool 1863mode_in_vsync_range(const struct drm_display_mode *mode, 1864 struct edid *edid, u8 *t) 1865{ 1866 int vsync, vmin, vmax; 1867 1868 vmin = t[5]; 1869 if (edid->revision >= 4) 1870 vmin += ((t[4] & 0x01) ? 255 : 0); 1871 vmax = t[6]; 1872 if (edid->revision >= 4) 1873 vmax += ((t[4] & 0x02) ? 255 : 0); 1874 vsync = drm_mode_vrefresh(mode); 1875 1876 return (vsync <= vmax && vsync >= vmin); 1877} 1878 1879static u32 1880range_pixel_clock(struct edid *edid, u8 *t) 1881{ 1882 /* unspecified */ 1883 if (t[9] == 0 || t[9] == 255) 1884 return 0; 1885 1886 /* 1.4 with CVT support gives us real precision, yay */ 1887 if (edid->revision >= 4 && t[10] == 0x04) 1888 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1889 1890 /* 1.3 is pathetic, so fuzz up a bit */ 1891 return t[9] * 10000 + 5001; 1892} 1893 1894static bool 1895mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1896 struct detailed_timing *timing) 1897{ 1898 u32 max_clock; 1899 u8 *t = (u8 *)timing; 1900 1901 if (!mode_in_hsync_range(mode, edid, t)) 1902 return false; 1903 1904 if (!mode_in_vsync_range(mode, edid, t)) 1905 return false; 1906 1907 if ((max_clock = range_pixel_clock(edid, t))) 1908 if (mode->clock > max_clock) 1909 return false; 1910 1911 /* 1.4 max horizontal check */ 1912 if (edid->revision >= 4 && t[10] == 0x04) 1913 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1914 return false; 1915 1916 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1917 return false; 1918 1919 return true; 1920} 1921 1922static bool valid_inferred_mode(const struct drm_connector *connector, 1923 const struct drm_display_mode *mode) 1924{ 1925 struct drm_display_mode *m; 1926 bool ok = false; 1927 1928 list_for_each_entry(m, &connector->probed_modes, head) { 1929 if (mode->hdisplay == m->hdisplay && 1930 mode->vdisplay == m->vdisplay && 1931 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 1932 return false; /* duplicated */ 1933 if (mode->hdisplay <= m->hdisplay && 1934 mode->vdisplay <= m->vdisplay) 1935 ok = true; 1936 } 1937 return ok; 1938} 1939 1940static int 1941drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1942 struct detailed_timing *timing) 1943{ 1944 int i, modes = 0; 1945 struct drm_display_mode *newmode; 1946 struct drm_device *dev = connector->dev; 1947 1948 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1949 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 1950 valid_inferred_mode(connector, drm_dmt_modes + i)) { 1951 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1952 if (newmode) { 1953 drm_mode_probed_add(connector, newmode); 1954 modes++; 1955 } 1956 } 1957 } 1958 1959 return modes; 1960} 1961 1962/* fix up 1366x768 mode from 1368x768; 1963 * GFT/CVT can't express 1366 width which isn't dividable by 8 1964 */ 1965static void fixup_mode_1366x768(struct drm_display_mode *mode) 1966{ 1967 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 1968 mode->hdisplay = 1366; 1969 mode->hsync_start--; 1970 mode->hsync_end--; 1971 drm_mode_set_name(mode); 1972 } 1973} 1974 1975static int 1976drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 1977 struct detailed_timing *timing) 1978{ 1979 int i, modes = 0; 1980 struct drm_display_mode *newmode; 1981 struct drm_device *dev = connector->dev; 1982 1983 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 1984 const struct minimode *m = &extra_modes[i]; 1985 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 1986 if (!newmode) 1987 return modes; 1988 1989 fixup_mode_1366x768(newmode); 1990 if (!mode_in_range(newmode, edid, timing) || 1991 !valid_inferred_mode(connector, newmode)) { 1992 drm_mode_destroy(dev, newmode); 1993 continue; 1994 } 1995 1996 drm_mode_probed_add(connector, newmode); 1997 modes++; 1998 } 1999 2000 return modes; 2001} 2002 2003static int 2004drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2005 struct detailed_timing *timing) 2006{ 2007 int i, modes = 0; 2008 struct drm_display_mode *newmode; 2009 struct drm_device *dev = connector->dev; 2010 bool rb = drm_monitor_supports_rb(edid); 2011 2012 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2013 const struct minimode *m = &extra_modes[i]; 2014 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2015 if (!newmode) 2016 return modes; 2017 2018 fixup_mode_1366x768(newmode); 2019 if (!mode_in_range(newmode, edid, timing) || 2020 !valid_inferred_mode(connector, newmode)) { 2021 drm_mode_destroy(dev, newmode); 2022 continue; 2023 } 2024 2025 drm_mode_probed_add(connector, newmode); 2026 modes++; 2027 } 2028 2029 return modes; 2030} 2031 2032static void 2033do_inferred_modes(struct detailed_timing *timing, void *c) 2034{ 2035 struct detailed_mode_closure *closure = c; 2036 struct detailed_non_pixel *data = &timing->data.other_data; 2037 struct detailed_data_monitor_range *range = &data->data.range; 2038 2039 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2040 return; 2041 2042 closure->modes += drm_dmt_modes_for_range(closure->connector, 2043 closure->edid, 2044 timing); 2045 2046 if (!version_greater(closure->edid, 1, 1)) 2047 return; /* GTF not defined yet */ 2048 2049 switch (range->flags) { 2050 case 0x02: /* secondary gtf, XXX could do more */ 2051 case 0x00: /* default gtf */ 2052 closure->modes += drm_gtf_modes_for_range(closure->connector, 2053 closure->edid, 2054 timing); 2055 break; 2056 case 0x04: /* cvt, only in 1.4+ */ 2057 if (!version_greater(closure->edid, 1, 3)) 2058 break; 2059 2060 closure->modes += drm_cvt_modes_for_range(closure->connector, 2061 closure->edid, 2062 timing); 2063 break; 2064 case 0x01: /* just the ranges, no formula */ 2065 default: 2066 break; 2067 } 2068} 2069 2070static int 2071add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2072{ 2073 struct detailed_mode_closure closure = { 2074 connector, edid, 0, 0, 0 2075 }; 2076 2077 if (version_greater(edid, 1, 0)) 2078 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2079 &closure); 2080 2081 return closure.modes; 2082} 2083 2084static int 2085drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2086{ 2087 int i, j, m, modes = 0; 2088 struct drm_display_mode *mode; 2089 u8 *est = ((u8 *)timing) + 5; 2090 2091 for (i = 0; i < 6; i++) { 2092 for (j = 7; j >= 0; j--) { 2093 m = (i * 8) + (7 - j); 2094 if (m >= ARRAY_SIZE(est3_modes)) 2095 break; 2096 if (est[i] & (1 << j)) { 2097 mode = drm_mode_find_dmt(connector->dev, 2098 est3_modes[m].w, 2099 est3_modes[m].h, 2100 est3_modes[m].r, 2101 est3_modes[m].rb); 2102 if (mode) { 2103 drm_mode_probed_add(connector, mode); 2104 modes++; 2105 } 2106 } 2107 } 2108 } 2109 2110 return modes; 2111} 2112 2113static void 2114do_established_modes(struct detailed_timing *timing, void *c) 2115{ 2116 struct detailed_mode_closure *closure = c; 2117 struct detailed_non_pixel *data = &timing->data.other_data; 2118 2119 if (data->type == EDID_DETAIL_EST_TIMINGS) 2120 closure->modes += drm_est3_modes(closure->connector, timing); 2121} 2122 2123/** 2124 * add_established_modes - get est. modes from EDID and add them 2125 * @edid: EDID block to scan 2126 * 2127 * Each EDID block contains a bitmap of the supported "established modes" list 2128 * (defined above). Tease them out and add them to the global modes list. 2129 */ 2130static int 2131add_established_modes(struct drm_connector *connector, struct edid *edid) 2132{ 2133 struct drm_device *dev = connector->dev; 2134 unsigned long est_bits = edid->established_timings.t1 | 2135 (edid->established_timings.t2 << 8) | 2136 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2137 int i, modes = 0; 2138 struct detailed_mode_closure closure = { 2139 connector, edid, 0, 0, 0 2140 }; 2141 2142 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2143 if (est_bits & (1<<i)) { 2144 struct drm_display_mode *newmode; 2145 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2146 if (newmode) { 2147 drm_mode_probed_add(connector, newmode); 2148 modes++; 2149 } 2150 } 2151 } 2152 2153 if (version_greater(edid, 1, 0)) 2154 drm_for_each_detailed_block((u8 *)edid, 2155 do_established_modes, &closure); 2156 2157 return modes + closure.modes; 2158} 2159 2160static void 2161do_standard_modes(struct detailed_timing *timing, void *c) 2162{ 2163 struct detailed_mode_closure *closure = c; 2164 struct detailed_non_pixel *data = &timing->data.other_data; 2165 struct drm_connector *connector = closure->connector; 2166 struct edid *edid = closure->edid; 2167 2168 if (data->type == EDID_DETAIL_STD_MODES) { 2169 int i; 2170 for (i = 0; i < 6; i++) { 2171 struct std_timing *std; 2172 struct drm_display_mode *newmode; 2173 2174 std = &data->data.timings[i]; 2175 newmode = drm_mode_std(connector, edid, std, 2176 edid->revision); 2177 if (newmode) { 2178 drm_mode_probed_add(connector, newmode); 2179 closure->modes++; 2180 } 2181 } 2182 } 2183} 2184 2185/** 2186 * add_standard_modes - get std. modes from EDID and add them 2187 * @edid: EDID block to scan 2188 * 2189 * Standard modes can be calculated using the appropriate standard (DMT, 2190 * GTF or CVT. Grab them from @edid and add them to the list. 2191 */ 2192static int 2193add_standard_modes(struct drm_connector *connector, struct edid *edid) 2194{ 2195 int i, modes = 0; 2196 struct detailed_mode_closure closure = { 2197 connector, edid, 0, 0, 0 2198 }; 2199 2200 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2201 struct drm_display_mode *newmode; 2202 2203 newmode = drm_mode_std(connector, edid, 2204 &edid->standard_timings[i], 2205 edid->revision); 2206 if (newmode) { 2207 drm_mode_probed_add(connector, newmode); 2208 modes++; 2209 } 2210 } 2211 2212 if (version_greater(edid, 1, 0)) 2213 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2214 &closure); 2215 2216 /* XXX should also look for standard codes in VTB blocks */ 2217 2218 return modes + closure.modes; 2219} 2220 2221static int drm_cvt_modes(struct drm_connector *connector, 2222 struct detailed_timing *timing) 2223{ 2224 int i, j, modes = 0; 2225 struct drm_display_mode *newmode; 2226 struct drm_device *dev = connector->dev; 2227 struct cvt_timing *cvt; 2228 const int rates[] = { 60, 85, 75, 60, 50 }; 2229 const u8 empty[3] = { 0, 0, 0 }; 2230 2231 for (i = 0; i < 4; i++) { 2232 int uninitialized_var(width), height; 2233 cvt = &(timing->data.other_data.data.cvt[i]); 2234 2235 if (!memcmp(cvt->code, empty, 3)) 2236 continue; 2237 2238 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2239 switch (cvt->code[1] & 0x0c) { 2240 case 0x00: 2241 width = height * 4 / 3; 2242 break; 2243 case 0x04: 2244 width = height * 16 / 9; 2245 break; 2246 case 0x08: 2247 width = height * 16 / 10; 2248 break; 2249 case 0x0c: 2250 width = height * 15 / 9; 2251 break; 2252 } 2253 2254 for (j = 1; j < 5; j++) { 2255 if (cvt->code[2] & (1 << j)) { 2256 newmode = drm_cvt_mode(dev, width, height, 2257 rates[j], j == 0, 2258 false, false); 2259 if (newmode) { 2260 drm_mode_probed_add(connector, newmode); 2261 modes++; 2262 } 2263 } 2264 } 2265 } 2266 2267 return modes; 2268} 2269 2270static void 2271do_cvt_mode(struct detailed_timing *timing, void *c) 2272{ 2273 struct detailed_mode_closure *closure = c; 2274 struct detailed_non_pixel *data = &timing->data.other_data; 2275 2276 if (data->type == EDID_DETAIL_CVT_3BYTE) 2277 closure->modes += drm_cvt_modes(closure->connector, timing); 2278} 2279 2280static int 2281add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2282{ 2283 struct detailed_mode_closure closure = { 2284 connector, edid, 0, 0, 0 2285 }; 2286 2287 if (version_greater(edid, 1, 2)) 2288 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2289 2290 /* XXX should also look for CVT codes in VTB blocks */ 2291 2292 return closure.modes; 2293} 2294 2295static void 2296do_detailed_mode(struct detailed_timing *timing, void *c) 2297{ 2298 struct detailed_mode_closure *closure = c; 2299 struct drm_display_mode *newmode; 2300 2301 if (timing->pixel_clock) { 2302 newmode = drm_mode_detailed(closure->connector->dev, 2303 closure->edid, timing, 2304 closure->quirks); 2305 if (!newmode) 2306 return; 2307 2308 if (closure->preferred) 2309 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2310 2311 drm_mode_probed_add(closure->connector, newmode); 2312 closure->modes++; 2313 closure->preferred = 0; 2314 } 2315} 2316 2317/* 2318 * add_detailed_modes - Add modes from detailed timings 2319 * @connector: attached connector 2320 * @edid: EDID block to scan 2321 * @quirks: quirks to apply 2322 */ 2323static int 2324add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2325 u32 quirks) 2326{ 2327 struct detailed_mode_closure closure = { 2328 connector, 2329 edid, 2330 1, 2331 quirks, 2332 0 2333 }; 2334 2335 if (closure.preferred && !version_greater(edid, 1, 3)) 2336 closure.preferred = 2337 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2338 2339 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2340 2341 return closure.modes; 2342} 2343 2344#define AUDIO_BLOCK 0x01 2345#define VIDEO_BLOCK 0x02 2346#define VENDOR_BLOCK 0x03 2347#define SPEAKER_BLOCK 0x04 2348#define VIDEO_CAPABILITY_BLOCK 0x07 2349#define EDID_BASIC_AUDIO (1 << 6) 2350#define EDID_CEA_YCRCB444 (1 << 5) 2351#define EDID_CEA_YCRCB422 (1 << 4) 2352#define EDID_CEA_VCDB_QS (1 << 6) 2353 2354/* 2355 * Search EDID for CEA extension block. 2356 */ 2357static u8 *drm_find_cea_extension(struct edid *edid) 2358{ 2359 u8 *edid_ext = NULL; 2360 int i; 2361 2362 /* No EDID or EDID extensions */ 2363 if (edid == NULL || edid->extensions == 0) 2364 return NULL; 2365 2366 /* Find CEA extension */ 2367 for (i = 0; i < edid->extensions; i++) { 2368 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2369 if (edid_ext[0] == CEA_EXT) 2370 break; 2371 } 2372 2373 if (i == edid->extensions) 2374 return NULL; 2375 2376 return edid_ext; 2377} 2378 2379/* 2380 * Calculate the alternate clock for the CEA mode 2381 * (60Hz vs. 59.94Hz etc.) 2382 */ 2383static unsigned int 2384cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2385{ 2386 unsigned int clock = cea_mode->clock; 2387 2388 if (cea_mode->vrefresh % 6 != 0) 2389 return clock; 2390 2391 /* 2392 * edid_cea_modes contains the 59.94Hz 2393 * variant for 240 and 480 line modes, 2394 * and the 60Hz variant otherwise. 2395 */ 2396 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2397 clock = clock * 1001 / 1000; 2398 else 2399 clock = DIV_ROUND_UP(clock * 1000, 1001); 2400 2401 return clock; 2402} 2403 2404/** 2405 * drm_match_cea_mode - look for a CEA mode matching given mode 2406 * @to_match: display mode 2407 * 2408 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2409 * mode. 2410 */ 2411u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2412{ 2413 u8 mode; 2414 2415 if (!to_match->clock) 2416 return 0; 2417 2418 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2419 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2420 unsigned int clock1, clock2; 2421 2422 /* Check both 60Hz and 59.94Hz */ 2423 clock1 = cea_mode->clock; 2424 clock2 = cea_mode_alternate_clock(cea_mode); 2425 2426 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2427 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2428 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2429 return mode + 1; 2430 } 2431 return 0; 2432} 2433EXPORT_SYMBOL(drm_match_cea_mode); 2434 2435/* 2436 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2437 * specific block). 2438 * 2439 * It's almost like cea_mode_alternate_clock(), we just need to add an 2440 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2441 * one. 2442 */ 2443static unsigned int 2444hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2445{ 2446 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2447 return hdmi_mode->clock; 2448 2449 return cea_mode_alternate_clock(hdmi_mode); 2450} 2451 2452/* 2453 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2454 * @to_match: display mode 2455 * 2456 * An HDMI mode is one defined in the HDMI vendor specific block. 2457 * 2458 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2459 */ 2460static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2461{ 2462 u8 mode; 2463 2464 if (!to_match->clock) 2465 return 0; 2466 2467 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2468 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2469 unsigned int clock1, clock2; 2470 2471 /* Make sure to also match alternate clocks */ 2472 clock1 = hdmi_mode->clock; 2473 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2474 2475 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2476 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2477 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2478 return mode + 1; 2479 } 2480 return 0; 2481} 2482 2483static int 2484add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2485{ 2486 struct drm_device *dev = connector->dev; 2487 struct drm_display_mode *mode, *tmp; 2488 LIST_HEAD(list); 2489 int modes = 0; 2490 2491 /* Don't add CEA modes if the CEA extension block is missing */ 2492 if (!drm_find_cea_extension(edid)) 2493 return 0; 2494 2495 /* 2496 * Go through all probed modes and create a new mode 2497 * with the alternate clock for certain CEA modes. 2498 */ 2499 list_for_each_entry(mode, &connector->probed_modes, head) { 2500 const struct drm_display_mode *cea_mode = NULL; 2501 struct drm_display_mode *newmode; 2502 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2503 unsigned int clock1, clock2; 2504 2505 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2506 cea_mode = &edid_cea_modes[mode_idx]; 2507 clock2 = cea_mode_alternate_clock(cea_mode); 2508 } else { 2509 mode_idx = drm_match_hdmi_mode(mode) - 1; 2510 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2511 cea_mode = &edid_4k_modes[mode_idx]; 2512 clock2 = hdmi_mode_alternate_clock(cea_mode); 2513 } 2514 } 2515 2516 if (!cea_mode) 2517 continue; 2518 2519 clock1 = cea_mode->clock; 2520 2521 if (clock1 == clock2) 2522 continue; 2523 2524 if (mode->clock != clock1 && mode->clock != clock2) 2525 continue; 2526 2527 newmode = drm_mode_duplicate(dev, cea_mode); 2528 if (!newmode) 2529 continue; 2530 2531 /* Carry over the stereo flags */ 2532 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2533 2534 /* 2535 * The current mode could be either variant. Make 2536 * sure to pick the "other" clock for the new mode. 2537 */ 2538 if (mode->clock != clock1) 2539 newmode->clock = clock1; 2540 else 2541 newmode->clock = clock2; 2542 2543 list_add_tail(&newmode->head, &list); 2544 } 2545 2546 list_for_each_entry_safe(mode, tmp, &list, head) { 2547 list_del(&mode->head); 2548 drm_mode_probed_add(connector, mode); 2549 modes++; 2550 } 2551 2552 return modes; 2553} 2554 2555static int 2556do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2557{ 2558 struct drm_device *dev = connector->dev; 2559 const u8 *mode; 2560 u8 cea_mode; 2561 int modes = 0; 2562 2563 for (mode = db; mode < db + len; mode++) { 2564 cea_mode = (*mode & 127) - 1; /* CEA modes are numbered 1..127 */ 2565 if (cea_mode < ARRAY_SIZE(edid_cea_modes)) { 2566 struct drm_display_mode *newmode; 2567 newmode = drm_mode_duplicate(dev, 2568 &edid_cea_modes[cea_mode]); 2569 if (newmode) { 2570 newmode->vrefresh = 0; 2571 drm_mode_probed_add(connector, newmode); 2572 modes++; 2573 } 2574 } 2575 } 2576 2577 return modes; 2578} 2579 2580struct stereo_mandatory_mode { 2581 int width, height, vrefresh; 2582 unsigned int flags; 2583}; 2584 2585static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2586 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2587 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2588 { 1920, 1080, 50, 2589 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2590 { 1920, 1080, 60, 2591 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2592 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2593 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2594 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2595 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2596}; 2597 2598static bool 2599stereo_match_mandatory(const struct drm_display_mode *mode, 2600 const struct stereo_mandatory_mode *stereo_mode) 2601{ 2602 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2603 2604 return mode->hdisplay == stereo_mode->width && 2605 mode->vdisplay == stereo_mode->height && 2606 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2607 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2608} 2609 2610static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2611{ 2612 struct drm_device *dev = connector->dev; 2613 const struct drm_display_mode *mode; 2614 struct list_head stereo_modes; 2615 int modes = 0, i; 2616 2617 INIT_LIST_HEAD(&stereo_modes); 2618 2619 list_for_each_entry(mode, &connector->probed_modes, head) { 2620 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2621 const struct stereo_mandatory_mode *mandatory; 2622 struct drm_display_mode *new_mode; 2623 2624 if (!stereo_match_mandatory(mode, 2625 &stereo_mandatory_modes[i])) 2626 continue; 2627 2628 mandatory = &stereo_mandatory_modes[i]; 2629 new_mode = drm_mode_duplicate(dev, mode); 2630 if (!new_mode) 2631 continue; 2632 2633 new_mode->flags |= mandatory->flags; 2634 list_add_tail(&new_mode->head, &stereo_modes); 2635 modes++; 2636 } 2637 } 2638 2639 list_splice_tail(&stereo_modes, &connector->probed_modes); 2640 2641 return modes; 2642} 2643 2644static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2645{ 2646 struct drm_device *dev = connector->dev; 2647 struct drm_display_mode *newmode; 2648 2649 vic--; /* VICs start at 1 */ 2650 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2651 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2652 return 0; 2653 } 2654 2655 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2656 if (!newmode) 2657 return 0; 2658 2659 drm_mode_probed_add(connector, newmode); 2660 2661 return 1; 2662} 2663 2664static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2665 const u8 *video_db, u8 video_len, u8 video_index) 2666{ 2667 struct drm_device *dev = connector->dev; 2668 struct drm_display_mode *newmode; 2669 int modes = 0; 2670 u8 cea_mode; 2671 2672 if (video_db == NULL || video_index > video_len) 2673 return 0; 2674 2675 /* CEA modes are numbered 1..127 */ 2676 cea_mode = (video_db[video_index] & 127) - 1; 2677 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2678 return 0; 2679 2680 if (structure & (1 << 0)) { 2681 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2682 if (newmode) { 2683 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2684 drm_mode_probed_add(connector, newmode); 2685 modes++; 2686 } 2687 } 2688 if (structure & (1 << 6)) { 2689 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2690 if (newmode) { 2691 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2692 drm_mode_probed_add(connector, newmode); 2693 modes++; 2694 } 2695 } 2696 if (structure & (1 << 8)) { 2697 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2698 if (newmode) { 2699 newmode->flags = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2700 drm_mode_probed_add(connector, newmode); 2701 modes++; 2702 } 2703 } 2704 2705 return modes; 2706} 2707 2708/* 2709 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2710 * @connector: connector corresponding to the HDMI sink 2711 * @db: start of the CEA vendor specific block 2712 * @len: length of the CEA block payload, ie. one can access up to db[len] 2713 * 2714 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2715 * also adds the stereo 3d modes when applicable. 2716 */ 2717static int 2718do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2719 const u8 *video_db, u8 video_len) 2720{ 2721 int modes = 0, offset = 0, i, multi_present = 0; 2722 u8 vic_len, hdmi_3d_len = 0; 2723 u16 mask; 2724 u16 structure_all; 2725 2726 if (len < 8) 2727 goto out; 2728 2729 /* no HDMI_Video_Present */ 2730 if (!(db[8] & (1 << 5))) 2731 goto out; 2732 2733 /* Latency_Fields_Present */ 2734 if (db[8] & (1 << 7)) 2735 offset += 2; 2736 2737 /* I_Latency_Fields_Present */ 2738 if (db[8] & (1 << 6)) 2739 offset += 2; 2740 2741 /* the declared length is not long enough for the 2 first bytes 2742 * of additional video format capabilities */ 2743 if (len < (8 + offset + 2)) 2744 goto out; 2745 2746 /* 3D_Present */ 2747 offset++; 2748 if (db[8 + offset] & (1 << 7)) { 2749 modes += add_hdmi_mandatory_stereo_modes(connector); 2750 2751 /* 3D_Multi_present */ 2752 multi_present = (db[8 + offset] & 0x60) >> 5; 2753 } 2754 2755 offset++; 2756 vic_len = db[8 + offset] >> 5; 2757 hdmi_3d_len = db[8 + offset] & 0x1f; 2758 2759 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2760 u8 vic; 2761 2762 vic = db[9 + offset + i]; 2763 modes += add_hdmi_mode(connector, vic); 2764 } 2765 offset += 1 + vic_len; 2766 2767 if (!(multi_present == 1 || multi_present == 2)) 2768 goto out; 2769 2770 if ((multi_present == 1 && len < (9 + offset)) || 2771 (multi_present == 2 && len < (11 + offset))) 2772 goto out; 2773 2774 if ((multi_present == 1 && hdmi_3d_len < 2) || 2775 (multi_present == 2 && hdmi_3d_len < 4)) 2776 goto out; 2777 2778 /* 3D_Structure_ALL */ 2779 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2780 2781 /* check if 3D_MASK is present */ 2782 if (multi_present == 2) 2783 mask = (db[10 + offset] << 8) | db[11 + offset]; 2784 else 2785 mask = 0xffff; 2786 2787 for (i = 0; i < 16; i++) { 2788 if (mask & (1 << i)) 2789 modes += add_3d_struct_modes(connector, 2790 structure_all, 2791 video_db, 2792 video_len, i); 2793 } 2794 2795out: 2796 return modes; 2797} 2798 2799static int 2800cea_db_payload_len(const u8 *db) 2801{ 2802 return db[0] & 0x1f; 2803} 2804 2805static int 2806cea_db_tag(const u8 *db) 2807{ 2808 return db[0] >> 5; 2809} 2810 2811static int 2812cea_revision(const u8 *cea) 2813{ 2814 return cea[1]; 2815} 2816 2817static int 2818cea_db_offsets(const u8 *cea, int *start, int *end) 2819{ 2820 /* Data block offset in CEA extension block */ 2821 *start = 4; 2822 *end = cea[2]; 2823 if (*end == 0) 2824 *end = 127; 2825 if (*end < 4 || *end > 127) 2826 return -ERANGE; 2827 return 0; 2828} 2829 2830static bool cea_db_is_hdmi_vsdb(const u8 *db) 2831{ 2832 int hdmi_id; 2833 2834 if (cea_db_tag(db) != VENDOR_BLOCK) 2835 return false; 2836 2837 if (cea_db_payload_len(db) < 5) 2838 return false; 2839 2840 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2841 2842 return hdmi_id == HDMI_IEEE_OUI; 2843} 2844 2845#define for_each_cea_db(cea, i, start, end) \ 2846 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2847 2848static int 2849add_cea_modes(struct drm_connector *connector, struct edid *edid) 2850{ 2851 const u8 *cea = drm_find_cea_extension(edid); 2852 const u8 *db, *hdmi = NULL, *video = NULL; 2853 u8 dbl, hdmi_len, video_len = 0; 2854 int modes = 0; 2855 2856 if (cea && cea_revision(cea) >= 3) { 2857 int i, start, end; 2858 2859 if (cea_db_offsets(cea, &start, &end)) 2860 return 0; 2861 2862 for_each_cea_db(cea, i, start, end) { 2863 db = &cea[i]; 2864 dbl = cea_db_payload_len(db); 2865 2866 if (cea_db_tag(db) == VIDEO_BLOCK) { 2867 video = db + 1; 2868 video_len = dbl; 2869 modes += do_cea_modes(connector, video, dbl); 2870 } 2871 else if (cea_db_is_hdmi_vsdb(db)) { 2872 hdmi = db; 2873 hdmi_len = dbl; 2874 } 2875 } 2876 } 2877 2878 /* 2879 * We parse the HDMI VSDB after having added the cea modes as we will 2880 * be patching their flags when the sink supports stereo 3D. 2881 */ 2882 if (hdmi) 2883 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 2884 video_len); 2885 2886 return modes; 2887} 2888 2889static void 2890parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 2891{ 2892 u8 len = cea_db_payload_len(db); 2893 2894 if (len >= 6) { 2895 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 2896 connector->dvi_dual = db[6] & 1; 2897 } 2898 if (len >= 7) 2899 connector->max_tmds_clock = db[7] * 5; 2900 if (len >= 8) { 2901 connector->latency_present[0] = db[8] >> 7; 2902 connector->latency_present[1] = (db[8] >> 6) & 1; 2903 } 2904 if (len >= 9) 2905 connector->video_latency[0] = db[9]; 2906 if (len >= 10) 2907 connector->audio_latency[0] = db[10]; 2908 if (len >= 11) 2909 connector->video_latency[1] = db[11]; 2910 if (len >= 12) 2911 connector->audio_latency[1] = db[12]; 2912 2913 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 2914 "max TMDS clock %d, " 2915 "latency present %d %d, " 2916 "video latency %d %d, " 2917 "audio latency %d %d\n", 2918 connector->dvi_dual, 2919 connector->max_tmds_clock, 2920 (int) connector->latency_present[0], 2921 (int) connector->latency_present[1], 2922 connector->video_latency[0], 2923 connector->video_latency[1], 2924 connector->audio_latency[0], 2925 connector->audio_latency[1]); 2926} 2927 2928static void 2929monitor_name(struct detailed_timing *t, void *data) 2930{ 2931 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 2932 *(u8 **)data = t->data.other_data.data.str.str; 2933} 2934 2935/** 2936 * drm_edid_to_eld - build ELD from EDID 2937 * @connector: connector corresponding to the HDMI/DP sink 2938 * @edid: EDID to parse 2939 * 2940 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. 2941 * Some ELD fields are left to the graphics driver caller: 2942 * - Conn_Type 2943 * - HDCP 2944 * - Port_ID 2945 */ 2946void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 2947{ 2948 uint8_t *eld = connector->eld; 2949 u8 *cea; 2950 u8 *name; 2951 u8 *db; 2952 int sad_count = 0; 2953 int mnl; 2954 int dbl; 2955 2956 memset(eld, 0, sizeof(connector->eld)); 2957 2958 cea = drm_find_cea_extension(edid); 2959 if (!cea) { 2960 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 2961 return; 2962 } 2963 2964 name = NULL; 2965 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 2966 for (mnl = 0; name && mnl < 13; mnl++) { 2967 if (name[mnl] == 0x0a) 2968 break; 2969 eld[20 + mnl] = name[mnl]; 2970 } 2971 eld[4] = (cea[1] << 5) | mnl; 2972 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 2973 2974 eld[0] = 2 << 3; /* ELD version: 2 */ 2975 2976 eld[16] = edid->mfg_id[0]; 2977 eld[17] = edid->mfg_id[1]; 2978 eld[18] = edid->prod_code[0]; 2979 eld[19] = edid->prod_code[1]; 2980 2981 if (cea_revision(cea) >= 3) { 2982 int i, start, end; 2983 2984 if (cea_db_offsets(cea, &start, &end)) { 2985 start = 0; 2986 end = 0; 2987 } 2988 2989 for_each_cea_db(cea, i, start, end) { 2990 db = &cea[i]; 2991 dbl = cea_db_payload_len(db); 2992 2993 switch (cea_db_tag(db)) { 2994 case AUDIO_BLOCK: 2995 /* Audio Data Block, contains SADs */ 2996 sad_count = dbl / 3; 2997 if (dbl >= 1) 2998 memcpy(eld + 20 + mnl, &db[1], dbl); 2999 break; 3000 case SPEAKER_BLOCK: 3001 /* Speaker Allocation Data Block */ 3002 if (dbl >= 1) 3003 eld[7] = db[1]; 3004 break; 3005 case VENDOR_BLOCK: 3006 /* HDMI Vendor-Specific Data Block */ 3007 if (cea_db_is_hdmi_vsdb(db)) 3008 parse_hdmi_vsdb(connector, db); 3009 break; 3010 default: 3011 break; 3012 } 3013 } 3014 } 3015 eld[5] |= sad_count << 4; 3016 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3017 3018 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3019} 3020EXPORT_SYMBOL(drm_edid_to_eld); 3021 3022/** 3023 * drm_edid_to_sad - extracts SADs from EDID 3024 * @edid: EDID to parse 3025 * @sads: pointer that will be set to the extracted SADs 3026 * 3027 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3028 * Note: returned pointer needs to be kfreed 3029 * 3030 * Return number of found SADs or negative number on error. 3031 */ 3032int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3033{ 3034 int count = 0; 3035 int i, start, end, dbl; 3036 u8 *cea; 3037 3038 cea = drm_find_cea_extension(edid); 3039 if (!cea) { 3040 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3041 return -ENOENT; 3042 } 3043 3044 if (cea_revision(cea) < 3) { 3045 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3046 return -ENOTSUPP; 3047 } 3048 3049 if (cea_db_offsets(cea, &start, &end)) { 3050 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3051 return -EPROTO; 3052 } 3053 3054 for_each_cea_db(cea, i, start, end) { 3055 u8 *db = &cea[i]; 3056 3057 if (cea_db_tag(db) == AUDIO_BLOCK) { 3058 int j; 3059 dbl = cea_db_payload_len(db); 3060 3061 count = dbl / 3; /* SAD is 3B */ 3062 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3063 if (!*sads) 3064 return -ENOMEM; 3065 for (j = 0; j < count; j++) { 3066 u8 *sad = &db[1 + j * 3]; 3067 3068 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3069 (*sads)[j].channels = sad[0] & 0x7; 3070 (*sads)[j].freq = sad[1] & 0x7F; 3071 (*sads)[j].byte2 = sad[2]; 3072 } 3073 break; 3074 } 3075 } 3076 3077 return count; 3078} 3079EXPORT_SYMBOL(drm_edid_to_sad); 3080 3081/** 3082 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3083 * @edid: EDID to parse 3084 * @sadb: pointer to the speaker block 3085 * 3086 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3087 * Note: returned pointer needs to be kfreed 3088 * 3089 * Return number of found Speaker Allocation Blocks or negative number on error. 3090 */ 3091int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3092{ 3093 int count = 0; 3094 int i, start, end, dbl; 3095 const u8 *cea; 3096 3097 cea = drm_find_cea_extension(edid); 3098 if (!cea) { 3099 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3100 return -ENOENT; 3101 } 3102 3103 if (cea_revision(cea) < 3) { 3104 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3105 return -ENOTSUPP; 3106 } 3107 3108 if (cea_db_offsets(cea, &start, &end)) { 3109 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3110 return -EPROTO; 3111 } 3112 3113 for_each_cea_db(cea, i, start, end) { 3114 const u8 *db = &cea[i]; 3115 3116 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3117 dbl = cea_db_payload_len(db); 3118 3119 /* Speaker Allocation Data Block */ 3120 if (dbl == 3) { 3121 *sadb = kmalloc(dbl, GFP_KERNEL); 3122 if (!*sadb) 3123 return -ENOMEM; 3124 memcpy(*sadb, &db[1], dbl); 3125 count = dbl; 3126 break; 3127 } 3128 } 3129 } 3130 3131 return count; 3132} 3133EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3134 3135/** 3136 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond 3137 * @connector: connector associated with the HDMI/DP sink 3138 * @mode: the display mode 3139 */ 3140int drm_av_sync_delay(struct drm_connector *connector, 3141 struct drm_display_mode *mode) 3142{ 3143 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3144 int a, v; 3145 3146 if (!connector->latency_present[0]) 3147 return 0; 3148 if (!connector->latency_present[1]) 3149 i = 0; 3150 3151 a = connector->audio_latency[i]; 3152 v = connector->video_latency[i]; 3153 3154 /* 3155 * HDMI/DP sink doesn't support audio or video? 3156 */ 3157 if (a == 255 || v == 255) 3158 return 0; 3159 3160 /* 3161 * Convert raw EDID values to millisecond. 3162 * Treat unknown latency as 0ms. 3163 */ 3164 if (a) 3165 a = min(2 * (a - 1), 500); 3166 if (v) 3167 v = min(2 * (v - 1), 500); 3168 3169 return max(v - a, 0); 3170} 3171EXPORT_SYMBOL(drm_av_sync_delay); 3172 3173/** 3174 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3175 * @encoder: the encoder just changed display mode 3176 * @mode: the adjusted display mode 3177 * 3178 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3179 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3180 */ 3181struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 3182 struct drm_display_mode *mode) 3183{ 3184 struct drm_connector *connector; 3185 struct drm_device *dev = encoder->dev; 3186 3187 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 3188 if (connector->encoder == encoder && connector->eld[0]) 3189 return connector; 3190 3191 return NULL; 3192} 3193EXPORT_SYMBOL(drm_select_eld); 3194 3195/** 3196 * drm_detect_hdmi_monitor - detect whether monitor is hdmi. 3197 * @edid: monitor EDID information 3198 * 3199 * Parse the CEA extension according to CEA-861-B. 3200 * Return true if HDMI, false if not or unknown. 3201 */ 3202bool drm_detect_hdmi_monitor(struct edid *edid) 3203{ 3204 u8 *edid_ext; 3205 int i; 3206 int start_offset, end_offset; 3207 3208 edid_ext = drm_find_cea_extension(edid); 3209 if (!edid_ext) 3210 return false; 3211 3212 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3213 return false; 3214 3215 /* 3216 * Because HDMI identifier is in Vendor Specific Block, 3217 * search it from all data blocks of CEA extension. 3218 */ 3219 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3220 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3221 return true; 3222 } 3223 3224 return false; 3225} 3226EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3227 3228/** 3229 * drm_detect_monitor_audio - check monitor audio capability 3230 * 3231 * Monitor should have CEA extension block. 3232 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3233 * audio' only. If there is any audio extension block and supported 3234 * audio format, assume at least 'basic audio' support, even if 'basic 3235 * audio' is not defined in EDID. 3236 * 3237 */ 3238bool drm_detect_monitor_audio(struct edid *edid) 3239{ 3240 u8 *edid_ext; 3241 int i, j; 3242 bool has_audio = false; 3243 int start_offset, end_offset; 3244 3245 edid_ext = drm_find_cea_extension(edid); 3246 if (!edid_ext) 3247 goto end; 3248 3249 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3250 3251 if (has_audio) { 3252 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3253 goto end; 3254 } 3255 3256 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3257 goto end; 3258 3259 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3260 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3261 has_audio = true; 3262 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3263 DRM_DEBUG_KMS("CEA audio format %d\n", 3264 (edid_ext[i + j] >> 3) & 0xf); 3265 goto end; 3266 } 3267 } 3268end: 3269 return has_audio; 3270} 3271EXPORT_SYMBOL(drm_detect_monitor_audio); 3272 3273/** 3274 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3275 * 3276 * Check whether the monitor reports the RGB quantization range selection 3277 * as supported. The AVI infoframe can then be used to inform the monitor 3278 * which quantization range (full or limited) is used. 3279 */ 3280bool drm_rgb_quant_range_selectable(struct edid *edid) 3281{ 3282 u8 *edid_ext; 3283 int i, start, end; 3284 3285 edid_ext = drm_find_cea_extension(edid); 3286 if (!edid_ext) 3287 return false; 3288 3289 if (cea_db_offsets(edid_ext, &start, &end)) 3290 return false; 3291 3292 for_each_cea_db(edid_ext, i, start, end) { 3293 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3294 cea_db_payload_len(&edid_ext[i]) == 2) { 3295 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3296 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3297 } 3298 } 3299 3300 return false; 3301} 3302EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3303 3304/** 3305 * drm_add_display_info - pull display info out if present 3306 * @edid: EDID data 3307 * @info: display info (attached to connector) 3308 * 3309 * Grab any available display info and stuff it into the drm_display_info 3310 * structure that's part of the connector. Useful for tracking bpp and 3311 * color spaces. 3312 */ 3313static void drm_add_display_info(struct edid *edid, 3314 struct drm_display_info *info) 3315{ 3316 u8 *edid_ext; 3317 3318 info->width_mm = edid->width_cm * 10; 3319 info->height_mm = edid->height_cm * 10; 3320 3321 /* driver figures it out in this case */ 3322 info->bpc = 0; 3323 info->color_formats = 0; 3324 3325 if (edid->revision < 3) 3326 return; 3327 3328 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3329 return; 3330 3331 /* Get data from CEA blocks if present */ 3332 edid_ext = drm_find_cea_extension(edid); 3333 if (edid_ext) { 3334 info->cea_rev = edid_ext[1]; 3335 3336 /* The existence of a CEA block should imply RGB support */ 3337 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3338 if (edid_ext[3] & EDID_CEA_YCRCB444) 3339 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3340 if (edid_ext[3] & EDID_CEA_YCRCB422) 3341 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3342 } 3343 3344 /* Only defined for 1.4 with digital displays */ 3345 if (edid->revision < 4) 3346 return; 3347 3348 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3349 case DRM_EDID_DIGITAL_DEPTH_6: 3350 info->bpc = 6; 3351 break; 3352 case DRM_EDID_DIGITAL_DEPTH_8: 3353 info->bpc = 8; 3354 break; 3355 case DRM_EDID_DIGITAL_DEPTH_10: 3356 info->bpc = 10; 3357 break; 3358 case DRM_EDID_DIGITAL_DEPTH_12: 3359 info->bpc = 12; 3360 break; 3361 case DRM_EDID_DIGITAL_DEPTH_14: 3362 info->bpc = 14; 3363 break; 3364 case DRM_EDID_DIGITAL_DEPTH_16: 3365 info->bpc = 16; 3366 break; 3367 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3368 default: 3369 info->bpc = 0; 3370 break; 3371 } 3372 3373 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3374 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3375 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3376 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3377 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3378} 3379 3380/** 3381 * drm_add_edid_modes - add modes from EDID data, if available 3382 * @connector: connector we're probing 3383 * @edid: edid data 3384 * 3385 * Add the specified modes to the connector's mode list. 3386 * 3387 * Return number of modes added or 0 if we couldn't find any. 3388 */ 3389int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3390{ 3391 int num_modes = 0; 3392 u32 quirks; 3393 3394 if (edid == NULL) { 3395 return 0; 3396 } 3397 if (!drm_edid_is_valid(edid)) { 3398 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3399 drm_get_connector_name(connector)); 3400 return 0; 3401 } 3402 3403 quirks = edid_get_quirks(edid); 3404 3405 /* 3406 * EDID spec says modes should be preferred in this order: 3407 * - preferred detailed mode 3408 * - other detailed modes from base block 3409 * - detailed modes from extension blocks 3410 * - CVT 3-byte code modes 3411 * - standard timing codes 3412 * - established timing codes 3413 * - modes inferred from GTF or CVT range information 3414 * 3415 * We get this pretty much right. 3416 * 3417 * XXX order for additional mode types in extension blocks? 3418 */ 3419 num_modes += add_detailed_modes(connector, edid, quirks); 3420 num_modes += add_cvt_modes(connector, edid); 3421 num_modes += add_standard_modes(connector, edid); 3422 num_modes += add_established_modes(connector, edid); 3423 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3424 num_modes += add_inferred_modes(connector, edid); 3425 num_modes += add_cea_modes(connector, edid); 3426 num_modes += add_alternate_cea_modes(connector, edid); 3427 3428 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3429 edid_fixup_preferred(connector, quirks); 3430 3431 drm_add_display_info(edid, &connector->display_info); 3432 3433 return num_modes; 3434} 3435EXPORT_SYMBOL(drm_add_edid_modes); 3436 3437/** 3438 * drm_add_modes_noedid - add modes for the connectors without EDID 3439 * @connector: connector we're probing 3440 * @hdisplay: the horizontal display limit 3441 * @vdisplay: the vertical display limit 3442 * 3443 * Add the specified modes to the connector's mode list. Only when the 3444 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3445 * 3446 * Return number of modes added or 0 if we couldn't find any. 3447 */ 3448int drm_add_modes_noedid(struct drm_connector *connector, 3449 int hdisplay, int vdisplay) 3450{ 3451 int i, count, num_modes = 0; 3452 struct drm_display_mode *mode; 3453 struct drm_device *dev = connector->dev; 3454 3455 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 3456 if (hdisplay < 0) 3457 hdisplay = 0; 3458 if (vdisplay < 0) 3459 vdisplay = 0; 3460 3461 for (i = 0; i < count; i++) { 3462 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3463 if (hdisplay && vdisplay) { 3464 /* 3465 * Only when two are valid, they will be used to check 3466 * whether the mode should be added to the mode list of 3467 * the connector. 3468 */ 3469 if (ptr->hdisplay > hdisplay || 3470 ptr->vdisplay > vdisplay) 3471 continue; 3472 } 3473 if (drm_mode_vrefresh(ptr) > 61) 3474 continue; 3475 mode = drm_mode_duplicate(dev, ptr); 3476 if (mode) { 3477 drm_mode_probed_add(connector, mode); 3478 num_modes++; 3479 } 3480 } 3481 return num_modes; 3482} 3483EXPORT_SYMBOL(drm_add_modes_noedid); 3484 3485void drm_set_preferred_mode(struct drm_connector *connector, 3486 int hpref, int vpref) 3487{ 3488 struct drm_display_mode *mode; 3489 3490 list_for_each_entry(mode, &connector->probed_modes, head) { 3491 if (drm_mode_width(mode) == hpref && 3492 drm_mode_height(mode) == vpref) 3493 mode->type |= DRM_MODE_TYPE_PREFERRED; 3494 } 3495} 3496EXPORT_SYMBOL(drm_set_preferred_mode); 3497 3498/** 3499 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3500 * data from a DRM display mode 3501 * @frame: HDMI AVI infoframe 3502 * @mode: DRM display mode 3503 * 3504 * Returns 0 on success or a negative error code on failure. 3505 */ 3506int 3507drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3508 const struct drm_display_mode *mode) 3509{ 3510 int err; 3511 3512 if (!frame || !mode) 3513 return -EINVAL; 3514 3515 err = hdmi_avi_infoframe_init(frame); 3516 if (err < 0) 3517 return err; 3518 3519 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3520 frame->pixel_repeat = 1; 3521 3522 frame->video_code = drm_match_cea_mode(mode); 3523 3524 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3525 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3526 3527 return 0; 3528} 3529EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3530 3531static enum hdmi_3d_structure 3532s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3533{ 3534 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3535 3536 switch (layout) { 3537 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3538 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3539 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3540 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3541 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3542 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3543 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3544 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3545 case DRM_MODE_FLAG_3D_L_DEPTH: 3546 return HDMI_3D_STRUCTURE_L_DEPTH; 3547 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3548 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3549 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3550 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3551 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3552 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3553 default: 3554 return HDMI_3D_STRUCTURE_INVALID; 3555 } 3556} 3557 3558/** 3559 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3560 * data from a DRM display mode 3561 * @frame: HDMI vendor infoframe 3562 * @mode: DRM display mode 3563 * 3564 * Note that there's is a need to send HDMI vendor infoframes only when using a 3565 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3566 * function will return -EINVAL, error that can be safely ignored. 3567 * 3568 * Returns 0 on success or a negative error code on failure. 3569 */ 3570int 3571drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3572 const struct drm_display_mode *mode) 3573{ 3574 int err; 3575 u32 s3d_flags; 3576 u8 vic; 3577 3578 if (!frame || !mode) 3579 return -EINVAL; 3580 3581 vic = drm_match_hdmi_mode(mode); 3582 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3583 3584 if (!vic && !s3d_flags) 3585 return -EINVAL; 3586 3587 if (vic && s3d_flags) 3588 return -EINVAL; 3589 3590 err = hdmi_vendor_infoframe_init(frame); 3591 if (err < 0) 3592 return err; 3593 3594 if (vic) 3595 frame->vic = vic; 3596 else 3597 frame->s3d_struct = s3d_structure_from_display_mode(mode); 3598 3599 return 0; 3600} 3601EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 3602