1/* 2 * Samsung SoC DP (Display Port) interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13#include <linux/module.h> 14#include <linux/platform_device.h> 15#include <linux/err.h> 16#include <linux/clk.h> 17#include <linux/io.h> 18#include <linux/interrupt.h> 19#include <linux/of.h> 20#include <linux/of_gpio.h> 21#include <linux/gpio.h> 22#include <linux/component.h> 23#include <linux/phy/phy.h> 24#include <video/of_display_timing.h> 25#include <video/of_videomode.h> 26 27#include <drm/drmP.h> 28#include <drm/drm_crtc.h> 29#include <drm/drm_crtc_helper.h> 30#include <drm/drm_panel.h> 31#include <drm/bridge/ptn3460.h> 32 33#include "exynos_drm_drv.h" 34#include "exynos_dp_core.h" 35 36#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ 37 connector) 38 39struct bridge_init { 40 struct i2c_client *client; 41 struct device_node *node; 42}; 43 44static void exynos_dp_init_dp(struct exynos_dp_device *dp) 45{ 46 exynos_dp_reset(dp); 47 48 exynos_dp_swreset(dp); 49 50 exynos_dp_init_analog_param(dp); 51 exynos_dp_init_interrupt(dp); 52 53 /* SW defined function Normal operation */ 54 exynos_dp_enable_sw_function(dp); 55 56 exynos_dp_config_interrupt(dp); 57 exynos_dp_init_analog_func(dp); 58 59 exynos_dp_init_hpd(dp); 60 exynos_dp_init_aux(dp); 61} 62 63static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) 64{ 65 int timeout_loop = 0; 66 67 while (exynos_dp_get_plug_in_status(dp) != 0) { 68 timeout_loop++; 69 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 70 dev_err(dp->dev, "failed to get hpd plug status\n"); 71 return -ETIMEDOUT; 72 } 73 usleep_range(10, 11); 74 } 75 76 return 0; 77} 78 79static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) 80{ 81 int i; 82 unsigned char sum = 0; 83 84 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 85 sum = sum + edid_data[i]; 86 87 return sum; 88} 89 90static int exynos_dp_read_edid(struct exynos_dp_device *dp) 91{ 92 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 93 unsigned int extend_block = 0; 94 unsigned char sum; 95 unsigned char test_vector; 96 int retval; 97 98 /* 99 * EDID device address is 0x50. 100 * However, if necessary, you must have set upper address 101 * into E-EDID in I2C device, 0x30. 102 */ 103 104 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 105 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 106 EDID_EXTENSION_FLAG, 107 &extend_block); 108 if (retval) 109 return retval; 110 111 if (extend_block > 0) { 112 dev_dbg(dp->dev, "EDID data includes a single extension!\n"); 113 114 /* Read EDID data */ 115 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, 116 EDID_HEADER_PATTERN, 117 EDID_BLOCK_LENGTH, 118 &edid[EDID_HEADER_PATTERN]); 119 if (retval != 0) { 120 dev_err(dp->dev, "EDID Read failed!\n"); 121 return -EIO; 122 } 123 sum = exynos_dp_calc_edid_check_sum(edid); 124 if (sum != 0) { 125 dev_err(dp->dev, "EDID bad checksum!\n"); 126 return -EIO; 127 } 128 129 /* Read additional EDID data */ 130 retval = exynos_dp_read_bytes_from_i2c(dp, 131 I2C_EDID_DEVICE_ADDR, 132 EDID_BLOCK_LENGTH, 133 EDID_BLOCK_LENGTH, 134 &edid[EDID_BLOCK_LENGTH]); 135 if (retval != 0) { 136 dev_err(dp->dev, "EDID Read failed!\n"); 137 return -EIO; 138 } 139 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); 140 if (sum != 0) { 141 dev_err(dp->dev, "EDID bad checksum!\n"); 142 return -EIO; 143 } 144 145 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, 146 &test_vector); 147 if (test_vector & DP_TEST_LINK_EDID_READ) { 148 exynos_dp_write_byte_to_dpcd(dp, 149 DP_TEST_EDID_CHECKSUM, 150 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 151 exynos_dp_write_byte_to_dpcd(dp, 152 DP_TEST_RESPONSE, 153 DP_TEST_EDID_CHECKSUM_WRITE); 154 } 155 } else { 156 dev_info(dp->dev, "EDID data does not include any extensions.\n"); 157 158 /* Read EDID data */ 159 retval = exynos_dp_read_bytes_from_i2c(dp, 160 I2C_EDID_DEVICE_ADDR, 161 EDID_HEADER_PATTERN, 162 EDID_BLOCK_LENGTH, 163 &edid[EDID_HEADER_PATTERN]); 164 if (retval != 0) { 165 dev_err(dp->dev, "EDID Read failed!\n"); 166 return -EIO; 167 } 168 sum = exynos_dp_calc_edid_check_sum(edid); 169 if (sum != 0) { 170 dev_err(dp->dev, "EDID bad checksum!\n"); 171 return -EIO; 172 } 173 174 exynos_dp_read_byte_from_dpcd(dp, 175 DP_TEST_REQUEST, 176 &test_vector); 177 if (test_vector & DP_TEST_LINK_EDID_READ) { 178 exynos_dp_write_byte_to_dpcd(dp, 179 DP_TEST_EDID_CHECKSUM, 180 edid[EDID_CHECKSUM]); 181 exynos_dp_write_byte_to_dpcd(dp, 182 DP_TEST_RESPONSE, 183 DP_TEST_EDID_CHECKSUM_WRITE); 184 } 185 } 186 187 dev_err(dp->dev, "EDID Read success!\n"); 188 return 0; 189} 190 191static int exynos_dp_handle_edid(struct exynos_dp_device *dp) 192{ 193 u8 buf[12]; 194 int i; 195 int retval; 196 197 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ 198 retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 199 12, buf); 200 if (retval) 201 return retval; 202 203 /* Read EDID */ 204 for (i = 0; i < 3; i++) { 205 retval = exynos_dp_read_edid(dp); 206 if (!retval) 207 break; 208 } 209 210 return retval; 211} 212 213static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, 214 bool enable) 215{ 216 u8 data; 217 218 exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); 219 220 if (enable) 221 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 222 DP_LANE_COUNT_ENHANCED_FRAME_EN | 223 DPCD_LANE_COUNT_SET(data)); 224 else 225 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, 226 DPCD_LANE_COUNT_SET(data)); 227} 228 229static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) 230{ 231 u8 data; 232 int retval; 233 234 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 235 retval = DPCD_ENHANCED_FRAME_CAP(data); 236 237 return retval; 238} 239 240static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) 241{ 242 u8 data; 243 244 data = exynos_dp_is_enhanced_mode_available(dp); 245 exynos_dp_enable_rx_to_enhanced_mode(dp, data); 246 exynos_dp_enable_enhanced_mode(dp, data); 247} 248 249static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) 250{ 251 exynos_dp_set_training_pattern(dp, DP_NONE); 252 253 exynos_dp_write_byte_to_dpcd(dp, 254 DP_TRAINING_PATTERN_SET, 255 DP_TRAINING_PATTERN_DISABLE); 256} 257 258static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, 259 int pre_emphasis, int lane) 260{ 261 switch (lane) { 262 case 0: 263 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); 264 break; 265 case 1: 266 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); 267 break; 268 269 case 2: 270 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); 271 break; 272 273 case 3: 274 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); 275 break; 276 } 277} 278 279static int exynos_dp_link_start(struct exynos_dp_device *dp) 280{ 281 u8 buf[4]; 282 int lane, lane_count, pll_tries, retval; 283 284 lane_count = dp->link_train.lane_count; 285 286 dp->link_train.lt_state = CLOCK_RECOVERY; 287 dp->link_train.eq_loop = 0; 288 289 for (lane = 0; lane < lane_count; lane++) 290 dp->link_train.cr_loop[lane] = 0; 291 292 /* Set link rate and count as you want to establish*/ 293 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); 294 exynos_dp_set_lane_count(dp, dp->link_train.lane_count); 295 296 /* Setup RX configuration */ 297 buf[0] = dp->link_train.link_rate; 298 buf[1] = dp->link_train.lane_count; 299 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 300 2, buf); 301 if (retval) 302 return retval; 303 304 /* Set TX pre-emphasis to minimum */ 305 for (lane = 0; lane < lane_count; lane++) 306 exynos_dp_set_lane_lane_pre_emphasis(dp, 307 PRE_EMPHASIS_LEVEL_0, lane); 308 309 /* Wait for PLL lock */ 310 pll_tries = 0; 311 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 312 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { 313 dev_err(dp->dev, "Wait for PLL lock timed out\n"); 314 return -ETIMEDOUT; 315 } 316 317 pll_tries++; 318 usleep_range(90, 120); 319 } 320 321 /* Set training pattern 1 */ 322 exynos_dp_set_training_pattern(dp, TRAINING_PTN1); 323 324 /* Set RX training pattern */ 325 retval = exynos_dp_write_byte_to_dpcd(dp, 326 DP_TRAINING_PATTERN_SET, 327 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); 328 if (retval) 329 return retval; 330 331 for (lane = 0; lane < lane_count; lane++) 332 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | 333 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 334 335 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 336 lane_count, buf); 337 338 return retval; 339} 340 341static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) 342{ 343 int shift = (lane & 1) * 4; 344 u8 link_value = link_status[lane>>1]; 345 346 return (link_value >> shift) & 0xf; 347} 348 349static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) 350{ 351 int lane; 352 u8 lane_status; 353 354 for (lane = 0; lane < lane_count; lane++) { 355 lane_status = exynos_dp_get_lane_status(link_status, lane); 356 if ((lane_status & DP_LANE_CR_DONE) == 0) 357 return -EINVAL; 358 } 359 return 0; 360} 361 362static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, 363 int lane_count) 364{ 365 int lane; 366 u8 lane_status; 367 368 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) 369 return -EINVAL; 370 371 for (lane = 0; lane < lane_count; lane++) { 372 lane_status = exynos_dp_get_lane_status(link_status, lane); 373 lane_status &= DP_CHANNEL_EQ_BITS; 374 if (lane_status != DP_CHANNEL_EQ_BITS) 375 return -EINVAL; 376 } 377 378 return 0; 379} 380 381static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], 382 int lane) 383{ 384 int shift = (lane & 1) * 4; 385 u8 link_value = adjust_request[lane>>1]; 386 387 return (link_value >> shift) & 0x3; 388} 389 390static unsigned char exynos_dp_get_adjust_request_pre_emphasis( 391 u8 adjust_request[2], 392 int lane) 393{ 394 int shift = (lane & 1) * 4; 395 u8 link_value = adjust_request[lane>>1]; 396 397 return ((link_value >> shift) & 0xc) >> 2; 398} 399 400static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, 401 u8 training_lane_set, int lane) 402{ 403 switch (lane) { 404 case 0: 405 exynos_dp_set_lane0_link_training(dp, training_lane_set); 406 break; 407 case 1: 408 exynos_dp_set_lane1_link_training(dp, training_lane_set); 409 break; 410 411 case 2: 412 exynos_dp_set_lane2_link_training(dp, training_lane_set); 413 break; 414 415 case 3: 416 exynos_dp_set_lane3_link_training(dp, training_lane_set); 417 break; 418 } 419} 420 421static unsigned int exynos_dp_get_lane_link_training( 422 struct exynos_dp_device *dp, 423 int lane) 424{ 425 u32 reg; 426 427 switch (lane) { 428 case 0: 429 reg = exynos_dp_get_lane0_link_training(dp); 430 break; 431 case 1: 432 reg = exynos_dp_get_lane1_link_training(dp); 433 break; 434 case 2: 435 reg = exynos_dp_get_lane2_link_training(dp); 436 break; 437 case 3: 438 reg = exynos_dp_get_lane3_link_training(dp); 439 break; 440 default: 441 WARN_ON(1); 442 return 0; 443 } 444 445 return reg; 446} 447 448static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) 449{ 450 exynos_dp_training_pattern_dis(dp); 451 exynos_dp_set_enhanced_mode(dp); 452 453 dp->link_train.lt_state = FAILED; 454} 455 456static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, 457 u8 adjust_request[2]) 458{ 459 int lane, lane_count; 460 u8 voltage_swing, pre_emphasis, training_lane; 461 462 lane_count = dp->link_train.lane_count; 463 for (lane = 0; lane < lane_count; lane++) { 464 voltage_swing = exynos_dp_get_adjust_request_voltage( 465 adjust_request, lane); 466 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( 467 adjust_request, lane); 468 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | 469 DPCD_PRE_EMPHASIS_SET(pre_emphasis); 470 471 if (voltage_swing == VOLTAGE_LEVEL_3) 472 training_lane |= DP_TRAIN_MAX_SWING_REACHED; 473 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) 474 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 475 476 dp->link_train.training_lane[lane] = training_lane; 477 } 478} 479 480static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) 481{ 482 int lane, lane_count, retval; 483 u8 voltage_swing, pre_emphasis, training_lane; 484 u8 link_status[2], adjust_request[2]; 485 486 usleep_range(100, 101); 487 488 lane_count = dp->link_train.lane_count; 489 490 retval = exynos_dp_read_bytes_from_dpcd(dp, 491 DP_LANE0_1_STATUS, 2, link_status); 492 if (retval) 493 return retval; 494 495 retval = exynos_dp_read_bytes_from_dpcd(dp, 496 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 497 if (retval) 498 return retval; 499 500 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { 501 /* set training pattern 2 for EQ */ 502 exynos_dp_set_training_pattern(dp, TRAINING_PTN2); 503 504 retval = exynos_dp_write_byte_to_dpcd(dp, 505 DP_TRAINING_PATTERN_SET, 506 DP_LINK_SCRAMBLING_DISABLE | 507 DP_TRAINING_PATTERN_2); 508 if (retval) 509 return retval; 510 511 dev_info(dp->dev, "Link Training Clock Recovery success\n"); 512 dp->link_train.lt_state = EQUALIZER_TRAINING; 513 } else { 514 for (lane = 0; lane < lane_count; lane++) { 515 training_lane = exynos_dp_get_lane_link_training( 516 dp, lane); 517 voltage_swing = exynos_dp_get_adjust_request_voltage( 518 adjust_request, lane); 519 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( 520 adjust_request, lane); 521 522 if (DPCD_VOLTAGE_SWING_GET(training_lane) == 523 voltage_swing && 524 DPCD_PRE_EMPHASIS_GET(training_lane) == 525 pre_emphasis) 526 dp->link_train.cr_loop[lane]++; 527 528 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || 529 voltage_swing == VOLTAGE_LEVEL_3 || 530 pre_emphasis == PRE_EMPHASIS_LEVEL_3) { 531 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", 532 dp->link_train.cr_loop[lane], 533 voltage_swing, pre_emphasis); 534 exynos_dp_reduce_link_rate(dp); 535 return -EIO; 536 } 537 } 538 } 539 540 exynos_dp_get_adjust_training_lane(dp, adjust_request); 541 542 for (lane = 0; lane < lane_count; lane++) 543 exynos_dp_set_lane_link_training(dp, 544 dp->link_train.training_lane[lane], lane); 545 546 retval = exynos_dp_write_bytes_to_dpcd(dp, 547 DP_TRAINING_LANE0_SET, lane_count, 548 dp->link_train.training_lane); 549 if (retval) 550 return retval; 551 552 return retval; 553} 554 555static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) 556{ 557 int lane, lane_count, retval; 558 u32 reg; 559 u8 link_align, link_status[2], adjust_request[2]; 560 561 usleep_range(400, 401); 562 563 lane_count = dp->link_train.lane_count; 564 565 retval = exynos_dp_read_bytes_from_dpcd(dp, 566 DP_LANE0_1_STATUS, 2, link_status); 567 if (retval) 568 return retval; 569 570 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { 571 exynos_dp_reduce_link_rate(dp); 572 return -EIO; 573 } 574 575 retval = exynos_dp_read_bytes_from_dpcd(dp, 576 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); 577 if (retval) 578 return retval; 579 580 retval = exynos_dp_read_byte_from_dpcd(dp, 581 DP_LANE_ALIGN_STATUS_UPDATED, &link_align); 582 if (retval) 583 return retval; 584 585 exynos_dp_get_adjust_training_lane(dp, adjust_request); 586 587 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) { 588 /* traing pattern Set to Normal */ 589 exynos_dp_training_pattern_dis(dp); 590 591 dev_info(dp->dev, "Link Training success!\n"); 592 593 exynos_dp_get_link_bandwidth(dp, ®); 594 dp->link_train.link_rate = reg; 595 dev_dbg(dp->dev, "final bandwidth = %.2x\n", 596 dp->link_train.link_rate); 597 598 exynos_dp_get_lane_count(dp, ®); 599 dp->link_train.lane_count = reg; 600 dev_dbg(dp->dev, "final lane count = %.2x\n", 601 dp->link_train.lane_count); 602 603 /* set enhanced mode if available */ 604 exynos_dp_set_enhanced_mode(dp); 605 dp->link_train.lt_state = FINISHED; 606 607 return 0; 608 } 609 610 /* not all locked */ 611 dp->link_train.eq_loop++; 612 613 if (dp->link_train.eq_loop > MAX_EQ_LOOP) { 614 dev_err(dp->dev, "EQ Max loop\n"); 615 exynos_dp_reduce_link_rate(dp); 616 return -EIO; 617 } 618 619 for (lane = 0; lane < lane_count; lane++) 620 exynos_dp_set_lane_link_training(dp, 621 dp->link_train.training_lane[lane], lane); 622 623 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 624 lane_count, dp->link_train.training_lane); 625 626 return retval; 627} 628 629static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, 630 u8 *bandwidth) 631{ 632 u8 data; 633 634 /* 635 * For DP rev.1.1, Maximum link rate of Main Link lanes 636 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps 637 */ 638 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); 639 *bandwidth = data; 640} 641 642static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, 643 u8 *lane_count) 644{ 645 u8 data; 646 647 /* 648 * For DP rev.1.1, Maximum number of Main Link lanes 649 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes 650 */ 651 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); 652 *lane_count = DPCD_MAX_LANE_COUNT(data); 653} 654 655static void exynos_dp_init_training(struct exynos_dp_device *dp, 656 enum link_lane_count_type max_lane, 657 enum link_rate_type max_rate) 658{ 659 /* 660 * MACRO_RST must be applied after the PLL_LOCK to avoid 661 * the DP inter pair skew issue for at least 10 us 662 */ 663 exynos_dp_reset_macro(dp); 664 665 /* Initialize by reading RX's DPCD */ 666 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); 667 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); 668 669 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && 670 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { 671 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", 672 dp->link_train.link_rate); 673 dp->link_train.link_rate = LINK_RATE_1_62GBPS; 674 } 675 676 if (dp->link_train.lane_count == 0) { 677 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", 678 dp->link_train.lane_count); 679 dp->link_train.lane_count = (u8)LANE_COUNT1; 680 } 681 682 /* Setup TX lane count & rate */ 683 if (dp->link_train.lane_count > max_lane) 684 dp->link_train.lane_count = max_lane; 685 if (dp->link_train.link_rate > max_rate) 686 dp->link_train.link_rate = max_rate; 687 688 /* All DP analog module power up */ 689 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); 690} 691 692static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) 693{ 694 int retval = 0, training_finished = 0; 695 696 dp->link_train.lt_state = START; 697 698 /* Process here */ 699 while (!retval && !training_finished) { 700 switch (dp->link_train.lt_state) { 701 case START: 702 retval = exynos_dp_link_start(dp); 703 if (retval) 704 dev_err(dp->dev, "LT link start failed!\n"); 705 break; 706 case CLOCK_RECOVERY: 707 retval = exynos_dp_process_clock_recovery(dp); 708 if (retval) 709 dev_err(dp->dev, "LT CR failed!\n"); 710 break; 711 case EQUALIZER_TRAINING: 712 retval = exynos_dp_process_equalizer_training(dp); 713 if (retval) 714 dev_err(dp->dev, "LT EQ failed!\n"); 715 break; 716 case FINISHED: 717 training_finished = 1; 718 break; 719 case FAILED: 720 return -EREMOTEIO; 721 } 722 } 723 if (retval) 724 dev_err(dp->dev, "eDP link training failed (%d)\n", retval); 725 726 return retval; 727} 728 729static int exynos_dp_set_link_train(struct exynos_dp_device *dp, 730 u32 count, 731 u32 bwtype) 732{ 733 int i; 734 int retval; 735 736 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { 737 exynos_dp_init_training(dp, count, bwtype); 738 retval = exynos_dp_sw_link_training(dp); 739 if (retval == 0) 740 break; 741 742 usleep_range(100, 110); 743 } 744 745 return retval; 746} 747 748static int exynos_dp_config_video(struct exynos_dp_device *dp) 749{ 750 int retval = 0; 751 int timeout_loop = 0; 752 int done_count = 0; 753 754 exynos_dp_config_video_slave_mode(dp); 755 756 exynos_dp_set_video_color_format(dp); 757 758 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 759 dev_err(dp->dev, "PLL is not locked yet.\n"); 760 return -EINVAL; 761 } 762 763 for (;;) { 764 timeout_loop++; 765 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) 766 break; 767 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 768 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 769 return -ETIMEDOUT; 770 } 771 772 usleep_range(1, 2); 773 } 774 775 /* Set to use the register calculated M/N video */ 776 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); 777 778 /* For video bist, Video timing must be generated by register */ 779 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); 780 781 /* Disable video mute */ 782 exynos_dp_enable_video_mute(dp, 0); 783 784 /* Configure video slave mode */ 785 exynos_dp_enable_video_master(dp, 0); 786 787 /* Enable video */ 788 exynos_dp_start_video(dp); 789 790 timeout_loop = 0; 791 792 for (;;) { 793 timeout_loop++; 794 if (exynos_dp_is_video_stream_on(dp) == 0) { 795 done_count++; 796 if (done_count > 10) 797 break; 798 } else if (done_count) { 799 done_count = 0; 800 } 801 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 802 dev_err(dp->dev, "Timeout of video streamclk ok\n"); 803 return -ETIMEDOUT; 804 } 805 806 usleep_range(1000, 1001); 807 } 808 809 if (retval != 0) 810 dev_err(dp->dev, "Video stream is not detected!\n"); 811 812 return retval; 813} 814 815static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) 816{ 817 u8 data; 818 819 if (enable) { 820 exynos_dp_enable_scrambling(dp); 821 822 exynos_dp_read_byte_from_dpcd(dp, 823 DP_TRAINING_PATTERN_SET, 824 &data); 825 exynos_dp_write_byte_to_dpcd(dp, 826 DP_TRAINING_PATTERN_SET, 827 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); 828 } else { 829 exynos_dp_disable_scrambling(dp); 830 831 exynos_dp_read_byte_from_dpcd(dp, 832 DP_TRAINING_PATTERN_SET, 833 &data); 834 exynos_dp_write_byte_to_dpcd(dp, 835 DP_TRAINING_PATTERN_SET, 836 (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); 837 } 838} 839 840static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) 841{ 842 struct exynos_dp_device *dp = arg; 843 844 enum dp_irq_type irq_type; 845 846 irq_type = exynos_dp_get_irq_type(dp); 847 switch (irq_type) { 848 case DP_IRQ_TYPE_HP_CABLE_IN: 849 dev_dbg(dp->dev, "Received irq - cable in\n"); 850 schedule_work(&dp->hotplug_work); 851 exynos_dp_clear_hotplug_interrupts(dp); 852 break; 853 case DP_IRQ_TYPE_HP_CABLE_OUT: 854 dev_dbg(dp->dev, "Received irq - cable out\n"); 855 exynos_dp_clear_hotplug_interrupts(dp); 856 break; 857 case DP_IRQ_TYPE_HP_CHANGE: 858 /* 859 * We get these change notifications once in a while, but there 860 * is nothing we can do with them. Just ignore it for now and 861 * only handle cable changes. 862 */ 863 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n"); 864 exynos_dp_clear_hotplug_interrupts(dp); 865 break; 866 default: 867 dev_err(dp->dev, "Received irq - unknown type!\n"); 868 break; 869 } 870 return IRQ_HANDLED; 871} 872 873static void exynos_dp_hotplug(struct work_struct *work) 874{ 875 struct exynos_dp_device *dp; 876 877 dp = container_of(work, struct exynos_dp_device, hotplug_work); 878 879 if (dp->drm_dev) 880 drm_helper_hpd_irq_event(dp->drm_dev); 881} 882 883static void exynos_dp_commit(struct exynos_drm_display *display) 884{ 885 struct exynos_dp_device *dp = display->ctx; 886 int ret; 887 888 /* Keep the panel disabled while we configure video */ 889 if (dp->panel) { 890 if (drm_panel_disable(dp->panel)) 891 DRM_ERROR("failed to disable the panel\n"); 892 } 893 894 ret = exynos_dp_detect_hpd(dp); 895 if (ret) { 896 /* Cable has been disconnected, we're done */ 897 return; 898 } 899 900 ret = exynos_dp_handle_edid(dp); 901 if (ret) { 902 dev_err(dp->dev, "unable to handle edid\n"); 903 return; 904 } 905 906 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count, 907 dp->video_info->link_rate); 908 if (ret) { 909 dev_err(dp->dev, "unable to do link train\n"); 910 return; 911 } 912 913 exynos_dp_enable_scramble(dp, 1); 914 exynos_dp_enable_rx_to_enhanced_mode(dp, 1); 915 exynos_dp_enable_enhanced_mode(dp, 1); 916 917 exynos_dp_set_lane_count(dp, dp->video_info->lane_count); 918 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); 919 920 exynos_dp_init_video(dp); 921 ret = exynos_dp_config_video(dp); 922 if (ret) 923 dev_err(dp->dev, "unable to config video\n"); 924 925 /* Safe to enable the panel now */ 926 if (dp->panel) { 927 if (drm_panel_enable(dp->panel)) 928 DRM_ERROR("failed to enable the panel\n"); 929 } 930} 931 932static enum drm_connector_status exynos_dp_detect( 933 struct drm_connector *connector, bool force) 934{ 935 return connector_status_connected; 936} 937 938static void exynos_dp_connector_destroy(struct drm_connector *connector) 939{ 940 drm_connector_unregister(connector); 941 drm_connector_cleanup(connector); 942} 943 944static struct drm_connector_funcs exynos_dp_connector_funcs = { 945 .dpms = drm_helper_connector_dpms, 946 .fill_modes = drm_helper_probe_single_connector_modes, 947 .detect = exynos_dp_detect, 948 .destroy = exynos_dp_connector_destroy, 949}; 950 951static int exynos_dp_get_modes(struct drm_connector *connector) 952{ 953 struct exynos_dp_device *dp = ctx_from_connector(connector); 954 struct drm_display_mode *mode; 955 956 if (dp->panel) 957 return drm_panel_get_modes(dp->panel); 958 959 mode = drm_mode_create(connector->dev); 960 if (!mode) { 961 DRM_ERROR("failed to create a new display mode.\n"); 962 return 0; 963 } 964 965 drm_display_mode_from_videomode(&dp->priv.vm, mode); 966 mode->width_mm = dp->priv.width_mm; 967 mode->height_mm = dp->priv.height_mm; 968 connector->display_info.width_mm = mode->width_mm; 969 connector->display_info.height_mm = mode->height_mm; 970 971 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 972 drm_mode_set_name(mode); 973 drm_mode_probed_add(connector, mode); 974 975 return 1; 976} 977 978static struct drm_encoder *exynos_dp_best_encoder( 979 struct drm_connector *connector) 980{ 981 struct exynos_dp_device *dp = ctx_from_connector(connector); 982 983 return dp->encoder; 984} 985 986static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = { 987 .get_modes = exynos_dp_get_modes, 988 .best_encoder = exynos_dp_best_encoder, 989}; 990 991static bool find_bridge(const char *compat, struct bridge_init *bridge) 992{ 993 bridge->client = NULL; 994 bridge->node = of_find_compatible_node(NULL, NULL, compat); 995 if (!bridge->node) 996 return false; 997 998 bridge->client = of_find_i2c_device_by_node(bridge->node); 999 if (!bridge->client) 1000 return false; 1001 1002 return true; 1003} 1004 1005/* returns the number of bridges attached */ 1006static int exynos_drm_attach_lcd_bridge(struct drm_device *dev, 1007 struct drm_encoder *encoder) 1008{ 1009 struct bridge_init bridge; 1010 int ret; 1011 1012 if (find_bridge("nxp,ptn3460", &bridge)) { 1013 ret = ptn3460_init(dev, encoder, bridge.client, bridge.node); 1014 if (!ret) 1015 return 1; 1016 } 1017 return 0; 1018} 1019 1020static int exynos_dp_create_connector(struct exynos_drm_display *display, 1021 struct drm_encoder *encoder) 1022{ 1023 struct exynos_dp_device *dp = display->ctx; 1024 struct drm_connector *connector = &dp->connector; 1025 int ret; 1026 1027 dp->encoder = encoder; 1028 1029 /* Pre-empt DP connector creation if there's a bridge */ 1030 ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder); 1031 if (ret) 1032 return 0; 1033 1034 connector->polled = DRM_CONNECTOR_POLL_HPD; 1035 1036 ret = drm_connector_init(dp->drm_dev, connector, 1037 &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP); 1038 if (ret) { 1039 DRM_ERROR("Failed to initialize connector with drm\n"); 1040 return ret; 1041 } 1042 1043 drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs); 1044 drm_connector_register(connector); 1045 drm_mode_connector_attach_encoder(connector, encoder); 1046 1047 if (dp->panel) 1048 ret = drm_panel_attach(dp->panel, &dp->connector); 1049 1050 return ret; 1051} 1052 1053static void exynos_dp_phy_init(struct exynos_dp_device *dp) 1054{ 1055 if (dp->phy) { 1056 phy_power_on(dp->phy); 1057 } else if (dp->phy_addr) { 1058 u32 reg; 1059 1060 reg = __raw_readl(dp->phy_addr); 1061 reg |= dp->enable_mask; 1062 __raw_writel(reg, dp->phy_addr); 1063 } 1064} 1065 1066static void exynos_dp_phy_exit(struct exynos_dp_device *dp) 1067{ 1068 if (dp->phy) { 1069 phy_power_off(dp->phy); 1070 } else if (dp->phy_addr) { 1071 u32 reg; 1072 1073 reg = __raw_readl(dp->phy_addr); 1074 reg &= ~(dp->enable_mask); 1075 __raw_writel(reg, dp->phy_addr); 1076 } 1077} 1078 1079static void exynos_dp_poweron(struct exynos_drm_display *display) 1080{ 1081 struct exynos_dp_device *dp = display->ctx; 1082 1083 if (dp->dpms_mode == DRM_MODE_DPMS_ON) 1084 return; 1085 1086 if (dp->panel) { 1087 if (drm_panel_prepare(dp->panel)) { 1088 DRM_ERROR("failed to setup the panel\n"); 1089 return; 1090 } 1091 } 1092 1093 clk_prepare_enable(dp->clock); 1094 exynos_dp_phy_init(dp); 1095 exynos_dp_init_dp(dp); 1096 enable_irq(dp->irq); 1097 exynos_dp_commit(display); 1098} 1099 1100static void exynos_dp_poweroff(struct exynos_drm_display *display) 1101{ 1102 struct exynos_dp_device *dp = display->ctx; 1103 1104 if (dp->dpms_mode != DRM_MODE_DPMS_ON) 1105 return; 1106 1107 if (dp->panel) { 1108 if (drm_panel_disable(dp->panel)) { 1109 DRM_ERROR("failed to disable the panel\n"); 1110 return; 1111 } 1112 } 1113 1114 disable_irq(dp->irq); 1115 flush_work(&dp->hotplug_work); 1116 exynos_dp_phy_exit(dp); 1117 clk_disable_unprepare(dp->clock); 1118 1119 if (dp->panel) { 1120 if (drm_panel_unprepare(dp->panel)) 1121 DRM_ERROR("failed to turnoff the panel\n"); 1122 } 1123} 1124 1125static void exynos_dp_dpms(struct exynos_drm_display *display, int mode) 1126{ 1127 struct exynos_dp_device *dp = display->ctx; 1128 1129 switch (mode) { 1130 case DRM_MODE_DPMS_ON: 1131 exynos_dp_poweron(display); 1132 break; 1133 case DRM_MODE_DPMS_STANDBY: 1134 case DRM_MODE_DPMS_SUSPEND: 1135 case DRM_MODE_DPMS_OFF: 1136 exynos_dp_poweroff(display); 1137 break; 1138 default: 1139 break; 1140 } 1141 dp->dpms_mode = mode; 1142} 1143 1144static struct exynos_drm_display_ops exynos_dp_display_ops = { 1145 .create_connector = exynos_dp_create_connector, 1146 .dpms = exynos_dp_dpms, 1147 .commit = exynos_dp_commit, 1148}; 1149 1150static struct exynos_drm_display exynos_dp_display = { 1151 .type = EXYNOS_DISPLAY_TYPE_LCD, 1152 .ops = &exynos_dp_display_ops, 1153}; 1154 1155static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev) 1156{ 1157 struct device_node *dp_node = dev->of_node; 1158 struct video_info *dp_video_config; 1159 1160 dp_video_config = devm_kzalloc(dev, 1161 sizeof(*dp_video_config), GFP_KERNEL); 1162 if (!dp_video_config) 1163 return ERR_PTR(-ENOMEM); 1164 1165 dp_video_config->h_sync_polarity = 1166 of_property_read_bool(dp_node, "hsync-active-high"); 1167 1168 dp_video_config->v_sync_polarity = 1169 of_property_read_bool(dp_node, "vsync-active-high"); 1170 1171 dp_video_config->interlaced = 1172 of_property_read_bool(dp_node, "interlaced"); 1173 1174 if (of_property_read_u32(dp_node, "samsung,color-space", 1175 &dp_video_config->color_space)) { 1176 dev_err(dev, "failed to get color-space\n"); 1177 return ERR_PTR(-EINVAL); 1178 } 1179 1180 if (of_property_read_u32(dp_node, "samsung,dynamic-range", 1181 &dp_video_config->dynamic_range)) { 1182 dev_err(dev, "failed to get dynamic-range\n"); 1183 return ERR_PTR(-EINVAL); 1184 } 1185 1186 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff", 1187 &dp_video_config->ycbcr_coeff)) { 1188 dev_err(dev, "failed to get ycbcr-coeff\n"); 1189 return ERR_PTR(-EINVAL); 1190 } 1191 1192 if (of_property_read_u32(dp_node, "samsung,color-depth", 1193 &dp_video_config->color_depth)) { 1194 dev_err(dev, "failed to get color-depth\n"); 1195 return ERR_PTR(-EINVAL); 1196 } 1197 1198 if (of_property_read_u32(dp_node, "samsung,link-rate", 1199 &dp_video_config->link_rate)) { 1200 dev_err(dev, "failed to get link-rate\n"); 1201 return ERR_PTR(-EINVAL); 1202 } 1203 1204 if (of_property_read_u32(dp_node, "samsung,lane-count", 1205 &dp_video_config->lane_count)) { 1206 dev_err(dev, "failed to get lane-count\n"); 1207 return ERR_PTR(-EINVAL); 1208 } 1209 1210 return dp_video_config; 1211} 1212 1213static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) 1214{ 1215 struct device_node *dp_phy_node = of_node_get(dp->dev->of_node); 1216 u32 phy_base; 1217 int ret = 0; 1218 1219 dp_phy_node = of_find_node_by_name(dp_phy_node, "dptx-phy"); 1220 if (!dp_phy_node) { 1221 dp->phy = devm_phy_get(dp->dev, "dp"); 1222 return PTR_ERR_OR_ZERO(dp->phy); 1223 } 1224 1225 if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) { 1226 dev_err(dp->dev, "failed to get reg for dptx-phy\n"); 1227 ret = -EINVAL; 1228 goto err; 1229 } 1230 1231 if (of_property_read_u32(dp_phy_node, "samsung,enable-mask", 1232 &dp->enable_mask)) { 1233 dev_err(dp->dev, "failed to get enable-mask for dptx-phy\n"); 1234 ret = -EINVAL; 1235 goto err; 1236 } 1237 1238 dp->phy_addr = ioremap(phy_base, SZ_4); 1239 if (!dp->phy_addr) { 1240 dev_err(dp->dev, "failed to ioremap dp-phy\n"); 1241 ret = -ENOMEM; 1242 goto err; 1243 } 1244 1245err: 1246 of_node_put(dp_phy_node); 1247 1248 return ret; 1249} 1250 1251static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp) 1252{ 1253 int ret; 1254 1255 ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm, 1256 OF_USE_NATIVE_MODE); 1257 if (ret) { 1258 DRM_ERROR("failed: of_get_videomode() : %d\n", ret); 1259 return ret; 1260 } 1261 return 0; 1262} 1263 1264static int exynos_dp_bind(struct device *dev, struct device *master, void *data) 1265{ 1266 struct platform_device *pdev = to_platform_device(dev); 1267 struct drm_device *drm_dev = data; 1268 struct resource *res; 1269 struct exynos_dp_device *dp = exynos_dp_display.ctx; 1270 unsigned int irq_flags; 1271 int ret = 0; 1272 1273 dp->dev = &pdev->dev; 1274 dp->dpms_mode = DRM_MODE_DPMS_OFF; 1275 1276 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev); 1277 if (IS_ERR(dp->video_info)) 1278 return PTR_ERR(dp->video_info); 1279 1280 ret = exynos_dp_dt_parse_phydata(dp); 1281 if (ret) 1282 return ret; 1283 1284 if (!dp->panel) { 1285 ret = exynos_dp_dt_parse_panel(dp); 1286 if (ret) 1287 return ret; 1288 } 1289 1290 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1291 if (IS_ERR(dp->clock)) { 1292 dev_err(&pdev->dev, "failed to get clock\n"); 1293 return PTR_ERR(dp->clock); 1294 } 1295 1296 clk_prepare_enable(dp->clock); 1297 1298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1299 1300 dp->reg_base = devm_ioremap_resource(&pdev->dev, res); 1301 if (IS_ERR(dp->reg_base)) 1302 return PTR_ERR(dp->reg_base); 1303 1304 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0); 1305 1306 if (gpio_is_valid(dp->hpd_gpio)) { 1307 /* 1308 * Set up the hotplug GPIO from the device tree as an interrupt. 1309 * Simply specifying a different interrupt in the device tree 1310 * doesn't work since we handle hotplug rather differently when 1311 * using a GPIO. We also need the actual GPIO specifier so 1312 * that we can get the current state of the GPIO. 1313 */ 1314 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, 1315 "hpd_gpio"); 1316 if (ret) { 1317 dev_err(&pdev->dev, "failed to get hpd gpio\n"); 1318 return ret; 1319 } 1320 dp->irq = gpio_to_irq(dp->hpd_gpio); 1321 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; 1322 } else { 1323 dp->hpd_gpio = -ENODEV; 1324 dp->irq = platform_get_irq(pdev, 0); 1325 irq_flags = 0; 1326 } 1327 1328 if (dp->irq == -ENXIO) { 1329 dev_err(&pdev->dev, "failed to get irq\n"); 1330 return -ENODEV; 1331 } 1332 1333 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); 1334 1335 exynos_dp_phy_init(dp); 1336 1337 exynos_dp_init_dp(dp); 1338 1339 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 1340 irq_flags, "exynos-dp", dp); 1341 if (ret) { 1342 dev_err(&pdev->dev, "failed to request irq\n"); 1343 return ret; 1344 } 1345 disable_irq(dp->irq); 1346 1347 dp->drm_dev = drm_dev; 1348 1349 platform_set_drvdata(pdev, &exynos_dp_display); 1350 1351 return exynos_drm_create_enc_conn(drm_dev, &exynos_dp_display); 1352} 1353 1354static void exynos_dp_unbind(struct device *dev, struct device *master, 1355 void *data) 1356{ 1357 struct exynos_drm_display *display = dev_get_drvdata(dev); 1358 1359 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF); 1360} 1361 1362static const struct component_ops exynos_dp_ops = { 1363 .bind = exynos_dp_bind, 1364 .unbind = exynos_dp_unbind, 1365}; 1366 1367static int exynos_dp_probe(struct platform_device *pdev) 1368{ 1369 struct device *dev = &pdev->dev; 1370 struct device_node *panel_node; 1371 struct exynos_dp_device *dp; 1372 int ret; 1373 1374 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR, 1375 exynos_dp_display.type); 1376 if (ret) 1377 return ret; 1378 1379 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), 1380 GFP_KERNEL); 1381 if (!dp) 1382 return -ENOMEM; 1383 1384 panel_node = of_parse_phandle(dev->of_node, "panel", 0); 1385 if (panel_node) { 1386 dp->panel = of_drm_find_panel(panel_node); 1387 of_node_put(panel_node); 1388 if (!dp->panel) 1389 return -EPROBE_DEFER; 1390 } 1391 1392 exynos_dp_display.ctx = dp; 1393 1394 ret = component_add(&pdev->dev, &exynos_dp_ops); 1395 if (ret) 1396 exynos_drm_component_del(&pdev->dev, 1397 EXYNOS_DEVICE_TYPE_CONNECTOR); 1398 1399 return ret; 1400} 1401 1402static int exynos_dp_remove(struct platform_device *pdev) 1403{ 1404 component_del(&pdev->dev, &exynos_dp_ops); 1405 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); 1406 1407 return 0; 1408} 1409 1410#ifdef CONFIG_PM_SLEEP 1411static int exynos_dp_suspend(struct device *dev) 1412{ 1413 struct platform_device *pdev = to_platform_device(dev); 1414 struct exynos_drm_display *display = platform_get_drvdata(pdev); 1415 1416 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF); 1417 return 0; 1418} 1419 1420static int exynos_dp_resume(struct device *dev) 1421{ 1422 struct platform_device *pdev = to_platform_device(dev); 1423 struct exynos_drm_display *display = platform_get_drvdata(pdev); 1424 1425 exynos_dp_dpms(display, DRM_MODE_DPMS_ON); 1426 return 0; 1427} 1428#endif 1429 1430static const struct dev_pm_ops exynos_dp_pm_ops = { 1431 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) 1432}; 1433 1434static const struct of_device_id exynos_dp_match[] = { 1435 { .compatible = "samsung,exynos5-dp" }, 1436 {}, 1437}; 1438MODULE_DEVICE_TABLE(of, exynos_dp_match); 1439 1440struct platform_driver dp_driver = { 1441 .probe = exynos_dp_probe, 1442 .remove = exynos_dp_remove, 1443 .driver = { 1444 .name = "exynos-dp", 1445 .owner = THIS_MODULE, 1446 .pm = &exynos_dp_pm_ops, 1447 .of_match_table = exynos_dp_match, 1448 }, 1449}; 1450 1451MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); 1452MODULE_DESCRIPTION("Samsung SoC DP Driver"); 1453MODULE_LICENSE("GPL v2"); 1454