i915_gpu_error.c revision 864c61811c7c3d877e8fb3162eeb8616f2c8e9b8
1/* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30#include <generated/utsrelease.h> 31#include "i915_drv.h" 32 33static const char *yesno(int v) 34{ 35 return v ? "yes" : "no"; 36} 37 38static const char *ring_str(int ring) 39{ 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 case VCS2: return "bsd2"; 46 default: return ""; 47 } 48} 49 50static const char *pin_flag(int pinned) 51{ 52 if (pinned > 0) 53 return " P"; 54 else if (pinned < 0) 55 return " p"; 56 else 57 return ""; 58} 59 60static const char *tiling_flag(int tiling) 61{ 62 switch (tiling) { 63 default: 64 case I915_TILING_NONE: return ""; 65 case I915_TILING_X: return " X"; 66 case I915_TILING_Y: return " Y"; 67 } 68} 69 70static const char *dirty_flag(int dirty) 71{ 72 return dirty ? " dirty" : ""; 73} 74 75static const char *purgeable_flag(int purgeable) 76{ 77 return purgeable ? " purgeable" : ""; 78} 79 80static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 81{ 82 83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 84 e->err = -ENOSPC; 85 return false; 86 } 87 88 if (e->bytes == e->size - 1 || e->err) 89 return false; 90 91 return true; 92} 93 94static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 95 unsigned len) 96{ 97 if (e->pos + len <= e->start) { 98 e->pos += len; 99 return false; 100 } 101 102 /* First vsnprintf needs to fit in its entirety for memmove */ 103 if (len >= e->size) { 104 e->err = -EIO; 105 return false; 106 } 107 108 return true; 109} 110 111static void __i915_error_advance(struct drm_i915_error_state_buf *e, 112 unsigned len) 113{ 114 /* If this is first printf in this window, adjust it so that 115 * start position matches start of the buffer 116 */ 117 118 if (e->pos < e->start) { 119 const size_t off = e->start - e->pos; 120 121 /* Should not happen but be paranoid */ 122 if (off > len || e->bytes) { 123 e->err = -EIO; 124 return; 125 } 126 127 memmove(e->buf, e->buf + off, len - off); 128 e->bytes = len - off; 129 e->pos = e->start; 130 return; 131 } 132 133 e->bytes += len; 134 e->pos += len; 135} 136 137static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 138 const char *f, va_list args) 139{ 140 unsigned len; 141 142 if (!__i915_error_ok(e)) 143 return; 144 145 /* Seek the first printf which is hits start position */ 146 if (e->pos < e->start) { 147 va_list tmp; 148 149 va_copy(tmp, args); 150 len = vsnprintf(NULL, 0, f, tmp); 151 va_end(tmp); 152 153 if (!__i915_error_seek(e, len)) 154 return; 155 } 156 157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 158 if (len >= e->size - e->bytes) 159 len = e->size - e->bytes - 1; 160 161 __i915_error_advance(e, len); 162} 163 164static void i915_error_puts(struct drm_i915_error_state_buf *e, 165 const char *str) 166{ 167 unsigned len; 168 169 if (!__i915_error_ok(e)) 170 return; 171 172 len = strlen(str); 173 174 /* Seek the first printf which is hits start position */ 175 if (e->pos < e->start) { 176 if (!__i915_error_seek(e, len)) 177 return; 178 } 179 180 if (len >= e->size - e->bytes) 181 len = e->size - e->bytes - 1; 182 memcpy(e->buf + e->bytes, str, len); 183 184 __i915_error_advance(e, len); 185} 186 187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 188#define err_puts(e, s) i915_error_puts(e, s) 189 190static void print_error_buffers(struct drm_i915_error_state_buf *m, 191 const char *name, 192 struct drm_i915_error_buffer *err, 193 int count) 194{ 195 err_printf(m, "%s [%d]:\n", name, count); 196 197 while (count--) { 198 err_printf(m, " %08x %8u %02x %02x %x %x", 199 err->gtt_offset, 200 err->size, 201 err->read_domains, 202 err->write_domain, 203 err->rseqno, err->wseqno); 204 err_puts(m, pin_flag(err->pinned)); 205 err_puts(m, tiling_flag(err->tiling)); 206 err_puts(m, dirty_flag(err->dirty)); 207 err_puts(m, purgeable_flag(err->purgeable)); 208 err_puts(m, err->userptr ? " userptr" : ""); 209 err_puts(m, err->ring != -1 ? " " : ""); 210 err_puts(m, ring_str(err->ring)); 211 err_puts(m, i915_cache_level_str(err->cache_level)); 212 213 if (err->name) 214 err_printf(m, " (name: %d)", err->name); 215 if (err->fence_reg != I915_FENCE_REG_NONE) 216 err_printf(m, " (fence: %d)", err->fence_reg); 217 218 err_puts(m, "\n"); 219 err++; 220 } 221} 222 223static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 224{ 225 switch (a) { 226 case HANGCHECK_IDLE: 227 return "idle"; 228 case HANGCHECK_WAIT: 229 return "wait"; 230 case HANGCHECK_ACTIVE: 231 return "active"; 232 case HANGCHECK_KICK: 233 return "kick"; 234 case HANGCHECK_HUNG: 235 return "hung"; 236 } 237 238 return "unknown"; 239} 240 241static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 242 struct drm_device *dev, 243 struct drm_i915_error_ring *ring) 244{ 245 if (!ring->valid) 246 return; 247 248 err_printf(m, " HEAD: 0x%08x\n", ring->head); 249 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 250 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 251 err_printf(m, " HWS: 0x%08x\n", ring->hws); 252 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 253 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 254 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 255 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 256 if (INTEL_INFO(dev)->gen >= 4) { 257 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 258 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 259 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 260 } 261 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 262 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 263 lower_32_bits(ring->faddr)); 264 if (INTEL_INFO(dev)->gen >= 6) { 265 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 266 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 267 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 268 ring->semaphore_mboxes[0], 269 ring->semaphore_seqno[0]); 270 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 271 ring->semaphore_mboxes[1], 272 ring->semaphore_seqno[1]); 273 if (HAS_VEBOX(dev)) { 274 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 275 ring->semaphore_mboxes[2], 276 ring->semaphore_seqno[2]); 277 } 278 } 279 if (USES_PPGTT(dev)) { 280 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 281 282 if (INTEL_INFO(dev)->gen >= 8) { 283 int i; 284 for (i = 0; i < 4; i++) 285 err_printf(m, " PDP%d: 0x%016llx\n", 286 i, ring->vm_info.pdp[i]); 287 } else { 288 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 289 ring->vm_info.pp_dir_base); 290 } 291 } 292 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 293 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 294 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 295 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 296 err_printf(m, " hangcheck: %s [%d]\n", 297 hangcheck_action_to_str(ring->hangcheck_action), 298 ring->hangcheck_score); 299} 300 301void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 302{ 303 va_list args; 304 305 va_start(args, f); 306 i915_error_vprintf(e, f, args); 307 va_end(args); 308} 309 310static void print_error_obj(struct drm_i915_error_state_buf *m, 311 struct drm_i915_error_object *obj) 312{ 313 int page, offset, elt; 314 315 for (page = offset = 0; page < obj->page_count; page++) { 316 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 317 err_printf(m, "%08x : %08x\n", offset, 318 obj->pages[page][elt]); 319 offset += 4; 320 } 321 } 322} 323 324int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 325 const struct i915_error_state_file_priv *error_priv) 326{ 327 struct drm_device *dev = error_priv->dev; 328 struct drm_i915_private *dev_priv = dev->dev_private; 329 struct drm_i915_error_state *error = error_priv->error; 330 struct drm_i915_error_object *obj; 331 int i, j, offset, elt; 332 int max_hangcheck_score; 333 334 if (!error) { 335 err_printf(m, "no error state collected\n"); 336 goto out; 337 } 338 339 err_printf(m, "%s\n", error->error_msg); 340 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 341 error->time.tv_usec); 342 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 343 max_hangcheck_score = 0; 344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 345 if (error->ring[i].hangcheck_score > max_hangcheck_score) 346 max_hangcheck_score = error->ring[i].hangcheck_score; 347 } 348 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 349 if (error->ring[i].hangcheck_score == max_hangcheck_score && 350 error->ring[i].pid != -1) { 351 err_printf(m, "Active process (on ring %s): %s [%d]\n", 352 ring_str(i), 353 error->ring[i].comm, 354 error->ring[i].pid); 355 } 356 } 357 err_printf(m, "Reset count: %u\n", error->reset_count); 358 err_printf(m, "Suspend count: %u\n", error->suspend_count); 359 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 360 err_printf(m, "EIR: 0x%08x\n", error->eir); 361 err_printf(m, "IER: 0x%08x\n", error->ier); 362 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 363 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 364 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 365 err_printf(m, "CCID: 0x%08x\n", error->ccid); 366 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 367 368 for (i = 0; i < dev_priv->num_fence_regs; i++) 369 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 370 371 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 372 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 373 error->extra_instdone[i]); 374 375 if (INTEL_INFO(dev)->gen >= 6) { 376 err_printf(m, "ERROR: 0x%08x\n", error->error); 377 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 378 } 379 380 if (INTEL_INFO(dev)->gen == 7) 381 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 382 383 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 384 err_printf(m, "%s command stream:\n", ring_str(i)); 385 i915_ring_error_state(m, dev, &error->ring[i]); 386 } 387 388 if (error->active_bo) 389 print_error_buffers(m, "Active", 390 error->active_bo[0], 391 error->active_bo_count[0]); 392 393 if (error->pinned_bo) 394 print_error_buffers(m, "Pinned", 395 error->pinned_bo[0], 396 error->pinned_bo_count[0]); 397 398 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 399 obj = error->ring[i].batchbuffer; 400 if (obj) { 401 err_puts(m, dev_priv->ring[i].name); 402 if (error->ring[i].pid != -1) 403 err_printf(m, " (submitted by %s [%d])", 404 error->ring[i].comm, 405 error->ring[i].pid); 406 err_printf(m, " --- gtt_offset = 0x%08x\n", 407 obj->gtt_offset); 408 print_error_obj(m, obj); 409 } 410 411 obj = error->ring[i].wa_batchbuffer; 412 if (obj) { 413 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 414 dev_priv->ring[i].name, obj->gtt_offset); 415 print_error_obj(m, obj); 416 } 417 418 if (error->ring[i].num_requests) { 419 err_printf(m, "%s --- %d requests\n", 420 dev_priv->ring[i].name, 421 error->ring[i].num_requests); 422 for (j = 0; j < error->ring[i].num_requests; j++) { 423 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 424 error->ring[i].requests[j].seqno, 425 error->ring[i].requests[j].jiffies, 426 error->ring[i].requests[j].tail); 427 } 428 } 429 430 if ((obj = error->ring[i].ringbuffer)) { 431 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 432 dev_priv->ring[i].name, 433 obj->gtt_offset); 434 print_error_obj(m, obj); 435 } 436 437 if ((obj = error->ring[i].hws_page)) { 438 err_printf(m, "%s --- HW Status = 0x%08x\n", 439 dev_priv->ring[i].name, 440 obj->gtt_offset); 441 offset = 0; 442 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 443 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 444 offset, 445 obj->pages[0][elt], 446 obj->pages[0][elt+1], 447 obj->pages[0][elt+2], 448 obj->pages[0][elt+3]); 449 offset += 16; 450 } 451 } 452 453 if ((obj = error->ring[i].ctx)) { 454 err_printf(m, "%s --- HW Context = 0x%08x\n", 455 dev_priv->ring[i].name, 456 obj->gtt_offset); 457 print_error_obj(m, obj); 458 } 459 } 460 461 if ((obj = error->semaphore_obj)) { 462 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset); 463 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 464 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 465 elt * 4, 466 obj->pages[0][elt], 467 obj->pages[0][elt+1], 468 obj->pages[0][elt+2], 469 obj->pages[0][elt+3]); 470 } 471 } 472 473 if (error->overlay) 474 intel_overlay_print_error_state(m, error->overlay); 475 476 if (error->display) 477 intel_display_print_error_state(m, dev, error->display); 478 479out: 480 if (m->bytes == 0 && m->err) 481 return m->err; 482 483 return 0; 484} 485 486int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 487 size_t count, loff_t pos) 488{ 489 memset(ebuf, 0, sizeof(*ebuf)); 490 491 /* We need to have enough room to store any i915_error_state printf 492 * so that we can move it to start position. 493 */ 494 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 495 ebuf->buf = kmalloc(ebuf->size, 496 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 497 498 if (ebuf->buf == NULL) { 499 ebuf->size = PAGE_SIZE; 500 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 501 } 502 503 if (ebuf->buf == NULL) { 504 ebuf->size = 128; 505 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 506 } 507 508 if (ebuf->buf == NULL) 509 return -ENOMEM; 510 511 ebuf->start = pos; 512 513 return 0; 514} 515 516static void i915_error_object_free(struct drm_i915_error_object *obj) 517{ 518 int page; 519 520 if (obj == NULL) 521 return; 522 523 for (page = 0; page < obj->page_count; page++) 524 kfree(obj->pages[page]); 525 526 kfree(obj); 527} 528 529static void i915_error_state_free(struct kref *error_ref) 530{ 531 struct drm_i915_error_state *error = container_of(error_ref, 532 typeof(*error), ref); 533 int i; 534 535 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 536 i915_error_object_free(error->ring[i].batchbuffer); 537 i915_error_object_free(error->ring[i].ringbuffer); 538 i915_error_object_free(error->ring[i].hws_page); 539 i915_error_object_free(error->ring[i].ctx); 540 kfree(error->ring[i].requests); 541 } 542 543 i915_error_object_free(error->semaphore_obj); 544 kfree(error->active_bo); 545 kfree(error->overlay); 546 kfree(error->display); 547 kfree(error); 548} 549 550static struct drm_i915_error_object * 551i915_error_object_create_sized(struct drm_i915_private *dev_priv, 552 struct drm_i915_gem_object *src, 553 struct i915_address_space *vm, 554 const int num_pages) 555{ 556 struct drm_i915_error_object *dst; 557 int i; 558 u32 reloc_offset; 559 560 if (src == NULL || src->pages == NULL) 561 return NULL; 562 563 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 564 if (dst == NULL) 565 return NULL; 566 567 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); 568 for (i = 0; i < num_pages; i++) { 569 unsigned long flags; 570 void *d; 571 572 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 573 if (d == NULL) 574 goto unwind; 575 576 local_irq_save(flags); 577 if (src->cache_level == I915_CACHE_NONE && 578 reloc_offset < dev_priv->gtt.mappable_end && 579 src->has_global_gtt_mapping && 580 i915_is_ggtt(vm)) { 581 void __iomem *s; 582 583 /* Simply ignore tiling or any overlapping fence. 584 * It's part of the error state, and this hopefully 585 * captures what the GPU read. 586 */ 587 588 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 589 reloc_offset); 590 memcpy_fromio(d, s, PAGE_SIZE); 591 io_mapping_unmap_atomic(s); 592 } else if (src->stolen) { 593 unsigned long offset; 594 595 offset = dev_priv->mm.stolen_base; 596 offset += src->stolen->start; 597 offset += i << PAGE_SHIFT; 598 599 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 600 } else { 601 struct page *page; 602 void *s; 603 604 page = i915_gem_object_get_page(src, i); 605 606 drm_clflush_pages(&page, 1); 607 608 s = kmap_atomic(page); 609 memcpy(d, s, PAGE_SIZE); 610 kunmap_atomic(s); 611 612 drm_clflush_pages(&page, 1); 613 } 614 local_irq_restore(flags); 615 616 dst->pages[i] = d; 617 618 reloc_offset += PAGE_SIZE; 619 } 620 dst->page_count = num_pages; 621 622 return dst; 623 624unwind: 625 while (i--) 626 kfree(dst->pages[i]); 627 kfree(dst); 628 return NULL; 629} 630#define i915_error_object_create(dev_priv, src, vm) \ 631 i915_error_object_create_sized((dev_priv), (src), (vm), \ 632 (src)->base.size>>PAGE_SHIFT) 633 634#define i915_error_ggtt_object_create(dev_priv, src) \ 635 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ 636 (src)->base.size>>PAGE_SHIFT) 637 638static void capture_bo(struct drm_i915_error_buffer *err, 639 struct drm_i915_gem_object *obj) 640{ 641 err->size = obj->base.size; 642 err->name = obj->base.name; 643 err->rseqno = obj->last_read_seqno; 644 err->wseqno = obj->last_write_seqno; 645 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 646 err->read_domains = obj->base.read_domains; 647 err->write_domain = obj->base.write_domain; 648 err->fence_reg = obj->fence_reg; 649 err->pinned = 0; 650 if (i915_gem_obj_is_pinned(obj)) 651 err->pinned = 1; 652 if (obj->user_pin_count > 0) 653 err->pinned = -1; 654 err->tiling = obj->tiling_mode; 655 err->dirty = obj->dirty; 656 err->purgeable = obj->madv != I915_MADV_WILLNEED; 657 err->userptr = obj->userptr.mm != NULL; 658 err->ring = obj->ring ? obj->ring->id : -1; 659 err->cache_level = obj->cache_level; 660} 661 662static u32 capture_active_bo(struct drm_i915_error_buffer *err, 663 int count, struct list_head *head) 664{ 665 struct i915_vma *vma; 666 int i = 0; 667 668 list_for_each_entry(vma, head, mm_list) { 669 capture_bo(err++, vma->obj); 670 if (++i == count) 671 break; 672 } 673 674 return i; 675} 676 677static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 678 int count, struct list_head *head) 679{ 680 struct drm_i915_gem_object *obj; 681 int i = 0; 682 683 list_for_each_entry(obj, head, global_list) { 684 if (!i915_gem_obj_is_pinned(obj)) 685 continue; 686 687 capture_bo(err++, obj); 688 if (++i == count) 689 break; 690 } 691 692 return i; 693} 694 695/* Generate a semi-unique error code. The code is not meant to have meaning, The 696 * code's only purpose is to try to prevent false duplicated bug reports by 697 * grossly estimating a GPU error state. 698 * 699 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 700 * the hang if we could strip the GTT offset information from it. 701 * 702 * It's only a small step better than a random number in its current form. 703 */ 704static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 705 struct drm_i915_error_state *error, 706 int *ring_id) 707{ 708 uint32_t error_code = 0; 709 int i; 710 711 /* IPEHR would be an ideal way to detect errors, as it's the gross 712 * measure of "the command that hung." However, has some very common 713 * synchronization commands which almost always appear in the case 714 * strictly a client bug. Use instdone to differentiate those some. 715 */ 716 for (i = 0; i < I915_NUM_RINGS; i++) { 717 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 718 if (ring_id) 719 *ring_id = i; 720 721 return error->ring[i].ipehr ^ error->ring[i].instdone; 722 } 723 } 724 725 return error_code; 726} 727 728static void i915_gem_record_fences(struct drm_device *dev, 729 struct drm_i915_error_state *error) 730{ 731 struct drm_i915_private *dev_priv = dev->dev_private; 732 int i; 733 734 /* Fences */ 735 switch (INTEL_INFO(dev)->gen) { 736 case 8: 737 case 7: 738 case 6: 739 for (i = 0; i < dev_priv->num_fence_regs; i++) 740 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 741 break; 742 case 5: 743 case 4: 744 for (i = 0; i < 16; i++) 745 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 746 break; 747 case 3: 748 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 749 for (i = 0; i < 8; i++) 750 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 751 case 2: 752 for (i = 0; i < 8; i++) 753 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 754 break; 755 756 default: 757 BUG(); 758 } 759} 760 761 762static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 763 struct drm_i915_error_state *error, 764 struct intel_engine_cs *ring, 765 struct drm_i915_error_ring *ering) 766{ 767 struct intel_engine_cs *to; 768 int i; 769 770 if (!i915_semaphore_is_enabled(dev_priv->dev)) 771 return; 772 773 if (!error->semaphore_obj) 774 error->semaphore_obj = 775 i915_error_object_create(dev_priv, 776 dev_priv->semaphore_obj, 777 &dev_priv->gtt.base); 778 779 for_each_ring(to, dev_priv, i) { 780 int idx; 781 u16 signal_offset; 782 u32 *tmp; 783 784 if (ring == to) 785 continue; 786 787 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 788 / 4; 789 tmp = error->semaphore_obj->pages[0]; 790 idx = intel_ring_sync_index(ring, to); 791 792 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 793 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 794 } 795} 796 797static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 798 struct intel_engine_cs *ring, 799 struct drm_i915_error_ring *ering) 800{ 801 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 802 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 803 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 804 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 805 806 if (HAS_VEBOX(dev_priv->dev)) { 807 ering->semaphore_mboxes[2] = 808 I915_READ(RING_SYNC_2(ring->mmio_base)); 809 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 810 } 811} 812 813static void i915_record_ring_state(struct drm_device *dev, 814 struct drm_i915_error_state *error, 815 struct intel_engine_cs *ring, 816 struct drm_i915_error_ring *ering) 817{ 818 struct drm_i915_private *dev_priv = dev->dev_private; 819 820 if (INTEL_INFO(dev)->gen >= 6) { 821 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 822 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 823 if (INTEL_INFO(dev)->gen >= 8) 824 gen8_record_semaphore_state(dev_priv, error, ring, ering); 825 else 826 gen6_record_semaphore_state(dev_priv, ring, ering); 827 } 828 829 if (INTEL_INFO(dev)->gen >= 4) { 830 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 831 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 832 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 833 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 834 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 835 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 836 if (INTEL_INFO(dev)->gen >= 8) { 837 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 838 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 839 } 840 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 841 } else { 842 ering->faddr = I915_READ(DMA_FADD_I8XX); 843 ering->ipeir = I915_READ(IPEIR); 844 ering->ipehr = I915_READ(IPEHR); 845 ering->instdone = I915_READ(INSTDONE); 846 } 847 848 ering->waiting = waitqueue_active(&ring->irq_queue); 849 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 850 ering->seqno = ring->get_seqno(ring, false); 851 ering->acthd = intel_ring_get_active_head(ring); 852 ering->head = I915_READ_HEAD(ring); 853 ering->tail = I915_READ_TAIL(ring); 854 ering->ctl = I915_READ_CTL(ring); 855 856 if (I915_NEED_GFX_HWS(dev)) { 857 int mmio; 858 859 if (IS_GEN7(dev)) { 860 switch (ring->id) { 861 default: 862 case RCS: 863 mmio = RENDER_HWS_PGA_GEN7; 864 break; 865 case BCS: 866 mmio = BLT_HWS_PGA_GEN7; 867 break; 868 case VCS: 869 mmio = BSD_HWS_PGA_GEN7; 870 break; 871 case VECS: 872 mmio = VEBOX_HWS_PGA_GEN7; 873 break; 874 } 875 } else if (IS_GEN6(ring->dev)) { 876 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 877 } else { 878 /* XXX: gen8 returns to sanity */ 879 mmio = RING_HWS_PGA(ring->mmio_base); 880 } 881 882 ering->hws = I915_READ(mmio); 883 } 884 885 ering->cpu_ring_head = ring->buffer->head; 886 ering->cpu_ring_tail = ring->buffer->tail; 887 888 ering->hangcheck_score = ring->hangcheck.score; 889 ering->hangcheck_action = ring->hangcheck.action; 890 891 if (USES_PPGTT(dev)) { 892 int i; 893 894 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 895 896 switch (INTEL_INFO(dev)->gen) { 897 case 8: 898 for (i = 0; i < 4; i++) { 899 ering->vm_info.pdp[i] = 900 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 901 ering->vm_info.pdp[i] <<= 32; 902 ering->vm_info.pdp[i] |= 903 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 904 } 905 break; 906 case 7: 907 ering->vm_info.pp_dir_base = 908 I915_READ(RING_PP_DIR_BASE(ring)); 909 break; 910 case 6: 911 ering->vm_info.pp_dir_base = 912 I915_READ(RING_PP_DIR_BASE_READ(ring)); 913 break; 914 } 915 } 916} 917 918 919static void i915_gem_record_active_context(struct intel_engine_cs *ring, 920 struct drm_i915_error_state *error, 921 struct drm_i915_error_ring *ering) 922{ 923 struct drm_i915_private *dev_priv = ring->dev->dev_private; 924 struct drm_i915_gem_object *obj; 925 926 /* Currently render ring is the only HW context user */ 927 if (ring->id != RCS || !error->ccid) 928 return; 929 930 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 931 if (!i915_gem_obj_ggtt_bound(obj)) 932 continue; 933 934 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 935 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 936 break; 937 } 938 } 939} 940 941static void i915_gem_record_rings(struct drm_device *dev, 942 struct drm_i915_error_state *error) 943{ 944 struct drm_i915_private *dev_priv = dev->dev_private; 945 struct drm_i915_gem_request *request; 946 int i, count; 947 948 for (i = 0; i < I915_NUM_RINGS; i++) { 949 struct intel_engine_cs *ring = &dev_priv->ring[i]; 950 951 error->ring[i].pid = -1; 952 953 if (ring->dev == NULL) 954 continue; 955 956 error->ring[i].valid = true; 957 958 i915_record_ring_state(dev, error, ring, &error->ring[i]); 959 960 request = i915_gem_find_active_request(ring); 961 if (request) { 962 /* We need to copy these to an anonymous buffer 963 * as the simplest method to avoid being overwritten 964 * by userspace. 965 */ 966 error->ring[i].batchbuffer = 967 i915_error_object_create(dev_priv, 968 request->batch_obj, 969 request->ctx ? 970 request->ctx->vm : 971 &dev_priv->gtt.base); 972 973 if (HAS_BROKEN_CS_TLB(dev_priv->dev) && 974 ring->scratch.obj) 975 error->ring[i].wa_batchbuffer = 976 i915_error_ggtt_object_create(dev_priv, 977 ring->scratch.obj); 978 979 if (request->file_priv) { 980 struct task_struct *task; 981 982 rcu_read_lock(); 983 task = pid_task(request->file_priv->file->pid, 984 PIDTYPE_PID); 985 if (task) { 986 strcpy(error->ring[i].comm, task->comm); 987 error->ring[i].pid = task->pid; 988 } 989 rcu_read_unlock(); 990 } 991 } 992 993 error->ring[i].ringbuffer = 994 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj); 995 996 if (ring->status_page.obj) 997 error->ring[i].hws_page = 998 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 999 1000 i915_gem_record_active_context(ring, error, &error->ring[i]); 1001 1002 count = 0; 1003 list_for_each_entry(request, &ring->request_list, list) 1004 count++; 1005 1006 error->ring[i].num_requests = count; 1007 error->ring[i].requests = 1008 kcalloc(count, sizeof(*error->ring[i].requests), 1009 GFP_ATOMIC); 1010 if (error->ring[i].requests == NULL) { 1011 error->ring[i].num_requests = 0; 1012 continue; 1013 } 1014 1015 count = 0; 1016 list_for_each_entry(request, &ring->request_list, list) { 1017 struct drm_i915_error_request *erq; 1018 1019 erq = &error->ring[i].requests[count++]; 1020 erq->seqno = request->seqno; 1021 erq->jiffies = request->emitted_jiffies; 1022 erq->tail = request->tail; 1023 } 1024 } 1025} 1026 1027/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1028 * VM. 1029 */ 1030static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1031 struct drm_i915_error_state *error, 1032 struct i915_address_space *vm, 1033 const int ndx) 1034{ 1035 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1036 struct drm_i915_gem_object *obj; 1037 struct i915_vma *vma; 1038 int i; 1039 1040 i = 0; 1041 list_for_each_entry(vma, &vm->active_list, mm_list) 1042 i++; 1043 error->active_bo_count[ndx] = i; 1044 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 1045 if (i915_gem_obj_is_pinned(obj)) 1046 i++; 1047 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1048 1049 if (i) { 1050 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1051 if (active_bo) 1052 pinned_bo = active_bo + error->active_bo_count[ndx]; 1053 } 1054 1055 if (active_bo) 1056 error->active_bo_count[ndx] = 1057 capture_active_bo(active_bo, 1058 error->active_bo_count[ndx], 1059 &vm->active_list); 1060 1061 if (pinned_bo) 1062 error->pinned_bo_count[ndx] = 1063 capture_pinned_bo(pinned_bo, 1064 error->pinned_bo_count[ndx], 1065 &dev_priv->mm.bound_list); 1066 error->active_bo[ndx] = active_bo; 1067 error->pinned_bo[ndx] = pinned_bo; 1068} 1069 1070static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1071 struct drm_i915_error_state *error) 1072{ 1073 struct i915_address_space *vm; 1074 int cnt = 0, i = 0; 1075 1076 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1077 cnt++; 1078 1079 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1080 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1081 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1082 GFP_ATOMIC); 1083 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1084 GFP_ATOMIC); 1085 1086 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1087 i915_gem_capture_vm(dev_priv, error, vm, i++); 1088} 1089 1090/* Capture all registers which don't fit into another category. */ 1091static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1092 struct drm_i915_error_state *error) 1093{ 1094 struct drm_device *dev = dev_priv->dev; 1095 1096 /* General organization 1097 * 1. Registers specific to a single generation 1098 * 2. Registers which belong to multiple generations 1099 * 3. Feature specific registers. 1100 * 4. Everything else 1101 * Please try to follow the order. 1102 */ 1103 1104 /* 1: Registers specific to a single generation */ 1105 if (IS_VALLEYVIEW(dev)) { 1106 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1107 error->forcewake = I915_READ(FORCEWAKE_VLV); 1108 } 1109 1110 if (IS_GEN7(dev)) 1111 error->err_int = I915_READ(GEN7_ERR_INT); 1112 1113 if (IS_GEN6(dev)) { 1114 error->forcewake = I915_READ(FORCEWAKE); 1115 error->gab_ctl = I915_READ(GAB_CTL); 1116 error->gfx_mode = I915_READ(GFX_MODE); 1117 } 1118 1119 /* 2: Registers which belong to multiple generations */ 1120 if (INTEL_INFO(dev)->gen >= 7) 1121 error->forcewake = I915_READ(FORCEWAKE_MT); 1122 1123 if (INTEL_INFO(dev)->gen >= 6) { 1124 error->derrmr = I915_READ(DERRMR); 1125 error->error = I915_READ(ERROR_GEN6); 1126 error->done_reg = I915_READ(DONE_REG); 1127 } 1128 1129 /* 3: Feature specific registers */ 1130 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1131 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1132 error->gac_eco = I915_READ(GAC_ECO_BITS); 1133 } 1134 1135 /* 4: Everything else */ 1136 if (HAS_HW_CONTEXTS(dev)) 1137 error->ccid = I915_READ(CCID); 1138 1139 if (HAS_PCH_SPLIT(dev)) 1140 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1141 else { 1142 if (IS_GEN2(dev)) 1143 error->ier = I915_READ16(IER); 1144 else 1145 error->ier = I915_READ(IER); 1146 } 1147 1148 /* 4: Everything else */ 1149 error->eir = I915_READ(EIR); 1150 error->pgtbl_er = I915_READ(PGTBL_ER); 1151 1152 i915_get_extra_instdone(dev, error->extra_instdone); 1153} 1154 1155static void i915_error_capture_msg(struct drm_device *dev, 1156 struct drm_i915_error_state *error, 1157 bool wedged, 1158 const char *error_msg) 1159{ 1160 struct drm_i915_private *dev_priv = dev->dev_private; 1161 u32 ecode; 1162 int ring_id = -1, len; 1163 1164 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1165 1166 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1167 "GPU HANG: ecode %d:0x%08x", ring_id, ecode); 1168 1169 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1170 len += scnprintf(error->error_msg + len, 1171 sizeof(error->error_msg) - len, 1172 ", in %s [%d]", 1173 error->ring[ring_id].comm, 1174 error->ring[ring_id].pid); 1175 1176 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1177 ", reason: %s, action: %s", 1178 error_msg, 1179 wedged ? "reset" : "continue"); 1180} 1181 1182static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1183 struct drm_i915_error_state *error) 1184{ 1185 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1186 error->suspend_count = dev_priv->suspend_count; 1187} 1188 1189/** 1190 * i915_capture_error_state - capture an error record for later analysis 1191 * @dev: drm device 1192 * 1193 * Should be called when an error is detected (either a hang or an error 1194 * interrupt) to capture error state from the time of the error. Fills 1195 * out a structure which becomes available in debugfs for user level tools 1196 * to pick up. 1197 */ 1198void i915_capture_error_state(struct drm_device *dev, bool wedged, 1199 const char *error_msg) 1200{ 1201 static bool warned; 1202 struct drm_i915_private *dev_priv = dev->dev_private; 1203 struct drm_i915_error_state *error; 1204 unsigned long flags; 1205 1206 /* Account for pipe specific data like PIPE*STAT */ 1207 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1208 if (!error) { 1209 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1210 return; 1211 } 1212 1213 kref_init(&error->ref); 1214 1215 i915_capture_gen_state(dev_priv, error); 1216 i915_capture_reg_state(dev_priv, error); 1217 i915_gem_capture_buffers(dev_priv, error); 1218 i915_gem_record_fences(dev, error); 1219 i915_gem_record_rings(dev, error); 1220 1221 do_gettimeofday(&error->time); 1222 1223 error->overlay = intel_overlay_capture_error_state(dev); 1224 error->display = intel_display_capture_error_state(dev); 1225 1226 i915_error_capture_msg(dev, error, wedged, error_msg); 1227 DRM_INFO("%s\n", error->error_msg); 1228 1229 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1230 if (dev_priv->gpu_error.first_error == NULL) { 1231 dev_priv->gpu_error.first_error = error; 1232 error = NULL; 1233 } 1234 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1235 1236 if (error) { 1237 i915_error_state_free(&error->ref); 1238 return; 1239 } 1240 1241 if (!warned) { 1242 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1243 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1244 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1245 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1246 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1247 warned = true; 1248 } 1249} 1250 1251void i915_error_state_get(struct drm_device *dev, 1252 struct i915_error_state_file_priv *error_priv) 1253{ 1254 struct drm_i915_private *dev_priv = dev->dev_private; 1255 unsigned long flags; 1256 1257 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1258 error_priv->error = dev_priv->gpu_error.first_error; 1259 if (error_priv->error) 1260 kref_get(&error_priv->error->ref); 1261 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1262 1263} 1264 1265void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1266{ 1267 if (error_priv->error) 1268 kref_put(&error_priv->error->ref, i915_error_state_free); 1269} 1270 1271void i915_destroy_error_state(struct drm_device *dev) 1272{ 1273 struct drm_i915_private *dev_priv = dev->dev_private; 1274 struct drm_i915_error_state *error; 1275 unsigned long flags; 1276 1277 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1278 error = dev_priv->gpu_error.first_error; 1279 dev_priv->gpu_error.first_error = NULL; 1280 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1281 1282 if (error) 1283 kref_put(&error->ref, i915_error_state_free); 1284} 1285 1286const char *i915_cache_level_str(int type) 1287{ 1288 switch (type) { 1289 case I915_CACHE_NONE: return " uncached"; 1290 case I915_CACHE_LLC: return " snooped or LLC"; 1291 case I915_CACHE_L3_LLC: return " L3+LLC"; 1292 case I915_CACHE_WT: return " WT"; 1293 default: return ""; 1294 } 1295} 1296 1297/* NB: please notice the memset */ 1298void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1299{ 1300 struct drm_i915_private *dev_priv = dev->dev_private; 1301 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1302 1303 switch (INTEL_INFO(dev)->gen) { 1304 case 2: 1305 case 3: 1306 instdone[0] = I915_READ(INSTDONE); 1307 break; 1308 case 4: 1309 case 5: 1310 case 6: 1311 instdone[0] = I915_READ(INSTDONE_I965); 1312 instdone[1] = I915_READ(INSTDONE1); 1313 break; 1314 default: 1315 WARN_ONCE(1, "Unsupported platform\n"); 1316 case 7: 1317 case 8: 1318 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1319 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1320 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1321 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1322 break; 1323 } 1324} 1325