i915_gpu_error.c revision 3dda20a974e013a4985560904c0e491a70a25251
1/* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30#include <generated/utsrelease.h> 31#include "i915_drv.h" 32 33static const char *yesno(int v) 34{ 35 return v ? "yes" : "no"; 36} 37 38static const char *ring_str(int ring) 39{ 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 default: return ""; 46 } 47} 48 49static const char *pin_flag(int pinned) 50{ 51 if (pinned > 0) 52 return " P"; 53 else if (pinned < 0) 54 return " p"; 55 else 56 return ""; 57} 58 59static const char *tiling_flag(int tiling) 60{ 61 switch (tiling) { 62 default: 63 case I915_TILING_NONE: return ""; 64 case I915_TILING_X: return " X"; 65 case I915_TILING_Y: return " Y"; 66 } 67} 68 69static const char *dirty_flag(int dirty) 70{ 71 return dirty ? " dirty" : ""; 72} 73 74static const char *purgeable_flag(int purgeable) 75{ 76 return purgeable ? " purgeable" : ""; 77} 78 79static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 80{ 81 82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 83 e->err = -ENOSPC; 84 return false; 85 } 86 87 if (e->bytes == e->size - 1 || e->err) 88 return false; 89 90 return true; 91} 92 93static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 94 unsigned len) 95{ 96 if (e->pos + len <= e->start) { 97 e->pos += len; 98 return false; 99 } 100 101 /* First vsnprintf needs to fit in its entirety for memmove */ 102 if (len >= e->size) { 103 e->err = -EIO; 104 return false; 105 } 106 107 return true; 108} 109 110static void __i915_error_advance(struct drm_i915_error_state_buf *e, 111 unsigned len) 112{ 113 /* If this is first printf in this window, adjust it so that 114 * start position matches start of the buffer 115 */ 116 117 if (e->pos < e->start) { 118 const size_t off = e->start - e->pos; 119 120 /* Should not happen but be paranoid */ 121 if (off > len || e->bytes) { 122 e->err = -EIO; 123 return; 124 } 125 126 memmove(e->buf, e->buf + off, len - off); 127 e->bytes = len - off; 128 e->pos = e->start; 129 return; 130 } 131 132 e->bytes += len; 133 e->pos += len; 134} 135 136static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 137 const char *f, va_list args) 138{ 139 unsigned len; 140 141 if (!__i915_error_ok(e)) 142 return; 143 144 /* Seek the first printf which is hits start position */ 145 if (e->pos < e->start) { 146 va_list tmp; 147 148 va_copy(tmp, args); 149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp))) 150 return; 151 } 152 153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 154 if (len >= e->size - e->bytes) 155 len = e->size - e->bytes - 1; 156 157 __i915_error_advance(e, len); 158} 159 160static void i915_error_puts(struct drm_i915_error_state_buf *e, 161 const char *str) 162{ 163 unsigned len; 164 165 if (!__i915_error_ok(e)) 166 return; 167 168 len = strlen(str); 169 170 /* Seek the first printf which is hits start position */ 171 if (e->pos < e->start) { 172 if (!__i915_error_seek(e, len)) 173 return; 174 } 175 176 if (len >= e->size - e->bytes) 177 len = e->size - e->bytes - 1; 178 memcpy(e->buf + e->bytes, str, len); 179 180 __i915_error_advance(e, len); 181} 182 183#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 184#define err_puts(e, s) i915_error_puts(e, s) 185 186static void print_error_buffers(struct drm_i915_error_state_buf *m, 187 const char *name, 188 struct drm_i915_error_buffer *err, 189 int count) 190{ 191 err_printf(m, "%s [%d]:\n", name, count); 192 193 while (count--) { 194 err_printf(m, " %08x %8u %02x %02x %x %x", 195 err->gtt_offset, 196 err->size, 197 err->read_domains, 198 err->write_domain, 199 err->rseqno, err->wseqno); 200 err_puts(m, pin_flag(err->pinned)); 201 err_puts(m, tiling_flag(err->tiling)); 202 err_puts(m, dirty_flag(err->dirty)); 203 err_puts(m, purgeable_flag(err->purgeable)); 204 err_puts(m, err->ring != -1 ? " " : ""); 205 err_puts(m, ring_str(err->ring)); 206 err_puts(m, i915_cache_level_str(err->cache_level)); 207 208 if (err->name) 209 err_printf(m, " (name: %d)", err->name); 210 if (err->fence_reg != I915_FENCE_REG_NONE) 211 err_printf(m, " (fence: %d)", err->fence_reg); 212 213 err_puts(m, "\n"); 214 err++; 215 } 216} 217 218static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 219{ 220 switch (a) { 221 case HANGCHECK_IDLE: 222 return "idle"; 223 case HANGCHECK_WAIT: 224 return "wait"; 225 case HANGCHECK_ACTIVE: 226 return "active"; 227 case HANGCHECK_KICK: 228 return "kick"; 229 case HANGCHECK_HUNG: 230 return "hung"; 231 } 232 233 return "unknown"; 234} 235 236static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 237 struct drm_device *dev, 238 struct drm_i915_error_state *error, 239 unsigned ring) 240{ 241 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */ 242 err_printf(m, "%s command stream:\n", ring_str(ring)); 243 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]); 244 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); 245 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]); 246 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); 247 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); 248 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); 249 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]); 250 if (INTEL_INFO(dev)->gen >= 4) { 251 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr[ring]); 252 err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]); 253 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]); 254 } 255 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]); 256 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]); 257 if (INTEL_INFO(dev)->gen >= 6) { 258 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]); 259 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]); 260 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 261 error->semaphore_mboxes[ring][0], 262 error->semaphore_seqno[ring][0]); 263 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 264 error->semaphore_mboxes[ring][1], 265 error->semaphore_seqno[ring][1]); 266 if (HAS_VEBOX(dev)) { 267 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 268 error->semaphore_mboxes[ring][2], 269 error->semaphore_seqno[ring][2]); 270 } 271 } 272 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]); 273 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring])); 274 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]); 275 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]); 276 err_printf(m, " hangcheck: %s [%d]\n", 277 hangcheck_action_to_str(error->hangcheck_action[ring]), 278 error->hangcheck_score[ring]); 279} 280 281void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 282{ 283 va_list args; 284 285 va_start(args, f); 286 i915_error_vprintf(e, f, args); 287 va_end(args); 288} 289 290int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 291 const struct i915_error_state_file_priv *error_priv) 292{ 293 struct drm_device *dev = error_priv->dev; 294 drm_i915_private_t *dev_priv = dev->dev_private; 295 struct drm_i915_error_state *error = error_priv->error; 296 struct intel_ring_buffer *ring; 297 int i, j, page, offset, elt; 298 299 if (!error) { 300 err_printf(m, "no error state collected\n"); 301 goto out; 302 } 303 304 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 305 error->time.tv_usec); 306 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 307 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 308 err_printf(m, "EIR: 0x%08x\n", error->eir); 309 err_printf(m, "IER: 0x%08x\n", error->ier); 310 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 311 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 312 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 313 err_printf(m, "CCID: 0x%08x\n", error->ccid); 314 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 315 316 for (i = 0; i < dev_priv->num_fence_regs; i++) 317 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 318 319 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 320 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 321 error->extra_instdone[i]); 322 323 if (INTEL_INFO(dev)->gen >= 6) { 324 err_printf(m, "ERROR: 0x%08x\n", error->error); 325 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 326 } 327 328 if (INTEL_INFO(dev)->gen == 7) 329 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 330 331 for_each_ring(ring, dev_priv, i) 332 i915_ring_error_state(m, dev, error, i); 333 334 if (error->active_bo) 335 print_error_buffers(m, "Active", 336 error->active_bo[0], 337 error->active_bo_count[0]); 338 339 if (error->pinned_bo) 340 print_error_buffers(m, "Pinned", 341 error->pinned_bo[0], 342 error->pinned_bo_count[0]); 343 344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 345 struct drm_i915_error_object *obj; 346 347 if ((obj = error->ring[i].batchbuffer)) { 348 err_printf(m, "%s --- gtt_offset = 0x%08x\n", 349 dev_priv->ring[i].name, 350 obj->gtt_offset); 351 offset = 0; 352 for (page = 0; page < obj->page_count; page++) { 353 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 354 err_printf(m, "%08x : %08x\n", offset, 355 obj->pages[page][elt]); 356 offset += 4; 357 } 358 } 359 } 360 361 if (error->ring[i].num_requests) { 362 err_printf(m, "%s --- %d requests\n", 363 dev_priv->ring[i].name, 364 error->ring[i].num_requests); 365 for (j = 0; j < error->ring[i].num_requests; j++) { 366 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 367 error->ring[i].requests[j].seqno, 368 error->ring[i].requests[j].jiffies, 369 error->ring[i].requests[j].tail); 370 } 371 } 372 373 if ((obj = error->ring[i].ringbuffer)) { 374 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 375 dev_priv->ring[i].name, 376 obj->gtt_offset); 377 offset = 0; 378 for (page = 0; page < obj->page_count; page++) { 379 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 380 err_printf(m, "%08x : %08x\n", 381 offset, 382 obj->pages[page][elt]); 383 offset += 4; 384 } 385 } 386 } 387 388 obj = error->ring[i].ctx; 389 if (obj) { 390 err_printf(m, "%s --- HW Context = 0x%08x\n", 391 dev_priv->ring[i].name, 392 obj->gtt_offset); 393 offset = 0; 394 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 395 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 396 offset, 397 obj->pages[0][elt], 398 obj->pages[0][elt+1], 399 obj->pages[0][elt+2], 400 obj->pages[0][elt+3]); 401 offset += 16; 402 } 403 } 404 } 405 406 if (error->overlay) 407 intel_overlay_print_error_state(m, error->overlay); 408 409 if (error->display) 410 intel_display_print_error_state(m, dev, error->display); 411 412out: 413 if (m->bytes == 0 && m->err) 414 return m->err; 415 416 return 0; 417} 418 419int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 420 size_t count, loff_t pos) 421{ 422 memset(ebuf, 0, sizeof(*ebuf)); 423 424 /* We need to have enough room to store any i915_error_state printf 425 * so that we can move it to start position. 426 */ 427 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 428 ebuf->buf = kmalloc(ebuf->size, 429 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 430 431 if (ebuf->buf == NULL) { 432 ebuf->size = PAGE_SIZE; 433 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 434 } 435 436 if (ebuf->buf == NULL) { 437 ebuf->size = 128; 438 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 439 } 440 441 if (ebuf->buf == NULL) 442 return -ENOMEM; 443 444 ebuf->start = pos; 445 446 return 0; 447} 448 449static void i915_error_object_free(struct drm_i915_error_object *obj) 450{ 451 int page; 452 453 if (obj == NULL) 454 return; 455 456 for (page = 0; page < obj->page_count; page++) 457 kfree(obj->pages[page]); 458 459 kfree(obj); 460} 461 462static void i915_error_state_free(struct kref *error_ref) 463{ 464 struct drm_i915_error_state *error = container_of(error_ref, 465 typeof(*error), ref); 466 int i; 467 468 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 469 i915_error_object_free(error->ring[i].batchbuffer); 470 i915_error_object_free(error->ring[i].ringbuffer); 471 i915_error_object_free(error->ring[i].ctx); 472 kfree(error->ring[i].requests); 473 } 474 475 kfree(error->active_bo); 476 kfree(error->overlay); 477 kfree(error->display); 478 kfree(error); 479} 480 481static struct drm_i915_error_object * 482i915_error_object_create_sized(struct drm_i915_private *dev_priv, 483 struct drm_i915_gem_object *src, 484 const int num_pages) 485{ 486 struct drm_i915_error_object *dst; 487 int i; 488 u32 reloc_offset; 489 490 if (src == NULL || src->pages == NULL) 491 return NULL; 492 493 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 494 if (dst == NULL) 495 return NULL; 496 497 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src); 498 for (i = 0; i < num_pages; i++) { 499 unsigned long flags; 500 void *d; 501 502 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 503 if (d == NULL) 504 goto unwind; 505 506 local_irq_save(flags); 507 if (reloc_offset < dev_priv->gtt.mappable_end && 508 src->has_global_gtt_mapping) { 509 void __iomem *s; 510 511 /* Simply ignore tiling or any overlapping fence. 512 * It's part of the error state, and this hopefully 513 * captures what the GPU read. 514 */ 515 516 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 517 reloc_offset); 518 memcpy_fromio(d, s, PAGE_SIZE); 519 io_mapping_unmap_atomic(s); 520 } else if (src->stolen) { 521 unsigned long offset; 522 523 offset = dev_priv->mm.stolen_base; 524 offset += src->stolen->start; 525 offset += i << PAGE_SHIFT; 526 527 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 528 } else { 529 struct page *page; 530 void *s; 531 532 page = i915_gem_object_get_page(src, i); 533 534 drm_clflush_pages(&page, 1); 535 536 s = kmap_atomic(page); 537 memcpy(d, s, PAGE_SIZE); 538 kunmap_atomic(s); 539 540 drm_clflush_pages(&page, 1); 541 } 542 local_irq_restore(flags); 543 544 dst->pages[i] = d; 545 546 reloc_offset += PAGE_SIZE; 547 } 548 dst->page_count = num_pages; 549 550 return dst; 551 552unwind: 553 while (i--) 554 kfree(dst->pages[i]); 555 kfree(dst); 556 return NULL; 557} 558#define i915_error_object_create(dev_priv, src) \ 559 i915_error_object_create_sized((dev_priv), (src), \ 560 (src)->base.size>>PAGE_SHIFT) 561 562static void capture_bo(struct drm_i915_error_buffer *err, 563 struct drm_i915_gem_object *obj) 564{ 565 err->size = obj->base.size; 566 err->name = obj->base.name; 567 err->rseqno = obj->last_read_seqno; 568 err->wseqno = obj->last_write_seqno; 569 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 570 err->read_domains = obj->base.read_domains; 571 err->write_domain = obj->base.write_domain; 572 err->fence_reg = obj->fence_reg; 573 err->pinned = 0; 574 if (obj->pin_count > 0) 575 err->pinned = 1; 576 if (obj->user_pin_count > 0) 577 err->pinned = -1; 578 err->tiling = obj->tiling_mode; 579 err->dirty = obj->dirty; 580 err->purgeable = obj->madv != I915_MADV_WILLNEED; 581 err->ring = obj->ring ? obj->ring->id : -1; 582 err->cache_level = obj->cache_level; 583} 584 585static u32 capture_active_bo(struct drm_i915_error_buffer *err, 586 int count, struct list_head *head) 587{ 588 struct i915_vma *vma; 589 int i = 0; 590 591 list_for_each_entry(vma, head, mm_list) { 592 capture_bo(err++, vma->obj); 593 if (++i == count) 594 break; 595 } 596 597 return i; 598} 599 600static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 601 int count, struct list_head *head) 602{ 603 struct drm_i915_gem_object *obj; 604 int i = 0; 605 606 list_for_each_entry(obj, head, global_list) { 607 if (obj->pin_count == 0) 608 continue; 609 610 capture_bo(err++, obj); 611 if (++i == count) 612 break; 613 } 614 615 return i; 616} 617 618static void i915_gem_record_fences(struct drm_device *dev, 619 struct drm_i915_error_state *error) 620{ 621 struct drm_i915_private *dev_priv = dev->dev_private; 622 int i; 623 624 /* Fences */ 625 switch (INTEL_INFO(dev)->gen) { 626 case 8: 627 case 7: 628 case 6: 629 for (i = 0; i < dev_priv->num_fence_regs; i++) 630 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 631 break; 632 case 5: 633 case 4: 634 for (i = 0; i < 16; i++) 635 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 636 break; 637 case 3: 638 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 639 for (i = 0; i < 8; i++) 640 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 641 case 2: 642 for (i = 0; i < 8; i++) 643 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 644 break; 645 646 default: 647 BUG(); 648 } 649} 650 651static struct drm_i915_error_object * 652i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 653 struct intel_ring_buffer *ring) 654{ 655 struct i915_address_space *vm; 656 struct i915_vma *vma; 657 struct drm_i915_gem_object *obj; 658 u32 seqno; 659 660 if (!ring->get_seqno) 661 return NULL; 662 663 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { 664 u32 acthd = I915_READ(ACTHD); 665 666 if (WARN_ON(ring->id != RCS)) 667 return NULL; 668 669 obj = ring->scratch.obj; 670 if (acthd >= i915_gem_obj_ggtt_offset(obj) && 671 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) 672 return i915_error_object_create(dev_priv, obj); 673 } 674 675 seqno = ring->get_seqno(ring, false); 676 list_for_each_entry(vm, &dev_priv->vm_list, global_link) { 677 list_for_each_entry(vma, &vm->active_list, mm_list) { 678 obj = vma->obj; 679 if (obj->ring != ring) 680 continue; 681 682 if (i915_seqno_passed(seqno, obj->last_read_seqno)) 683 continue; 684 685 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 686 continue; 687 688 /* We need to copy these to an anonymous buffer as the simplest 689 * method to avoid being overwritten by userspace. 690 */ 691 return i915_error_object_create(dev_priv, obj); 692 } 693 } 694 695 return NULL; 696} 697 698static void i915_record_ring_state(struct drm_device *dev, 699 struct drm_i915_error_state *error, 700 struct intel_ring_buffer *ring) 701{ 702 struct drm_i915_private *dev_priv = dev->dev_private; 703 704 if (INTEL_INFO(dev)->gen >= 6) { 705 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); 706 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 707 error->semaphore_mboxes[ring->id][0] 708 = I915_READ(RING_SYNC_0(ring->mmio_base)); 709 error->semaphore_mboxes[ring->id][1] 710 = I915_READ(RING_SYNC_1(ring->mmio_base)); 711 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; 712 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; 713 } 714 715 if (HAS_VEBOX(dev)) { 716 error->semaphore_mboxes[ring->id][2] = 717 I915_READ(RING_SYNC_2(ring->mmio_base)); 718 error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2]; 719 } 720 721 if (INTEL_INFO(dev)->gen >= 4) { 722 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 723 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 724 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 725 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 726 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 727 error->bbaddr[ring->id] = I915_READ(RING_BBADDR(ring->mmio_base)); 728 if (INTEL_INFO(dev)->gen >= 8) 729 error->bbaddr[ring->id] |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 730 error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base)); 731 } else { 732 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 733 error->ipeir[ring->id] = I915_READ(IPEIR); 734 error->ipehr[ring->id] = I915_READ(IPEHR); 735 error->instdone[ring->id] = I915_READ(INSTDONE); 736 } 737 738 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); 739 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 740 error->seqno[ring->id] = ring->get_seqno(ring, false); 741 error->acthd[ring->id] = intel_ring_get_active_head(ring); 742 error->head[ring->id] = I915_READ_HEAD(ring); 743 error->tail[ring->id] = I915_READ_TAIL(ring); 744 error->ctl[ring->id] = I915_READ_CTL(ring); 745 746 error->cpu_ring_head[ring->id] = ring->head; 747 error->cpu_ring_tail[ring->id] = ring->tail; 748 749 error->hangcheck_score[ring->id] = ring->hangcheck.score; 750 error->hangcheck_action[ring->id] = ring->hangcheck.action; 751} 752 753 754static void i915_gem_record_active_context(struct intel_ring_buffer *ring, 755 struct drm_i915_error_state *error, 756 struct drm_i915_error_ring *ering) 757{ 758 struct drm_i915_private *dev_priv = ring->dev->dev_private; 759 struct drm_i915_gem_object *obj; 760 761 /* Currently render ring is the only HW context user */ 762 if (ring->id != RCS || !error->ccid) 763 return; 764 765 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 766 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 767 ering->ctx = i915_error_object_create_sized(dev_priv, 768 obj, 1); 769 break; 770 } 771 } 772} 773 774static void i915_gem_record_rings(struct drm_device *dev, 775 struct drm_i915_error_state *error) 776{ 777 struct drm_i915_private *dev_priv = dev->dev_private; 778 struct intel_ring_buffer *ring; 779 struct drm_i915_gem_request *request; 780 int i, count; 781 782 for_each_ring(ring, dev_priv, i) { 783 i915_record_ring_state(dev, error, ring); 784 785 error->ring[i].batchbuffer = 786 i915_error_first_batchbuffer(dev_priv, ring); 787 788 error->ring[i].ringbuffer = 789 i915_error_object_create(dev_priv, ring->obj); 790 791 792 i915_gem_record_active_context(ring, error, &error->ring[i]); 793 794 count = 0; 795 list_for_each_entry(request, &ring->request_list, list) 796 count++; 797 798 error->ring[i].num_requests = count; 799 error->ring[i].requests = 800 kcalloc(count, sizeof(*error->ring[i].requests), 801 GFP_ATOMIC); 802 if (error->ring[i].requests == NULL) { 803 error->ring[i].num_requests = 0; 804 continue; 805 } 806 807 count = 0; 808 list_for_each_entry(request, &ring->request_list, list) { 809 struct drm_i915_error_request *erq; 810 811 erq = &error->ring[i].requests[count++]; 812 erq->seqno = request->seqno; 813 erq->jiffies = request->emitted_jiffies; 814 erq->tail = request->tail; 815 } 816 } 817} 818 819/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 820 * VM. 821 */ 822static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 823 struct drm_i915_error_state *error, 824 struct i915_address_space *vm, 825 const int ndx) 826{ 827 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 828 struct drm_i915_gem_object *obj; 829 struct i915_vma *vma; 830 int i; 831 832 i = 0; 833 list_for_each_entry(vma, &vm->active_list, mm_list) 834 i++; 835 error->active_bo_count[ndx] = i; 836 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 837 if (obj->pin_count) 838 i++; 839 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 840 841 if (i) { 842 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 843 if (active_bo) 844 pinned_bo = active_bo + error->active_bo_count[ndx]; 845 } 846 847 if (active_bo) 848 error->active_bo_count[ndx] = 849 capture_active_bo(active_bo, 850 error->active_bo_count[ndx], 851 &vm->active_list); 852 853 if (pinned_bo) 854 error->pinned_bo_count[ndx] = 855 capture_pinned_bo(pinned_bo, 856 error->pinned_bo_count[ndx], 857 &dev_priv->mm.bound_list); 858 error->active_bo[ndx] = active_bo; 859 error->pinned_bo[ndx] = pinned_bo; 860} 861 862static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 863 struct drm_i915_error_state *error) 864{ 865 struct i915_address_space *vm; 866 int cnt = 0, i = 0; 867 868 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 869 cnt++; 870 871 if (WARN(cnt > 1, "Multiple VMs not yet supported\n")) 872 cnt = 1; 873 874 vm = &dev_priv->gtt.base; 875 876 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 877 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 878 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 879 GFP_ATOMIC); 880 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 881 GFP_ATOMIC); 882 883 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 884 i915_gem_capture_vm(dev_priv, error, vm, i++); 885} 886 887/** 888 * i915_capture_error_state - capture an error record for later analysis 889 * @dev: drm device 890 * 891 * Should be called when an error is detected (either a hang or an error 892 * interrupt) to capture error state from the time of the error. Fills 893 * out a structure which becomes available in debugfs for user level tools 894 * to pick up. 895 */ 896void i915_capture_error_state(struct drm_device *dev) 897{ 898 struct drm_i915_private *dev_priv = dev->dev_private; 899 struct drm_i915_error_state *error; 900 unsigned long flags; 901 int pipe; 902 903 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 904 error = dev_priv->gpu_error.first_error; 905 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 906 if (error) 907 return; 908 909 /* Account for pipe specific data like PIPE*STAT */ 910 error = kzalloc(sizeof(*error), GFP_ATOMIC); 911 if (!error) { 912 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 913 return; 914 } 915 916 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", 917 dev->primary->index); 918 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 919 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 920 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 921 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 922 923 kref_init(&error->ref); 924 error->eir = I915_READ(EIR); 925 error->pgtbl_er = I915_READ(PGTBL_ER); 926 if (HAS_HW_CONTEXTS(dev)) 927 error->ccid = I915_READ(CCID); 928 929 if (HAS_PCH_SPLIT(dev)) 930 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 931 else if (IS_VALLEYVIEW(dev)) 932 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 933 else if (IS_GEN2(dev)) 934 error->ier = I915_READ16(IER); 935 else 936 error->ier = I915_READ(IER); 937 938 if (INTEL_INFO(dev)->gen >= 6) 939 error->derrmr = I915_READ(DERRMR); 940 941 if (IS_VALLEYVIEW(dev)) 942 error->forcewake = I915_READ(FORCEWAKE_VLV); 943 else if (INTEL_INFO(dev)->gen >= 7) 944 error->forcewake = I915_READ(FORCEWAKE_MT); 945 else if (INTEL_INFO(dev)->gen == 6) 946 error->forcewake = I915_READ(FORCEWAKE); 947 948 if (!HAS_PCH_SPLIT(dev)) 949 for_each_pipe(pipe) 950 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 951 952 if (INTEL_INFO(dev)->gen >= 6) { 953 error->error = I915_READ(ERROR_GEN6); 954 error->done_reg = I915_READ(DONE_REG); 955 } 956 957 if (INTEL_INFO(dev)->gen == 7) 958 error->err_int = I915_READ(GEN7_ERR_INT); 959 960 i915_get_extra_instdone(dev, error->extra_instdone); 961 962 i915_gem_capture_buffers(dev_priv, error); 963 i915_gem_record_fences(dev, error); 964 i915_gem_record_rings(dev, error); 965 966 do_gettimeofday(&error->time); 967 968 error->overlay = intel_overlay_capture_error_state(dev); 969 error->display = intel_display_capture_error_state(dev); 970 971 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 972 if (dev_priv->gpu_error.first_error == NULL) { 973 dev_priv->gpu_error.first_error = error; 974 error = NULL; 975 } 976 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 977 978 if (error) 979 i915_error_state_free(&error->ref); 980} 981 982void i915_error_state_get(struct drm_device *dev, 983 struct i915_error_state_file_priv *error_priv) 984{ 985 struct drm_i915_private *dev_priv = dev->dev_private; 986 unsigned long flags; 987 988 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 989 error_priv->error = dev_priv->gpu_error.first_error; 990 if (error_priv->error) 991 kref_get(&error_priv->error->ref); 992 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 993 994} 995 996void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 997{ 998 if (error_priv->error) 999 kref_put(&error_priv->error->ref, i915_error_state_free); 1000} 1001 1002void i915_destroy_error_state(struct drm_device *dev) 1003{ 1004 struct drm_i915_private *dev_priv = dev->dev_private; 1005 struct drm_i915_error_state *error; 1006 unsigned long flags; 1007 1008 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1009 error = dev_priv->gpu_error.first_error; 1010 dev_priv->gpu_error.first_error = NULL; 1011 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1012 1013 if (error) 1014 kref_put(&error->ref, i915_error_state_free); 1015} 1016 1017const char *i915_cache_level_str(int type) 1018{ 1019 switch (type) { 1020 case I915_CACHE_NONE: return " uncached"; 1021 case I915_CACHE_LLC: return " snooped or LLC"; 1022 case I915_CACHE_L3_LLC: return " L3+LLC"; 1023 case I915_CACHE_WT: return " WT"; 1024 default: return ""; 1025 } 1026} 1027 1028/* NB: please notice the memset */ 1029void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1030{ 1031 struct drm_i915_private *dev_priv = dev->dev_private; 1032 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1033 1034 switch (INTEL_INFO(dev)->gen) { 1035 case 2: 1036 case 3: 1037 instdone[0] = I915_READ(INSTDONE); 1038 break; 1039 case 4: 1040 case 5: 1041 case 6: 1042 instdone[0] = I915_READ(INSTDONE_I965); 1043 instdone[1] = I915_READ(INSTDONE1); 1044 break; 1045 default: 1046 WARN_ONCE(1, "Unsupported platform\n"); 1047 case 7: 1048 case 8: 1049 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1050 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1051 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1052 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1053 break; 1054 } 1055} 1056