i915_gpu_error.c revision f301b1e116396804c6fcd4a33eb4477a24e0a3b8
1/* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30#include <generated/utsrelease.h> 31#include "i915_drv.h" 32 33static const char *yesno(int v) 34{ 35 return v ? "yes" : "no"; 36} 37 38static const char *ring_str(int ring) 39{ 40 switch (ring) { 41 case RCS: return "render"; 42 case VCS: return "bsd"; 43 case BCS: return "blt"; 44 case VECS: return "vebox"; 45 case VCS2: return "bsd2"; 46 default: return ""; 47 } 48} 49 50static const char *pin_flag(int pinned) 51{ 52 if (pinned > 0) 53 return " P"; 54 else if (pinned < 0) 55 return " p"; 56 else 57 return ""; 58} 59 60static const char *tiling_flag(int tiling) 61{ 62 switch (tiling) { 63 default: 64 case I915_TILING_NONE: return ""; 65 case I915_TILING_X: return " X"; 66 case I915_TILING_Y: return " Y"; 67 } 68} 69 70static const char *dirty_flag(int dirty) 71{ 72 return dirty ? " dirty" : ""; 73} 74 75static const char *purgeable_flag(int purgeable) 76{ 77 return purgeable ? " purgeable" : ""; 78} 79 80static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 81{ 82 83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 84 e->err = -ENOSPC; 85 return false; 86 } 87 88 if (e->bytes == e->size - 1 || e->err) 89 return false; 90 91 return true; 92} 93 94static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 95 unsigned len) 96{ 97 if (e->pos + len <= e->start) { 98 e->pos += len; 99 return false; 100 } 101 102 /* First vsnprintf needs to fit in its entirety for memmove */ 103 if (len >= e->size) { 104 e->err = -EIO; 105 return false; 106 } 107 108 return true; 109} 110 111static void __i915_error_advance(struct drm_i915_error_state_buf *e, 112 unsigned len) 113{ 114 /* If this is first printf in this window, adjust it so that 115 * start position matches start of the buffer 116 */ 117 118 if (e->pos < e->start) { 119 const size_t off = e->start - e->pos; 120 121 /* Should not happen but be paranoid */ 122 if (off > len || e->bytes) { 123 e->err = -EIO; 124 return; 125 } 126 127 memmove(e->buf, e->buf + off, len - off); 128 e->bytes = len - off; 129 e->pos = e->start; 130 return; 131 } 132 133 e->bytes += len; 134 e->pos += len; 135} 136 137static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 138 const char *f, va_list args) 139{ 140 unsigned len; 141 142 if (!__i915_error_ok(e)) 143 return; 144 145 /* Seek the first printf which is hits start position */ 146 if (e->pos < e->start) { 147 va_list tmp; 148 149 va_copy(tmp, args); 150 len = vsnprintf(NULL, 0, f, tmp); 151 va_end(tmp); 152 153 if (!__i915_error_seek(e, len)) 154 return; 155 } 156 157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 158 if (len >= e->size - e->bytes) 159 len = e->size - e->bytes - 1; 160 161 __i915_error_advance(e, len); 162} 163 164static void i915_error_puts(struct drm_i915_error_state_buf *e, 165 const char *str) 166{ 167 unsigned len; 168 169 if (!__i915_error_ok(e)) 170 return; 171 172 len = strlen(str); 173 174 /* Seek the first printf which is hits start position */ 175 if (e->pos < e->start) { 176 if (!__i915_error_seek(e, len)) 177 return; 178 } 179 180 if (len >= e->size - e->bytes) 181 len = e->size - e->bytes - 1; 182 memcpy(e->buf + e->bytes, str, len); 183 184 __i915_error_advance(e, len); 185} 186 187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 188#define err_puts(e, s) i915_error_puts(e, s) 189 190static void print_error_buffers(struct drm_i915_error_state_buf *m, 191 const char *name, 192 struct drm_i915_error_buffer *err, 193 int count) 194{ 195 err_printf(m, "%s [%d]:\n", name, count); 196 197 while (count--) { 198 err_printf(m, " %08x %8u %02x %02x %x %x", 199 err->gtt_offset, 200 err->size, 201 err->read_domains, 202 err->write_domain, 203 err->rseqno, err->wseqno); 204 err_puts(m, pin_flag(err->pinned)); 205 err_puts(m, tiling_flag(err->tiling)); 206 err_puts(m, dirty_flag(err->dirty)); 207 err_puts(m, purgeable_flag(err->purgeable)); 208 err_puts(m, err->ring != -1 ? " " : ""); 209 err_puts(m, ring_str(err->ring)); 210 err_puts(m, i915_cache_level_str(err->cache_level)); 211 212 if (err->name) 213 err_printf(m, " (name: %d)", err->name); 214 if (err->fence_reg != I915_FENCE_REG_NONE) 215 err_printf(m, " (fence: %d)", err->fence_reg); 216 217 err_puts(m, "\n"); 218 err++; 219 } 220} 221 222static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 223{ 224 switch (a) { 225 case HANGCHECK_IDLE: 226 return "idle"; 227 case HANGCHECK_WAIT: 228 return "wait"; 229 case HANGCHECK_ACTIVE: 230 return "active"; 231 case HANGCHECK_KICK: 232 return "kick"; 233 case HANGCHECK_HUNG: 234 return "hung"; 235 } 236 237 return "unknown"; 238} 239 240static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 241 struct drm_device *dev, 242 struct drm_i915_error_ring *ring) 243{ 244 if (!ring->valid) 245 return; 246 247 err_printf(m, " HEAD: 0x%08x\n", ring->head); 248 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 249 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 250 err_printf(m, " HWS: 0x%08x\n", ring->hws); 251 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 252 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 253 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 254 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 255 if (INTEL_INFO(dev)->gen >= 4) { 256 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 257 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 258 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 259 } 260 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 261 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 262 lower_32_bits(ring->faddr)); 263 if (INTEL_INFO(dev)->gen >= 6) { 264 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 265 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 266 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 267 ring->semaphore_mboxes[0], 268 ring->semaphore_seqno[0]); 269 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 270 ring->semaphore_mboxes[1], 271 ring->semaphore_seqno[1]); 272 if (HAS_VEBOX(dev)) { 273 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 274 ring->semaphore_mboxes[2], 275 ring->semaphore_seqno[2]); 276 } 277 } 278 if (USES_PPGTT(dev)) { 279 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 280 281 if (INTEL_INFO(dev)->gen >= 8) { 282 int i; 283 for (i = 0; i < 4; i++) 284 err_printf(m, " PDP%d: 0x%016llx\n", 285 i, ring->vm_info.pdp[i]); 286 } else { 287 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 288 ring->vm_info.pp_dir_base); 289 } 290 } 291 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 292 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 293 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 294 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 295 err_printf(m, " hangcheck: %s [%d]\n", 296 hangcheck_action_to_str(ring->hangcheck_action), 297 ring->hangcheck_score); 298} 299 300void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 301{ 302 va_list args; 303 304 va_start(args, f); 305 i915_error_vprintf(e, f, args); 306 va_end(args); 307} 308 309static void print_error_obj(struct drm_i915_error_state_buf *m, 310 struct drm_i915_error_object *obj) 311{ 312 int page, offset, elt; 313 314 for (page = offset = 0; page < obj->page_count; page++) { 315 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 316 err_printf(m, "%08x : %08x\n", offset, 317 obj->pages[page][elt]); 318 offset += 4; 319 } 320 } 321} 322 323int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 324 const struct i915_error_state_file_priv *error_priv) 325{ 326 struct drm_device *dev = error_priv->dev; 327 struct drm_i915_private *dev_priv = dev->dev_private; 328 struct drm_i915_error_state *error = error_priv->error; 329 int i, j, offset, elt; 330 int max_hangcheck_score; 331 332 if (!error) { 333 err_printf(m, "no error state collected\n"); 334 goto out; 335 } 336 337 err_printf(m, "%s\n", error->error_msg); 338 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 339 error->time.tv_usec); 340 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 341 max_hangcheck_score = 0; 342 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 343 if (error->ring[i].hangcheck_score > max_hangcheck_score) 344 max_hangcheck_score = error->ring[i].hangcheck_score; 345 } 346 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 347 if (error->ring[i].hangcheck_score == max_hangcheck_score && 348 error->ring[i].pid != -1) { 349 err_printf(m, "Active process (on ring %s): %s [%d]\n", 350 ring_str(i), 351 error->ring[i].comm, 352 error->ring[i].pid); 353 } 354 } 355 err_printf(m, "Reset count: %u\n", error->reset_count); 356 err_printf(m, "Suspend count: %u\n", error->suspend_count); 357 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 358 err_printf(m, "EIR: 0x%08x\n", error->eir); 359 err_printf(m, "IER: 0x%08x\n", error->ier); 360 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 361 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 362 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 363 err_printf(m, "CCID: 0x%08x\n", error->ccid); 364 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 365 366 for (i = 0; i < dev_priv->num_fence_regs; i++) 367 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 368 369 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 370 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 371 error->extra_instdone[i]); 372 373 if (INTEL_INFO(dev)->gen >= 6) { 374 err_printf(m, "ERROR: 0x%08x\n", error->error); 375 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 376 } 377 378 if (INTEL_INFO(dev)->gen == 7) 379 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 380 381 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 382 err_printf(m, "%s command stream:\n", ring_str(i)); 383 i915_ring_error_state(m, dev, &error->ring[i]); 384 } 385 386 if (error->active_bo) 387 print_error_buffers(m, "Active", 388 error->active_bo[0], 389 error->active_bo_count[0]); 390 391 if (error->pinned_bo) 392 print_error_buffers(m, "Pinned", 393 error->pinned_bo[0], 394 error->pinned_bo_count[0]); 395 396 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 397 struct drm_i915_error_object *obj; 398 399 obj = error->ring[i].batchbuffer; 400 if (obj) { 401 err_puts(m, dev_priv->ring[i].name); 402 if (error->ring[i].pid != -1) 403 err_printf(m, " (submitted by %s [%d])", 404 error->ring[i].comm, 405 error->ring[i].pid); 406 err_printf(m, " --- gtt_offset = 0x%08x\n", 407 obj->gtt_offset); 408 print_error_obj(m, obj); 409 } 410 411 obj = error->ring[i].wa_batchbuffer; 412 if (obj) { 413 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 414 dev_priv->ring[i].name, obj->gtt_offset); 415 print_error_obj(m, obj); 416 } 417 418 if (error->ring[i].num_requests) { 419 err_printf(m, "%s --- %d requests\n", 420 dev_priv->ring[i].name, 421 error->ring[i].num_requests); 422 for (j = 0; j < error->ring[i].num_requests; j++) { 423 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 424 error->ring[i].requests[j].seqno, 425 error->ring[i].requests[j].jiffies, 426 error->ring[i].requests[j].tail); 427 } 428 } 429 430 if ((obj = error->ring[i].ringbuffer)) { 431 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 432 dev_priv->ring[i].name, 433 obj->gtt_offset); 434 print_error_obj(m, obj); 435 } 436 437 if ((obj = error->ring[i].hws_page)) { 438 err_printf(m, "%s --- HW Status = 0x%08x\n", 439 dev_priv->ring[i].name, 440 obj->gtt_offset); 441 offset = 0; 442 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 443 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 444 offset, 445 obj->pages[0][elt], 446 obj->pages[0][elt+1], 447 obj->pages[0][elt+2], 448 obj->pages[0][elt+3]); 449 offset += 16; 450 } 451 } 452 453 if ((obj = error->ring[i].ctx)) { 454 err_printf(m, "%s --- HW Context = 0x%08x\n", 455 dev_priv->ring[i].name, 456 obj->gtt_offset); 457 print_error_obj(m, obj); 458 } 459 } 460 461 if (error->overlay) 462 intel_overlay_print_error_state(m, error->overlay); 463 464 if (error->display) 465 intel_display_print_error_state(m, dev, error->display); 466 467out: 468 if (m->bytes == 0 && m->err) 469 return m->err; 470 471 return 0; 472} 473 474int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 475 size_t count, loff_t pos) 476{ 477 memset(ebuf, 0, sizeof(*ebuf)); 478 479 /* We need to have enough room to store any i915_error_state printf 480 * so that we can move it to start position. 481 */ 482 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 483 ebuf->buf = kmalloc(ebuf->size, 484 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 485 486 if (ebuf->buf == NULL) { 487 ebuf->size = PAGE_SIZE; 488 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 489 } 490 491 if (ebuf->buf == NULL) { 492 ebuf->size = 128; 493 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 494 } 495 496 if (ebuf->buf == NULL) 497 return -ENOMEM; 498 499 ebuf->start = pos; 500 501 return 0; 502} 503 504static void i915_error_object_free(struct drm_i915_error_object *obj) 505{ 506 int page; 507 508 if (obj == NULL) 509 return; 510 511 for (page = 0; page < obj->page_count; page++) 512 kfree(obj->pages[page]); 513 514 kfree(obj); 515} 516 517static void i915_error_state_free(struct kref *error_ref) 518{ 519 struct drm_i915_error_state *error = container_of(error_ref, 520 typeof(*error), ref); 521 int i; 522 523 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 524 i915_error_object_free(error->ring[i].batchbuffer); 525 i915_error_object_free(error->ring[i].ringbuffer); 526 i915_error_object_free(error->ring[i].hws_page); 527 i915_error_object_free(error->ring[i].ctx); 528 kfree(error->ring[i].requests); 529 } 530 531 kfree(error->active_bo); 532 kfree(error->overlay); 533 kfree(error->display); 534 kfree(error); 535} 536 537static struct drm_i915_error_object * 538i915_error_object_create_sized(struct drm_i915_private *dev_priv, 539 struct drm_i915_gem_object *src, 540 struct i915_address_space *vm, 541 const int num_pages) 542{ 543 struct drm_i915_error_object *dst; 544 int i; 545 u32 reloc_offset; 546 547 if (src == NULL || src->pages == NULL) 548 return NULL; 549 550 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 551 if (dst == NULL) 552 return NULL; 553 554 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); 555 for (i = 0; i < num_pages; i++) { 556 unsigned long flags; 557 void *d; 558 559 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 560 if (d == NULL) 561 goto unwind; 562 563 local_irq_save(flags); 564 if (src->cache_level == I915_CACHE_NONE && 565 reloc_offset < dev_priv->gtt.mappable_end && 566 src->has_global_gtt_mapping && 567 i915_is_ggtt(vm)) { 568 void __iomem *s; 569 570 /* Simply ignore tiling or any overlapping fence. 571 * It's part of the error state, and this hopefully 572 * captures what the GPU read. 573 */ 574 575 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 576 reloc_offset); 577 memcpy_fromio(d, s, PAGE_SIZE); 578 io_mapping_unmap_atomic(s); 579 } else if (src->stolen) { 580 unsigned long offset; 581 582 offset = dev_priv->mm.stolen_base; 583 offset += src->stolen->start; 584 offset += i << PAGE_SHIFT; 585 586 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); 587 } else { 588 struct page *page; 589 void *s; 590 591 page = i915_gem_object_get_page(src, i); 592 593 drm_clflush_pages(&page, 1); 594 595 s = kmap_atomic(page); 596 memcpy(d, s, PAGE_SIZE); 597 kunmap_atomic(s); 598 599 drm_clflush_pages(&page, 1); 600 } 601 local_irq_restore(flags); 602 603 dst->pages[i] = d; 604 605 reloc_offset += PAGE_SIZE; 606 } 607 dst->page_count = num_pages; 608 609 return dst; 610 611unwind: 612 while (i--) 613 kfree(dst->pages[i]); 614 kfree(dst); 615 return NULL; 616} 617#define i915_error_object_create(dev_priv, src, vm) \ 618 i915_error_object_create_sized((dev_priv), (src), (vm), \ 619 (src)->base.size>>PAGE_SHIFT) 620 621#define i915_error_ggtt_object_create(dev_priv, src) \ 622 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ 623 (src)->base.size>>PAGE_SHIFT) 624 625static void capture_bo(struct drm_i915_error_buffer *err, 626 struct drm_i915_gem_object *obj) 627{ 628 err->size = obj->base.size; 629 err->name = obj->base.name; 630 err->rseqno = obj->last_read_seqno; 631 err->wseqno = obj->last_write_seqno; 632 err->gtt_offset = i915_gem_obj_ggtt_offset(obj); 633 err->read_domains = obj->base.read_domains; 634 err->write_domain = obj->base.write_domain; 635 err->fence_reg = obj->fence_reg; 636 err->pinned = 0; 637 if (i915_gem_obj_is_pinned(obj)) 638 err->pinned = 1; 639 if (obj->user_pin_count > 0) 640 err->pinned = -1; 641 err->tiling = obj->tiling_mode; 642 err->dirty = obj->dirty; 643 err->purgeable = obj->madv != I915_MADV_WILLNEED; 644 err->ring = obj->ring ? obj->ring->id : -1; 645 err->cache_level = obj->cache_level; 646} 647 648static u32 capture_active_bo(struct drm_i915_error_buffer *err, 649 int count, struct list_head *head) 650{ 651 struct i915_vma *vma; 652 int i = 0; 653 654 list_for_each_entry(vma, head, mm_list) { 655 capture_bo(err++, vma->obj); 656 if (++i == count) 657 break; 658 } 659 660 return i; 661} 662 663static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 664 int count, struct list_head *head) 665{ 666 struct drm_i915_gem_object *obj; 667 int i = 0; 668 669 list_for_each_entry(obj, head, global_list) { 670 if (!i915_gem_obj_is_pinned(obj)) 671 continue; 672 673 capture_bo(err++, obj); 674 if (++i == count) 675 break; 676 } 677 678 return i; 679} 680 681/* Generate a semi-unique error code. The code is not meant to have meaning, The 682 * code's only purpose is to try to prevent false duplicated bug reports by 683 * grossly estimating a GPU error state. 684 * 685 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 686 * the hang if we could strip the GTT offset information from it. 687 * 688 * It's only a small step better than a random number in its current form. 689 */ 690static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 691 struct drm_i915_error_state *error, 692 int *ring_id) 693{ 694 uint32_t error_code = 0; 695 int i; 696 697 /* IPEHR would be an ideal way to detect errors, as it's the gross 698 * measure of "the command that hung." However, has some very common 699 * synchronization commands which almost always appear in the case 700 * strictly a client bug. Use instdone to differentiate those some. 701 */ 702 for (i = 0; i < I915_NUM_RINGS; i++) { 703 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 704 if (ring_id) 705 *ring_id = i; 706 707 return error->ring[i].ipehr ^ error->ring[i].instdone; 708 } 709 } 710 711 return error_code; 712} 713 714static void i915_gem_record_fences(struct drm_device *dev, 715 struct drm_i915_error_state *error) 716{ 717 struct drm_i915_private *dev_priv = dev->dev_private; 718 int i; 719 720 /* Fences */ 721 switch (INTEL_INFO(dev)->gen) { 722 case 8: 723 case 7: 724 case 6: 725 for (i = 0; i < dev_priv->num_fence_regs; i++) 726 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 727 break; 728 case 5: 729 case 4: 730 for (i = 0; i < 16; i++) 731 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 732 break; 733 case 3: 734 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 735 for (i = 0; i < 8; i++) 736 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 737 case 2: 738 for (i = 0; i < 8; i++) 739 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 740 break; 741 742 default: 743 BUG(); 744 } 745} 746 747static void i915_record_ring_state(struct drm_device *dev, 748 struct intel_ring_buffer *ring, 749 struct drm_i915_error_ring *ering) 750{ 751 struct drm_i915_private *dev_priv = dev->dev_private; 752 753 if (INTEL_INFO(dev)->gen >= 6) { 754 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 755 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 756 ering->semaphore_mboxes[0] 757 = I915_READ(RING_SYNC_0(ring->mmio_base)); 758 ering->semaphore_mboxes[1] 759 = I915_READ(RING_SYNC_1(ring->mmio_base)); 760 ering->semaphore_seqno[0] = ring->sync_seqno[0]; 761 ering->semaphore_seqno[1] = ring->sync_seqno[1]; 762 } 763 764 if (HAS_VEBOX(dev)) { 765 ering->semaphore_mboxes[2] = 766 I915_READ(RING_SYNC_2(ring->mmio_base)); 767 ering->semaphore_seqno[2] = ring->sync_seqno[2]; 768 } 769 770 if (INTEL_INFO(dev)->gen >= 4) { 771 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 772 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 773 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 774 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 775 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 776 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 777 if (INTEL_INFO(dev)->gen >= 8) { 778 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 779 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 780 } 781 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 782 } else { 783 ering->faddr = I915_READ(DMA_FADD_I8XX); 784 ering->ipeir = I915_READ(IPEIR); 785 ering->ipehr = I915_READ(IPEHR); 786 ering->instdone = I915_READ(INSTDONE); 787 } 788 789 ering->waiting = waitqueue_active(&ring->irq_queue); 790 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 791 ering->seqno = ring->get_seqno(ring, false); 792 ering->acthd = intel_ring_get_active_head(ring); 793 ering->head = I915_READ_HEAD(ring); 794 ering->tail = I915_READ_TAIL(ring); 795 ering->ctl = I915_READ_CTL(ring); 796 797 if (I915_NEED_GFX_HWS(dev)) { 798 int mmio; 799 800 if (IS_GEN7(dev)) { 801 switch (ring->id) { 802 default: 803 case RCS: 804 mmio = RENDER_HWS_PGA_GEN7; 805 break; 806 case BCS: 807 mmio = BLT_HWS_PGA_GEN7; 808 break; 809 case VCS: 810 mmio = BSD_HWS_PGA_GEN7; 811 break; 812 case VECS: 813 mmio = VEBOX_HWS_PGA_GEN7; 814 break; 815 } 816 } else if (IS_GEN6(ring->dev)) { 817 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 818 } else { 819 /* XXX: gen8 returns to sanity */ 820 mmio = RING_HWS_PGA(ring->mmio_base); 821 } 822 823 ering->hws = I915_READ(mmio); 824 } 825 826 ering->cpu_ring_head = ring->head; 827 ering->cpu_ring_tail = ring->tail; 828 829 ering->hangcheck_score = ring->hangcheck.score; 830 ering->hangcheck_action = ring->hangcheck.action; 831 832 if (USES_PPGTT(dev)) { 833 int i; 834 835 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 836 837 switch (INTEL_INFO(dev)->gen) { 838 case 8: 839 for (i = 0; i < 4; i++) { 840 ering->vm_info.pdp[i] = 841 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 842 ering->vm_info.pdp[i] <<= 32; 843 ering->vm_info.pdp[i] |= 844 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 845 } 846 break; 847 case 7: 848 ering->vm_info.pp_dir_base = 849 I915_READ(RING_PP_DIR_BASE(ring)); 850 break; 851 case 6: 852 ering->vm_info.pp_dir_base = 853 I915_READ(RING_PP_DIR_BASE_READ(ring)); 854 break; 855 } 856 } 857} 858 859 860static void i915_gem_record_active_context(struct intel_ring_buffer *ring, 861 struct drm_i915_error_state *error, 862 struct drm_i915_error_ring *ering) 863{ 864 struct drm_i915_private *dev_priv = ring->dev->dev_private; 865 struct drm_i915_gem_object *obj; 866 867 /* Currently render ring is the only HW context user */ 868 if (ring->id != RCS || !error->ccid) 869 return; 870 871 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 872 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 873 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 874 break; 875 } 876 } 877} 878 879static void i915_gem_record_rings(struct drm_device *dev, 880 struct drm_i915_error_state *error) 881{ 882 struct drm_i915_private *dev_priv = dev->dev_private; 883 struct drm_i915_gem_request *request; 884 int i, count; 885 886 for (i = 0; i < I915_NUM_RINGS; i++) { 887 struct intel_ring_buffer *ring = &dev_priv->ring[i]; 888 889 if (ring->dev == NULL) 890 continue; 891 892 error->ring[i].valid = true; 893 894 i915_record_ring_state(dev, ring, &error->ring[i]); 895 896 error->ring[i].pid = -1; 897 request = i915_gem_find_active_request(ring); 898 if (request) { 899 /* We need to copy these to an anonymous buffer 900 * as the simplest method to avoid being overwritten 901 * by userspace. 902 */ 903 error->ring[i].batchbuffer = 904 i915_error_object_create(dev_priv, 905 request->batch_obj, 906 request->ctx ? 907 request->ctx->vm : 908 &dev_priv->gtt.base); 909 910 if (HAS_BROKEN_CS_TLB(dev_priv->dev) && 911 ring->scratch.obj) 912 error->ring[i].wa_batchbuffer = 913 i915_error_ggtt_object_create(dev_priv, 914 ring->scratch.obj); 915 916 if (request->file_priv) { 917 struct task_struct *task; 918 919 rcu_read_lock(); 920 task = pid_task(request->file_priv->file->pid, 921 PIDTYPE_PID); 922 if (task) { 923 strcpy(error->ring[i].comm, task->comm); 924 error->ring[i].pid = task->pid; 925 } 926 rcu_read_unlock(); 927 } 928 } 929 930 error->ring[i].ringbuffer = 931 i915_error_ggtt_object_create(dev_priv, ring->obj); 932 933 if (ring->status_page.obj) 934 error->ring[i].hws_page = 935 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 936 937 i915_gem_record_active_context(ring, error, &error->ring[i]); 938 939 count = 0; 940 list_for_each_entry(request, &ring->request_list, list) 941 count++; 942 943 error->ring[i].num_requests = count; 944 error->ring[i].requests = 945 kcalloc(count, sizeof(*error->ring[i].requests), 946 GFP_ATOMIC); 947 if (error->ring[i].requests == NULL) { 948 error->ring[i].num_requests = 0; 949 continue; 950 } 951 952 count = 0; 953 list_for_each_entry(request, &ring->request_list, list) { 954 struct drm_i915_error_request *erq; 955 956 erq = &error->ring[i].requests[count++]; 957 erq->seqno = request->seqno; 958 erq->jiffies = request->emitted_jiffies; 959 erq->tail = request->tail; 960 } 961 } 962} 963 964/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 965 * VM. 966 */ 967static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 968 struct drm_i915_error_state *error, 969 struct i915_address_space *vm, 970 const int ndx) 971{ 972 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 973 struct drm_i915_gem_object *obj; 974 struct i915_vma *vma; 975 int i; 976 977 i = 0; 978 list_for_each_entry(vma, &vm->active_list, mm_list) 979 i++; 980 error->active_bo_count[ndx] = i; 981 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 982 if (i915_gem_obj_is_pinned(obj)) 983 i++; 984 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 985 986 if (i) { 987 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 988 if (active_bo) 989 pinned_bo = active_bo + error->active_bo_count[ndx]; 990 } 991 992 if (active_bo) 993 error->active_bo_count[ndx] = 994 capture_active_bo(active_bo, 995 error->active_bo_count[ndx], 996 &vm->active_list); 997 998 if (pinned_bo) 999 error->pinned_bo_count[ndx] = 1000 capture_pinned_bo(pinned_bo, 1001 error->pinned_bo_count[ndx], 1002 &dev_priv->mm.bound_list); 1003 error->active_bo[ndx] = active_bo; 1004 error->pinned_bo[ndx] = pinned_bo; 1005} 1006 1007static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1008 struct drm_i915_error_state *error) 1009{ 1010 struct i915_address_space *vm; 1011 int cnt = 0, i = 0; 1012 1013 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1014 cnt++; 1015 1016 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1017 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1018 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1019 GFP_ATOMIC); 1020 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1021 GFP_ATOMIC); 1022 1023 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1024 i915_gem_capture_vm(dev_priv, error, vm, i++); 1025} 1026 1027/* Capture all registers which don't fit into another category. */ 1028static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1029 struct drm_i915_error_state *error) 1030{ 1031 struct drm_device *dev = dev_priv->dev; 1032 1033 /* General organization 1034 * 1. Registers specific to a single generation 1035 * 2. Registers which belong to multiple generations 1036 * 3. Feature specific registers. 1037 * 4. Everything else 1038 * Please try to follow the order. 1039 */ 1040 1041 /* 1: Registers specific to a single generation */ 1042 if (IS_VALLEYVIEW(dev)) { 1043 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1044 error->forcewake = I915_READ(FORCEWAKE_VLV); 1045 } 1046 1047 if (IS_GEN7(dev)) 1048 error->err_int = I915_READ(GEN7_ERR_INT); 1049 1050 if (IS_GEN6(dev)) { 1051 error->forcewake = I915_READ(FORCEWAKE); 1052 error->gab_ctl = I915_READ(GAB_CTL); 1053 error->gfx_mode = I915_READ(GFX_MODE); 1054 } 1055 1056 /* 2: Registers which belong to multiple generations */ 1057 if (INTEL_INFO(dev)->gen >= 7) 1058 error->forcewake = I915_READ(FORCEWAKE_MT); 1059 1060 if (INTEL_INFO(dev)->gen >= 6) { 1061 error->derrmr = I915_READ(DERRMR); 1062 error->error = I915_READ(ERROR_GEN6); 1063 error->done_reg = I915_READ(DONE_REG); 1064 } 1065 1066 /* 3: Feature specific registers */ 1067 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1068 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1069 error->gac_eco = I915_READ(GAC_ECO_BITS); 1070 } 1071 1072 /* 4: Everything else */ 1073 if (HAS_HW_CONTEXTS(dev)) 1074 error->ccid = I915_READ(CCID); 1075 1076 if (HAS_PCH_SPLIT(dev)) 1077 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1078 else { 1079 if (IS_GEN2(dev)) 1080 error->ier = I915_READ16(IER); 1081 else 1082 error->ier = I915_READ(IER); 1083 } 1084 1085 /* 4: Everything else */ 1086 error->eir = I915_READ(EIR); 1087 error->pgtbl_er = I915_READ(PGTBL_ER); 1088 1089 i915_get_extra_instdone(dev, error->extra_instdone); 1090} 1091 1092static void i915_error_capture_msg(struct drm_device *dev, 1093 struct drm_i915_error_state *error, 1094 bool wedged, 1095 const char *error_msg) 1096{ 1097 struct drm_i915_private *dev_priv = dev->dev_private; 1098 u32 ecode; 1099 int ring_id = -1, len; 1100 1101 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1102 1103 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1104 "GPU HANG: ecode %d:0x%08x", ring_id, ecode); 1105 1106 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1107 len += scnprintf(error->error_msg + len, 1108 sizeof(error->error_msg) - len, 1109 ", in %s [%d]", 1110 error->ring[ring_id].comm, 1111 error->ring[ring_id].pid); 1112 1113 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1114 ", reason: %s, action: %s", 1115 error_msg, 1116 wedged ? "reset" : "continue"); 1117} 1118 1119static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1120 struct drm_i915_error_state *error) 1121{ 1122 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1123 error->suspend_count = dev_priv->suspend_count; 1124} 1125 1126/** 1127 * i915_capture_error_state - capture an error record for later analysis 1128 * @dev: drm device 1129 * 1130 * Should be called when an error is detected (either a hang or an error 1131 * interrupt) to capture error state from the time of the error. Fills 1132 * out a structure which becomes available in debugfs for user level tools 1133 * to pick up. 1134 */ 1135void i915_capture_error_state(struct drm_device *dev, bool wedged, 1136 const char *error_msg) 1137{ 1138 static bool warned; 1139 struct drm_i915_private *dev_priv = dev->dev_private; 1140 struct drm_i915_error_state *error; 1141 unsigned long flags; 1142 1143 /* Account for pipe specific data like PIPE*STAT */ 1144 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1145 if (!error) { 1146 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1147 return; 1148 } 1149 1150 kref_init(&error->ref); 1151 1152 i915_capture_gen_state(dev_priv, error); 1153 i915_capture_reg_state(dev_priv, error); 1154 i915_gem_capture_buffers(dev_priv, error); 1155 i915_gem_record_fences(dev, error); 1156 i915_gem_record_rings(dev, error); 1157 1158 do_gettimeofday(&error->time); 1159 1160 error->overlay = intel_overlay_capture_error_state(dev); 1161 error->display = intel_display_capture_error_state(dev); 1162 1163 i915_error_capture_msg(dev, error, wedged, error_msg); 1164 DRM_INFO("%s\n", error->error_msg); 1165 1166 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1167 if (dev_priv->gpu_error.first_error == NULL) { 1168 dev_priv->gpu_error.first_error = error; 1169 error = NULL; 1170 } 1171 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1172 1173 if (error) { 1174 i915_error_state_free(&error->ref); 1175 return; 1176 } 1177 1178 if (!warned) { 1179 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1180 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1181 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1182 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1183 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1184 warned = true; 1185 } 1186} 1187 1188void i915_error_state_get(struct drm_device *dev, 1189 struct i915_error_state_file_priv *error_priv) 1190{ 1191 struct drm_i915_private *dev_priv = dev->dev_private; 1192 unsigned long flags; 1193 1194 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1195 error_priv->error = dev_priv->gpu_error.first_error; 1196 if (error_priv->error) 1197 kref_get(&error_priv->error->ref); 1198 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1199 1200} 1201 1202void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1203{ 1204 if (error_priv->error) 1205 kref_put(&error_priv->error->ref, i915_error_state_free); 1206} 1207 1208void i915_destroy_error_state(struct drm_device *dev) 1209{ 1210 struct drm_i915_private *dev_priv = dev->dev_private; 1211 struct drm_i915_error_state *error; 1212 unsigned long flags; 1213 1214 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1215 error = dev_priv->gpu_error.first_error; 1216 dev_priv->gpu_error.first_error = NULL; 1217 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1218 1219 if (error) 1220 kref_put(&error->ref, i915_error_state_free); 1221} 1222 1223const char *i915_cache_level_str(int type) 1224{ 1225 switch (type) { 1226 case I915_CACHE_NONE: return " uncached"; 1227 case I915_CACHE_LLC: return " snooped or LLC"; 1228 case I915_CACHE_L3_LLC: return " L3+LLC"; 1229 case I915_CACHE_WT: return " WT"; 1230 default: return ""; 1231 } 1232} 1233 1234/* NB: please notice the memset */ 1235void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1236{ 1237 struct drm_i915_private *dev_priv = dev->dev_private; 1238 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1239 1240 switch (INTEL_INFO(dev)->gen) { 1241 case 2: 1242 case 3: 1243 instdone[0] = I915_READ(INSTDONE); 1244 break; 1245 case 4: 1246 case 5: 1247 case 6: 1248 instdone[0] = I915_READ(INSTDONE_I965); 1249 instdone[1] = I915_READ(INSTDONE1); 1250 break; 1251 default: 1252 WARN_ONCE(1, "Unsupported platform\n"); 1253 case 7: 1254 case 8: 1255 instdone[0] = I915_READ(GEN7_INSTDONE_1); 1256 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1257 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1258 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1259 break; 1260 } 1261} 1262