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nv84_fence.c revision f589be88caf32501a734e531180d5df5d6089ef3 
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_dma.h"
28#include <engine/fifo.h>
29#include <core/ramht.h>
30#include "nouveau_fence.h"
31#include "nv50_display.h"
32
33struct nv84_fence_chan {
34	struct nouveau_fence_chan base;
35};
36
37struct nv84_fence_priv {
38	struct nouveau_fence_priv base;
39	struct nouveau_gpuobj *mem;
40};
41
42static int
43nv84_fence_emit(struct nouveau_fence *fence)
44{
45	struct nouveau_channel *chan = fence->channel;
46	int ret = RING_SPACE(chan, 7);
47	if (ret == 0) {
48		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
49		OUT_RING  (chan, NvSema);
50		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
51		OUT_RING  (chan, upper_32_bits(chan->id * 16));
52		OUT_RING  (chan, lower_32_bits(chan->id * 16));
53		OUT_RING  (chan, fence->sequence);
54		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
55		FIRE_RING (chan);
56	}
57	return ret;
58}
59
60
61static int
62nv84_fence_sync(struct nouveau_fence *fence,
63		struct nouveau_channel *prev, struct nouveau_channel *chan)
64{
65	int ret = RING_SPACE(chan, 7);
66	if (ret == 0) {
67		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
68		OUT_RING  (chan, NvSema);
69		BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
70		OUT_RING  (chan, upper_32_bits(prev->id * 16));
71		OUT_RING  (chan, lower_32_bits(prev->id * 16));
72		OUT_RING  (chan, fence->sequence);
73		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
74		FIRE_RING (chan);
75	}
76	return ret;
77}
78
79static u32
80nv84_fence_read(struct nouveau_channel *chan)
81{
82	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
83	struct nv84_fence_priv *priv = dev_priv->fence.func;
84	return nv_ro32(priv->mem, chan->id * 16);
85}
86
87static void
88nv84_fence_context_del(struct nouveau_channel *chan)
89{
90	struct nv84_fence_chan *fctx = chan->fence;
91	nouveau_fence_context_del(&fctx->base);
92	chan->fence = NULL;
93	kfree(fctx);
94}
95
96static int
97nv84_fence_context_new(struct nouveau_channel *chan)
98{
99	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
100	struct nv84_fence_priv *priv = dev_priv->fence.func;
101	struct nv84_fence_chan *fctx;
102	struct nouveau_gpuobj *obj;
103	int ret, i;
104
105	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
106	if (!fctx)
107		return -ENOMEM;
108
109	nouveau_fence_context_new(&fctx->base);
110
111	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
112				     priv->mem->addr, priv->mem->size,
113				     NV_MEM_ACCESS_RW,
114				     NV_MEM_TARGET_VRAM, &obj);
115	if (ret == 0) {
116		ret = nouveau_ramht_insert(chan, NvSema, obj);
117		nouveau_gpuobj_ref(NULL, &obj);
118		nv_wo32(priv->mem, chan->id * 16, 0x00000000);
119	}
120
121	/* dma objects for display sync channel semaphore blocks */
122	for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
123		struct nv50_display *pdisp = nv50_display(chan->dev);
124		struct nv50_display_crtc *dispc = &pdisp->crtc[i];
125		struct nouveau_gpuobj *obj = NULL;
126
127		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
128					     dispc->sem.bo->bo.offset, 0x1000,
129					     NV_MEM_ACCESS_RW,
130					     NV_MEM_TARGET_VRAM, &obj);
131		if (ret)
132			break;
133
134		ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
135		nouveau_gpuobj_ref(NULL, &obj);
136	}
137
138	if (ret)
139		nv84_fence_context_del(chan);
140	return ret;
141}
142
143static void
144nv84_fence_destroy(struct drm_device *dev)
145{
146	struct drm_nouveau_private *dev_priv = dev->dev_private;
147	struct nv84_fence_priv *priv = dev_priv->fence.func;
148
149	nouveau_gpuobj_ref(NULL, &priv->mem);
150	dev_priv->fence.func = NULL;
151	kfree(priv);
152}
153
154int
155nv84_fence_create(struct drm_device *dev)
156{
157	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
158	struct drm_nouveau_private *dev_priv = dev->dev_private;
159	struct nv84_fence_priv *priv;
160	int ret;
161
162	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
163	if (!priv)
164		return -ENOMEM;
165
166	priv->base.dtor = nv84_fence_destroy;
167	priv->base.context_new = nv84_fence_context_new;
168	priv->base.context_del = nv84_fence_context_del;
169	priv->base.emit = nv84_fence_emit;
170	priv->base.sync = nv84_fence_sync;
171	priv->base.read = nv84_fence_read;
172	dev_priv->fence.func = priv;
173
174	ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
175				 0x1000, 0, &priv->mem);
176	if (ret)
177		goto out;
178
179out:
180	if (ret)
181		nv84_fence_destroy(dev);
182	return ret;
183}
184