base.c revision ff4b42c7532e6ed6a5ae3c9cb71395b41a0a4022
1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25#include <core/object.h> 26#include <core/device.h> 27#include <core/client.h> 28#include <core/option.h> 29 30#include <core/class.h> 31 32#include <engine/device.h> 33 34static DEFINE_MUTEX(nv_devices_mutex); 35static LIST_HEAD(nv_devices); 36 37struct nouveau_device * 38nouveau_device_find(u64 name) 39{ 40 struct nouveau_device *device, *match = NULL; 41 mutex_lock(&nv_devices_mutex); 42 list_for_each_entry(device, &nv_devices, head) { 43 if (device->handle == name) { 44 match = device; 45 break; 46 } 47 } 48 mutex_unlock(&nv_devices_mutex); 49 return match; 50} 51 52/****************************************************************************** 53 * nouveau_devobj (0x0080): class implementation 54 *****************************************************************************/ 55struct nouveau_devobj { 56 struct nouveau_parent base; 57 struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; 58}; 59 60static const u64 disable_map[] = { 61 [NVDEV_SUBDEV_VBIOS] = NV_DEVICE_DISABLE_VBIOS, 62 [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_DISABLE_CORE, 63 [NVDEV_SUBDEV_GPIO] = NV_DEVICE_DISABLE_CORE, 64 [NVDEV_SUBDEV_I2C] = NV_DEVICE_DISABLE_CORE, 65 [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_DISABLE_CORE, 66 [NVDEV_SUBDEV_MXM] = NV_DEVICE_DISABLE_CORE, 67 [NVDEV_SUBDEV_MC] = NV_DEVICE_DISABLE_CORE, 68 [NVDEV_SUBDEV_BUS] = NV_DEVICE_DISABLE_CORE, 69 [NVDEV_SUBDEV_TIMER] = NV_DEVICE_DISABLE_CORE, 70 [NVDEV_SUBDEV_FB] = NV_DEVICE_DISABLE_CORE, 71 [NVDEV_SUBDEV_LTCG] = NV_DEVICE_DISABLE_CORE, 72 [NVDEV_SUBDEV_IBUS] = NV_DEVICE_DISABLE_CORE, 73 [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_DISABLE_CORE, 74 [NVDEV_SUBDEV_VM] = NV_DEVICE_DISABLE_CORE, 75 [NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE, 76 [NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE, 77 [NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE, 78 [NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE, 79 [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE, 80 [NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO, 81 [NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO, 82 [NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH, 83 [NVDEV_ENGINE_MPEG] = NV_DEVICE_DISABLE_MPEG, 84 [NVDEV_ENGINE_ME] = NV_DEVICE_DISABLE_ME, 85 [NVDEV_ENGINE_VP] = NV_DEVICE_DISABLE_VP, 86 [NVDEV_ENGINE_CRYPT] = NV_DEVICE_DISABLE_CRYPT, 87 [NVDEV_ENGINE_BSP] = NV_DEVICE_DISABLE_BSP, 88 [NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP, 89 [NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0, 90 [NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1, 91 [NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC, 92 [NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC, 93 [NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP, 94 [NVDEV_SUBDEV_NR] = 0, 95}; 96 97static int 98nouveau_devobj_ctor(struct nouveau_object *parent, 99 struct nouveau_object *engine, 100 struct nouveau_oclass *oclass, void *data, u32 size, 101 struct nouveau_object **pobject) 102{ 103 struct nouveau_client *client = nv_client(parent); 104 struct nouveau_device *device; 105 struct nouveau_devobj *devobj; 106 struct nv_device_class *args = data; 107 u32 boot0, strap; 108 u64 disable, mmio_base, mmio_size; 109 void __iomem *map; 110 int ret, i, c; 111 112 if (size < sizeof(struct nv_device_class)) 113 return -EINVAL; 114 115 /* find the device subdev that matches what the client requested */ 116 device = nv_device(client->device); 117 if (args->device != ~0) { 118 device = nouveau_device_find(args->device); 119 if (!device) 120 return -ENODEV; 121 } 122 123 ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL, 124 (1ULL << NVDEV_ENGINE_DMAOBJ) | 125 (1ULL << NVDEV_ENGINE_FIFO) | 126 (1ULL << NVDEV_ENGINE_DISP), &devobj); 127 *pobject = nv_object(devobj); 128 if (ret) 129 return ret; 130 131 mmio_base = pci_resource_start(device->pdev, 0); 132 mmio_size = pci_resource_len(device->pdev, 0); 133 134 /* translate api disable mask into internal mapping */ 135 disable = args->debug0; 136 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 137 if (args->disable & disable_map[i]) 138 disable |= (1ULL << i); 139 } 140 141 /* identify the chipset, and determine classes of subdev/engines */ 142 if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) && 143 !device->card_type) { 144 map = ioremap(mmio_base, 0x102000); 145 if (map == NULL) 146 return -ENOMEM; 147 148 /* switch mmio to cpu's native endianness */ 149#ifndef __BIG_ENDIAN 150 if (ioread32_native(map + 0x000004) != 0x00000000) 151#else 152 if (ioread32_native(map + 0x000004) == 0x00000000) 153#endif 154 iowrite32_native(0x01000001, map + 0x000004); 155 156 /* read boot0 and strapping information */ 157 boot0 = ioread32_native(map + 0x000000); 158 strap = ioread32_native(map + 0x101000); 159 iounmap(map); 160 161 /* determine chipset and derive architecture from it */ 162 if ((boot0 & 0x1f000000) > 0) { 163 device->chipset = (boot0 & 0x1ff00000) >> 20; 164 switch (device->chipset & 0x1f0) { 165 case 0x010: { 166 if (0x461 & (1 << (device->chipset & 0xf))) 167 device->card_type = NV_10; 168 else 169 device->card_type = NV_11; 170 break; 171 } 172 case 0x020: device->card_type = NV_20; break; 173 case 0x030: device->card_type = NV_30; break; 174 case 0x040: 175 case 0x060: device->card_type = NV_40; break; 176 case 0x050: 177 case 0x080: 178 case 0x090: 179 case 0x0a0: device->card_type = NV_50; break; 180 case 0x0c0: device->card_type = NV_C0; break; 181 case 0x0d0: device->card_type = NV_D0; break; 182 case 0x0e0: 183 case 0x0f0: 184 case 0x100: device->card_type = NV_E0; break; 185 default: 186 break; 187 } 188 } else 189 if ((boot0 & 0xff00fff0) == 0x20004000) { 190 if (boot0 & 0x00f00000) 191 device->chipset = 0x05; 192 else 193 device->chipset = 0x04; 194 device->card_type = NV_04; 195 } 196 197 switch (device->card_type) { 198 case NV_04: ret = nv04_identify(device); break; 199 case NV_10: 200 case NV_11: ret = nv10_identify(device); break; 201 case NV_20: ret = nv20_identify(device); break; 202 case NV_30: ret = nv30_identify(device); break; 203 case NV_40: ret = nv40_identify(device); break; 204 case NV_50: ret = nv50_identify(device); break; 205 case NV_C0: 206 case NV_D0: ret = nvc0_identify(device); break; 207 case NV_E0: ret = nve0_identify(device); break; 208 default: 209 ret = -EINVAL; 210 break; 211 } 212 213 if (ret) { 214 nv_error(device, "unknown chipset, 0x%08x\n", boot0); 215 return ret; 216 } 217 218 nv_info(device, "BOOT0 : 0x%08x\n", boot0); 219 nv_info(device, "Chipset: %s (NV%02X)\n", 220 device->cname, device->chipset); 221 nv_info(device, "Family : NV%02X\n", device->card_type); 222 223 /* determine frequency of timing crystal */ 224 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 225 (device->chipset >= 0x20 && device->chipset < 0x25)) 226 strap &= 0x00000040; 227 else 228 strap &= 0x00400040; 229 230 switch (strap) { 231 case 0x00000000: device->crystal = 13500; break; 232 case 0x00000040: device->crystal = 14318; break; 233 case 0x00400000: device->crystal = 27000; break; 234 case 0x00400040: device->crystal = 25000; break; 235 } 236 237 nv_debug(device, "crystal freq: %dKHz\n", device->crystal); 238 } 239 240 if (!(args->disable & NV_DEVICE_DISABLE_MMIO) && 241 !nv_subdev(device)->mmio) { 242 nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size); 243 if (!nv_subdev(device)->mmio) { 244 nv_error(device, "unable to map device registers\n"); 245 return -ENOMEM; 246 } 247 } 248 249 /* ensure requested subsystems are available for use */ 250 for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) { 251 if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) 252 continue; 253 254 if (device->subdev[i]) { 255 nouveau_object_ref(device->subdev[i], 256 &devobj->subdev[i]); 257 continue; 258 } 259 260 ret = nouveau_object_ctor(nv_object(device), NULL, 261 oclass, NULL, i, 262 &devobj->subdev[i]); 263 if (ret == -ENODEV) 264 continue; 265 if (ret) 266 return ret; 267 268 /* note: can't init *any* subdevs until devinit has been run 269 * due to not knowing exactly what the vbios init tables will 270 * mess with. devinit also can't be run until all of its 271 * dependencies have been created. 272 * 273 * this code delays init of any subdev until all of devinit's 274 * dependencies have been created, and then initialises each 275 * subdev in turn as they're created. 276 */ 277 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { 278 struct nouveau_object *subdev = devobj->subdev[c++]; 279 if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { 280 ret = nouveau_object_inc(subdev); 281 if (ret) 282 return ret; 283 atomic_dec(&nv_object(device)->usecount); 284 } else 285 if (subdev) { 286 nouveau_subdev_reset(subdev); 287 } 288 } 289 } 290 291 return 0; 292} 293 294static void 295nouveau_devobj_dtor(struct nouveau_object *object) 296{ 297 struct nouveau_devobj *devobj = (void *)object; 298 int i; 299 300 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) 301 nouveau_object_ref(NULL, &devobj->subdev[i]); 302 303 nouveau_parent_destroy(&devobj->base); 304} 305 306static u8 307nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) 308{ 309 return nv_rd08(object->engine, addr); 310} 311 312static u16 313nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) 314{ 315 return nv_rd16(object->engine, addr); 316} 317 318static u32 319nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) 320{ 321 return nv_rd32(object->engine, addr); 322} 323 324static void 325nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) 326{ 327 nv_wr08(object->engine, addr, data); 328} 329 330static void 331nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) 332{ 333 nv_wr16(object->engine, addr, data); 334} 335 336static void 337nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) 338{ 339 nv_wr32(object->engine, addr, data); 340} 341 342static struct nouveau_ofuncs 343nouveau_devobj_ofuncs = { 344 .ctor = nouveau_devobj_ctor, 345 .dtor = nouveau_devobj_dtor, 346 .init = _nouveau_parent_init, 347 .fini = _nouveau_parent_fini, 348 .rd08 = nouveau_devobj_rd08, 349 .rd16 = nouveau_devobj_rd16, 350 .rd32 = nouveau_devobj_rd32, 351 .wr08 = nouveau_devobj_wr08, 352 .wr16 = nouveau_devobj_wr16, 353 .wr32 = nouveau_devobj_wr32, 354}; 355 356/****************************************************************************** 357 * nouveau_device: engine functions 358 *****************************************************************************/ 359static struct nouveau_oclass 360nouveau_device_sclass[] = { 361 { 0x0080, &nouveau_devobj_ofuncs }, 362 {} 363}; 364 365static int 366nouveau_device_fini(struct nouveau_object *object, bool suspend) 367{ 368 struct nouveau_device *device = (void *)object; 369 struct nouveau_object *subdev; 370 int ret, i; 371 372 for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { 373 if ((subdev = device->subdev[i])) { 374 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 375 ret = nouveau_object_dec(subdev, suspend); 376 if (ret && suspend) 377 goto fail; 378 } 379 } 380 } 381 382 ret = 0; 383fail: 384 for (; ret && i < NVDEV_SUBDEV_NR; i++) { 385 if ((subdev = device->subdev[i])) { 386 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 387 ret = nouveau_object_inc(subdev); 388 if (ret) { 389 /* XXX */ 390 } 391 } 392 } 393 } 394 395 return ret; 396} 397 398static int 399nouveau_device_init(struct nouveau_object *object) 400{ 401 struct nouveau_device *device = (void *)object; 402 struct nouveau_object *subdev; 403 int ret, i; 404 405 for (i = 0; i < NVDEV_SUBDEV_NR; i++) { 406 if ((subdev = device->subdev[i])) { 407 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { 408 ret = nouveau_object_inc(subdev); 409 if (ret) 410 goto fail; 411 } else { 412 nouveau_subdev_reset(subdev); 413 } 414 } 415 } 416 417 ret = 0; 418fail: 419 for (--i; ret && i >= 0; i--) { 420 if ((subdev = device->subdev[i])) { 421 if (!nv_iclass(subdev, NV_ENGINE_CLASS)) 422 nouveau_object_dec(subdev, false); 423 } 424 } 425 426 return ret; 427} 428 429static void 430nouveau_device_dtor(struct nouveau_object *object) 431{ 432 struct nouveau_device *device = (void *)object; 433 434 mutex_lock(&nv_devices_mutex); 435 list_del(&device->head); 436 mutex_unlock(&nv_devices_mutex); 437 438 if (nv_subdev(device)->mmio) 439 iounmap(nv_subdev(device)->mmio); 440 441 nouveau_engine_destroy(&device->base); 442} 443 444static struct nouveau_oclass 445nouveau_device_oclass = { 446 .handle = NV_ENGINE(DEVICE, 0x00), 447 .ofuncs = &(struct nouveau_ofuncs) { 448 .dtor = nouveau_device_dtor, 449 .init = nouveau_device_init, 450 .fini = nouveau_device_fini, 451 }, 452}; 453 454int 455nouveau_device_create_(struct pci_dev *pdev, u64 name, const char *sname, 456 const char *cfg, const char *dbg, 457 int length, void **pobject) 458{ 459 struct nouveau_device *device; 460 int ret = -EEXIST; 461 462 mutex_lock(&nv_devices_mutex); 463 list_for_each_entry(device, &nv_devices, head) { 464 if (device->handle == name) 465 goto done; 466 } 467 468 ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, 469 "DEVICE", "device", length, pobject); 470 device = *pobject; 471 if (ret) 472 goto done; 473 474 device->pdev = pdev; 475 device->handle = name; 476 device->cfgopt = cfg; 477 device->dbgopt = dbg; 478 device->name = sname; 479 480 nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); 481 nv_engine(device)->sclass = nouveau_device_sclass; 482 list_add(&device->head, &nv_devices); 483done: 484 mutex_unlock(&nv_devices_mutex); 485 return ret; 486} 487