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1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/bios.h>
26#include <subdev/bios/bit.h>
27#include <subdev/bios/pll.h>
28#include <subdev/bios/init.h>
29#include <subdev/clock.h>
30#include <subdev/clock/pll.h>
31#include <subdev/timer.h>
32
33#include <engine/fifo.h>
34
35#include "nv40.h"
36
37int
38nv40_ram_calc(struct nouveau_fb *pfb, u32 freq)
39{
40	struct nouveau_bios *bios = nouveau_bios(pfb);
41	struct nv40_ram *ram = (void *)pfb->ram;
42	struct nvbios_pll pll;
43	int N1, M1, N2, M2;
44	int log2P, ret;
45
46	ret = nvbios_pll_parse(bios, 0x04, &pll);
47	if (ret) {
48		nv_error(pfb, "mclk pll data not found\n");
49		return ret;
50	}
51
52	ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,
53			    &N1, &M1, &N2, &M2, &log2P);
54	if (ret < 0)
55		return ret;
56
57	ram->ctrl  = 0x80000000 | (log2P << 16);
58	ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;
59	if (N2 == M2) {
60		ram->ctrl |= 0x00000100;
61		ram->coef  = (N1 << 8) | M1;
62	} else {
63		ram->ctrl |= 0x40000000;
64		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
65	}
66
67	return 0;
68}
69
70int
71nv40_ram_prog(struct nouveau_fb *pfb)
72{
73	struct nouveau_bios *bios = nouveau_bios(pfb);
74	struct nv40_ram *ram = (void *)pfb->ram;
75	struct bit_entry M;
76	u32 crtc_mask = 0;
77	u8  sr1[2];
78	int i;
79
80	/* determine which CRTCs are active, fetch VGA_SR1 for each */
81	for (i = 0; i < 2; i++) {
82		u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));
83		u32 cnt = 0;
84		do {
85			if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) {
86				nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
87				sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000));
88				if (!(sr1[i] & 0x20))
89					crtc_mask |= (1 << i);
90				break;
91			}
92			udelay(1);
93		} while (cnt++ < 32);
94	}
95
96	/* wait for vblank start on active crtcs, disable memory access */
97	for (i = 0; i < 2; i++) {
98		if (!(crtc_mask & (1 << i)))
99			continue;
100		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
101		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
102		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
103		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
104	}
105
106	/* prepare ram for reclocking */
107	nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */
108	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
109	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */
110	nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
111	nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */
112
113	/* change the PLL of each memory partition */
114	nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000);
115	switch (nv_device(pfb)->chipset) {
116	case 0x40:
117	case 0x45:
118	case 0x41:
119	case 0x42:
120	case 0x47:
121		nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);
122		nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);
123		nv_wr32(pfb, 0x004048, ram->coef);
124		nv_wr32(pfb, 0x004030, ram->coef);
125	case 0x43:
126	case 0x49:
127	case 0x4b:
128		nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);
129		nv_wr32(pfb, 0x00403c, ram->coef);
130	default:
131		nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);
132		nv_wr32(pfb, 0x004024, ram->coef);
133		break;
134	}
135	udelay(100);
136	nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000);
137
138	/* re-enable normal operation of memory controller */
139	nv_wr32(pfb, 0x1002dc, 0x00000000);
140	nv_mask(pfb, 0x100210, 0x80000000, 0x80000000);
141	udelay(100);
142
143	/* execute memory reset script from vbios */
144	if (!bit_entry(bios, 'M', &M)) {
145		struct nvbios_init init = {
146			.subdev = nv_subdev(pfb),
147			.bios = bios,
148			.offset = nv_ro16(bios, M.offset + 0x00),
149			.execute = 1,
150		};
151
152		nvbios_exec(&init);
153	}
154
155	/* make sure we're in vblank (hopefully the same one as before), and
156	 * then re-enable crtc memory access
157	 */
158	for (i = 0; i < 2; i++) {
159		if (!(crtc_mask & (1 << i)))
160			continue;
161		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
162		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);
163		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]);
164	}
165
166	return 0;
167}
168
169void
170nv40_ram_tidy(struct nouveau_fb *pfb)
171{
172}
173
174static int
175nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
176		struct nouveau_oclass *oclass, void *data, u32 size,
177		struct nouveau_object **pobject)
178{
179	struct nouveau_fb *pfb = nouveau_fb(parent);
180	struct nv40_ram *ram;
181	u32 pbus1218 = nv_rd32(pfb, 0x001218);
182	int ret;
183
184	ret = nouveau_ram_create(parent, engine, oclass, &ram);
185	*pobject = nv_object(ram);
186	if (ret)
187		return ret;
188
189	switch (pbus1218 & 0x00000300) {
190	case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break;
191	case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break;
192	case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break;
193	case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
194	}
195
196	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
197	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
198	ram->base.tags  =  nv_rd32(pfb, 0x100320);
199	ram->base.calc = nv40_ram_calc;
200	ram->base.prog = nv40_ram_prog;
201	ram->base.tidy = nv40_ram_tidy;
202	return 0;
203}
204
205
206struct nouveau_oclass
207nv40_ram_oclass = {
208	.handle = 0,
209	.ofuncs = &(struct nouveau_ofuncs) {
210		.ctor = nv40_ram_create,
211		.dtor = _nouveau_ram_dtor,
212		.init = _nouveau_ram_init,
213		.fini = _nouveau_ram_fini,
214	}
215};
216