[go: nahoru, domu]
1/*
2 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
3 *
4 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * Author: Yang, Bin <bin.yang@intel.com>
16 */
17
18#include <linux/interrupt.h>
19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/seq_file.h>
22#include <linux/bitops.h>
23#include <linux/regmap.h>
24#include <linux/mfd/intel_soc_pmic.h>
25
26#define CRYSTALCOVE_GPIO_NUM	16
27#define CRYSTALCOVE_VGPIO_NUM	94
28
29#define UPDATE_IRQ_TYPE		BIT(0)
30#define UPDATE_IRQ_MASK		BIT(1)
31
32#define GPIO0IRQ		0x0b
33#define GPIO1IRQ		0x0c
34#define MGPIO0IRQS0		0x19
35#define MGPIO1IRQS0		0x1a
36#define MGPIO0IRQSX		0x1b
37#define MGPIO1IRQSX		0x1c
38#define GPIO0P0CTLO		0x2b
39#define GPIO0P0CTLI		0x33
40#define GPIO1P0CTLO		0x3b
41#define GPIO1P0CTLI		0x43
42
43#define CTLI_INTCNT_DIS		(0)
44#define CTLI_INTCNT_NE		(1 << 1)
45#define CTLI_INTCNT_PE		(2 << 1)
46#define CTLI_INTCNT_BE		(3 << 1)
47
48#define CTLO_DIR_IN		(0)
49#define CTLO_DIR_OUT		(1 << 5)
50
51#define CTLO_DRV_CMOS		(0)
52#define CTLO_DRV_OD		(1 << 4)
53
54#define CTLO_DRV_REN		(1 << 3)
55
56#define CTLO_RVAL_2KDW		(0)
57#define CTLO_RVAL_2KUP		(1 << 1)
58#define CTLO_RVAL_50KDW		(2 << 1)
59#define CTLO_RVAL_50KUP		(3 << 1)
60
61#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
62#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)
63
64enum ctrl_register {
65	CTRL_IN,
66	CTRL_OUT,
67};
68
69/**
70 * struct crystalcove_gpio - Crystal Cove GPIO controller
71 * @buslock: for bus lock/sync and unlock.
72 * @chip: the abstract gpio_chip structure.
73 * @regmap: the regmap from the parent device.
74 * @update: pending IRQ setting update, to be written to the chip upon unlock.
75 * @intcnt_value: the Interrupt Detect value to be written.
76 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
77 */
78struct crystalcove_gpio {
79	struct mutex buslock; /* irq_bus_lock */
80	struct gpio_chip chip;
81	struct regmap *regmap;
82	int update;
83	int intcnt_value;
84	bool set_irq_mask;
85};
86
87static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
88{
89	return container_of(gc, struct crystalcove_gpio, chip);
90}
91
92static inline int to_reg(int gpio, enum ctrl_register reg_type)
93{
94	int reg;
95
96	if (reg_type == CTRL_IN) {
97		if (gpio < 8)
98			reg = GPIO0P0CTLI;
99		else
100			reg = GPIO1P0CTLI;
101	} else {
102		if (gpio < 8)
103			reg = GPIO0P0CTLO;
104		else
105			reg = GPIO1P0CTLO;
106	}
107
108	return reg + gpio % 8;
109}
110
111static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
112					int gpio)
113{
114	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
115	int mask = BIT(gpio % 8);
116
117	if (cg->set_irq_mask)
118		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
119	else
120		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
121}
122
123static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
124{
125	int reg = to_reg(gpio, CTRL_IN);
126
127	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
128}
129
130static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
131{
132	struct crystalcove_gpio *cg = to_cg(chip);
133
134	if (gpio > CRYSTALCOVE_VGPIO_NUM)
135		return 0;
136
137	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
138			    CTLO_INPUT_SET);
139}
140
141static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
142				    int value)
143{
144	struct crystalcove_gpio *cg = to_cg(chip);
145
146	if (gpio > CRYSTALCOVE_VGPIO_NUM)
147		return 0;
148
149	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
150			    CTLO_OUTPUT_SET | value);
151}
152
153static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
154{
155	struct crystalcove_gpio *cg = to_cg(chip);
156	int ret;
157	unsigned int val;
158
159	if (gpio > CRYSTALCOVE_VGPIO_NUM)
160		return 0;
161
162	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
163	if (ret)
164		return ret;
165
166	return val & 0x1;
167}
168
169static void crystalcove_gpio_set(struct gpio_chip *chip,
170				 unsigned gpio, int value)
171{
172	struct crystalcove_gpio *cg = to_cg(chip);
173
174	if (gpio > CRYSTALCOVE_VGPIO_NUM)
175		return;
176
177	if (value)
178		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
179	else
180		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
181}
182
183static int crystalcove_irq_type(struct irq_data *data, unsigned type)
184{
185	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
186
187	switch (type) {
188	case IRQ_TYPE_NONE:
189		cg->intcnt_value = CTLI_INTCNT_DIS;
190		break;
191	case IRQ_TYPE_EDGE_BOTH:
192		cg->intcnt_value = CTLI_INTCNT_BE;
193		break;
194	case IRQ_TYPE_EDGE_RISING:
195		cg->intcnt_value = CTLI_INTCNT_PE;
196		break;
197	case IRQ_TYPE_EDGE_FALLING:
198		cg->intcnt_value = CTLI_INTCNT_NE;
199		break;
200	default:
201		return -EINVAL;
202	}
203
204	cg->update |= UPDATE_IRQ_TYPE;
205
206	return 0;
207}
208
209static void crystalcove_bus_lock(struct irq_data *data)
210{
211	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
212
213	mutex_lock(&cg->buslock);
214}
215
216static void crystalcove_bus_sync_unlock(struct irq_data *data)
217{
218	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
219	int gpio = data->hwirq;
220
221	if (cg->update & UPDATE_IRQ_TYPE)
222		crystalcove_update_irq_ctrl(cg, gpio);
223	if (cg->update & UPDATE_IRQ_MASK)
224		crystalcove_update_irq_mask(cg, gpio);
225	cg->update = 0;
226
227	mutex_unlock(&cg->buslock);
228}
229
230static void crystalcove_irq_unmask(struct irq_data *data)
231{
232	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
233
234	cg->set_irq_mask = false;
235	cg->update |= UPDATE_IRQ_MASK;
236}
237
238static void crystalcove_irq_mask(struct irq_data *data)
239{
240	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
241
242	cg->set_irq_mask = true;
243	cg->update |= UPDATE_IRQ_MASK;
244}
245
246static struct irq_chip crystalcove_irqchip = {
247	.name			= "Crystal Cove",
248	.irq_mask		= crystalcove_irq_mask,
249	.irq_unmask		= crystalcove_irq_unmask,
250	.irq_set_type		= crystalcove_irq_type,
251	.irq_bus_lock		= crystalcove_bus_lock,
252	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
253};
254
255static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
256{
257	struct crystalcove_gpio *cg = data;
258	unsigned int p0, p1;
259	int pending;
260	int gpio;
261	unsigned int virq;
262
263	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
264	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
265		return IRQ_NONE;
266
267	regmap_write(cg->regmap, GPIO0IRQ, p0);
268	regmap_write(cg->regmap, GPIO1IRQ, p1);
269
270	pending = p0 | p1 << 8;
271
272	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
273		if (pending & BIT(gpio)) {
274			virq = irq_find_mapping(cg->chip.irqdomain, gpio);
275			generic_handle_irq(virq);
276		}
277	}
278
279	return IRQ_HANDLED;
280}
281
282static void crystalcove_gpio_dbg_show(struct seq_file *s,
283				      struct gpio_chip *chip)
284{
285	struct crystalcove_gpio *cg = to_cg(chip);
286	int gpio, offset;
287	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
288
289	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
290		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
291		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
292		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
293			    &mirqs0);
294		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
295			    &mirqsx);
296		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
297			    &irq);
298
299		offset = gpio % 8;
300		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
301			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
302			   ctli & 0x1 ? "hi" : "lo",
303			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
304			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
305			   ctlo,
306			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
307			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
308			   irq & BIT(offset) ? "pending" : "       ");
309	}
310}
311
312static int crystalcove_gpio_probe(struct platform_device *pdev)
313{
314	int irq = platform_get_irq(pdev, 0);
315	struct crystalcove_gpio *cg;
316	int retval;
317	struct device *dev = pdev->dev.parent;
318	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
319
320	if (irq < 0)
321		return irq;
322
323	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
324	if (!cg)
325		return -ENOMEM;
326
327	platform_set_drvdata(pdev, cg);
328
329	mutex_init(&cg->buslock);
330	cg->chip.label = KBUILD_MODNAME;
331	cg->chip.direction_input = crystalcove_gpio_dir_in;
332	cg->chip.direction_output = crystalcove_gpio_dir_out;
333	cg->chip.get = crystalcove_gpio_get;
334	cg->chip.set = crystalcove_gpio_set;
335	cg->chip.base = -1;
336	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
337	cg->chip.can_sleep = true;
338	cg->chip.dev = dev;
339	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
340	cg->regmap = pmic->regmap;
341
342	retval = gpiochip_add(&cg->chip);
343	if (retval) {
344		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
345		return retval;
346	}
347
348	gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
349			     handle_simple_irq, IRQ_TYPE_NONE);
350
351	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
352				      IRQF_ONESHOT, KBUILD_MODNAME, cg);
353
354	if (retval) {
355		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
356		goto out_remove_gpio;
357	}
358
359	return 0;
360
361out_remove_gpio:
362	gpiochip_remove(&cg->chip);
363	return retval;
364}
365
366static int crystalcove_gpio_remove(struct platform_device *pdev)
367{
368	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
369	int irq = platform_get_irq(pdev, 0);
370
371	gpiochip_remove(&cg->chip);
372	if (irq >= 0)
373		free_irq(irq, cg);
374	return 0;
375}
376
377static struct platform_driver crystalcove_gpio_driver = {
378	.probe = crystalcove_gpio_probe,
379	.remove = crystalcove_gpio_remove,
380	.driver = {
381		.name = "crystal_cove_gpio",
382		.owner = THIS_MODULE,
383	},
384};
385
386module_platform_driver(crystalcove_gpio_driver);
387
388MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
389MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
390MODULE_LICENSE("GPL v2");
391