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1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 *     Redistribution and use in source and binary forms, with or
12 *     without modification, are permitted provided that the following
13 *     conditions are met:
14 *
15 *      - Redistributions of source code must retain the above
16 *        copyright notice, this list of conditions and the following
17 *        disclaimer.
18 *
19 *      - Redistributions in binary form must reproduce the above
20 *        copyright notice, this list of conditions and the following
21 *        disclaimer in the documentation and/or other materials
22 *        provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/log2.h>
35#include <linux/slab.h>
36#include <linux/netdevice.h>
37
38#include <rdma/ib_cache.h>
39#include <rdma/ib_pack.h>
40#include <rdma/ib_addr.h>
41#include <rdma/ib_mad.h>
42
43#include <linux/mlx4/qp.h>
44
45#include "mlx4_ib.h"
46#include "user.h"
47
48enum {
49	MLX4_IB_ACK_REQ_FREQ	= 8,
50};
51
52enum {
53	MLX4_IB_DEFAULT_SCHED_QUEUE	= 0x83,
54	MLX4_IB_DEFAULT_QP0_SCHED_QUEUE	= 0x3f,
55	MLX4_IB_LINK_TYPE_IB		= 0,
56	MLX4_IB_LINK_TYPE_ETH		= 1
57};
58
59enum {
60	/*
61	 * Largest possible UD header: send with GRH and immediate
62	 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
63	 * tag.  (LRH would only use 8 bytes, so Ethernet is the
64	 * biggest case)
65	 */
66	MLX4_IB_UD_HEADER_SIZE		= 82,
67	MLX4_IB_LSO_HEADER_SPARE	= 128,
68};
69
70enum {
71	MLX4_IB_IBOE_ETHERTYPE		= 0x8915
72};
73
74struct mlx4_ib_sqp {
75	struct mlx4_ib_qp	qp;
76	int			pkey_index;
77	u32			qkey;
78	u32			send_psn;
79	struct ib_ud_header	ud_header;
80	u8			header_buf[MLX4_IB_UD_HEADER_SIZE];
81};
82
83enum {
84	MLX4_IB_MIN_SQ_STRIDE	= 6,
85	MLX4_IB_CACHE_LINE_SIZE	= 64,
86};
87
88enum {
89	MLX4_RAW_QP_MTU		= 7,
90	MLX4_RAW_QP_MSGMAX	= 31,
91};
92
93#ifndef ETH_ALEN
94#define ETH_ALEN        6
95#endif
96static inline u64 mlx4_mac_to_u64(u8 *addr)
97{
98	u64 mac = 0;
99	int i;
100
101	for (i = 0; i < ETH_ALEN; i++) {
102		mac <<= 8;
103		mac |= addr[i];
104	}
105	return mac;
106}
107
108static const __be32 mlx4_ib_opcode[] = {
109	[IB_WR_SEND]				= cpu_to_be32(MLX4_OPCODE_SEND),
110	[IB_WR_LSO]				= cpu_to_be32(MLX4_OPCODE_LSO),
111	[IB_WR_SEND_WITH_IMM]			= cpu_to_be32(MLX4_OPCODE_SEND_IMM),
112	[IB_WR_RDMA_WRITE]			= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
113	[IB_WR_RDMA_WRITE_WITH_IMM]		= cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
114	[IB_WR_RDMA_READ]			= cpu_to_be32(MLX4_OPCODE_RDMA_READ),
115	[IB_WR_ATOMIC_CMP_AND_SWP]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
116	[IB_WR_ATOMIC_FETCH_AND_ADD]		= cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
117	[IB_WR_SEND_WITH_INV]			= cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
118	[IB_WR_LOCAL_INV]			= cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
119	[IB_WR_FAST_REG_MR]			= cpu_to_be32(MLX4_OPCODE_FMR),
120	[IB_WR_MASKED_ATOMIC_CMP_AND_SWP]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
121	[IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]	= cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
122	[IB_WR_BIND_MW]				= cpu_to_be32(MLX4_OPCODE_BIND_MW),
123};
124
125static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
126{
127	return container_of(mqp, struct mlx4_ib_sqp, qp);
128}
129
130static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
131{
132	if (!mlx4_is_master(dev->dev))
133		return 0;
134
135	return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
136	       qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
137		8 * MLX4_MFUNC_MAX;
138}
139
140static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
141{
142	int proxy_sqp = 0;
143	int real_sqp = 0;
144	int i;
145	/* PPF or Native -- real SQP */
146	real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
147		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
148		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
149	if (real_sqp)
150		return 1;
151	/* VF or PF -- proxy SQP */
152	if (mlx4_is_mfunc(dev->dev)) {
153		for (i = 0; i < dev->dev->caps.num_ports; i++) {
154			if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
155			    qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
156				proxy_sqp = 1;
157				break;
158			}
159		}
160	}
161	return proxy_sqp;
162}
163
164/* used for INIT/CLOSE port logic */
165static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
166{
167	int proxy_qp0 = 0;
168	int real_qp0 = 0;
169	int i;
170	/* PPF or Native -- real QP0 */
171	real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
172		    qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
173		    qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
174	if (real_qp0)
175		return 1;
176	/* VF or PF -- proxy QP0 */
177	if (mlx4_is_mfunc(dev->dev)) {
178		for (i = 0; i < dev->dev->caps.num_ports; i++) {
179			if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
180				proxy_qp0 = 1;
181				break;
182			}
183		}
184	}
185	return proxy_qp0;
186}
187
188static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
189{
190	return mlx4_buf_offset(&qp->buf, offset);
191}
192
193static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
194{
195	return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
196}
197
198static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
199{
200	return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
201}
202
203/*
204 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
205 * first four bytes of every 64 byte chunk with
206 *     0x7FFFFFF | (invalid_ownership_value << 31).
207 *
208 * When the max work request size is less than or equal to the WQE
209 * basic block size, as an optimization, we can stamp all WQEs with
210 * 0xffffffff, and skip the very first chunk of each WQE.
211 */
212static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
213{
214	__be32 *wqe;
215	int i;
216	int s;
217	int ind;
218	void *buf;
219	__be32 stamp;
220	struct mlx4_wqe_ctrl_seg *ctrl;
221
222	if (qp->sq_max_wqes_per_wr > 1) {
223		s = roundup(size, 1U << qp->sq.wqe_shift);
224		for (i = 0; i < s; i += 64) {
225			ind = (i >> qp->sq.wqe_shift) + n;
226			stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
227						       cpu_to_be32(0xffffffff);
228			buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
229			wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
230			*wqe = stamp;
231		}
232	} else {
233		ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
234		s = (ctrl->fence_size & 0x3f) << 4;
235		for (i = 64; i < s; i += 64) {
236			wqe = buf + i;
237			*wqe = cpu_to_be32(0xffffffff);
238		}
239	}
240}
241
242static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
243{
244	struct mlx4_wqe_ctrl_seg *ctrl;
245	struct mlx4_wqe_inline_seg *inl;
246	void *wqe;
247	int s;
248
249	ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
250	s = sizeof(struct mlx4_wqe_ctrl_seg);
251
252	if (qp->ibqp.qp_type == IB_QPT_UD) {
253		struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
254		struct mlx4_av *av = (struct mlx4_av *)dgram->av;
255		memset(dgram, 0, sizeof *dgram);
256		av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
257		s += sizeof(struct mlx4_wqe_datagram_seg);
258	}
259
260	/* Pad the remainder of the WQE with an inline data segment. */
261	if (size > s) {
262		inl = wqe + s;
263		inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
264	}
265	ctrl->srcrb_flags = 0;
266	ctrl->fence_size = size / 16;
267	/*
268	 * Make sure descriptor is fully written before setting ownership bit
269	 * (because HW can start executing as soon as we do).
270	 */
271	wmb();
272
273	ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
274		(n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
275
276	stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
277}
278
279/* Post NOP WQE to prevent wrap-around in the middle of WR */
280static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
281{
282	unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
283	if (unlikely(s < qp->sq_max_wqes_per_wr)) {
284		post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
285		ind += s;
286	}
287	return ind;
288}
289
290static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
291{
292	struct ib_event event;
293	struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
294
295	if (type == MLX4_EVENT_TYPE_PATH_MIG)
296		to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
297
298	if (ibqp->event_handler) {
299		event.device     = ibqp->device;
300		event.element.qp = ibqp;
301		switch (type) {
302		case MLX4_EVENT_TYPE_PATH_MIG:
303			event.event = IB_EVENT_PATH_MIG;
304			break;
305		case MLX4_EVENT_TYPE_COMM_EST:
306			event.event = IB_EVENT_COMM_EST;
307			break;
308		case MLX4_EVENT_TYPE_SQ_DRAINED:
309			event.event = IB_EVENT_SQ_DRAINED;
310			break;
311		case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
312			event.event = IB_EVENT_QP_LAST_WQE_REACHED;
313			break;
314		case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
315			event.event = IB_EVENT_QP_FATAL;
316			break;
317		case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
318			event.event = IB_EVENT_PATH_MIG_ERR;
319			break;
320		case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
321			event.event = IB_EVENT_QP_REQ_ERR;
322			break;
323		case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
324			event.event = IB_EVENT_QP_ACCESS_ERR;
325			break;
326		default:
327			pr_warn("Unexpected event type %d "
328			       "on QP %06x\n", type, qp->qpn);
329			return;
330		}
331
332		ibqp->event_handler(&event, ibqp->qp_context);
333	}
334}
335
336static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
337{
338	/*
339	 * UD WQEs must have a datagram segment.
340	 * RC and UC WQEs might have a remote address segment.
341	 * MLX WQEs need two extra inline data segments (for the UD
342	 * header and space for the ICRC).
343	 */
344	switch (type) {
345	case MLX4_IB_QPT_UD:
346		return sizeof (struct mlx4_wqe_ctrl_seg) +
347			sizeof (struct mlx4_wqe_datagram_seg) +
348			((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
349	case MLX4_IB_QPT_PROXY_SMI_OWNER:
350	case MLX4_IB_QPT_PROXY_SMI:
351	case MLX4_IB_QPT_PROXY_GSI:
352		return sizeof (struct mlx4_wqe_ctrl_seg) +
353			sizeof (struct mlx4_wqe_datagram_seg) + 64;
354	case MLX4_IB_QPT_TUN_SMI_OWNER:
355	case MLX4_IB_QPT_TUN_GSI:
356		return sizeof (struct mlx4_wqe_ctrl_seg) +
357			sizeof (struct mlx4_wqe_datagram_seg);
358
359	case MLX4_IB_QPT_UC:
360		return sizeof (struct mlx4_wqe_ctrl_seg) +
361			sizeof (struct mlx4_wqe_raddr_seg);
362	case MLX4_IB_QPT_RC:
363		return sizeof (struct mlx4_wqe_ctrl_seg) +
364			sizeof (struct mlx4_wqe_atomic_seg) +
365			sizeof (struct mlx4_wqe_raddr_seg);
366	case MLX4_IB_QPT_SMI:
367	case MLX4_IB_QPT_GSI:
368		return sizeof (struct mlx4_wqe_ctrl_seg) +
369			ALIGN(MLX4_IB_UD_HEADER_SIZE +
370			      DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
371					   MLX4_INLINE_ALIGN) *
372			      sizeof (struct mlx4_wqe_inline_seg),
373			      sizeof (struct mlx4_wqe_data_seg)) +
374			ALIGN(4 +
375			      sizeof (struct mlx4_wqe_inline_seg),
376			      sizeof (struct mlx4_wqe_data_seg));
377	default:
378		return sizeof (struct mlx4_wqe_ctrl_seg);
379	}
380}
381
382static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
383		       int is_user, int has_rq, struct mlx4_ib_qp *qp)
384{
385	/* Sanity check RQ size before proceeding */
386	if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
387	    cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
388		return -EINVAL;
389
390	if (!has_rq) {
391		if (cap->max_recv_wr)
392			return -EINVAL;
393
394		qp->rq.wqe_cnt = qp->rq.max_gs = 0;
395	} else {
396		/* HW requires >= 1 RQ entry with >= 1 gather entry */
397		if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
398			return -EINVAL;
399
400		qp->rq.wqe_cnt	 = roundup_pow_of_two(max(1U, cap->max_recv_wr));
401		qp->rq.max_gs	 = roundup_pow_of_two(max(1U, cap->max_recv_sge));
402		qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
403	}
404
405	/* leave userspace return values as they were, so as not to break ABI */
406	if (is_user) {
407		cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
408		cap->max_recv_sge = qp->rq.max_gs;
409	} else {
410		cap->max_recv_wr  = qp->rq.max_post =
411			min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
412		cap->max_recv_sge = min(qp->rq.max_gs,
413					min(dev->dev->caps.max_sq_sg,
414					    dev->dev->caps.max_rq_sg));
415	}
416
417	return 0;
418}
419
420static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
421			      enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
422{
423	int s;
424
425	/* Sanity check SQ size before proceeding */
426	if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
427	    cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
428	    cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
429	    sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
430		return -EINVAL;
431
432	/*
433	 * For MLX transport we need 2 extra S/G entries:
434	 * one for the header and one for the checksum at the end
435	 */
436	if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
437	     type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
438	    cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
439		return -EINVAL;
440
441	s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
442		cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
443		send_wqe_overhead(type, qp->flags);
444
445	if (s > dev->dev->caps.max_sq_desc_sz)
446		return -EINVAL;
447
448	/*
449	 * Hermon supports shrinking WQEs, such that a single work
450	 * request can include multiple units of 1 << wqe_shift.  This
451	 * way, work requests can differ in size, and do not have to
452	 * be a power of 2 in size, saving memory and speeding up send
453	 * WR posting.  Unfortunately, if we do this then the
454	 * wqe_index field in CQEs can't be used to look up the WR ID
455	 * anymore, so we do this only if selective signaling is off.
456	 *
457	 * Further, on 32-bit platforms, we can't use vmap() to make
458	 * the QP buffer virtually contiguous.  Thus we have to use
459	 * constant-sized WRs to make sure a WR is always fully within
460	 * a single page-sized chunk.
461	 *
462	 * Finally, we use NOP work requests to pad the end of the
463	 * work queue, to avoid wrap-around in the middle of WR.  We
464	 * set NEC bit to avoid getting completions with error for
465	 * these NOP WRs, but since NEC is only supported starting
466	 * with firmware 2.2.232, we use constant-sized WRs for older
467	 * firmware.
468	 *
469	 * And, since MLX QPs only support SEND, we use constant-sized
470	 * WRs in this case.
471	 *
472	 * We look for the smallest value of wqe_shift such that the
473	 * resulting number of wqes does not exceed device
474	 * capabilities.
475	 *
476	 * We set WQE size to at least 64 bytes, this way stamping
477	 * invalidates each WQE.
478	 */
479	if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
480	    qp->sq_signal_bits && BITS_PER_LONG == 64 &&
481	    type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
482	    !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
483		      MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
484		qp->sq.wqe_shift = ilog2(64);
485	else
486		qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
487
488	for (;;) {
489		qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
490
491		/*
492		 * We need to leave 2 KB + 1 WR of headroom in the SQ to
493		 * allow HW to prefetch.
494		 */
495		qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
496		qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
497						    qp->sq_max_wqes_per_wr +
498						    qp->sq_spare_wqes);
499
500		if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
501			break;
502
503		if (qp->sq_max_wqes_per_wr <= 1)
504			return -EINVAL;
505
506		++qp->sq.wqe_shift;
507	}
508
509	qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
510			     (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
511			 send_wqe_overhead(type, qp->flags)) /
512		sizeof (struct mlx4_wqe_data_seg);
513
514	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
515		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
516	if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
517		qp->rq.offset = 0;
518		qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
519	} else {
520		qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
521		qp->sq.offset = 0;
522	}
523
524	cap->max_send_wr  = qp->sq.max_post =
525		(qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
526	cap->max_send_sge = min(qp->sq.max_gs,
527				min(dev->dev->caps.max_sq_sg,
528				    dev->dev->caps.max_rq_sg));
529	/* We don't support inline sends for kernel QPs (yet) */
530	cap->max_inline_data = 0;
531
532	return 0;
533}
534
535static int set_user_sq_size(struct mlx4_ib_dev *dev,
536			    struct mlx4_ib_qp *qp,
537			    struct mlx4_ib_create_qp *ucmd)
538{
539	/* Sanity check SQ size before proceeding */
540	if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes	 ||
541	    ucmd->log_sq_stride >
542		ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
543	    ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
544		return -EINVAL;
545
546	qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
547	qp->sq.wqe_shift = ucmd->log_sq_stride;
548
549	qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
550		(qp->sq.wqe_cnt << qp->sq.wqe_shift);
551
552	return 0;
553}
554
555static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
556{
557	int i;
558
559	qp->sqp_proxy_rcv =
560		kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
561			GFP_KERNEL);
562	if (!qp->sqp_proxy_rcv)
563		return -ENOMEM;
564	for (i = 0; i < qp->rq.wqe_cnt; i++) {
565		qp->sqp_proxy_rcv[i].addr =
566			kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
567				GFP_KERNEL);
568		if (!qp->sqp_proxy_rcv[i].addr)
569			goto err;
570		qp->sqp_proxy_rcv[i].map =
571			ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
572					  sizeof (struct mlx4_ib_proxy_sqp_hdr),
573					  DMA_FROM_DEVICE);
574	}
575	return 0;
576
577err:
578	while (i > 0) {
579		--i;
580		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
581				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
582				    DMA_FROM_DEVICE);
583		kfree(qp->sqp_proxy_rcv[i].addr);
584	}
585	kfree(qp->sqp_proxy_rcv);
586	qp->sqp_proxy_rcv = NULL;
587	return -ENOMEM;
588}
589
590static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
591{
592	int i;
593
594	for (i = 0; i < qp->rq.wqe_cnt; i++) {
595		ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
596				    sizeof (struct mlx4_ib_proxy_sqp_hdr),
597				    DMA_FROM_DEVICE);
598		kfree(qp->sqp_proxy_rcv[i].addr);
599	}
600	kfree(qp->sqp_proxy_rcv);
601}
602
603static int qp_has_rq(struct ib_qp_init_attr *attr)
604{
605	if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
606		return 0;
607
608	return !attr->srq;
609}
610
611static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
612{
613	int i;
614	for (i = 0; i < dev->caps.num_ports; i++) {
615		if (qpn == dev->caps.qp0_proxy[i])
616			return !!dev->caps.qp0_qkey[i];
617	}
618	return 0;
619}
620
621static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
622			    struct ib_qp_init_attr *init_attr,
623			    struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
624			    gfp_t gfp)
625{
626	int qpn;
627	int err;
628	struct mlx4_ib_sqp *sqp;
629	struct mlx4_ib_qp *qp;
630	enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
631
632	/* When tunneling special qps, we use a plain UD qp */
633	if (sqpn) {
634		if (mlx4_is_mfunc(dev->dev) &&
635		    (!mlx4_is_master(dev->dev) ||
636		     !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
637			if (init_attr->qp_type == IB_QPT_GSI)
638				qp_type = MLX4_IB_QPT_PROXY_GSI;
639			else {
640				if (mlx4_is_master(dev->dev) ||
641				    qp0_enabled_vf(dev->dev, sqpn))
642					qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
643				else
644					qp_type = MLX4_IB_QPT_PROXY_SMI;
645			}
646		}
647		qpn = sqpn;
648		/* add extra sg entry for tunneling */
649		init_attr->cap.max_recv_sge++;
650	} else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
651		struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
652			container_of(init_attr,
653				     struct mlx4_ib_qp_tunnel_init_attr, init_attr);
654		if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
655		     tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
656		    !mlx4_is_master(dev->dev))
657			return -EINVAL;
658		if (tnl_init->proxy_qp_type == IB_QPT_GSI)
659			qp_type = MLX4_IB_QPT_TUN_GSI;
660		else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
661			 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
662					     tnl_init->port))
663			qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
664		else
665			qp_type = MLX4_IB_QPT_TUN_SMI;
666		/* we are definitely in the PPF here, since we are creating
667		 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
668		qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
669			+ tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
670		sqpn = qpn;
671	}
672
673	if (!*caller_qp) {
674		if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
675		    (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
676				MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
677			sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
678			if (!sqp)
679				return -ENOMEM;
680			qp = &sqp->qp;
681			qp->pri.vid = 0xFFFF;
682			qp->alt.vid = 0xFFFF;
683		} else {
684			qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
685			if (!qp)
686				return -ENOMEM;
687			qp->pri.vid = 0xFFFF;
688			qp->alt.vid = 0xFFFF;
689		}
690	} else
691		qp = *caller_qp;
692
693	qp->mlx4_ib_qp_type = qp_type;
694
695	mutex_init(&qp->mutex);
696	spin_lock_init(&qp->sq.lock);
697	spin_lock_init(&qp->rq.lock);
698	INIT_LIST_HEAD(&qp->gid_list);
699	INIT_LIST_HEAD(&qp->steering_rules);
700
701	qp->state	 = IB_QPS_RESET;
702	if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
703		qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
704
705	err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
706	if (err)
707		goto err;
708
709	if (pd->uobject) {
710		struct mlx4_ib_create_qp ucmd;
711
712		if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
713			err = -EFAULT;
714			goto err;
715		}
716
717		qp->sq_no_prefetch = ucmd.sq_no_prefetch;
718
719		err = set_user_sq_size(dev, qp, &ucmd);
720		if (err)
721			goto err;
722
723		qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
724				       qp->buf_size, 0, 0);
725		if (IS_ERR(qp->umem)) {
726			err = PTR_ERR(qp->umem);
727			goto err;
728		}
729
730		err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
731				    ilog2(qp->umem->page_size), &qp->mtt);
732		if (err)
733			goto err_buf;
734
735		err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
736		if (err)
737			goto err_mtt;
738
739		if (qp_has_rq(init_attr)) {
740			err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
741						  ucmd.db_addr, &qp->db);
742			if (err)
743				goto err_mtt;
744		}
745	} else {
746		qp->sq_no_prefetch = 0;
747
748		if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
749			qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
750
751		if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
752			qp->flags |= MLX4_IB_QP_LSO;
753
754		if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
755			if (dev->steering_support ==
756			    MLX4_STEERING_MODE_DEVICE_MANAGED)
757				qp->flags |= MLX4_IB_QP_NETIF;
758			else
759				goto err;
760		}
761
762		err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
763		if (err)
764			goto err;
765
766		if (qp_has_rq(init_attr)) {
767			err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
768			if (err)
769				goto err;
770
771			*qp->db.db = 0;
772		}
773
774		if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
775			err = -ENOMEM;
776			goto err_db;
777		}
778
779		err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
780				    &qp->mtt);
781		if (err)
782			goto err_buf;
783
784		err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
785		if (err)
786			goto err_mtt;
787
788		qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
789		qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
790		if (!qp->sq.wrid || !qp->rq.wrid) {
791			err = -ENOMEM;
792			goto err_wrid;
793		}
794	}
795
796	if (sqpn) {
797		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
798		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
799			if (alloc_proxy_bufs(pd->device, qp)) {
800				err = -ENOMEM;
801				goto err_wrid;
802			}
803		}
804	} else {
805		/* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
806		 * BlueFlame setup flow wrongly causes VLAN insertion. */
807		if (init_attr->qp_type == IB_QPT_RAW_PACKET)
808			err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
809		else
810			if (qp->flags & MLX4_IB_QP_NETIF)
811				err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
812			else
813				err = mlx4_qp_reserve_range(dev->dev, 1, 1,
814							    &qpn);
815		if (err)
816			goto err_proxy;
817	}
818
819	err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
820	if (err)
821		goto err_qpn;
822
823	if (init_attr->qp_type == IB_QPT_XRC_TGT)
824		qp->mqp.qpn |= (1 << 23);
825
826	/*
827	 * Hardware wants QPN written in big-endian order (after
828	 * shifting) for send doorbell.  Precompute this value to save
829	 * a little bit when posting sends.
830	 */
831	qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
832
833	qp->mqp.event = mlx4_ib_qp_event;
834	if (!*caller_qp)
835		*caller_qp = qp;
836	return 0;
837
838err_qpn:
839	if (!sqpn) {
840		if (qp->flags & MLX4_IB_QP_NETIF)
841			mlx4_ib_steer_qp_free(dev, qpn, 1);
842		else
843			mlx4_qp_release_range(dev->dev, qpn, 1);
844	}
845err_proxy:
846	if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
847		free_proxy_bufs(pd->device, qp);
848err_wrid:
849	if (pd->uobject) {
850		if (qp_has_rq(init_attr))
851			mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
852	} else {
853		kfree(qp->sq.wrid);
854		kfree(qp->rq.wrid);
855	}
856
857err_mtt:
858	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
859
860err_buf:
861	if (pd->uobject)
862		ib_umem_release(qp->umem);
863	else
864		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
865
866err_db:
867	if (!pd->uobject && qp_has_rq(init_attr))
868		mlx4_db_free(dev->dev, &qp->db);
869
870err:
871	if (!*caller_qp)
872		kfree(qp);
873	return err;
874}
875
876static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
877{
878	switch (state) {
879	case IB_QPS_RESET:	return MLX4_QP_STATE_RST;
880	case IB_QPS_INIT:	return MLX4_QP_STATE_INIT;
881	case IB_QPS_RTR:	return MLX4_QP_STATE_RTR;
882	case IB_QPS_RTS:	return MLX4_QP_STATE_RTS;
883	case IB_QPS_SQD:	return MLX4_QP_STATE_SQD;
884	case IB_QPS_SQE:	return MLX4_QP_STATE_SQER;
885	case IB_QPS_ERR:	return MLX4_QP_STATE_ERR;
886	default:		return -1;
887	}
888}
889
890static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
891	__acquires(&send_cq->lock) __acquires(&recv_cq->lock)
892{
893	if (send_cq == recv_cq) {
894		spin_lock_irq(&send_cq->lock);
895		__acquire(&recv_cq->lock);
896	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
897		spin_lock_irq(&send_cq->lock);
898		spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
899	} else {
900		spin_lock_irq(&recv_cq->lock);
901		spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
902	}
903}
904
905static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
906	__releases(&send_cq->lock) __releases(&recv_cq->lock)
907{
908	if (send_cq == recv_cq) {
909		__release(&recv_cq->lock);
910		spin_unlock_irq(&send_cq->lock);
911	} else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
912		spin_unlock(&recv_cq->lock);
913		spin_unlock_irq(&send_cq->lock);
914	} else {
915		spin_unlock(&send_cq->lock);
916		spin_unlock_irq(&recv_cq->lock);
917	}
918}
919
920static void del_gid_entries(struct mlx4_ib_qp *qp)
921{
922	struct mlx4_ib_gid_entry *ge, *tmp;
923
924	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
925		list_del(&ge->list);
926		kfree(ge);
927	}
928}
929
930static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
931{
932	if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
933		return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
934	else
935		return to_mpd(qp->ibqp.pd);
936}
937
938static void get_cqs(struct mlx4_ib_qp *qp,
939		    struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
940{
941	switch (qp->ibqp.qp_type) {
942	case IB_QPT_XRC_TGT:
943		*send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
944		*recv_cq = *send_cq;
945		break;
946	case IB_QPT_XRC_INI:
947		*send_cq = to_mcq(qp->ibqp.send_cq);
948		*recv_cq = *send_cq;
949		break;
950	default:
951		*send_cq = to_mcq(qp->ibqp.send_cq);
952		*recv_cq = to_mcq(qp->ibqp.recv_cq);
953		break;
954	}
955}
956
957static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
958			      int is_user)
959{
960	struct mlx4_ib_cq *send_cq, *recv_cq;
961
962	if (qp->state != IB_QPS_RESET) {
963		if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
964				   MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
965			pr_warn("modify QP %06x to RESET failed.\n",
966			       qp->mqp.qpn);
967		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
968			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
969			qp->pri.smac = 0;
970			qp->pri.smac_port = 0;
971		}
972		if (qp->alt.smac) {
973			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
974			qp->alt.smac = 0;
975		}
976		if (qp->pri.vid < 0x1000) {
977			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
978			qp->pri.vid = 0xFFFF;
979			qp->pri.candidate_vid = 0xFFFF;
980			qp->pri.update_vid = 0;
981		}
982		if (qp->alt.vid < 0x1000) {
983			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
984			qp->alt.vid = 0xFFFF;
985			qp->alt.candidate_vid = 0xFFFF;
986			qp->alt.update_vid = 0;
987		}
988	}
989
990	get_cqs(qp, &send_cq, &recv_cq);
991
992	mlx4_ib_lock_cqs(send_cq, recv_cq);
993
994	if (!is_user) {
995		__mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
996				 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
997		if (send_cq != recv_cq)
998			__mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
999	}
1000
1001	mlx4_qp_remove(dev->dev, &qp->mqp);
1002
1003	mlx4_ib_unlock_cqs(send_cq, recv_cq);
1004
1005	mlx4_qp_free(dev->dev, &qp->mqp);
1006
1007	if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1008		if (qp->flags & MLX4_IB_QP_NETIF)
1009			mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1010		else
1011			mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1012	}
1013
1014	mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1015
1016	if (is_user) {
1017		if (qp->rq.wqe_cnt)
1018			mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1019					      &qp->db);
1020		ib_umem_release(qp->umem);
1021	} else {
1022		kfree(qp->sq.wrid);
1023		kfree(qp->rq.wrid);
1024		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1025		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1026			free_proxy_bufs(&dev->ib_dev, qp);
1027		mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1028		if (qp->rq.wqe_cnt)
1029			mlx4_db_free(dev->dev, &qp->db);
1030	}
1031
1032	del_gid_entries(qp);
1033}
1034
1035static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1036{
1037	/* Native or PPF */
1038	if (!mlx4_is_mfunc(dev->dev) ||
1039	    (mlx4_is_master(dev->dev) &&
1040	     attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1041		return  dev->dev->phys_caps.base_sqpn +
1042			(attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1043			attr->port_num - 1;
1044	}
1045	/* PF or VF -- creating proxies */
1046	if (attr->qp_type == IB_QPT_SMI)
1047		return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1048	else
1049		return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1050}
1051
1052struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1053				struct ib_qp_init_attr *init_attr,
1054				struct ib_udata *udata)
1055{
1056	struct mlx4_ib_qp *qp = NULL;
1057	int err;
1058	u16 xrcdn = 0;
1059	gfp_t gfp;
1060
1061	gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1062		GFP_NOIO : GFP_KERNEL;
1063	/*
1064	 * We only support LSO, vendor flag1, and multicast loopback blocking,
1065	 * and only for kernel UD QPs.
1066	 */
1067	if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1068					MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1069					MLX4_IB_SRIOV_TUNNEL_QP |
1070					MLX4_IB_SRIOV_SQP |
1071					MLX4_IB_QP_NETIF |
1072					MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1073		return ERR_PTR(-EINVAL);
1074
1075	if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1076		if (init_attr->qp_type != IB_QPT_UD)
1077			return ERR_PTR(-EINVAL);
1078	}
1079
1080	if (init_attr->create_flags &&
1081	    (udata ||
1082	     ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | MLX4_IB_QP_CREATE_USE_GFP_NOIO)) &&
1083	      init_attr->qp_type != IB_QPT_UD) ||
1084	     ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1085	      init_attr->qp_type > IB_QPT_GSI)))
1086		return ERR_PTR(-EINVAL);
1087
1088	switch (init_attr->qp_type) {
1089	case IB_QPT_XRC_TGT:
1090		pd = to_mxrcd(init_attr->xrcd)->pd;
1091		xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1092		init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1093		/* fall through */
1094	case IB_QPT_XRC_INI:
1095		if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1096			return ERR_PTR(-ENOSYS);
1097		init_attr->recv_cq = init_attr->send_cq;
1098		/* fall through */
1099	case IB_QPT_RC:
1100	case IB_QPT_UC:
1101	case IB_QPT_RAW_PACKET:
1102		qp = kzalloc(sizeof *qp, gfp);
1103		if (!qp)
1104			return ERR_PTR(-ENOMEM);
1105		qp->pri.vid = 0xFFFF;
1106		qp->alt.vid = 0xFFFF;
1107		/* fall through */
1108	case IB_QPT_UD:
1109	{
1110		err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1111				       udata, 0, &qp, gfp);
1112		if (err)
1113			return ERR_PTR(err);
1114
1115		qp->ibqp.qp_num = qp->mqp.qpn;
1116		qp->xrcdn = xrcdn;
1117
1118		break;
1119	}
1120	case IB_QPT_SMI:
1121	case IB_QPT_GSI:
1122	{
1123		/* Userspace is not allowed to create special QPs: */
1124		if (udata)
1125			return ERR_PTR(-EINVAL);
1126
1127		err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1128				       get_sqp_num(to_mdev(pd->device), init_attr),
1129				       &qp, gfp);
1130		if (err)
1131			return ERR_PTR(err);
1132
1133		qp->port	= init_attr->port_num;
1134		qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1135
1136		break;
1137	}
1138	default:
1139		/* Don't support raw QPs */
1140		return ERR_PTR(-EINVAL);
1141	}
1142
1143	return &qp->ibqp;
1144}
1145
1146int mlx4_ib_destroy_qp(struct ib_qp *qp)
1147{
1148	struct mlx4_ib_dev *dev = to_mdev(qp->device);
1149	struct mlx4_ib_qp *mqp = to_mqp(qp);
1150	struct mlx4_ib_pd *pd;
1151
1152	if (is_qp0(dev, mqp))
1153		mlx4_CLOSE_PORT(dev->dev, mqp->port);
1154
1155	if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1156		mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1157		dev->qp1_proxy[mqp->port - 1] = NULL;
1158		mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1159	}
1160
1161	pd = get_pd(mqp);
1162	destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1163
1164	if (is_sqp(dev, mqp))
1165		kfree(to_msqp(mqp));
1166	else
1167		kfree(mqp);
1168
1169	return 0;
1170}
1171
1172static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1173{
1174	switch (type) {
1175	case MLX4_IB_QPT_RC:		return MLX4_QP_ST_RC;
1176	case MLX4_IB_QPT_UC:		return MLX4_QP_ST_UC;
1177	case MLX4_IB_QPT_UD:		return MLX4_QP_ST_UD;
1178	case MLX4_IB_QPT_XRC_INI:
1179	case MLX4_IB_QPT_XRC_TGT:	return MLX4_QP_ST_XRC;
1180	case MLX4_IB_QPT_SMI:
1181	case MLX4_IB_QPT_GSI:
1182	case MLX4_IB_QPT_RAW_PACKET:	return MLX4_QP_ST_MLX;
1183
1184	case MLX4_IB_QPT_PROXY_SMI_OWNER:
1185	case MLX4_IB_QPT_TUN_SMI_OWNER:	return (mlx4_is_mfunc(dev->dev) ?
1186						MLX4_QP_ST_MLX : -1);
1187	case MLX4_IB_QPT_PROXY_SMI:
1188	case MLX4_IB_QPT_TUN_SMI:
1189	case MLX4_IB_QPT_PROXY_GSI:
1190	case MLX4_IB_QPT_TUN_GSI:	return (mlx4_is_mfunc(dev->dev) ?
1191						MLX4_QP_ST_UD : -1);
1192	default:			return -1;
1193	}
1194}
1195
1196static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1197				   int attr_mask)
1198{
1199	u8 dest_rd_atomic;
1200	u32 access_flags;
1201	u32 hw_access_flags = 0;
1202
1203	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1204		dest_rd_atomic = attr->max_dest_rd_atomic;
1205	else
1206		dest_rd_atomic = qp->resp_depth;
1207
1208	if (attr_mask & IB_QP_ACCESS_FLAGS)
1209		access_flags = attr->qp_access_flags;
1210	else
1211		access_flags = qp->atomic_rd_en;
1212
1213	if (!dest_rd_atomic)
1214		access_flags &= IB_ACCESS_REMOTE_WRITE;
1215
1216	if (access_flags & IB_ACCESS_REMOTE_READ)
1217		hw_access_flags |= MLX4_QP_BIT_RRE;
1218	if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1219		hw_access_flags |= MLX4_QP_BIT_RAE;
1220	if (access_flags & IB_ACCESS_REMOTE_WRITE)
1221		hw_access_flags |= MLX4_QP_BIT_RWE;
1222
1223	return cpu_to_be32(hw_access_flags);
1224}
1225
1226static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1227			    int attr_mask)
1228{
1229	if (attr_mask & IB_QP_PKEY_INDEX)
1230		sqp->pkey_index = attr->pkey_index;
1231	if (attr_mask & IB_QP_QKEY)
1232		sqp->qkey = attr->qkey;
1233	if (attr_mask & IB_QP_SQ_PSN)
1234		sqp->send_psn = attr->sq_psn;
1235}
1236
1237static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1238{
1239	path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1240}
1241
1242static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1243			  u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1244			  struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1245{
1246	int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1247		IB_LINK_LAYER_ETHERNET;
1248	int vidx;
1249	int smac_index;
1250	int err;
1251
1252
1253	path->grh_mylmc     = ah->src_path_bits & 0x7f;
1254	path->rlid	    = cpu_to_be16(ah->dlid);
1255	if (ah->static_rate) {
1256		path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1257		while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1258		       !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1259			--path->static_rate;
1260	} else
1261		path->static_rate = 0;
1262
1263	if (ah->ah_flags & IB_AH_GRH) {
1264		if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1265			pr_err("sgid_index (%u) too large. max is %d\n",
1266			       ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1267			return -1;
1268		}
1269
1270		path->grh_mylmc |= 1 << 7;
1271		path->mgid_index = ah->grh.sgid_index;
1272		path->hop_limit  = ah->grh.hop_limit;
1273		path->tclass_flowlabel =
1274			cpu_to_be32((ah->grh.traffic_class << 20) |
1275				    (ah->grh.flow_label));
1276		memcpy(path->rgid, ah->grh.dgid.raw, 16);
1277	}
1278
1279	if (is_eth) {
1280		if (!(ah->ah_flags & IB_AH_GRH))
1281			return -1;
1282
1283		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1284			((port - 1) << 6) | ((ah->sl & 7) << 3);
1285
1286		path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1287		if (vlan_tag < 0x1000) {
1288			if (smac_info->vid < 0x1000) {
1289				/* both valid vlan ids */
1290				if (smac_info->vid != vlan_tag) {
1291					/* different VIDs.  unreg old and reg new */
1292					err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1293					if (err)
1294						return err;
1295					smac_info->candidate_vid = vlan_tag;
1296					smac_info->candidate_vlan_index = vidx;
1297					smac_info->candidate_vlan_port = port;
1298					smac_info->update_vid = 1;
1299					path->vlan_index = vidx;
1300				} else {
1301					path->vlan_index = smac_info->vlan_index;
1302				}
1303			} else {
1304				/* no current vlan tag in qp */
1305				err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1306				if (err)
1307					return err;
1308				smac_info->candidate_vid = vlan_tag;
1309				smac_info->candidate_vlan_index = vidx;
1310				smac_info->candidate_vlan_port = port;
1311				smac_info->update_vid = 1;
1312				path->vlan_index = vidx;
1313			}
1314			path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1315			path->fl = 1 << 6;
1316		} else {
1317			/* have current vlan tag. unregister it at modify-qp success */
1318			if (smac_info->vid < 0x1000) {
1319				smac_info->candidate_vid = 0xFFFF;
1320				smac_info->update_vid = 1;
1321			}
1322		}
1323
1324		/* get smac_index for RoCE use.
1325		 * If no smac was yet assigned, register one.
1326		 * If one was already assigned, but the new mac differs,
1327		 * unregister the old one and register the new one.
1328		*/
1329		if ((!smac_info->smac && !smac_info->smac_port) ||
1330		    smac_info->smac != smac) {
1331			/* register candidate now, unreg if needed, after success */
1332			smac_index = mlx4_register_mac(dev->dev, port, smac);
1333			if (smac_index >= 0) {
1334				smac_info->candidate_smac_index = smac_index;
1335				smac_info->candidate_smac = smac;
1336				smac_info->candidate_smac_port = port;
1337			} else {
1338				return -EINVAL;
1339			}
1340		} else {
1341			smac_index = smac_info->smac_index;
1342		}
1343
1344		memcpy(path->dmac, ah->dmac, 6);
1345		path->ackto = MLX4_IB_LINK_TYPE_ETH;
1346		/* put MAC table smac index for IBoE */
1347		path->grh_mylmc = (u8) (smac_index) | 0x80;
1348	} else {
1349		path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1350			((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1351	}
1352
1353	return 0;
1354}
1355
1356static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1357			 enum ib_qp_attr_mask qp_attr_mask,
1358			 struct mlx4_ib_qp *mqp,
1359			 struct mlx4_qp_path *path, u8 port)
1360{
1361	return _mlx4_set_path(dev, &qp->ah_attr,
1362			      mlx4_mac_to_u64((u8 *)qp->smac),
1363			      (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1364			      path, &mqp->pri, port);
1365}
1366
1367static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1368			     const struct ib_qp_attr *qp,
1369			     enum ib_qp_attr_mask qp_attr_mask,
1370			     struct mlx4_ib_qp *mqp,
1371			     struct mlx4_qp_path *path, u8 port)
1372{
1373	return _mlx4_set_path(dev, &qp->alt_ah_attr,
1374			      mlx4_mac_to_u64((u8 *)qp->alt_smac),
1375			      (qp_attr_mask & IB_QP_ALT_VID) ?
1376			      qp->alt_vlan_id : 0xffff,
1377			      path, &mqp->alt, port);
1378}
1379
1380static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1381{
1382	struct mlx4_ib_gid_entry *ge, *tmp;
1383
1384	list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1385		if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1386			ge->added = 1;
1387			ge->port = qp->port;
1388		}
1389	}
1390}
1391
1392static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1393				    struct mlx4_qp_context *context)
1394{
1395	u64 u64_mac;
1396	int smac_index;
1397
1398	u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1399
1400	context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1401	if (!qp->pri.smac && !qp->pri.smac_port) {
1402		smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1403		if (smac_index >= 0) {
1404			qp->pri.candidate_smac_index = smac_index;
1405			qp->pri.candidate_smac = u64_mac;
1406			qp->pri.candidate_smac_port = qp->port;
1407			context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1408		} else {
1409			return -ENOENT;
1410		}
1411	}
1412	return 0;
1413}
1414
1415static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1416			       const struct ib_qp_attr *attr, int attr_mask,
1417			       enum ib_qp_state cur_state, enum ib_qp_state new_state)
1418{
1419	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1420	struct mlx4_ib_qp *qp = to_mqp(ibqp);
1421	struct mlx4_ib_pd *pd;
1422	struct mlx4_ib_cq *send_cq, *recv_cq;
1423	struct mlx4_qp_context *context;
1424	enum mlx4_qp_optpar optpar = 0;
1425	int sqd_event;
1426	int steer_qp = 0;
1427	int err = -EINVAL;
1428
1429	/* APM is not supported under RoCE */
1430	if (attr_mask & IB_QP_ALT_PATH &&
1431	    rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1432	    IB_LINK_LAYER_ETHERNET)
1433		return -ENOTSUPP;
1434
1435	context = kzalloc(sizeof *context, GFP_KERNEL);
1436	if (!context)
1437		return -ENOMEM;
1438
1439	context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1440				     (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1441
1442	if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1443		context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1444	else {
1445		optpar |= MLX4_QP_OPTPAR_PM_STATE;
1446		switch (attr->path_mig_state) {
1447		case IB_MIG_MIGRATED:
1448			context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1449			break;
1450		case IB_MIG_REARM:
1451			context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1452			break;
1453		case IB_MIG_ARMED:
1454			context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1455			break;
1456		}
1457	}
1458
1459	if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1460		context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1461	else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1462		context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1463	else if (ibqp->qp_type == IB_QPT_UD) {
1464		if (qp->flags & MLX4_IB_QP_LSO)
1465			context->mtu_msgmax = (IB_MTU_4096 << 5) |
1466					      ilog2(dev->dev->caps.max_gso_sz);
1467		else
1468			context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1469	} else if (attr_mask & IB_QP_PATH_MTU) {
1470		if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1471			pr_err("path MTU (%u) is invalid\n",
1472			       attr->path_mtu);
1473			goto out;
1474		}
1475		context->mtu_msgmax = (attr->path_mtu << 5) |
1476			ilog2(dev->dev->caps.max_msg_sz);
1477	}
1478
1479	if (qp->rq.wqe_cnt)
1480		context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1481	context->rq_size_stride |= qp->rq.wqe_shift - 4;
1482
1483	if (qp->sq.wqe_cnt)
1484		context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1485	context->sq_size_stride |= qp->sq.wqe_shift - 4;
1486
1487	if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1488		context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1489		context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1490		if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1491			context->param3 |= cpu_to_be32(1 << 30);
1492	}
1493
1494	if (qp->ibqp.uobject)
1495		context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1496	else
1497		context->usr_page = cpu_to_be32(dev->priv_uar.index);
1498
1499	if (attr_mask & IB_QP_DEST_QPN)
1500		context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1501
1502	if (attr_mask & IB_QP_PORT) {
1503		if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1504		    !(attr_mask & IB_QP_AV)) {
1505			mlx4_set_sched(&context->pri_path, attr->port_num);
1506			optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1507		}
1508	}
1509
1510	if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1511		if (dev->counters[qp->port - 1] != -1) {
1512			context->pri_path.counter_index =
1513						dev->counters[qp->port - 1];
1514			optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1515		} else
1516			context->pri_path.counter_index = 0xff;
1517
1518		if (qp->flags & MLX4_IB_QP_NETIF) {
1519			mlx4_ib_steer_qp_reg(dev, qp, 1);
1520			steer_qp = 1;
1521		}
1522	}
1523
1524	if (attr_mask & IB_QP_PKEY_INDEX) {
1525		if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1526			context->pri_path.disable_pkey_check = 0x40;
1527		context->pri_path.pkey_index = attr->pkey_index;
1528		optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1529	}
1530
1531	if (attr_mask & IB_QP_AV) {
1532		if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1533				  attr_mask & IB_QP_PORT ?
1534				  attr->port_num : qp->port))
1535			goto out;
1536
1537		optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1538			   MLX4_QP_OPTPAR_SCHED_QUEUE);
1539	}
1540
1541	if (attr_mask & IB_QP_TIMEOUT) {
1542		context->pri_path.ackto |= attr->timeout << 3;
1543		optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1544	}
1545
1546	if (attr_mask & IB_QP_ALT_PATH) {
1547		if (attr->alt_port_num == 0 ||
1548		    attr->alt_port_num > dev->dev->caps.num_ports)
1549			goto out;
1550
1551		if (attr->alt_pkey_index >=
1552		    dev->dev->caps.pkey_table_len[attr->alt_port_num])
1553			goto out;
1554
1555		if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1556				      &context->alt_path,
1557				      attr->alt_port_num))
1558			goto out;
1559
1560		context->alt_path.pkey_index = attr->alt_pkey_index;
1561		context->alt_path.ackto = attr->alt_timeout << 3;
1562		optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1563	}
1564
1565	pd = get_pd(qp);
1566	get_cqs(qp, &send_cq, &recv_cq);
1567	context->pd       = cpu_to_be32(pd->pdn);
1568	context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1569	context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1570	context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1571
1572	/* Set "fast registration enabled" for all kernel QPs */
1573	if (!qp->ibqp.uobject)
1574		context->params1 |= cpu_to_be32(1 << 11);
1575
1576	if (attr_mask & IB_QP_RNR_RETRY) {
1577		context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1578		optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1579	}
1580
1581	if (attr_mask & IB_QP_RETRY_CNT) {
1582		context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1583		optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1584	}
1585
1586	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1587		if (attr->max_rd_atomic)
1588			context->params1 |=
1589				cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1590		optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1591	}
1592
1593	if (attr_mask & IB_QP_SQ_PSN)
1594		context->next_send_psn = cpu_to_be32(attr->sq_psn);
1595
1596	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1597		if (attr->max_dest_rd_atomic)
1598			context->params2 |=
1599				cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1600		optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1601	}
1602
1603	if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1604		context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1605		optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1606	}
1607
1608	if (ibqp->srq)
1609		context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1610
1611	if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1612		context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1613		optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1614	}
1615	if (attr_mask & IB_QP_RQ_PSN)
1616		context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1617
1618	/* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1619	if (attr_mask & IB_QP_QKEY) {
1620		if (qp->mlx4_ib_qp_type &
1621		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1622			context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1623		else {
1624			if (mlx4_is_mfunc(dev->dev) &&
1625			    !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1626			    (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1627			    MLX4_RESERVED_QKEY_BASE) {
1628				pr_err("Cannot use reserved QKEY"
1629				       " 0x%x (range 0xffff0000..0xffffffff"
1630				       " is reserved)\n", attr->qkey);
1631				err = -EINVAL;
1632				goto out;
1633			}
1634			context->qkey = cpu_to_be32(attr->qkey);
1635		}
1636		optpar |= MLX4_QP_OPTPAR_Q_KEY;
1637	}
1638
1639	if (ibqp->srq)
1640		context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1641
1642	if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1643		context->db_rec_addr = cpu_to_be64(qp->db.dma);
1644
1645	if (cur_state == IB_QPS_INIT &&
1646	    new_state == IB_QPS_RTR  &&
1647	    (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1648	     ibqp->qp_type == IB_QPT_UD ||
1649	     ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1650		context->pri_path.sched_queue = (qp->port - 1) << 6;
1651		if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1652		    qp->mlx4_ib_qp_type &
1653		    (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1654			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1655			if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1656				context->pri_path.fl = 0x80;
1657		} else {
1658			if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1659				context->pri_path.fl = 0x80;
1660			context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1661		}
1662		if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1663		    IB_LINK_LAYER_ETHERNET) {
1664			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1665			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1666				context->pri_path.feup = 1 << 7; /* don't fsm */
1667			/* handle smac_index */
1668			if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1669			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1670			    qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1671				err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1672				if (err)
1673					return -EINVAL;
1674				if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1675					dev->qp1_proxy[qp->port - 1] = qp;
1676			}
1677		}
1678	}
1679
1680	if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1681		context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1682					MLX4_IB_LINK_TYPE_ETH;
1683		if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1684			/* set QP to receive both tunneled & non-tunneled packets */
1685			if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1686				context->srqn = cpu_to_be32(7 << 28);
1687		}
1688	}
1689
1690	if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1691		int is_eth = rdma_port_get_link_layer(
1692				&dev->ib_dev, qp->port) ==
1693				IB_LINK_LAYER_ETHERNET;
1694		if (is_eth) {
1695			context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1696			optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1697		}
1698	}
1699
1700
1701	if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD	&&
1702	    attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1703		sqd_event = 1;
1704	else
1705		sqd_event = 0;
1706
1707	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1708		context->rlkey |= (1 << 4);
1709
1710	/*
1711	 * Before passing a kernel QP to the HW, make sure that the
1712	 * ownership bits of the send queue are set and the SQ
1713	 * headroom is stamped so that the hardware doesn't start
1714	 * processing stale work requests.
1715	 */
1716	if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1717		struct mlx4_wqe_ctrl_seg *ctrl;
1718		int i;
1719
1720		for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1721			ctrl = get_send_wqe(qp, i);
1722			ctrl->owner_opcode = cpu_to_be32(1 << 31);
1723			if (qp->sq_max_wqes_per_wr == 1)
1724				ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1725
1726			stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1727		}
1728	}
1729
1730	err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1731			     to_mlx4_state(new_state), context, optpar,
1732			     sqd_event, &qp->mqp);
1733	if (err)
1734		goto out;
1735
1736	qp->state = new_state;
1737
1738	if (attr_mask & IB_QP_ACCESS_FLAGS)
1739		qp->atomic_rd_en = attr->qp_access_flags;
1740	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1741		qp->resp_depth = attr->max_dest_rd_atomic;
1742	if (attr_mask & IB_QP_PORT) {
1743		qp->port = attr->port_num;
1744		update_mcg_macs(dev, qp);
1745	}
1746	if (attr_mask & IB_QP_ALT_PATH)
1747		qp->alt_port = attr->alt_port_num;
1748
1749	if (is_sqp(dev, qp))
1750		store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1751
1752	/*
1753	 * If we moved QP0 to RTR, bring the IB link up; if we moved
1754	 * QP0 to RESET or ERROR, bring the link back down.
1755	 */
1756	if (is_qp0(dev, qp)) {
1757		if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1758			if (mlx4_INIT_PORT(dev->dev, qp->port))
1759				pr_warn("INIT_PORT failed for port %d\n",
1760				       qp->port);
1761
1762		if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1763		    (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1764			mlx4_CLOSE_PORT(dev->dev, qp->port);
1765	}
1766
1767	/*
1768	 * If we moved a kernel QP to RESET, clean up all old CQ
1769	 * entries and reinitialize the QP.
1770	 */
1771	if (new_state == IB_QPS_RESET) {
1772		if (!ibqp->uobject) {
1773			mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1774					 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1775			if (send_cq != recv_cq)
1776				mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1777
1778			qp->rq.head = 0;
1779			qp->rq.tail = 0;
1780			qp->sq.head = 0;
1781			qp->sq.tail = 0;
1782			qp->sq_next_wqe = 0;
1783			if (qp->rq.wqe_cnt)
1784				*qp->db.db  = 0;
1785
1786			if (qp->flags & MLX4_IB_QP_NETIF)
1787				mlx4_ib_steer_qp_reg(dev, qp, 0);
1788		}
1789		if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1790			mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1791			qp->pri.smac = 0;
1792			qp->pri.smac_port = 0;
1793		}
1794		if (qp->alt.smac) {
1795			mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1796			qp->alt.smac = 0;
1797		}
1798		if (qp->pri.vid < 0x1000) {
1799			mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1800			qp->pri.vid = 0xFFFF;
1801			qp->pri.candidate_vid = 0xFFFF;
1802			qp->pri.update_vid = 0;
1803		}
1804
1805		if (qp->alt.vid < 0x1000) {
1806			mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1807			qp->alt.vid = 0xFFFF;
1808			qp->alt.candidate_vid = 0xFFFF;
1809			qp->alt.update_vid = 0;
1810		}
1811	}
1812out:
1813	if (err && steer_qp)
1814		mlx4_ib_steer_qp_reg(dev, qp, 0);
1815	kfree(context);
1816	if (qp->pri.candidate_smac ||
1817	    (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1818		if (err) {
1819			mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1820		} else {
1821			if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1822				mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1823			qp->pri.smac = qp->pri.candidate_smac;
1824			qp->pri.smac_index = qp->pri.candidate_smac_index;
1825			qp->pri.smac_port = qp->pri.candidate_smac_port;
1826		}
1827		qp->pri.candidate_smac = 0;
1828		qp->pri.candidate_smac_index = 0;
1829		qp->pri.candidate_smac_port = 0;
1830	}
1831	if (qp->alt.candidate_smac) {
1832		if (err) {
1833			mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1834		} else {
1835			if (qp->alt.smac)
1836				mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1837			qp->alt.smac = qp->alt.candidate_smac;
1838			qp->alt.smac_index = qp->alt.candidate_smac_index;
1839			qp->alt.smac_port = qp->alt.candidate_smac_port;
1840		}
1841		qp->alt.candidate_smac = 0;
1842		qp->alt.candidate_smac_index = 0;
1843		qp->alt.candidate_smac_port = 0;
1844	}
1845
1846	if (qp->pri.update_vid) {
1847		if (err) {
1848			if (qp->pri.candidate_vid < 0x1000)
1849				mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1850						     qp->pri.candidate_vid);
1851		} else {
1852			if (qp->pri.vid < 0x1000)
1853				mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1854						     qp->pri.vid);
1855			qp->pri.vid = qp->pri.candidate_vid;
1856			qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1857			qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1858		}
1859		qp->pri.candidate_vid = 0xFFFF;
1860		qp->pri.update_vid = 0;
1861	}
1862
1863	if (qp->alt.update_vid) {
1864		if (err) {
1865			if (qp->alt.candidate_vid < 0x1000)
1866				mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1867						     qp->alt.candidate_vid);
1868		} else {
1869			if (qp->alt.vid < 0x1000)
1870				mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1871						     qp->alt.vid);
1872			qp->alt.vid = qp->alt.candidate_vid;
1873			qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1874			qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1875		}
1876		qp->alt.candidate_vid = 0xFFFF;
1877		qp->alt.update_vid = 0;
1878	}
1879
1880	return err;
1881}
1882
1883int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1884		      int attr_mask, struct ib_udata *udata)
1885{
1886	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1887	struct mlx4_ib_qp *qp = to_mqp(ibqp);
1888	enum ib_qp_state cur_state, new_state;
1889	int err = -EINVAL;
1890	int ll;
1891	mutex_lock(&qp->mutex);
1892
1893	cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1894	new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1895
1896	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1897		ll = IB_LINK_LAYER_UNSPECIFIED;
1898	} else {
1899		int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1900		ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1901	}
1902
1903	if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1904				attr_mask, ll)) {
1905		pr_debug("qpn 0x%x: invalid attribute mask specified "
1906			 "for transition %d to %d. qp_type %d,"
1907			 " attr_mask 0x%x\n",
1908			 ibqp->qp_num, cur_state, new_state,
1909			 ibqp->qp_type, attr_mask);
1910		goto out;
1911	}
1912
1913	if ((attr_mask & IB_QP_PORT) &&
1914	    (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1915		pr_debug("qpn 0x%x: invalid port number (%d) specified "
1916			 "for transition %d to %d. qp_type %d\n",
1917			 ibqp->qp_num, attr->port_num, cur_state,
1918			 new_state, ibqp->qp_type);
1919		goto out;
1920	}
1921
1922	if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1923	    (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1924	     IB_LINK_LAYER_ETHERNET))
1925		goto out;
1926
1927	if (attr_mask & IB_QP_PKEY_INDEX) {
1928		int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1929		if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1930			pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1931				 "for transition %d to %d. qp_type %d\n",
1932				 ibqp->qp_num, attr->pkey_index, cur_state,
1933				 new_state, ibqp->qp_type);
1934			goto out;
1935		}
1936	}
1937
1938	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1939	    attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1940		pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1941			 "Transition %d to %d. qp_type %d\n",
1942			 ibqp->qp_num, attr->max_rd_atomic, cur_state,
1943			 new_state, ibqp->qp_type);
1944		goto out;
1945	}
1946
1947	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1948	    attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1949		pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1950			 "Transition %d to %d. qp_type %d\n",
1951			 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1952			 new_state, ibqp->qp_type);
1953		goto out;
1954	}
1955
1956	if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1957		err = 0;
1958		goto out;
1959	}
1960
1961	err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1962
1963out:
1964	mutex_unlock(&qp->mutex);
1965	return err;
1966}
1967
1968static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
1969{
1970	int i;
1971	for (i = 0; i < dev->caps.num_ports; i++) {
1972		if (qpn == dev->caps.qp0_proxy[i] ||
1973		    qpn == dev->caps.qp0_tunnel[i]) {
1974			*qkey = dev->caps.qp0_qkey[i];
1975			return 0;
1976		}
1977	}
1978	return -EINVAL;
1979}
1980
1981static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1982				  struct ib_send_wr *wr,
1983				  void *wqe, unsigned *mlx_seg_len)
1984{
1985	struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1986	struct ib_device *ib_dev = &mdev->ib_dev;
1987	struct mlx4_wqe_mlx_seg *mlx = wqe;
1988	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1989	struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1990	u16 pkey;
1991	u32 qkey;
1992	int send_size;
1993	int header_size;
1994	int spc;
1995	int i;
1996
1997	if (wr->opcode != IB_WR_SEND)
1998		return -EINVAL;
1999
2000	send_size = 0;
2001
2002	for (i = 0; i < wr->num_sge; ++i)
2003		send_size += wr->sg_list[i].length;
2004
2005	/* for proxy-qp0 sends, need to add in size of tunnel header */
2006	/* for tunnel-qp0 sends, tunnel header is already in s/g list */
2007	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2008		send_size += sizeof (struct mlx4_ib_tunnel_header);
2009
2010	ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2011
2012	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2013		sqp->ud_header.lrh.service_level =
2014			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2015		sqp->ud_header.lrh.destination_lid =
2016			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2017		sqp->ud_header.lrh.source_lid =
2018			cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2019	}
2020
2021	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2022
2023	/* force loopback */
2024	mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2025	mlx->rlid = sqp->ud_header.lrh.destination_lid;
2026
2027	sqp->ud_header.lrh.virtual_lane    = 0;
2028	sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2029	ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2030	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2031	if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2032		sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2033	else
2034		sqp->ud_header.bth.destination_qpn =
2035			cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2036
2037	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2038	if (mlx4_is_master(mdev->dev)) {
2039		if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2040			return -EINVAL;
2041	} else {
2042		if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2043			return -EINVAL;
2044	}
2045	sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2046	sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2047
2048	sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2049	sqp->ud_header.immediate_present = 0;
2050
2051	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2052
2053	/*
2054	 * Inline data segments may not cross a 64 byte boundary.  If
2055	 * our UD header is bigger than the space available up to the
2056	 * next 64 byte boundary in the WQE, use two inline data
2057	 * segments to hold the UD header.
2058	 */
2059	spc = MLX4_INLINE_ALIGN -
2060	      ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2061	if (header_size <= spc) {
2062		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2063		memcpy(inl + 1, sqp->header_buf, header_size);
2064		i = 1;
2065	} else {
2066		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2067		memcpy(inl + 1, sqp->header_buf, spc);
2068
2069		inl = (void *) (inl + 1) + spc;
2070		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2071		/*
2072		 * Need a barrier here to make sure all the data is
2073		 * visible before the byte_count field is set.
2074		 * Otherwise the HCA prefetcher could grab the 64-byte
2075		 * chunk with this inline segment and get a valid (!=
2076		 * 0xffffffff) byte count but stale data, and end up
2077		 * generating a packet with bad headers.
2078		 *
2079		 * The first inline segment's byte_count field doesn't
2080		 * need a barrier, because it comes after a
2081		 * control/MLX segment and therefore is at an offset
2082		 * of 16 mod 64.
2083		 */
2084		wmb();
2085		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2086		i = 2;
2087	}
2088
2089	*mlx_seg_len =
2090	ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2091	return 0;
2092}
2093
2094static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2095{
2096	int i;
2097
2098	for (i = ETH_ALEN; i; i--) {
2099		dst_mac[i - 1] = src_mac & 0xff;
2100		src_mac >>= 8;
2101	}
2102}
2103
2104static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2105			    void *wqe, unsigned *mlx_seg_len)
2106{
2107	struct ib_device *ib_dev = sqp->qp.ibqp.device;
2108	struct mlx4_wqe_mlx_seg *mlx = wqe;
2109	struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2110	struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2111	struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2112	union ib_gid sgid;
2113	u16 pkey;
2114	int send_size;
2115	int header_size;
2116	int spc;
2117	int i;
2118	int err = 0;
2119	u16 vlan = 0xffff;
2120	bool is_eth;
2121	bool is_vlan = false;
2122	bool is_grh;
2123
2124	send_size = 0;
2125	for (i = 0; i < wr->num_sge; ++i)
2126		send_size += wr->sg_list[i].length;
2127
2128	is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2129	is_grh = mlx4_ib_ah_grh_present(ah);
2130	if (is_eth) {
2131		if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2132			/* When multi-function is enabled, the ib_core gid
2133			 * indexes don't necessarily match the hw ones, so
2134			 * we must use our own cache */
2135			err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2136							   be32_to_cpu(ah->av.ib.port_pd) >> 24,
2137							   ah->av.ib.gid_index, &sgid.raw[0]);
2138			if (err)
2139				return err;
2140		} else  {
2141			err = ib_get_cached_gid(ib_dev,
2142						be32_to_cpu(ah->av.ib.port_pd) >> 24,
2143						ah->av.ib.gid_index, &sgid);
2144			if (err)
2145				return err;
2146		}
2147
2148		if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2149			vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2150			is_vlan = 1;
2151		}
2152	}
2153	ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2154
2155	if (!is_eth) {
2156		sqp->ud_header.lrh.service_level =
2157			be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2158		sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2159		sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2160	}
2161
2162	if (is_grh) {
2163		sqp->ud_header.grh.traffic_class =
2164			(be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2165		sqp->ud_header.grh.flow_label    =
2166			ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2167		sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2168		if (is_eth)
2169			memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2170		else {
2171		if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2172			/* When multi-function is enabled, the ib_core gid
2173			 * indexes don't necessarily match the hw ones, so
2174			 * we must use our own cache */
2175			sqp->ud_header.grh.source_gid.global.subnet_prefix =
2176				to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2177						       subnet_prefix;
2178			sqp->ud_header.grh.source_gid.global.interface_id =
2179				to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2180					       guid_cache[ah->av.ib.gid_index];
2181		} else
2182			ib_get_cached_gid(ib_dev,
2183					  be32_to_cpu(ah->av.ib.port_pd) >> 24,
2184					  ah->av.ib.gid_index,
2185					  &sqp->ud_header.grh.source_gid);
2186		}
2187		memcpy(sqp->ud_header.grh.destination_gid.raw,
2188		       ah->av.ib.dgid, 16);
2189	}
2190
2191	mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2192
2193	if (!is_eth) {
2194		mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2195					  (sqp->ud_header.lrh.destination_lid ==
2196					   IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2197					  (sqp->ud_header.lrh.service_level << 8));
2198		if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2199			mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2200		mlx->rlid = sqp->ud_header.lrh.destination_lid;
2201	}
2202
2203	switch (wr->opcode) {
2204	case IB_WR_SEND:
2205		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY;
2206		sqp->ud_header.immediate_present = 0;
2207		break;
2208	case IB_WR_SEND_WITH_IMM:
2209		sqp->ud_header.bth.opcode	 = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2210		sqp->ud_header.immediate_present = 1;
2211		sqp->ud_header.immediate_data    = wr->ex.imm_data;
2212		break;
2213	default:
2214		return -EINVAL;
2215	}
2216
2217	if (is_eth) {
2218		struct in6_addr in6;
2219
2220		u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2221
2222		mlx->sched_prio = cpu_to_be16(pcp);
2223
2224		memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2225		/* FIXME: cache smac value? */
2226		memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2227		memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2228		memcpy(&in6, sgid.raw, sizeof(in6));
2229
2230		if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2231			u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2232			u8 smac[ETH_ALEN];
2233
2234			mlx4_u64_to_smac(smac, mac);
2235			memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2236		} else {
2237			/* use the src mac of the tunnel */
2238			memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2239		}
2240
2241		if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2242			mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2243		if (!is_vlan) {
2244			sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2245		} else {
2246			sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2247			sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2248		}
2249	} else {
2250		sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2251		if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2252			sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2253	}
2254	sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2255	if (!sqp->qp.ibqp.qp_num)
2256		ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2257	else
2258		ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2259	sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2260	sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2261	sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2262	sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2263					       sqp->qkey : wr->wr.ud.remote_qkey);
2264	sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2265
2266	header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2267
2268	if (0) {
2269		pr_err("built UD header of size %d:\n", header_size);
2270		for (i = 0; i < header_size / 4; ++i) {
2271			if (i % 8 == 0)
2272				pr_err("  [%02x] ", i * 4);
2273			pr_cont(" %08x",
2274				be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2275			if ((i + 1) % 8 == 0)
2276				pr_cont("\n");
2277		}
2278		pr_err("\n");
2279	}
2280
2281	/*
2282	 * Inline data segments may not cross a 64 byte boundary.  If
2283	 * our UD header is bigger than the space available up to the
2284	 * next 64 byte boundary in the WQE, use two inline data
2285	 * segments to hold the UD header.
2286	 */
2287	spc = MLX4_INLINE_ALIGN -
2288		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2289	if (header_size <= spc) {
2290		inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2291		memcpy(inl + 1, sqp->header_buf, header_size);
2292		i = 1;
2293	} else {
2294		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2295		memcpy(inl + 1, sqp->header_buf, spc);
2296
2297		inl = (void *) (inl + 1) + spc;
2298		memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2299		/*
2300		 * Need a barrier here to make sure all the data is
2301		 * visible before the byte_count field is set.
2302		 * Otherwise the HCA prefetcher could grab the 64-byte
2303		 * chunk with this inline segment and get a valid (!=
2304		 * 0xffffffff) byte count but stale data, and end up
2305		 * generating a packet with bad headers.
2306		 *
2307		 * The first inline segment's byte_count field doesn't
2308		 * need a barrier, because it comes after a
2309		 * control/MLX segment and therefore is at an offset
2310		 * of 16 mod 64.
2311		 */
2312		wmb();
2313		inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2314		i = 2;
2315	}
2316
2317	*mlx_seg_len =
2318		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2319	return 0;
2320}
2321
2322static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2323{
2324	unsigned cur;
2325	struct mlx4_ib_cq *cq;
2326
2327	cur = wq->head - wq->tail;
2328	if (likely(cur + nreq < wq->max_post))
2329		return 0;
2330
2331	cq = to_mcq(ib_cq);
2332	spin_lock(&cq->lock);
2333	cur = wq->head - wq->tail;
2334	spin_unlock(&cq->lock);
2335
2336	return cur + nreq >= wq->max_post;
2337}
2338
2339static __be32 convert_access(int acc)
2340{
2341	return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2342		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2343	       (acc & IB_ACCESS_REMOTE_WRITE  ?
2344		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2345	       (acc & IB_ACCESS_REMOTE_READ   ?
2346		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2347	       (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2348		cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2349}
2350
2351static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2352{
2353	struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2354	int i;
2355
2356	for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2357		mfrpl->mapped_page_list[i] =
2358			cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2359				    MLX4_MTT_FLAG_PRESENT);
2360
2361	fseg->flags		= convert_access(wr->wr.fast_reg.access_flags);
2362	fseg->mem_key		= cpu_to_be32(wr->wr.fast_reg.rkey);
2363	fseg->buf_list		= cpu_to_be64(mfrpl->map);
2364	fseg->start_addr	= cpu_to_be64(wr->wr.fast_reg.iova_start);
2365	fseg->reg_len		= cpu_to_be64(wr->wr.fast_reg.length);
2366	fseg->offset		= 0; /* XXX -- is this just for ZBVA? */
2367	fseg->page_size		= cpu_to_be32(wr->wr.fast_reg.page_shift);
2368	fseg->reserved[0]	= 0;
2369	fseg->reserved[1]	= 0;
2370}
2371
2372static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2373{
2374	bseg->flags1 =
2375		convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2376		cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2377			    MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2378			    MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2379	bseg->flags2 = 0;
2380	if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2381		bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2382	if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2383		bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2384	bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2385	bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2386	bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2387	bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2388}
2389
2390static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2391{
2392	memset(iseg, 0, sizeof(*iseg));
2393	iseg->mem_key = cpu_to_be32(rkey);
2394}
2395
2396static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2397					  u64 remote_addr, u32 rkey)
2398{
2399	rseg->raddr    = cpu_to_be64(remote_addr);
2400	rseg->rkey     = cpu_to_be32(rkey);
2401	rseg->reserved = 0;
2402}
2403
2404static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2405{
2406	if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2407		aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2408		aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2409	} else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2410		aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2411		aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2412	} else {
2413		aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2414		aseg->compare  = 0;
2415	}
2416
2417}
2418
2419static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2420				  struct ib_send_wr *wr)
2421{
2422	aseg->swap_add		= cpu_to_be64(wr->wr.atomic.swap);
2423	aseg->swap_add_mask	= cpu_to_be64(wr->wr.atomic.swap_mask);
2424	aseg->compare		= cpu_to_be64(wr->wr.atomic.compare_add);
2425	aseg->compare_mask	= cpu_to_be64(wr->wr.atomic.compare_add_mask);
2426}
2427
2428static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2429			     struct ib_send_wr *wr)
2430{
2431	memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2432	dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2433	dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2434	dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2435	memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2436}
2437
2438static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2439				    struct mlx4_wqe_datagram_seg *dseg,
2440				    struct ib_send_wr *wr,
2441				    enum mlx4_ib_qp_type qpt)
2442{
2443	union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2444	struct mlx4_av sqp_av = {0};
2445	int port = *((u8 *) &av->ib.port_pd) & 0x3;
2446
2447	/* force loopback */
2448	sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2449	sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2450	sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2451			cpu_to_be32(0xf0000000);
2452
2453	memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2454	if (qpt == MLX4_IB_QPT_PROXY_GSI)
2455		dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2456	else
2457		dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2458	/* Use QKEY from the QP context, which is set by master */
2459	dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2460}
2461
2462static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2463{
2464	struct mlx4_wqe_inline_seg *inl = wqe;
2465	struct mlx4_ib_tunnel_header hdr;
2466	struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2467	int spc;
2468	int i;
2469
2470	memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2471	hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2472	hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2473	hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2474	memcpy(hdr.mac, ah->av.eth.mac, 6);
2475	hdr.vlan = ah->av.eth.vlan;
2476
2477	spc = MLX4_INLINE_ALIGN -
2478		((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2479	if (sizeof (hdr) <= spc) {
2480		memcpy(inl + 1, &hdr, sizeof (hdr));
2481		wmb();
2482		inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2483		i = 1;
2484	} else {
2485		memcpy(inl + 1, &hdr, spc);
2486		wmb();
2487		inl->byte_count = cpu_to_be32(1 << 31 | spc);
2488
2489		inl = (void *) (inl + 1) + spc;
2490		memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2491		wmb();
2492		inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2493		i = 2;
2494	}
2495
2496	*mlx_seg_len =
2497		ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2498}
2499
2500static void set_mlx_icrc_seg(void *dseg)
2501{
2502	u32 *t = dseg;
2503	struct mlx4_wqe_inline_seg *iseg = dseg;
2504
2505	t[1] = 0;
2506
2507	/*
2508	 * Need a barrier here before writing the byte_count field to
2509	 * make sure that all the data is visible before the
2510	 * byte_count field is set.  Otherwise, if the segment begins
2511	 * a new cacheline, the HCA prefetcher could grab the 64-byte
2512	 * chunk and get a valid (!= * 0xffffffff) byte count but
2513	 * stale data, and end up sending the wrong data.
2514	 */
2515	wmb();
2516
2517	iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2518}
2519
2520static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2521{
2522	dseg->lkey       = cpu_to_be32(sg->lkey);
2523	dseg->addr       = cpu_to_be64(sg->addr);
2524
2525	/*
2526	 * Need a barrier here before writing the byte_count field to
2527	 * make sure that all the data is visible before the
2528	 * byte_count field is set.  Otherwise, if the segment begins
2529	 * a new cacheline, the HCA prefetcher could grab the 64-byte
2530	 * chunk and get a valid (!= * 0xffffffff) byte count but
2531	 * stale data, and end up sending the wrong data.
2532	 */
2533	wmb();
2534
2535	dseg->byte_count = cpu_to_be32(sg->length);
2536}
2537
2538static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2539{
2540	dseg->byte_count = cpu_to_be32(sg->length);
2541	dseg->lkey       = cpu_to_be32(sg->lkey);
2542	dseg->addr       = cpu_to_be64(sg->addr);
2543}
2544
2545static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2546			 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2547			 __be32 *lso_hdr_sz, __be32 *blh)
2548{
2549	unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2550
2551	if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2552		*blh = cpu_to_be32(1 << 6);
2553
2554	if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2555		     wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2556		return -EINVAL;
2557
2558	memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2559
2560	*lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2561				   wr->wr.ud.hlen);
2562	*lso_seg_len = halign;
2563	return 0;
2564}
2565
2566static __be32 send_ieth(struct ib_send_wr *wr)
2567{
2568	switch (wr->opcode) {
2569	case IB_WR_SEND_WITH_IMM:
2570	case IB_WR_RDMA_WRITE_WITH_IMM:
2571		return wr->ex.imm_data;
2572
2573	case IB_WR_SEND_WITH_INV:
2574		return cpu_to_be32(wr->ex.invalidate_rkey);
2575
2576	default:
2577		return 0;
2578	}
2579}
2580
2581static void add_zero_len_inline(void *wqe)
2582{
2583	struct mlx4_wqe_inline_seg *inl = wqe;
2584	memset(wqe, 0, 16);
2585	inl->byte_count = cpu_to_be32(1 << 31);
2586}
2587
2588int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2589		      struct ib_send_wr **bad_wr)
2590{
2591	struct mlx4_ib_qp *qp = to_mqp(ibqp);
2592	void *wqe;
2593	struct mlx4_wqe_ctrl_seg *ctrl;
2594	struct mlx4_wqe_data_seg *dseg;
2595	unsigned long flags;
2596	int nreq;
2597	int err = 0;
2598	unsigned ind;
2599	int uninitialized_var(stamp);
2600	int uninitialized_var(size);
2601	unsigned uninitialized_var(seglen);
2602	__be32 dummy;
2603	__be32 *lso_wqe;
2604	__be32 uninitialized_var(lso_hdr_sz);
2605	__be32 blh;
2606	int i;
2607
2608	spin_lock_irqsave(&qp->sq.lock, flags);
2609
2610	ind = qp->sq_next_wqe;
2611
2612	for (nreq = 0; wr; ++nreq, wr = wr->next) {
2613		lso_wqe = &dummy;
2614		blh = 0;
2615
2616		if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2617			err = -ENOMEM;
2618			*bad_wr = wr;
2619			goto out;
2620		}
2621
2622		if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2623			err = -EINVAL;
2624			*bad_wr = wr;
2625			goto out;
2626		}
2627
2628		ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2629		qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2630
2631		ctrl->srcrb_flags =
2632			(wr->send_flags & IB_SEND_SIGNALED ?
2633			 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2634			(wr->send_flags & IB_SEND_SOLICITED ?
2635			 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2636			((wr->send_flags & IB_SEND_IP_CSUM) ?
2637			 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2638				     MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2639			qp->sq_signal_bits;
2640
2641		ctrl->imm = send_ieth(wr);
2642
2643		wqe += sizeof *ctrl;
2644		size = sizeof *ctrl / 16;
2645
2646		switch (qp->mlx4_ib_qp_type) {
2647		case MLX4_IB_QPT_RC:
2648		case MLX4_IB_QPT_UC:
2649			switch (wr->opcode) {
2650			case IB_WR_ATOMIC_CMP_AND_SWP:
2651			case IB_WR_ATOMIC_FETCH_AND_ADD:
2652			case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2653				set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2654					      wr->wr.atomic.rkey);
2655				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2656
2657				set_atomic_seg(wqe, wr);
2658				wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2659
2660				size += (sizeof (struct mlx4_wqe_raddr_seg) +
2661					 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2662
2663				break;
2664
2665			case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2666				set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2667					      wr->wr.atomic.rkey);
2668				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2669
2670				set_masked_atomic_seg(wqe, wr);
2671				wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2672
2673				size += (sizeof (struct mlx4_wqe_raddr_seg) +
2674					 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2675
2676				break;
2677
2678			case IB_WR_RDMA_READ:
2679			case IB_WR_RDMA_WRITE:
2680			case IB_WR_RDMA_WRITE_WITH_IMM:
2681				set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2682					      wr->wr.rdma.rkey);
2683				wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2684				size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2685				break;
2686
2687			case IB_WR_LOCAL_INV:
2688				ctrl->srcrb_flags |=
2689					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2690				set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2691				wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2692				size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2693				break;
2694
2695			case IB_WR_FAST_REG_MR:
2696				ctrl->srcrb_flags |=
2697					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2698				set_fmr_seg(wqe, wr);
2699				wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2700				size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2701				break;
2702
2703			case IB_WR_BIND_MW:
2704				ctrl->srcrb_flags |=
2705					cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2706				set_bind_seg(wqe, wr);
2707				wqe  += sizeof(struct mlx4_wqe_bind_seg);
2708				size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2709				break;
2710			default:
2711				/* No extra segments required for sends */
2712				break;
2713			}
2714			break;
2715
2716		case MLX4_IB_QPT_TUN_SMI_OWNER:
2717			err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2718			if (unlikely(err)) {
2719				*bad_wr = wr;
2720				goto out;
2721			}
2722			wqe  += seglen;
2723			size += seglen / 16;
2724			break;
2725		case MLX4_IB_QPT_TUN_SMI:
2726		case MLX4_IB_QPT_TUN_GSI:
2727			/* this is a UD qp used in MAD responses to slaves. */
2728			set_datagram_seg(wqe, wr);
2729			/* set the forced-loopback bit in the data seg av */
2730			*(__be32 *) wqe |= cpu_to_be32(0x80000000);
2731			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2732			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2733			break;
2734		case MLX4_IB_QPT_UD:
2735			set_datagram_seg(wqe, wr);
2736			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2737			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2738
2739			if (wr->opcode == IB_WR_LSO) {
2740				err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2741				if (unlikely(err)) {
2742					*bad_wr = wr;
2743					goto out;
2744				}
2745				lso_wqe = (__be32 *) wqe;
2746				wqe  += seglen;
2747				size += seglen / 16;
2748			}
2749			break;
2750
2751		case MLX4_IB_QPT_PROXY_SMI_OWNER:
2752			err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2753			if (unlikely(err)) {
2754				*bad_wr = wr;
2755				goto out;
2756			}
2757			wqe  += seglen;
2758			size += seglen / 16;
2759			/* to start tunnel header on a cache-line boundary */
2760			add_zero_len_inline(wqe);
2761			wqe += 16;
2762			size++;
2763			build_tunnel_header(wr, wqe, &seglen);
2764			wqe  += seglen;
2765			size += seglen / 16;
2766			break;
2767		case MLX4_IB_QPT_PROXY_SMI:
2768		case MLX4_IB_QPT_PROXY_GSI:
2769			/* If we are tunneling special qps, this is a UD qp.
2770			 * In this case we first add a UD segment targeting
2771			 * the tunnel qp, and then add a header with address
2772			 * information */
2773			set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2774						qp->mlx4_ib_qp_type);
2775			wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2776			size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2777			build_tunnel_header(wr, wqe, &seglen);
2778			wqe  += seglen;
2779			size += seglen / 16;
2780			break;
2781
2782		case MLX4_IB_QPT_SMI:
2783		case MLX4_IB_QPT_GSI:
2784			err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2785			if (unlikely(err)) {
2786				*bad_wr = wr;
2787				goto out;
2788			}
2789			wqe  += seglen;
2790			size += seglen / 16;
2791			break;
2792
2793		default:
2794			break;
2795		}
2796
2797		/*
2798		 * Write data segments in reverse order, so as to
2799		 * overwrite cacheline stamp last within each
2800		 * cacheline.  This avoids issues with WQE
2801		 * prefetching.
2802		 */
2803
2804		dseg = wqe;
2805		dseg += wr->num_sge - 1;
2806		size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2807
2808		/* Add one more inline data segment for ICRC for MLX sends */
2809		if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2810			     qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2811			     qp->mlx4_ib_qp_type &
2812			     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2813			set_mlx_icrc_seg(dseg + 1);
2814			size += sizeof (struct mlx4_wqe_data_seg) / 16;
2815		}
2816
2817		for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2818			set_data_seg(dseg, wr->sg_list + i);
2819
2820		/*
2821		 * Possibly overwrite stamping in cacheline with LSO
2822		 * segment only after making sure all data segments
2823		 * are written.
2824		 */
2825		wmb();
2826		*lso_wqe = lso_hdr_sz;
2827
2828		ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2829				    MLX4_WQE_CTRL_FENCE : 0) | size;
2830
2831		/*
2832		 * Make sure descriptor is fully written before
2833		 * setting ownership bit (because HW can start
2834		 * executing as soon as we do).
2835		 */
2836		wmb();
2837
2838		if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2839			*bad_wr = wr;
2840			err = -EINVAL;
2841			goto out;
2842		}
2843
2844		ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2845			(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2846
2847		stamp = ind + qp->sq_spare_wqes;
2848		ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2849
2850		/*
2851		 * We can improve latency by not stamping the last
2852		 * send queue WQE until after ringing the doorbell, so
2853		 * only stamp here if there are still more WQEs to post.
2854		 *
2855		 * Same optimization applies to padding with NOP wqe
2856		 * in case of WQE shrinking (used to prevent wrap-around
2857		 * in the middle of WR).
2858		 */
2859		if (wr->next) {
2860			stamp_send_wqe(qp, stamp, size * 16);
2861			ind = pad_wraparound(qp, ind);
2862		}
2863	}
2864
2865out:
2866	if (likely(nreq)) {
2867		qp->sq.head += nreq;
2868
2869		/*
2870		 * Make sure that descriptors are written before
2871		 * doorbell record.
2872		 */
2873		wmb();
2874
2875		writel(qp->doorbell_qpn,
2876		       to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2877
2878		/*
2879		 * Make sure doorbells don't leak out of SQ spinlock
2880		 * and reach the HCA out of order.
2881		 */
2882		mmiowb();
2883
2884		stamp_send_wqe(qp, stamp, size * 16);
2885
2886		ind = pad_wraparound(qp, ind);
2887		qp->sq_next_wqe = ind;
2888	}
2889
2890	spin_unlock_irqrestore(&qp->sq.lock, flags);
2891
2892	return err;
2893}
2894
2895int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2896		      struct ib_recv_wr **bad_wr)
2897{
2898	struct mlx4_ib_qp *qp = to_mqp(ibqp);
2899	struct mlx4_wqe_data_seg *scat;
2900	unsigned long flags;
2901	int err = 0;
2902	int nreq;
2903	int ind;
2904	int max_gs;
2905	int i;
2906
2907	max_gs = qp->rq.max_gs;
2908	spin_lock_irqsave(&qp->rq.lock, flags);
2909
2910	ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2911
2912	for (nreq = 0; wr; ++nreq, wr = wr->next) {
2913		if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2914			err = -ENOMEM;
2915			*bad_wr = wr;
2916			goto out;
2917		}
2918
2919		if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2920			err = -EINVAL;
2921			*bad_wr = wr;
2922			goto out;
2923		}
2924
2925		scat = get_recv_wqe(qp, ind);
2926
2927		if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2928		    MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2929			ib_dma_sync_single_for_device(ibqp->device,
2930						      qp->sqp_proxy_rcv[ind].map,
2931						      sizeof (struct mlx4_ib_proxy_sqp_hdr),
2932						      DMA_FROM_DEVICE);
2933			scat->byte_count =
2934				cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2935			/* use dma lkey from upper layer entry */
2936			scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2937			scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2938			scat++;
2939			max_gs--;
2940		}
2941
2942		for (i = 0; i < wr->num_sge; ++i)
2943			__set_data_seg(scat + i, wr->sg_list + i);
2944
2945		if (i < max_gs) {
2946			scat[i].byte_count = 0;
2947			scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2948			scat[i].addr       = 0;
2949		}
2950
2951		qp->rq.wrid[ind] = wr->wr_id;
2952
2953		ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2954	}
2955
2956out:
2957	if (likely(nreq)) {
2958		qp->rq.head += nreq;
2959
2960		/*
2961		 * Make sure that descriptors are written before
2962		 * doorbell record.
2963		 */
2964		wmb();
2965
2966		*qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2967	}
2968
2969	spin_unlock_irqrestore(&qp->rq.lock, flags);
2970
2971	return err;
2972}
2973
2974static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2975{
2976	switch (mlx4_state) {
2977	case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2978	case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2979	case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2980	case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2981	case MLX4_QP_STATE_SQ_DRAINING:
2982	case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2983	case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2984	case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2985	default:		     return -1;
2986	}
2987}
2988
2989static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2990{
2991	switch (mlx4_mig_state) {
2992	case MLX4_QP_PM_ARMED:		return IB_MIG_ARMED;
2993	case MLX4_QP_PM_REARM:		return IB_MIG_REARM;
2994	case MLX4_QP_PM_MIGRATED:	return IB_MIG_MIGRATED;
2995	default: return -1;
2996	}
2997}
2998
2999static int to_ib_qp_access_flags(int mlx4_flags)
3000{
3001	int ib_flags = 0;
3002
3003	if (mlx4_flags & MLX4_QP_BIT_RRE)
3004		ib_flags |= IB_ACCESS_REMOTE_READ;
3005	if (mlx4_flags & MLX4_QP_BIT_RWE)
3006		ib_flags |= IB_ACCESS_REMOTE_WRITE;
3007	if (mlx4_flags & MLX4_QP_BIT_RAE)
3008		ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3009
3010	return ib_flags;
3011}
3012
3013static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3014				struct mlx4_qp_path *path)
3015{
3016	struct mlx4_dev *dev = ibdev->dev;
3017	int is_eth;
3018
3019	memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3020	ib_ah_attr->port_num	  = path->sched_queue & 0x40 ? 2 : 1;
3021
3022	if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3023		return;
3024
3025	is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3026		IB_LINK_LAYER_ETHERNET;
3027	if (is_eth)
3028		ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3029		((path->sched_queue & 4) << 1);
3030	else
3031		ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3032
3033	ib_ah_attr->dlid	  = be16_to_cpu(path->rlid);
3034	ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3035	ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3036	ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3037	if (ib_ah_attr->ah_flags) {
3038		ib_ah_attr->grh.sgid_index = path->mgid_index;
3039		ib_ah_attr->grh.hop_limit  = path->hop_limit;
3040		ib_ah_attr->grh.traffic_class =
3041			(be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3042		ib_ah_attr->grh.flow_label =
3043			be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3044		memcpy(ib_ah_attr->grh.dgid.raw,
3045			path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3046	}
3047}
3048
3049int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3050		     struct ib_qp_init_attr *qp_init_attr)
3051{
3052	struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3053	struct mlx4_ib_qp *qp = to_mqp(ibqp);
3054	struct mlx4_qp_context context;
3055	int mlx4_state;
3056	int err = 0;
3057
3058	mutex_lock(&qp->mutex);
3059
3060	if (qp->state == IB_QPS_RESET) {
3061		qp_attr->qp_state = IB_QPS_RESET;
3062		goto done;
3063	}
3064
3065	err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3066	if (err) {
3067		err = -EINVAL;
3068		goto out;
3069	}
3070
3071	mlx4_state = be32_to_cpu(context.flags) >> 28;
3072
3073	qp->state		     = to_ib_qp_state(mlx4_state);
3074	qp_attr->qp_state	     = qp->state;
3075	qp_attr->path_mtu	     = context.mtu_msgmax >> 5;
3076	qp_attr->path_mig_state	     =
3077		to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3078	qp_attr->qkey		     = be32_to_cpu(context.qkey);
3079	qp_attr->rq_psn		     = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3080	qp_attr->sq_psn		     = be32_to_cpu(context.next_send_psn) & 0xffffff;
3081	qp_attr->dest_qp_num	     = be32_to_cpu(context.remote_qpn) & 0xffffff;
3082	qp_attr->qp_access_flags     =
3083		to_ib_qp_access_flags(be32_to_cpu(context.params2));
3084
3085	if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3086		to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3087		to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3088		qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3089		qp_attr->alt_port_num	= qp_attr->alt_ah_attr.port_num;
3090	}
3091
3092	qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3093	if (qp_attr->qp_state == IB_QPS_INIT)
3094		qp_attr->port_num = qp->port;
3095	else
3096		qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3097
3098	/* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3099	qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3100
3101	qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3102
3103	qp_attr->max_dest_rd_atomic =
3104		1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3105	qp_attr->min_rnr_timer	    =
3106		(be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3107	qp_attr->timeout	    = context.pri_path.ackto >> 3;
3108	qp_attr->retry_cnt	    = (be32_to_cpu(context.params1) >> 16) & 0x7;
3109	qp_attr->rnr_retry	    = (be32_to_cpu(context.params1) >> 13) & 0x7;
3110	qp_attr->alt_timeout	    = context.alt_path.ackto >> 3;
3111
3112done:
3113	qp_attr->cur_qp_state	     = qp_attr->qp_state;
3114	qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3115	qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3116
3117	if (!ibqp->uobject) {
3118		qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3119		qp_attr->cap.max_send_sge = qp->sq.max_gs;
3120	} else {
3121		qp_attr->cap.max_send_wr  = 0;
3122		qp_attr->cap.max_send_sge = 0;
3123	}
3124
3125	/*
3126	 * We don't support inline sends for kernel QPs (yet), and we
3127	 * don't know what userspace's value should be.
3128	 */
3129	qp_attr->cap.max_inline_data = 0;
3130
3131	qp_init_attr->cap	     = qp_attr->cap;
3132
3133	qp_init_attr->create_flags = 0;
3134	if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3135		qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3136
3137	if (qp->flags & MLX4_IB_QP_LSO)
3138		qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3139
3140	if (qp->flags & MLX4_IB_QP_NETIF)
3141		qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3142
3143	qp_init_attr->sq_sig_type =
3144		qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3145		IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3146
3147out:
3148	mutex_unlock(&qp->mutex);
3149	return err;
3150}
3151
3152