1/* 2 * Copyright (c) 2012 Intel Corporation. All rights reserved. 3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved. 4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#include <linux/delay.h> 36#include <linux/pci.h> 37#include <linux/vmalloc.h> 38 39#include "qib.h" 40 41/* 42 * QLogic_IB "Two Wire Serial Interface" driver. 43 * Originally written for a not-quite-i2c serial eeprom, which is 44 * still used on some supported boards. Later boards have added a 45 * variety of other uses, most board-specific, so the bit-boffing 46 * part has been split off to this file, while the other parts 47 * have been moved to chip-specific files. 48 * 49 * We have also dropped all pretense of fully generic (e.g. pretend 50 * we don't know whether '1' is the higher voltage) interface, as 51 * the restrictions of the generic i2c interface (e.g. no access from 52 * driver itself) make it unsuitable for this use. 53 */ 54 55#define READ_CMD 1 56#define WRITE_CMD 0 57 58/** 59 * i2c_wait_for_writes - wait for a write 60 * @dd: the qlogic_ib device 61 * 62 * We use this instead of udelay directly, so we can make sure 63 * that previous register writes have been flushed all the way 64 * to the chip. Since we are delaying anyway, the cost doesn't 65 * hurt, and makes the bit twiddling more regular 66 */ 67static void i2c_wait_for_writes(struct qib_devdata *dd) 68{ 69 /* 70 * implicit read of EXTStatus is as good as explicit 71 * read of scratch, if all we want to do is flush 72 * writes. 73 */ 74 dd->f_gpio_mod(dd, 0, 0, 0); 75 rmb(); /* inlined, so prevent compiler reordering */ 76} 77 78/* 79 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that 80 * for "almost compliant" modules 81 */ 82#define SCL_WAIT_USEC 1000 83 84/* BUF_WAIT is time bus must be free between STOP or ACK and to next START. 85 * Should be 20, but some chips need more. 86 */ 87#define TWSI_BUF_WAIT_USEC 60 88 89static void scl_out(struct qib_devdata *dd, u8 bit) 90{ 91 u32 mask; 92 93 udelay(1); 94 95 mask = 1UL << dd->gpio_scl_num; 96 97 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */ 98 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); 99 100 /* 101 * Allow for slow slaves by simple 102 * delay for falling edge, sampling on rise. 103 */ 104 if (!bit) 105 udelay(2); 106 else { 107 int rise_usec; 108 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) { 109 if (mask & dd->f_gpio_mod(dd, 0, 0, 0)) 110 break; 111 udelay(2); 112 } 113 if (rise_usec <= 0) 114 qib_dev_err(dd, "SCL interface stuck low > %d uSec\n", 115 SCL_WAIT_USEC); 116 } 117 i2c_wait_for_writes(dd); 118} 119 120static void sda_out(struct qib_devdata *dd, u8 bit) 121{ 122 u32 mask; 123 124 mask = 1UL << dd->gpio_sda_num; 125 126 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */ 127 dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); 128 129 i2c_wait_for_writes(dd); 130 udelay(2); 131} 132 133static u8 sda_in(struct qib_devdata *dd, int wait) 134{ 135 int bnum; 136 u32 read_val, mask; 137 138 bnum = dd->gpio_sda_num; 139 mask = (1UL << bnum); 140 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */ 141 dd->f_gpio_mod(dd, 0, 0, mask); 142 read_val = dd->f_gpio_mod(dd, 0, 0, 0); 143 if (wait) 144 i2c_wait_for_writes(dd); 145 return (read_val & mask) >> bnum; 146} 147 148/** 149 * i2c_ackrcv - see if ack following write is true 150 * @dd: the qlogic_ib device 151 */ 152static int i2c_ackrcv(struct qib_devdata *dd) 153{ 154 u8 ack_received; 155 156 /* AT ENTRY SCL = LOW */ 157 /* change direction, ignore data */ 158 ack_received = sda_in(dd, 1); 159 scl_out(dd, 1); 160 ack_received = sda_in(dd, 1) == 0; 161 scl_out(dd, 0); 162 return ack_received; 163} 164 165static void stop_cmd(struct qib_devdata *dd); 166 167/** 168 * rd_byte - read a byte, sending STOP on last, else ACK 169 * @dd: the qlogic_ib device 170 * 171 * Returns byte shifted out of device 172 */ 173static int rd_byte(struct qib_devdata *dd, int last) 174{ 175 int bit_cntr, data; 176 177 data = 0; 178 179 for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) { 180 data <<= 1; 181 scl_out(dd, 1); 182 data |= sda_in(dd, 0); 183 scl_out(dd, 0); 184 } 185 if (last) { 186 scl_out(dd, 1); 187 stop_cmd(dd); 188 } else { 189 sda_out(dd, 0); 190 scl_out(dd, 1); 191 scl_out(dd, 0); 192 sda_out(dd, 1); 193 } 194 return data; 195} 196 197/** 198 * wr_byte - write a byte, one bit at a time 199 * @dd: the qlogic_ib device 200 * @data: the byte to write 201 * 202 * Returns 0 if we got the following ack, otherwise 1 203 */ 204static int wr_byte(struct qib_devdata *dd, u8 data) 205{ 206 int bit_cntr; 207 u8 bit; 208 209 for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) { 210 bit = (data >> bit_cntr) & 1; 211 sda_out(dd, bit); 212 scl_out(dd, 1); 213 scl_out(dd, 0); 214 } 215 return (!i2c_ackrcv(dd)) ? 1 : 0; 216} 217 218/* 219 * issue TWSI start sequence: 220 * (both clock/data high, clock high, data low while clock is high) 221 */ 222static void start_seq(struct qib_devdata *dd) 223{ 224 sda_out(dd, 1); 225 scl_out(dd, 1); 226 sda_out(dd, 0); 227 udelay(1); 228 scl_out(dd, 0); 229} 230 231/** 232 * stop_seq - transmit the stop sequence 233 * @dd: the qlogic_ib device 234 * 235 * (both clock/data low, clock high, data high while clock is high) 236 */ 237static void stop_seq(struct qib_devdata *dd) 238{ 239 scl_out(dd, 0); 240 sda_out(dd, 0); 241 scl_out(dd, 1); 242 sda_out(dd, 1); 243} 244 245/** 246 * stop_cmd - transmit the stop condition 247 * @dd: the qlogic_ib device 248 * 249 * (both clock/data low, clock high, data high while clock is high) 250 */ 251static void stop_cmd(struct qib_devdata *dd) 252{ 253 stop_seq(dd); 254 udelay(TWSI_BUF_WAIT_USEC); 255} 256 257/** 258 * qib_twsi_reset - reset I2C communication 259 * @dd: the qlogic_ib device 260 */ 261 262int qib_twsi_reset(struct qib_devdata *dd) 263{ 264 int clock_cycles_left = 9; 265 int was_high = 0; 266 u32 pins, mask; 267 268 /* Both SCL and SDA should be high. If not, there 269 * is something wrong. 270 */ 271 mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num); 272 273 /* 274 * Force pins to desired innocuous state. 275 * This is the default power-on state with out=0 and dir=0, 276 * So tri-stated and should be floating high (barring HW problems) 277 */ 278 dd->f_gpio_mod(dd, 0, 0, mask); 279 280 /* 281 * Clock nine times to get all listeners into a sane state. 282 * If SDA does not go high at any point, we are wedged. 283 * One vendor recommends then issuing START followed by STOP. 284 * we cannot use our "normal" functions to do that, because 285 * if SCL drops between them, another vendor's part will 286 * wedge, dropping SDA and keeping it low forever, at the end of 287 * the next transaction (even if it was not the device addressed). 288 * So our START and STOP take place with SCL held high. 289 */ 290 while (clock_cycles_left--) { 291 scl_out(dd, 0); 292 scl_out(dd, 1); 293 /* Note if SDA is high, but keep clocking to sync slave */ 294 was_high |= sda_in(dd, 0); 295 } 296 297 if (was_high) { 298 /* 299 * We saw a high, which we hope means the slave is sync'd. 300 * Issue START, STOP, pause for T_BUF. 301 */ 302 303 pins = dd->f_gpio_mod(dd, 0, 0, 0); 304 if ((pins & mask) != mask) 305 qib_dev_err(dd, "GPIO pins not at rest: %d\n", 306 pins & mask); 307 /* Drop SDA to issue START */ 308 udelay(1); /* Guarantee .6 uSec setup */ 309 sda_out(dd, 0); 310 udelay(1); /* Guarantee .6 uSec hold */ 311 /* At this point, SCL is high, SDA low. Raise SDA for STOP */ 312 sda_out(dd, 1); 313 udelay(TWSI_BUF_WAIT_USEC); 314 } 315 316 return !was_high; 317} 318 319#define QIB_TWSI_START 0x100 320#define QIB_TWSI_STOP 0x200 321 322/* Write byte to TWSI, optionally prefixed with START or suffixed with 323 * STOP. 324 * returns 0 if OK (ACK received), else != 0 325 */ 326static int qib_twsi_wr(struct qib_devdata *dd, int data, int flags) 327{ 328 int ret = 1; 329 if (flags & QIB_TWSI_START) 330 start_seq(dd); 331 332 ret = wr_byte(dd, data); /* Leaves SCL low (from i2c_ackrcv()) */ 333 334 if (flags & QIB_TWSI_STOP) 335 stop_cmd(dd); 336 return ret; 337} 338 339/* Added functionality for IBA7220-based cards */ 340#define QIB_TEMP_DEV 0x98 341 342/* 343 * qib_twsi_blk_rd 344 * Formerly called qib_eeprom_internal_read, and only used for eeprom, 345 * but now the general interface for data transfer from twsi devices. 346 * One vestige of its former role is that it recognizes a device 347 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part, 348 * which responded to all TWSI device codes, interpreting them as 349 * address within device. On all other devices found on board handled by 350 * this driver, the device is followed by a one-byte "address" which selects 351 * the "register" or "offset" within the device from which data should 352 * be read. 353 */ 354int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, 355 void *buffer, int len) 356{ 357 int ret; 358 u8 *bp = buffer; 359 360 ret = 1; 361 362 if (dev == QIB_TWSI_NO_DEV) { 363 /* legacy not-really-I2C */ 364 addr = (addr << 1) | READ_CMD; 365 ret = qib_twsi_wr(dd, addr, QIB_TWSI_START); 366 } else { 367 /* Actual I2C */ 368 ret = qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START); 369 if (ret) { 370 stop_cmd(dd); 371 ret = 1; 372 goto bail; 373 } 374 /* 375 * SFF spec claims we do _not_ stop after the addr 376 * but simply issue a start with the "read" dev-addr. 377 * Since we are implicitely waiting for ACK here, 378 * we need t_buf (nominally 20uSec) before that start, 379 * and cannot rely on the delay built in to the STOP 380 */ 381 ret = qib_twsi_wr(dd, addr, 0); 382 udelay(TWSI_BUF_WAIT_USEC); 383 384 if (ret) { 385 qib_dev_err(dd, 386 "Failed to write interface read addr %02X\n", 387 addr); 388 ret = 1; 389 goto bail; 390 } 391 ret = qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START); 392 } 393 if (ret) { 394 stop_cmd(dd); 395 ret = 1; 396 goto bail; 397 } 398 399 /* 400 * block devices keeps clocking data out as long as we ack, 401 * automatically incrementing the address. Some have "pages" 402 * whose boundaries will not be crossed, but the handling 403 * of these is left to the caller, who is in a better 404 * position to know. 405 */ 406 while (len-- > 0) { 407 /* 408 * Get and store data, sending ACK if length remaining, 409 * else STOP 410 */ 411 *bp++ = rd_byte(dd, !len); 412 } 413 414 ret = 0; 415 416bail: 417 return ret; 418} 419 420/* 421 * qib_twsi_blk_wr 422 * Formerly called qib_eeprom_internal_write, and only used for eeprom, 423 * but now the general interface for data transfer to twsi devices. 424 * One vestige of its former role is that it recognizes a device 425 * QIB_TWSI_NO_DEV and does the correct operation for the legacy part, 426 * which responded to all TWSI device codes, interpreting them as 427 * address within device. On all other devices found on board handled by 428 * this driver, the device is followed by a one-byte "address" which selects 429 * the "register" or "offset" within the device to which data should 430 * be written. 431 */ 432int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr, 433 const void *buffer, int len) 434{ 435 int sub_len; 436 const u8 *bp = buffer; 437 int max_wait_time, i; 438 int ret; 439 ret = 1; 440 441 while (len > 0) { 442 if (dev == QIB_TWSI_NO_DEV) { 443 if (qib_twsi_wr(dd, (addr << 1) | WRITE_CMD, 444 QIB_TWSI_START)) { 445 goto failed_write; 446 } 447 } else { 448 /* Real I2C */ 449 if (qib_twsi_wr(dd, dev | WRITE_CMD, QIB_TWSI_START)) 450 goto failed_write; 451 ret = qib_twsi_wr(dd, addr, 0); 452 if (ret) { 453 qib_dev_err(dd, 454 "Failed to write interface write addr %02X\n", 455 addr); 456 goto failed_write; 457 } 458 } 459 460 sub_len = min(len, 4); 461 addr += sub_len; 462 len -= sub_len; 463 464 for (i = 0; i < sub_len; i++) 465 if (qib_twsi_wr(dd, *bp++, 0)) 466 goto failed_write; 467 468 stop_cmd(dd); 469 470 /* 471 * Wait for write complete by waiting for a successful 472 * read (the chip replies with a zero after the write 473 * cmd completes, and before it writes to the eeprom. 474 * The startcmd for the read will fail the ack until 475 * the writes have completed. We do this inline to avoid 476 * the debug prints that are in the real read routine 477 * if the startcmd fails. 478 * We also use the proper device address, so it doesn't matter 479 * whether we have real eeprom_dev. Legacy likes any address. 480 */ 481 max_wait_time = 100; 482 while (qib_twsi_wr(dd, dev | READ_CMD, QIB_TWSI_START)) { 483 stop_cmd(dd); 484 if (!--max_wait_time) 485 goto failed_write; 486 } 487 /* now read (and ignore) the resulting byte */ 488 rd_byte(dd, 1); 489 } 490 491 ret = 0; 492 goto bail; 493 494failed_write: 495 stop_cmd(dd); 496 ret = 1; 497 498bail: 499 return ret; 500} 501