1d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* 2d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * STMicroelectronics accelerometers driver 3d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * 4d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * Copyright 2012-2013 STMicroelectronics Inc. 5d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * 6d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * Denis Ciocca <denis.ciocca@st.com> 7d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * 8d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca * Licensed under the GPL-2. 9d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca */ 10d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 11d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/kernel.h> 12d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/module.h> 13d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/slab.h> 14d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/errno.h> 15d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/types.h> 16d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/mutex.h> 17d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/interrupt.h> 18d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/i2c.h> 19d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/gpio.h> 20d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/irq.h> 21d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/iio/iio.h> 22d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/iio/sysfs.h> 238ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#include <linux/iio/trigger.h> 24d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/iio/buffer.h> 25d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 26d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include <linux/iio/common/st_sensors.h> 27d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#include "st_accel.h" 28d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 29607a568ab69c5ac345a286267a27294888f8bb5fDenis CIOCCA#define ST_ACCEL_NUMBER_DATA_CHANNELS 3 30607a568ab69c5ac345a286267a27294888f8bb5fDenis CIOCCA 31d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* DEFAULT VALUE FOR SENSORS */ 32d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_DEFAULT_OUT_X_L_ADDR 0x28 33d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_DEFAULT_OUT_Y_L_ADDR 0x2a 34d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_DEFAULT_OUT_Z_L_ADDR 0x2c 35d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 36d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* FULLSCALE */ 37d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_FS_AVL_2G 2 38d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_FS_AVL_4G 4 39d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_FS_AVL_6G 6 40d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_FS_AVL_8G 8 41d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_FS_AVL_16G 16 42d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 43d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* CUSTOM VALUES FOR SENSOR 1 */ 44d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_WAI_EXP 0x33 45d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_ADDR 0x20 46d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_MASK 0xf0 47d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_1HZ_VAL 0x01 48d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_10HZ_VAL 0x02 49d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_25HZ_VAL 0x03 50d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_50HZ_VAL 0x04 51d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_100HZ_VAL 0x05 52d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_200HZ_VAL 0x06 53d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_400HZ_VAL 0x07 54d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_ODR_AVL_1600HZ_VAL 0x08 55d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_ADDR 0x23 56d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_MASK 0x30 57d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_2_VAL 0x00 58d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_4_VAL 0x01 59d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_8_VAL 0x02 60d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_16_VAL 0x03 61d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000) 62d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000) 63d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_8_GAIN IIO_G_TO_M_S_2(4000) 64d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_FS_AVL_16_GAIN IIO_G_TO_M_S_2(12000) 65d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_BDU_ADDR 0x23 66d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_BDU_MASK 0x80 67d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_DRDY_IRQ_ADDR 0x22 6823cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_1_DRDY_IRQ_INT1_MASK 0x10 6923cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_1_DRDY_IRQ_INT2_MASK 0x08 70d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_1_MULTIREAD_BIT true 71d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 72d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* CUSTOM VALUES FOR SENSOR 2 */ 73d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_WAI_EXP 0x32 74d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_ADDR 0x20 75d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_MASK 0x18 76d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_AVL_50HZ_VAL 0x00 77d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_AVL_100HZ_VAL 0x01 78d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_AVL_400HZ_VAL 0x02 79d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_ODR_AVL_1000HZ_VAL 0x03 80d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_PW_ADDR 0x20 81d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_PW_MASK 0xe0 82d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_ADDR 0x23 83d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_MASK 0x30 84d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_2_VAL 0X00 85d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_4_VAL 0X01 86d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_8_VAL 0x03 87d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000) 88d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000) 89d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_FS_AVL_8_GAIN IIO_G_TO_M_S_2(3900) 90d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_BDU_ADDR 0x23 91d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_BDU_MASK 0x80 92d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_DRDY_IRQ_ADDR 0x22 9323cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_2_DRDY_IRQ_INT1_MASK 0x02 9423cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_2_DRDY_IRQ_INT2_MASK 0x10 95d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_2_MULTIREAD_BIT true 96d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 97d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca/* CUSTOM VALUES FOR SENSOR 3 */ 98d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_WAI_EXP 0x40 99d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_ADDR 0x20 100d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_MASK 0xf0 101d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_3HZ_VAL 0x01 102d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_6HZ_VAL 0x02 103d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_12HZ_VAL 0x03 104d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_25HZ_VAL 0x04 105d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_50HZ_VAL 0x05 106d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_100HZ_VAL 0x06 107d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_200HZ_VAL 0x07 108d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_400HZ_VAL 0x08 109d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_800HZ_VAL 0x09 110d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_ODR_AVL_1600HZ_VAL 0x0a 111d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_ADDR 0x24 112d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_MASK 0x38 113d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_2_VAL 0X00 114d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_4_VAL 0X01 115d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_6_VAL 0x02 116d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_8_VAL 0x03 117d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_16_VAL 0x04 118d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_2_GAIN IIO_G_TO_M_S_2(61) 119d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_4_GAIN IIO_G_TO_M_S_2(122) 120d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_6_GAIN IIO_G_TO_M_S_2(183) 121d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_8_GAIN IIO_G_TO_M_S_2(244) 122d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_FS_AVL_16_GAIN IIO_G_TO_M_S_2(732) 123d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_BDU_ADDR 0x20 124d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_BDU_MASK 0x08 125d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_DRDY_IRQ_ADDR 0x23 12623cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_3_DRDY_IRQ_INT1_MASK 0x80 12723cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA#define ST_ACCEL_3_DRDY_IRQ_INT2_MASK 0x00 128d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_IG1_EN_ADDR 0x23 129d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_IG1_EN_MASK 0x08 130d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca#define ST_ACCEL_3_MULTIREAD_BIT false 131d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 132d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct iio_chan_spec st_accel_12bit_channels[] = { 133762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 134762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 135762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 12, 16, 136762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_X_L_ADDR), 137762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 138762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 139762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 12, 16, 140762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_Y_L_ADDR), 141762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 142762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 143762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 12, 16, 144762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_Z_L_ADDR), 145d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca IIO_CHAN_SOFT_TIMESTAMP(3) 146d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 147d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 148d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct iio_chan_spec st_accel_16bit_channels[] = { 149762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 150762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 151762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 16, 16, 152762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_X_L_ADDR), 153762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 154762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 155762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 16, 16, 156762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_Y_L_ADDR), 157762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_LSM_CHANNELS(IIO_ACCEL, 158762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), 159762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 16, 16, 160762011d6193f8b9af9b491ded87dde3221d0600aDenis CIOCCA ST_ACCEL_DEFAULT_OUT_Z_L_ADDR), 161d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca IIO_CHAN_SOFT_TIMESTAMP(3) 162d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 163d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 164d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct st_sensors st_accel_sensors[] = { 165d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 166d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .wai = ST_ACCEL_1_WAI_EXP, 167d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .sensors_supported = { 168d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = LIS3DH_ACCEL_DEV_NAME, 169d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [1] = LSM303DLHC_ACCEL_DEV_NAME, 170d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [2] = LSM330D_ACCEL_DEV_NAME, 171d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [3] = LSM330DL_ACCEL_DEV_NAME, 172d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [4] = LSM330DLC_ACCEL_DEV_NAME, 173d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 174d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .ch = (struct iio_chan_spec *)st_accel_12bit_channels, 175d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr = { 176d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_1_ODR_ADDR, 177d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_1_ODR_MASK, 178d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr_avl = { 179d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 1, ST_ACCEL_1_ODR_AVL_1HZ_VAL, }, 180d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 10, ST_ACCEL_1_ODR_AVL_10HZ_VAL, }, 181d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 25, ST_ACCEL_1_ODR_AVL_25HZ_VAL, }, 182d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 50, ST_ACCEL_1_ODR_AVL_50HZ_VAL, }, 183d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 100, ST_ACCEL_1_ODR_AVL_100HZ_VAL, }, 184d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 200, ST_ACCEL_1_ODR_AVL_200HZ_VAL, }, 185d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 400, ST_ACCEL_1_ODR_AVL_400HZ_VAL, }, 186d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 1600, ST_ACCEL_1_ODR_AVL_1600HZ_VAL, }, 187d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 188d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 189d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .pw = { 190d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_1_ODR_ADDR, 191d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_1_ODR_MASK, 192d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, 193d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 194d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .enable_axis = { 195d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_SENSORS_DEFAULT_AXIS_ADDR, 196d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_SENSORS_DEFAULT_AXIS_MASK, 197d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 198d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs = { 199d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_1_FS_ADDR, 200d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_1_FS_MASK, 201d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs_avl = { 202d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = { 203d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_2G, 204d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_1_FS_AVL_2_VAL, 205d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_1_FS_AVL_2_GAIN, 206d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 207d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [1] = { 208d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_4G, 209d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_1_FS_AVL_4_VAL, 210d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_1_FS_AVL_4_GAIN, 211d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 212d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [2] = { 213d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_8G, 214d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_1_FS_AVL_8_VAL, 215d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_1_FS_AVL_8_GAIN, 216d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 217d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [3] = { 218d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_16G, 219d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_1_FS_AVL_16_VAL, 220d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_1_FS_AVL_16_GAIN, 221d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 222d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 223d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 224d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bdu = { 225d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_1_BDU_ADDR, 226d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_1_BDU_MASK, 227d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 228d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .drdy_irq = { 229d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_1_DRDY_IRQ_ADDR, 23023cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int1 = ST_ACCEL_1_DRDY_IRQ_INT1_MASK, 23123cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int2 = ST_ACCEL_1_DRDY_IRQ_INT2_MASK, 232d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 233d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .multi_read_bit = ST_ACCEL_1_MULTIREAD_BIT, 234d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bootime = 2, 235d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 236d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 237d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .wai = ST_ACCEL_2_WAI_EXP, 238d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .sensors_supported = { 239d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = LIS331DLH_ACCEL_DEV_NAME, 240d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [1] = LSM303DL_ACCEL_DEV_NAME, 241d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [2] = LSM303DLH_ACCEL_DEV_NAME, 242d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [3] = LSM303DLM_ACCEL_DEV_NAME, 243d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 244d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .ch = (struct iio_chan_spec *)st_accel_12bit_channels, 245d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr = { 246d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_2_ODR_ADDR, 247d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_2_ODR_MASK, 248d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr_avl = { 249d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 50, ST_ACCEL_2_ODR_AVL_50HZ_VAL, }, 250d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 100, ST_ACCEL_2_ODR_AVL_100HZ_VAL, }, 251d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 400, ST_ACCEL_2_ODR_AVL_400HZ_VAL, }, 252d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 1000, ST_ACCEL_2_ODR_AVL_1000HZ_VAL, }, 253d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 254d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 255d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .pw = { 256d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_2_PW_ADDR, 257d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_2_PW_MASK, 258d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE, 259d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, 260d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 261d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .enable_axis = { 262d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_SENSORS_DEFAULT_AXIS_ADDR, 263d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_SENSORS_DEFAULT_AXIS_MASK, 264d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 265d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs = { 266d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_2_FS_ADDR, 267d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_2_FS_MASK, 268d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs_avl = { 269d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = { 270d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_2G, 271d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_2_FS_AVL_2_VAL, 272d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_2_FS_AVL_2_GAIN, 273d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 274d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [1] = { 275d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_4G, 276d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_2_FS_AVL_4_VAL, 277d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_2_FS_AVL_4_GAIN, 278d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 279d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [2] = { 280d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_8G, 281d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_2_FS_AVL_8_VAL, 282d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_2_FS_AVL_8_GAIN, 283d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 284d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 285d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 286d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bdu = { 287d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_2_BDU_ADDR, 288d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_2_BDU_MASK, 289d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 290d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .drdy_irq = { 291d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_2_DRDY_IRQ_ADDR, 29223cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int1 = ST_ACCEL_2_DRDY_IRQ_INT1_MASK, 29323cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int2 = ST_ACCEL_2_DRDY_IRQ_INT2_MASK, 294d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 295d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .multi_read_bit = ST_ACCEL_2_MULTIREAD_BIT, 296d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bootime = 2, 297d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 298d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 299d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .wai = ST_ACCEL_3_WAI_EXP, 300d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .sensors_supported = { 301d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = LSM330_ACCEL_DEV_NAME, 302d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 303d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .ch = (struct iio_chan_spec *)st_accel_16bit_channels, 304d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr = { 305d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_3_ODR_ADDR, 306d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_3_ODR_MASK, 307d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .odr_avl = { 308d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 3, ST_ACCEL_3_ODR_AVL_3HZ_VAL }, 309d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 6, ST_ACCEL_3_ODR_AVL_6HZ_VAL, }, 310d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 12, ST_ACCEL_3_ODR_AVL_12HZ_VAL, }, 311d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 25, ST_ACCEL_3_ODR_AVL_25HZ_VAL, }, 312d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 50, ST_ACCEL_3_ODR_AVL_50HZ_VAL, }, 313d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 100, ST_ACCEL_3_ODR_AVL_100HZ_VAL, }, 314d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 200, ST_ACCEL_3_ODR_AVL_200HZ_VAL, }, 315d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 400, ST_ACCEL_3_ODR_AVL_400HZ_VAL, }, 316d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 800, ST_ACCEL_3_ODR_AVL_800HZ_VAL, }, 317d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca { 1600, ST_ACCEL_3_ODR_AVL_1600HZ_VAL, }, 318d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 319d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 320d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .pw = { 321d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_3_ODR_ADDR, 322d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_3_ODR_MASK, 323d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE, 324d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 325d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .enable_axis = { 326d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_SENSORS_DEFAULT_AXIS_ADDR, 327d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_SENSORS_DEFAULT_AXIS_MASK, 328d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 329d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs = { 330d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_3_FS_ADDR, 331d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_3_FS_MASK, 332d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .fs_avl = { 333d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [0] = { 334d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_2G, 335d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_3_FS_AVL_2_VAL, 336d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_3_FS_AVL_2_GAIN, 337d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 338d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [1] = { 339d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_4G, 340d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_3_FS_AVL_4_VAL, 341d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_3_FS_AVL_4_GAIN, 342d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 343d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [2] = { 344d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_6G, 345d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_3_FS_AVL_6_VAL, 346d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_3_FS_AVL_6_GAIN, 347d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 348d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [3] = { 349d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_8G, 350d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_3_FS_AVL_8_VAL, 351d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_3_FS_AVL_8_GAIN, 352d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 353d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca [4] = { 354d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .num = ST_ACCEL_FS_AVL_16G, 355d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .value = ST_ACCEL_3_FS_AVL_16_VAL, 356d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .gain = ST_ACCEL_3_FS_AVL_16_GAIN, 357d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 358d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 359d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 360d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bdu = { 361d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_3_BDU_ADDR, 362d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .mask = ST_ACCEL_3_BDU_MASK, 363d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 364d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .drdy_irq = { 365d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .addr = ST_ACCEL_3_DRDY_IRQ_ADDR, 36623cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int1 = ST_ACCEL_3_DRDY_IRQ_INT1_MASK, 36723cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA .mask_int2 = ST_ACCEL_3_DRDY_IRQ_INT2_MASK, 368d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .ig1 = { 369d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .en_addr = ST_ACCEL_3_IG1_EN_ADDR, 370d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .en_mask = ST_ACCEL_3_IG1_EN_MASK, 371d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 372d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 373d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .multi_read_bit = ST_ACCEL_3_MULTIREAD_BIT, 374d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .bootime = 2, 375d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca }, 376d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 377d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 378d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic int st_accel_read_raw(struct iio_dev *indio_dev, 379d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca struct iio_chan_spec const *ch, int *val, 380d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca int *val2, long mask) 381d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca{ 382d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca int err; 383d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca struct st_sensor_data *adata = iio_priv(indio_dev); 384d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 385d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca switch (mask) { 386d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca case IIO_CHAN_INFO_RAW: 387d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca err = st_sensors_read_info_raw(indio_dev, ch, val); 388d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca if (err < 0) 389d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca goto read_error; 390d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 391d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return IIO_VAL_INT; 392d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca case IIO_CHAN_INFO_SCALE: 393d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca *val = 0; 394d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca *val2 = adata->current_fullscale->gain; 395d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return IIO_VAL_INT_PLUS_MICRO; 3962d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron case IIO_CHAN_INFO_SAMP_FREQ: 3972d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron *val = adata->odr; 3982d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron return IIO_VAL_INT; 399d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca default: 400d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return -EINVAL; 401d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca } 402d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 403d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccaread_error: 404d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return err; 405d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca} 406d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 407d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic int st_accel_write_raw(struct iio_dev *indio_dev, 408d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca struct iio_chan_spec const *chan, int val, int val2, long mask) 409d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca{ 410d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca int err; 411d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 412d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca switch (mask) { 413d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca case IIO_CHAN_INFO_SCALE: 414d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca err = st_sensors_set_fullscale_by_gain(indio_dev, val2); 415d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca break; 4162d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron case IIO_CHAN_INFO_SAMP_FREQ: 4172d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron if (val2) 4182d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron return -EINVAL; 4192d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron mutex_lock(&indio_dev->mlock); 4202d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron err = st_sensors_set_odr(indio_dev, val); 4212d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron mutex_unlock(&indio_dev->mlock); 4222d239c9e92087d5f4f667371ae350db9f76e3191Jonathan Cameron return err; 423d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca default: 424d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return -EINVAL; 425d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca } 426d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 427d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return err; 428d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca} 429d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 430d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic ST_SENSORS_DEV_ATTR_SAMP_FREQ_AVAIL(); 431d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic ST_SENSORS_DEV_ATTR_SCALE_AVAIL(in_accel_scale_available); 432d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 433d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic struct attribute *st_accel_attributes[] = { 434d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 435d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 436d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca NULL, 437d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 438d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 439d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct attribute_group st_accel_attribute_group = { 440d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .attrs = st_accel_attributes, 441d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 442d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 443d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct iio_info accel_info = { 444d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .driver_module = THIS_MODULE, 445d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .attrs = &st_accel_attribute_group, 446d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .read_raw = &st_accel_read_raw, 447d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .write_raw = &st_accel_write_raw, 448d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 449d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 4508ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#ifdef CONFIG_IIO_TRIGGER 451d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccastatic const struct iio_trigger_ops st_accel_trigger_ops = { 452d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .owner = THIS_MODULE, 453d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca .set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE, 454d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca}; 4558ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#define ST_ACCEL_TRIGGER_OPS (&st_accel_trigger_ops) 4568ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#else 4578ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#define ST_ACCEL_TRIGGER_OPS NULL 4588ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron#endif 459d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 46023cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCAint st_accel_common_probe(struct iio_dev *indio_dev, 46123cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA struct st_sensors_platform_data *plat_data) 462d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca{ 463d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca struct st_sensor_data *adata = iio_priv(indio_dev); 464cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones int irq = adata->get_irq_data_ready(indio_dev); 465cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones int err; 466d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 467d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca indio_dev->modes = INDIO_DIRECT_MODE; 468d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca indio_dev->info = &accel_info; 469d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 470ea7e586bdd331fd6fba2b6f9fd3777928c2814d8Linus Walleij st_sensors_power_enable(indio_dev); 471ea7e586bdd331fd6fba2b6f9fd3777928c2814d8Linus Walleij 472d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca err = st_sensors_check_device_support(indio_dev, 473d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca ARRAY_SIZE(st_accel_sensors), st_accel_sensors); 474d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca if (err < 0) 475cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones return err; 476d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 477607a568ab69c5ac345a286267a27294888f8bb5fDenis CIOCCA adata->num_data_channels = ST_ACCEL_NUMBER_DATA_CHANNELS; 478d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca adata->multiread_bit = adata->sensor->multi_read_bit; 479d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca indio_dev->channels = adata->sensor->ch; 480d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca indio_dev->num_channels = ST_SENSORS_NUMBER_ALL_CHANNELS; 481d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 482d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca adata->current_fullscale = (struct st_sensor_fullscale_avl *) 483d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca &adata->sensor->fs.fs_avl[0]; 484d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca adata->odr = adata->sensor->odr.odr_avl[0].hz; 485d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 48623cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA if (!plat_data) 48723cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA plat_data = 48823cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA (struct st_sensors_platform_data *)&default_accel_pdata; 48923cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA 49023cde4d65cc7d11e2048d2b240cdf13927ac50d0Denis CIOCCA err = st_sensors_init_sensor(indio_dev, plat_data); 491d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca if (err < 0) 492cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones return err; 493d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 494e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA err = st_accel_allocate_ring(indio_dev); 495e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA if (err < 0) 496e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA return err; 497d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 498e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA if (irq > 0) { 499d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca err = st_sensors_allocate_trigger(indio_dev, 5008ce4a56a52bf566659768a9e46e759e7cd5f33d9Jonathan Cameron ST_ACCEL_TRIGGER_OPS); 501d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca if (err < 0) 502d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca goto st_accel_probe_trigger_error; 503d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca } 504d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 505d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca err = iio_device_register(indio_dev); 506d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca if (err) 507d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca goto st_accel_device_register_error; 508d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 5094f544ced19b3d300ac11414b68a676a2c42f6d06Linus Walleij dev_info(&indio_dev->dev, "registered accelerometer %s\n", 5104f544ced19b3d300ac11414b68a676a2c42f6d06Linus Walleij indio_dev->name); 5114f544ced19b3d300ac11414b68a676a2c42f6d06Linus Walleij 512cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones return 0; 513d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 514d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccast_accel_device_register_error: 515cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones if (irq > 0) 516d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca st_sensors_deallocate_trigger(indio_dev); 517d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccast_accel_probe_trigger_error: 518e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA st_accel_deallocate_ring(indio_dev); 519cf4dd430c4cfeb2b41e2de43f3463d0a3dba2463Lee Jones 520d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca return err; 521d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca} 522d62511689de5d34d3a07c43db1f46a234bb77b5fDenis CioccaEXPORT_SYMBOL(st_accel_common_probe); 523d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 524d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Cioccavoid st_accel_common_remove(struct iio_dev *indio_dev) 525d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca{ 526d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca struct st_sensor_data *adata = iio_priv(indio_dev); 527d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 528ea7e586bdd331fd6fba2b6f9fd3777928c2814d8Linus Walleij st_sensors_power_disable(indio_dev); 529ea7e586bdd331fd6fba2b6f9fd3777928c2814d8Linus Walleij 530d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca iio_device_unregister(indio_dev); 531e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA if (adata->get_irq_data_ready(indio_dev) > 0) 532d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca st_sensors_deallocate_trigger(indio_dev); 533e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA 534e21e254e49831075f7fb13d9dbe33defb00a3d3dDenis CIOCCA st_accel_deallocate_ring(indio_dev); 535d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca} 536d62511689de5d34d3a07c43db1f46a234bb77b5fDenis CioccaEXPORT_SYMBOL(st_accel_common_remove); 537d62511689de5d34d3a07c43db1f46a234bb77b5fDenis Ciocca 538d62511689de5d34d3a07c43db1f46a234bb77b5fDenis CioccaMODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); 539d62511689de5d34d3a07c43db1f46a234bb77b5fDenis CioccaMODULE_DESCRIPTION("STMicroelectronics accelerometers driver"); 540d62511689de5d34d3a07c43db1f46a234bb77b5fDenis CioccaMODULE_LICENSE("GPL v2"); 541