1/* 2* Copyright (C) 2012 Invensense, Inc. 3* 4* This software is licensed under the terms of the GNU General Public 5* License version 2, as published by the Free Software Foundation, and 6* may be copied, distributed, and modified under those terms. 7* 8* This program is distributed in the hope that it will be useful, 9* but WITHOUT ANY WARRANTY; without even the implied warranty of 10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11* GNU General Public License for more details. 12*/ 13#include <linux/i2c.h> 14#include <linux/kfifo.h> 15#include <linux/spinlock.h> 16#include <linux/iio/iio.h> 17#include <linux/iio/buffer.h> 18#include <linux/iio/sysfs.h> 19#include <linux/iio/kfifo_buf.h> 20#include <linux/iio/trigger.h> 21#include <linux/iio/triggered_buffer.h> 22#include <linux/iio/trigger_consumer.h> 23#include <linux/platform_data/invensense_mpu6050.h> 24 25/** 26 * struct inv_mpu6050_reg_map - Notable registers. 27 * @sample_rate_div: Divider applied to gyro output rate. 28 * @lpf: Configures internal low pass filter. 29 * @user_ctrl: Enables/resets the FIFO. 30 * @fifo_en: Determines which data will appear in FIFO. 31 * @gyro_config: gyro config register. 32 * @accl_config: accel config register 33 * @fifo_count_h: Upper byte of FIFO count. 34 * @fifo_r_w: FIFO register. 35 * @raw_gyro: Address of first gyro register. 36 * @raw_accl: Address of first accel register. 37 * @temperature: temperature register 38 * @int_enable: Interrupt enable register. 39 * @pwr_mgmt_1: Controls chip's power state and clock source. 40 * @pwr_mgmt_2: Controls power state of individual sensors. 41 */ 42struct inv_mpu6050_reg_map { 43 u8 sample_rate_div; 44 u8 lpf; 45 u8 user_ctrl; 46 u8 fifo_en; 47 u8 gyro_config; 48 u8 accl_config; 49 u8 fifo_count_h; 50 u8 fifo_r_w; 51 u8 raw_gyro; 52 u8 raw_accl; 53 u8 temperature; 54 u8 int_enable; 55 u8 pwr_mgmt_1; 56 u8 pwr_mgmt_2; 57}; 58 59/*device enum */ 60enum inv_devices { 61 INV_MPU6050, 62 INV_MPU6500, 63 INV_NUM_PARTS 64}; 65 66/** 67 * struct inv_mpu6050_chip_config - Cached chip configuration data. 68 * @fsr: Full scale range. 69 * @lpf: Digital low pass filter frequency. 70 * @accl_fs: accel full scale range. 71 * @enable: master enable state. 72 * @accl_fifo_enable: enable accel data output 73 * @gyro_fifo_enable: enable gyro data output 74 * @fifo_rate: FIFO update rate. 75 */ 76struct inv_mpu6050_chip_config { 77 unsigned int fsr:2; 78 unsigned int lpf:3; 79 unsigned int accl_fs:2; 80 unsigned int enable:1; 81 unsigned int accl_fifo_enable:1; 82 unsigned int gyro_fifo_enable:1; 83 u16 fifo_rate; 84}; 85 86/** 87 * struct inv_mpu6050_hw - Other important hardware information. 88 * @num_reg: Number of registers on device. 89 * @name: name of the chip. 90 * @reg: register map of the chip. 91 * @config: configuration of the chip. 92 */ 93struct inv_mpu6050_hw { 94 u8 num_reg; 95 u8 *name; 96 const struct inv_mpu6050_reg_map *reg; 97 const struct inv_mpu6050_chip_config *config; 98}; 99 100/* 101 * struct inv_mpu6050_state - Driver state variables. 102 * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. 103 * @trig: IIO trigger. 104 * @chip_config: Cached attribute information. 105 * @reg: Map of important registers. 106 * @hw: Other hardware-specific information. 107 * @chip_type: chip type. 108 * @time_stamp_lock: spin lock to time stamp. 109 * @client: i2c client handle. 110 * @plat_data: platform data. 111 * @timestamps: kfifo queue to store time stamp. 112 */ 113struct inv_mpu6050_state { 114#define TIMESTAMP_FIFO_SIZE 16 115 struct iio_trigger *trig; 116 struct inv_mpu6050_chip_config chip_config; 117 const struct inv_mpu6050_reg_map *reg; 118 const struct inv_mpu6050_hw *hw; 119 enum inv_devices chip_type; 120 spinlock_t time_stamp_lock; 121 struct i2c_client *client; 122 struct inv_mpu6050_platform_data plat_data; 123 DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); 124}; 125 126/*register and associated bit definition*/ 127#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 128#define INV_MPU6050_REG_CONFIG 0x1A 129#define INV_MPU6050_REG_GYRO_CONFIG 0x1B 130#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 131 132#define INV_MPU6050_REG_FIFO_EN 0x23 133#define INV_MPU6050_BIT_ACCEL_OUT 0x08 134#define INV_MPU6050_BITS_GYRO_OUT 0x70 135 136#define INV_MPU6050_REG_INT_ENABLE 0x38 137#define INV_MPU6050_BIT_DATA_RDY_EN 0x01 138#define INV_MPU6050_BIT_DMP_INT_EN 0x02 139 140#define INV_MPU6050_REG_RAW_ACCEL 0x3B 141#define INV_MPU6050_REG_TEMPERATURE 0x41 142#define INV_MPU6050_REG_RAW_GYRO 0x43 143 144#define INV_MPU6050_REG_USER_CTRL 0x6A 145#define INV_MPU6050_BIT_FIFO_RST 0x04 146#define INV_MPU6050_BIT_DMP_RST 0x08 147#define INV_MPU6050_BIT_I2C_MST_EN 0x20 148#define INV_MPU6050_BIT_FIFO_EN 0x40 149#define INV_MPU6050_BIT_DMP_EN 0x80 150 151#define INV_MPU6050_REG_PWR_MGMT_1 0x6B 152#define INV_MPU6050_BIT_H_RESET 0x80 153#define INV_MPU6050_BIT_SLEEP 0x40 154#define INV_MPU6050_BIT_CLK_MASK 0x7 155 156#define INV_MPU6050_REG_PWR_MGMT_2 0x6C 157#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 158#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 159 160#define INV_MPU6050_REG_FIFO_COUNT_H 0x72 161#define INV_MPU6050_REG_FIFO_R_W 0x74 162 163#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 164#define INV_MPU6050_FIFO_COUNT_BYTE 2 165#define INV_MPU6050_FIFO_THRESHOLD 500 166#define INV_MPU6050_POWER_UP_TIME 100 167#define INV_MPU6050_TEMP_UP_TIME 100 168#define INV_MPU6050_SENSOR_UP_TIME 30 169#define INV_MPU6050_REG_UP_TIME 5 170 171#define INV_MPU6050_TEMP_OFFSET 12421 172#define INV_MPU6050_TEMP_SCALE 2941 173#define INV_MPU6050_MAX_GYRO_FS_PARAM 3 174#define INV_MPU6050_MAX_ACCL_FS_PARAM 3 175#define INV_MPU6050_THREE_AXIS 3 176#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 177#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 178 179/* 6 + 6 round up and plus 8 */ 180#define INV_MPU6050_OUTPUT_DATA_SIZE 24 181 182/* init parameters */ 183#define INV_MPU6050_INIT_FIFO_RATE 50 184#define INV_MPU6050_TIME_STAMP_TOR 5 185#define INV_MPU6050_MAX_FIFO_RATE 1000 186#define INV_MPU6050_MIN_FIFO_RATE 4 187#define INV_MPU6050_ONE_K_HZ 1000 188 189/* scan element definition */ 190enum inv_mpu6050_scan { 191 INV_MPU6050_SCAN_ACCL_X, 192 INV_MPU6050_SCAN_ACCL_Y, 193 INV_MPU6050_SCAN_ACCL_Z, 194 INV_MPU6050_SCAN_GYRO_X, 195 INV_MPU6050_SCAN_GYRO_Y, 196 INV_MPU6050_SCAN_GYRO_Z, 197 INV_MPU6050_SCAN_TIMESTAMP, 198}; 199 200enum inv_mpu6050_filter_e { 201 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 202 INV_MPU6050_FILTER_188HZ, 203 INV_MPU6050_FILTER_98HZ, 204 INV_MPU6050_FILTER_42HZ, 205 INV_MPU6050_FILTER_20HZ, 206 INV_MPU6050_FILTER_10HZ, 207 INV_MPU6050_FILTER_5HZ, 208 INV_MPU6050_FILTER_2100HZ_NOLPF, 209 NUM_MPU6050_FILTER 210}; 211 212/* IIO attribute address */ 213enum INV_MPU6050_IIO_ATTR_ADDR { 214 ATTR_GYRO_MATRIX, 215 ATTR_ACCL_MATRIX, 216}; 217 218enum inv_mpu6050_accl_fs_e { 219 INV_MPU6050_FS_02G = 0, 220 INV_MPU6050_FS_04G, 221 INV_MPU6050_FS_08G, 222 INV_MPU6050_FS_16G, 223 NUM_ACCL_FSR 224}; 225 226enum inv_mpu6050_fsr_e { 227 INV_MPU6050_FSR_250DPS = 0, 228 INV_MPU6050_FSR_500DPS, 229 INV_MPU6050_FSR_1000DPS, 230 INV_MPU6050_FSR_2000DPS, 231 NUM_MPU6050_FSR 232}; 233 234enum inv_mpu6050_clock_sel_e { 235 INV_CLK_INTERNAL = 0, 236 INV_CLK_PLL, 237 NUM_CLK 238}; 239 240irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); 241irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 242int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev); 243void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st); 244int inv_reset_fifo(struct iio_dev *indio_dev); 245int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 246int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 247int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 248