1/* 2 * scc2698.h 3 * 4 * driver for the IPOCTAL boards 5 * 6 * Copyright (C) 2009-2012 CERN (www.cern.ch) 7 * Author: Nicolas Serafini, EIC2 SA 8 * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the Free 12 * Software Foundation; version 2 of the License. 13 */ 14 15#ifndef SCC2698_H_ 16#define SCC2698_H_ 17 18/* 19 * union scc2698_channel - Channel access to scc2698 IO 20 * 21 * dn value are only spacer. 22 * 23 */ 24union scc2698_channel { 25 struct { 26 u8 d0, mr; /* Mode register 1/2*/ 27 u8 d1, sr; /* Status register */ 28 u8 d2, r1; /* reserved */ 29 u8 d3, rhr; /* Receive holding register (R) */ 30 u8 junk[8]; /* other crap for block control */ 31 } __packed r; /* Read access */ 32 struct { 33 u8 d0, mr; /* Mode register 1/2 */ 34 u8 d1, csr; /* Clock select register */ 35 u8 d2, cr; /* Command register */ 36 u8 d3, thr; /* Transmit holding register */ 37 u8 junk[8]; /* other crap for block control */ 38 } __packed w; /* Write access */ 39}; 40 41/* 42 * union scc2698_block - Block access to scc2698 IO 43 * 44 * The scc2698 contain 4 block. 45 * Each block containt two channel a and b. 46 * dn value are only spacer. 47 * 48 */ 49union scc2698_block { 50 struct { 51 u8 d0, mra; /* Mode register 1/2 (a) */ 52 u8 d1, sra; /* Status register (a) */ 53 u8 d2, r1; /* reserved */ 54 u8 d3, rhra; /* Receive holding register (a) */ 55 u8 d4, ipcr; /* Input port change register of block */ 56 u8 d5, isr; /* Interrupt status register of block */ 57 u8 d6, ctur; /* Counter timer upper register of block */ 58 u8 d7, ctlr; /* Counter timer lower register of block */ 59 u8 d8, mrb; /* Mode register 1/2 (b) */ 60 u8 d9, srb; /* Status register (b) */ 61 u8 da, r2; /* reserved */ 62 u8 db, rhrb; /* Receive holding register (b) */ 63 u8 dc, r3; /* reserved */ 64 u8 dd, ip; /* Input port register of block */ 65 u8 de, ctg; /* Start counter timer of block */ 66 u8 df, cts; /* Stop counter timer of block */ 67 } __packed r; /* Read access */ 68 struct { 69 u8 d0, mra; /* Mode register 1/2 (a) */ 70 u8 d1, csra; /* Clock select register (a) */ 71 u8 d2, cra; /* Command register (a) */ 72 u8 d3, thra; /* Transmit holding register (a) */ 73 u8 d4, acr; /* Auxiliary control register of block */ 74 u8 d5, imr; /* Interrupt mask register of block */ 75 u8 d6, ctu; /* Counter timer upper register of block */ 76 u8 d7, ctl; /* Counter timer lower register of block */ 77 u8 d8, mrb; /* Mode register 1/2 (b) */ 78 u8 d9, csrb; /* Clock select register (a) */ 79 u8 da, crb; /* Command register (b) */ 80 u8 db, thrb; /* Transmit holding register (b) */ 81 u8 dc, r1; /* reserved */ 82 u8 dd, opcr; /* Output port configuration register of block */ 83 u8 de, r2; /* reserved */ 84 u8 df, r3; /* reserved */ 85 } __packed w; /* Write access */ 86}; 87 88#define MR1_CHRL_5_BITS (0x0 << 0) 89#define MR1_CHRL_6_BITS (0x1 << 0) 90#define MR1_CHRL_7_BITS (0x2 << 0) 91#define MR1_CHRL_8_BITS (0x3 << 0) 92#define MR1_PARITY_EVEN (0x1 << 2) 93#define MR1_PARITY_ODD (0x0 << 2) 94#define MR1_PARITY_ON (0x0 << 3) 95#define MR1_PARITY_FORCE (0x1 << 3) 96#define MR1_PARITY_OFF (0x2 << 3) 97#define MR1_PARITY_SPECIAL (0x3 << 3) 98#define MR1_ERROR_CHAR (0x0 << 5) 99#define MR1_ERROR_BLOCK (0x1 << 5) 100#define MR1_RxINT_RxRDY (0x0 << 6) 101#define MR1_RxINT_FFULL (0x1 << 6) 102#define MR1_RxRTS_CONTROL_ON (0x1 << 7) 103#define MR1_RxRTS_CONTROL_OFF (0x0 << 7) 104 105#define MR2_STOP_BITS_LENGTH_1 (0x7 << 0) 106#define MR2_STOP_BITS_LENGTH_2 (0xF << 0) 107#define MR2_CTS_ENABLE_TX_ON (0x1 << 4) 108#define MR2_CTS_ENABLE_TX_OFF (0x0 << 4) 109#define MR2_TxRTS_CONTROL_ON (0x1 << 5) 110#define MR2_TxRTS_CONTROL_OFF (0x0 << 5) 111#define MR2_CH_MODE_NORMAL (0x0 << 6) 112#define MR2_CH_MODE_ECHO (0x1 << 6) 113#define MR2_CH_MODE_LOCAL (0x2 << 6) 114#define MR2_CH_MODE_REMOTE (0x3 << 6) 115 116#define CR_ENABLE_RX (0x1 << 0) 117#define CR_DISABLE_RX (0x1 << 1) 118#define CR_ENABLE_TX (0x1 << 2) 119#define CR_DISABLE_TX (0x1 << 3) 120#define CR_CMD_RESET_MR (0x1 << 4) 121#define CR_CMD_RESET_RX (0x2 << 4) 122#define CR_CMD_RESET_TX (0x3 << 4) 123#define CR_CMD_RESET_ERR_STATUS (0x4 << 4) 124#define CR_CMD_RESET_BREAK_CHANGE (0x5 << 4) 125#define CR_CMD_START_BREAK (0x6 << 4) 126#define CR_CMD_STOP_BREAK (0x7 << 4) 127#define CR_CMD_ASSERT_RTSN (0x8 << 4) 128#define CR_CMD_NEGATE_RTSN (0x9 << 4) 129#define CR_CMD_SET_TIMEOUT_MODE (0xA << 4) 130#define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4) 131 132#define SR_RX_READY (0x1 << 0) 133#define SR_FIFO_FULL (0x1 << 1) 134#define SR_TX_READY (0x1 << 2) 135#define SR_TX_EMPTY (0x1 << 3) 136#define SR_OVERRUN_ERROR (0x1 << 4) 137#define SR_PARITY_ERROR (0x1 << 5) 138#define SR_FRAMING_ERROR (0x1 << 6) 139#define SR_RECEIVED_BREAK (0x1 << 7) 140 141#define SR_ERROR (0xF0) 142 143#define ACR_DELTA_IP0_IRQ_EN (0x1 << 0) 144#define ACR_DELTA_IP1_IRQ_EN (0x1 << 1) 145#define ACR_DELTA_IP2_IRQ_EN (0x1 << 2) 146#define ACR_DELTA_IP3_IRQ_EN (0x1 << 3) 147#define ACR_CT_Mask (0x7 << 4) 148#define ACR_CExt (0x0 << 4) 149#define ACR_CTxCA (0x1 << 4) 150#define ACR_CTxCB (0x2 << 4) 151#define ACR_CClk16 (0x3 << 4) 152#define ACR_TExt (0x4 << 4) 153#define ACR_TExt16 (0x5 << 4) 154#define ACR_TClk (0x6 << 4) 155#define ACR_TClk16 (0x7 << 4) 156#define ACR_BRG_SET1 (0x0 << 7) 157#define ACR_BRG_SET2 (0x1 << 7) 158 159#define TX_CLK_75 (0x0 << 0) 160#define TX_CLK_110 (0x1 << 0) 161#define TX_CLK_38400 (0x2 << 0) 162#define TX_CLK_150 (0x3 << 0) 163#define TX_CLK_300 (0x4 << 0) 164#define TX_CLK_600 (0x5 << 0) 165#define TX_CLK_1200 (0x6 << 0) 166#define TX_CLK_2000 (0x7 << 0) 167#define TX_CLK_2400 (0x8 << 0) 168#define TX_CLK_4800 (0x9 << 0) 169#define TX_CLK_1800 (0xA << 0) 170#define TX_CLK_9600 (0xB << 0) 171#define TX_CLK_19200 (0xC << 0) 172#define RX_CLK_75 (0x0 << 4) 173#define RX_CLK_110 (0x1 << 4) 174#define RX_CLK_38400 (0x2 << 4) 175#define RX_CLK_150 (0x3 << 4) 176#define RX_CLK_300 (0x4 << 4) 177#define RX_CLK_600 (0x5 << 4) 178#define RX_CLK_1200 (0x6 << 4) 179#define RX_CLK_2000 (0x7 << 4) 180#define RX_CLK_2400 (0x8 << 4) 181#define RX_CLK_4800 (0x9 << 4) 182#define RX_CLK_1800 (0xA << 4) 183#define RX_CLK_9600 (0xB << 4) 184#define RX_CLK_19200 (0xC << 4) 185 186#define OPCR_MPOa_RTSN (0x0 << 0) 187#define OPCR_MPOa_C_TO (0x1 << 0) 188#define OPCR_MPOa_TxC1X (0x2 << 0) 189#define OPCR_MPOa_TxC16X (0x3 << 0) 190#define OPCR_MPOa_RxC1X (0x4 << 0) 191#define OPCR_MPOa_RxC16X (0x5 << 0) 192#define OPCR_MPOa_TxRDY (0x6 << 0) 193#define OPCR_MPOa_RxRDY_FF (0x7 << 0) 194 195#define OPCR_MPOb_RTSN (0x0 << 4) 196#define OPCR_MPOb_C_TO (0x1 << 4) 197#define OPCR_MPOb_TxC1X (0x2 << 4) 198#define OPCR_MPOb_TxC16X (0x3 << 4) 199#define OPCR_MPOb_RxC1X (0x4 << 4) 200#define OPCR_MPOb_RxC16X (0x5 << 4) 201#define OPCR_MPOb_TxRDY (0x6 << 4) 202#define OPCR_MPOb_RxRDY_FF (0x7 << 4) 203 204#define OPCR_MPP_INPUT (0x0 << 7) 205#define OPCR_MPP_OUTPUT (0x1 << 7) 206 207#define IMR_TxRDY_A (0x1 << 0) 208#define IMR_RxRDY_FFULL_A (0x1 << 1) 209#define IMR_DELTA_BREAK_A (0x1 << 2) 210#define IMR_COUNTER_READY (0x1 << 3) 211#define IMR_TxRDY_B (0x1 << 4) 212#define IMR_RxRDY_FFULL_B (0x1 << 5) 213#define IMR_DELTA_BREAK_B (0x1 << 6) 214#define IMR_INPUT_PORT_CHANGE (0x1 << 7) 215 216#define ISR_TxRDY_A (0x1 << 0) 217#define ISR_RxRDY_FFULL_A (0x1 << 1) 218#define ISR_DELTA_BREAK_A (0x1 << 2) 219#define ISR_COUNTER_READY (0x1 << 3) 220#define ISR_TxRDY_B (0x1 << 4) 221#define ISR_RxRDY_FFULL_B (0x1 << 5) 222#define ISR_DELTA_BREAK_B (0x1 << 6) 223#define ISR_INPUT_PORT_CHANGE (0x1 << 7) 224 225#define ACK_INT_REQ0 0 226#define ACK_INT_REQ1 2 227 228#endif /* SCC2698_H_ */ 229