1/* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13#ifndef __SDHCI_HW_H 14#define __SDHCI_HW_H 15 16#include <linux/scatterlist.h> 17#include <linux/compiler.h> 18#include <linux/types.h> 19#include <linux/io.h> 20 21#include <linux/mmc/sdhci.h> 22 23/* 24 * Controller registers 25 */ 26 27#define SDHCI_DMA_ADDRESS 0x00 28#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 29 30#define SDHCI_BLOCK_SIZE 0x04 31#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33#define SDHCI_BLOCK_COUNT 0x06 34 35#define SDHCI_ARGUMENT 0x08 36 37#define SDHCI_TRANSFER_MODE 0x0C 38#define SDHCI_TRNS_DMA 0x01 39#define SDHCI_TRNS_BLK_CNT_EN 0x02 40#define SDHCI_TRNS_AUTO_CMD12 0x04 41#define SDHCI_TRNS_AUTO_CMD23 0x08 42#define SDHCI_TRNS_READ 0x10 43#define SDHCI_TRNS_MULTI 0x20 44 45#define SDHCI_COMMAND 0x0E 46#define SDHCI_CMD_RESP_MASK 0x03 47#define SDHCI_CMD_CRC 0x08 48#define SDHCI_CMD_INDEX 0x10 49#define SDHCI_CMD_DATA 0x20 50#define SDHCI_CMD_ABORTCMD 0xC0 51 52#define SDHCI_CMD_RESP_NONE 0x00 53#define SDHCI_CMD_RESP_LONG 0x01 54#define SDHCI_CMD_RESP_SHORT 0x02 55#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 56 57#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 58#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 59 60#define SDHCI_RESPONSE 0x10 61 62#define SDHCI_BUFFER 0x20 63 64#define SDHCI_PRESENT_STATE 0x24 65#define SDHCI_CMD_INHIBIT 0x00000001 66#define SDHCI_DATA_INHIBIT 0x00000002 67#define SDHCI_DOING_WRITE 0x00000100 68#define SDHCI_DOING_READ 0x00000200 69#define SDHCI_SPACE_AVAILABLE 0x00000400 70#define SDHCI_DATA_AVAILABLE 0x00000800 71#define SDHCI_CARD_PRESENT 0x00010000 72#define SDHCI_WRITE_PROTECT 0x00080000 73#define SDHCI_DATA_LVL_MASK 0x00F00000 74#define SDHCI_DATA_LVL_SHIFT 20 75#define SDHCI_DATA_0_LVL_MASK 0x00100000 76 77#define SDHCI_HOST_CONTROL 0x28 78#define SDHCI_CTRL_LED 0x01 79#define SDHCI_CTRL_4BITBUS 0x02 80#define SDHCI_CTRL_HISPD 0x04 81#define SDHCI_CTRL_DMA_MASK 0x18 82#define SDHCI_CTRL_SDMA 0x00 83#define SDHCI_CTRL_ADMA1 0x08 84#define SDHCI_CTRL_ADMA32 0x10 85#define SDHCI_CTRL_ADMA64 0x18 86#define SDHCI_CTRL_8BITBUS 0x20 87 88#define SDHCI_POWER_CONTROL 0x29 89#define SDHCI_POWER_ON 0x01 90#define SDHCI_POWER_180 0x0A 91#define SDHCI_POWER_300 0x0C 92#define SDHCI_POWER_330 0x0E 93 94#define SDHCI_BLOCK_GAP_CONTROL 0x2A 95 96#define SDHCI_WAKE_UP_CONTROL 0x2B 97#define SDHCI_WAKE_ON_INT 0x01 98#define SDHCI_WAKE_ON_INSERT 0x02 99#define SDHCI_WAKE_ON_REMOVE 0x04 100 101#define SDHCI_CLOCK_CONTROL 0x2C 102#define SDHCI_DIVIDER_SHIFT 8 103#define SDHCI_DIVIDER_HI_SHIFT 6 104#define SDHCI_DIV_MASK 0xFF 105#define SDHCI_DIV_MASK_LEN 8 106#define SDHCI_DIV_HI_MASK 0x300 107#define SDHCI_PROG_CLOCK_MODE 0x0020 108#define SDHCI_CLOCK_CARD_EN 0x0004 109#define SDHCI_CLOCK_INT_STABLE 0x0002 110#define SDHCI_CLOCK_INT_EN 0x0001 111 112#define SDHCI_TIMEOUT_CONTROL 0x2E 113 114#define SDHCI_SOFTWARE_RESET 0x2F 115#define SDHCI_RESET_ALL 0x01 116#define SDHCI_RESET_CMD 0x02 117#define SDHCI_RESET_DATA 0x04 118 119#define SDHCI_INT_STATUS 0x30 120#define SDHCI_INT_ENABLE 0x34 121#define SDHCI_SIGNAL_ENABLE 0x38 122#define SDHCI_INT_RESPONSE 0x00000001 123#define SDHCI_INT_DATA_END 0x00000002 124#define SDHCI_INT_BLK_GAP 0x00000004 125#define SDHCI_INT_DMA_END 0x00000008 126#define SDHCI_INT_SPACE_AVAIL 0x00000010 127#define SDHCI_INT_DATA_AVAIL 0x00000020 128#define SDHCI_INT_CARD_INSERT 0x00000040 129#define SDHCI_INT_CARD_REMOVE 0x00000080 130#define SDHCI_INT_CARD_INT 0x00000100 131#define SDHCI_INT_ERROR 0x00008000 132#define SDHCI_INT_TIMEOUT 0x00010000 133#define SDHCI_INT_CRC 0x00020000 134#define SDHCI_INT_END_BIT 0x00040000 135#define SDHCI_INT_INDEX 0x00080000 136#define SDHCI_INT_DATA_TIMEOUT 0x00100000 137#define SDHCI_INT_DATA_CRC 0x00200000 138#define SDHCI_INT_DATA_END_BIT 0x00400000 139#define SDHCI_INT_BUS_POWER 0x00800000 140#define SDHCI_INT_ACMD12ERR 0x01000000 141#define SDHCI_INT_ADMA_ERROR 0x02000000 142 143#define SDHCI_INT_NORMAL_MASK 0x00007FFF 144#define SDHCI_INT_ERROR_MASK 0xFFFF8000 145 146#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 147 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 148#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 149 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 150 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 151 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 152 SDHCI_INT_BLK_GAP) 153#define SDHCI_INT_ALL_MASK ((unsigned int)-1) 154 155#define SDHCI_ACMD12_ERR 0x3C 156 157#define SDHCI_HOST_CONTROL2 0x3E 158#define SDHCI_CTRL_UHS_MASK 0x0007 159#define SDHCI_CTRL_UHS_SDR12 0x0000 160#define SDHCI_CTRL_UHS_SDR25 0x0001 161#define SDHCI_CTRL_UHS_SDR50 0x0002 162#define SDHCI_CTRL_UHS_SDR104 0x0003 163#define SDHCI_CTRL_UHS_DDR50 0x0004 164#define SDHCI_CTRL_HS_SDR200 0x0005 /* reserved value in SDIO spec */ 165#define SDHCI_CTRL_VDD_180 0x0008 166#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 167#define SDHCI_CTRL_DRV_TYPE_B 0x0000 168#define SDHCI_CTRL_DRV_TYPE_A 0x0010 169#define SDHCI_CTRL_DRV_TYPE_C 0x0020 170#define SDHCI_CTRL_DRV_TYPE_D 0x0030 171#define SDHCI_CTRL_EXEC_TUNING 0x0040 172#define SDHCI_CTRL_TUNED_CLK 0x0080 173#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 174 175#define SDHCI_CAPABILITIES 0x40 176#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 177#define SDHCI_TIMEOUT_CLK_SHIFT 0 178#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 179#define SDHCI_CLOCK_BASE_MASK 0x00003F00 180#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 181#define SDHCI_CLOCK_BASE_SHIFT 8 182#define SDHCI_MAX_BLOCK_MASK 0x00030000 183#define SDHCI_MAX_BLOCK_SHIFT 16 184#define SDHCI_CAN_DO_8BIT 0x00040000 185#define SDHCI_CAN_DO_ADMA2 0x00080000 186#define SDHCI_CAN_DO_ADMA1 0x00100000 187#define SDHCI_CAN_DO_HISPD 0x00200000 188#define SDHCI_CAN_DO_SDMA 0x00400000 189#define SDHCI_CAN_VDD_330 0x01000000 190#define SDHCI_CAN_VDD_300 0x02000000 191#define SDHCI_CAN_VDD_180 0x04000000 192#define SDHCI_CAN_64BIT 0x10000000 193 194#define SDHCI_SUPPORT_SDR50 0x00000001 195#define SDHCI_SUPPORT_SDR104 0x00000002 196#define SDHCI_SUPPORT_DDR50 0x00000004 197#define SDHCI_DRIVER_TYPE_A 0x00000010 198#define SDHCI_DRIVER_TYPE_C 0x00000020 199#define SDHCI_DRIVER_TYPE_D 0x00000040 200#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 201#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 202#define SDHCI_USE_SDR50_TUNING 0x00002000 203#define SDHCI_RETUNING_MODE_MASK 0x0000C000 204#define SDHCI_RETUNING_MODE_SHIFT 14 205#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 206#define SDHCI_CLOCK_MUL_SHIFT 16 207 208#define SDHCI_CAPABILITIES_1 0x44 209 210#define SDHCI_MAX_CURRENT 0x48 211#define SDHCI_MAX_CURRENT_LIMIT 0xFF 212#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF 213#define SDHCI_MAX_CURRENT_330_SHIFT 0 214#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 215#define SDHCI_MAX_CURRENT_300_SHIFT 8 216#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 217#define SDHCI_MAX_CURRENT_180_SHIFT 16 218#define SDHCI_MAX_CURRENT_MULTIPLIER 4 219 220/* 4C-4F reserved for more max current */ 221 222#define SDHCI_SET_ACMD12_ERROR 0x50 223#define SDHCI_SET_INT_ERROR 0x52 224 225#define SDHCI_ADMA_ERROR 0x54 226 227/* 55-57 reserved */ 228 229#define SDHCI_ADMA_ADDRESS 0x58 230 231/* 60-FB reserved */ 232 233#define SDHCI_PRESET_FOR_SDR12 0x66 234#define SDHCI_PRESET_FOR_SDR25 0x68 235#define SDHCI_PRESET_FOR_SDR50 0x6A 236#define SDHCI_PRESET_FOR_SDR104 0x6C 237#define SDHCI_PRESET_FOR_DDR50 0x6E 238#define SDHCI_PRESET_DRV_MASK 0xC000 239#define SDHCI_PRESET_DRV_SHIFT 14 240#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400 241#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10 242#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF 243#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 244 245#define SDHCI_SLOT_INT_STATUS 0xFC 246 247#define SDHCI_HOST_VERSION 0xFE 248#define SDHCI_VENDOR_VER_MASK 0xFF00 249#define SDHCI_VENDOR_VER_SHIFT 8 250#define SDHCI_SPEC_VER_MASK 0x00FF 251#define SDHCI_SPEC_VER_SHIFT 0 252#define SDHCI_SPEC_100 0 253#define SDHCI_SPEC_200 1 254#define SDHCI_SPEC_300 2 255 256/* 257 * End of controller registers. 258 */ 259 260#define SDHCI_MAX_DIV_SPEC_200 256 261#define SDHCI_MAX_DIV_SPEC_300 2046 262 263/* 264 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 265 */ 266#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 267#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 268 269struct sdhci_ops { 270#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 271 u32 (*read_l)(struct sdhci_host *host, int reg); 272 u16 (*read_w)(struct sdhci_host *host, int reg); 273 u8 (*read_b)(struct sdhci_host *host, int reg); 274 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 275 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 276 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 277#endif 278 279 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 280 281 int (*enable_dma)(struct sdhci_host *host); 282 unsigned int (*get_max_clock)(struct sdhci_host *host); 283 unsigned int (*get_min_clock)(struct sdhci_host *host); 284 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 285 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 286 void (*set_timeout)(struct sdhci_host *host, 287 struct mmc_command *cmd); 288 void (*set_bus_width)(struct sdhci_host *host, int width); 289 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 290 u8 power_mode); 291 unsigned int (*get_ro)(struct sdhci_host *host); 292 void (*reset)(struct sdhci_host *host, u8 mask); 293 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 294 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 295 void (*hw_reset)(struct sdhci_host *host); 296 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 297 void (*platform_init)(struct sdhci_host *host); 298 void (*card_event)(struct sdhci_host *host); 299}; 300 301#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 302 303static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 304{ 305 if (unlikely(host->ops->write_l)) 306 host->ops->write_l(host, val, reg); 307 else 308 writel(val, host->ioaddr + reg); 309} 310 311static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 312{ 313 if (unlikely(host->ops->write_w)) 314 host->ops->write_w(host, val, reg); 315 else 316 writew(val, host->ioaddr + reg); 317} 318 319static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 320{ 321 if (unlikely(host->ops->write_b)) 322 host->ops->write_b(host, val, reg); 323 else 324 writeb(val, host->ioaddr + reg); 325} 326 327static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 328{ 329 if (unlikely(host->ops->read_l)) 330 return host->ops->read_l(host, reg); 331 else 332 return readl(host->ioaddr + reg); 333} 334 335static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 336{ 337 if (unlikely(host->ops->read_w)) 338 return host->ops->read_w(host, reg); 339 else 340 return readw(host->ioaddr + reg); 341} 342 343static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 344{ 345 if (unlikely(host->ops->read_b)) 346 return host->ops->read_b(host, reg); 347 else 348 return readb(host->ioaddr + reg); 349} 350 351#else 352 353static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 354{ 355 writel(val, host->ioaddr + reg); 356} 357 358static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 359{ 360 writew(val, host->ioaddr + reg); 361} 362 363static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 364{ 365 writeb(val, host->ioaddr + reg); 366} 367 368static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 369{ 370 return readl(host->ioaddr + reg); 371} 372 373static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 374{ 375 return readw(host->ioaddr + reg); 376} 377 378static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 379{ 380 return readb(host->ioaddr + reg); 381} 382 383#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 384 385extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 386 size_t priv_size); 387extern void sdhci_free_host(struct sdhci_host *host); 388 389static inline void *sdhci_priv(struct sdhci_host *host) 390{ 391 return (void *)host->private; 392} 393 394extern void sdhci_card_detect(struct sdhci_host *host); 395extern int sdhci_add_host(struct sdhci_host *host); 396extern void sdhci_remove_host(struct sdhci_host *host, int dead); 397extern void sdhci_send_command(struct sdhci_host *host, 398 struct mmc_command *cmd); 399 400static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host) 401{ 402 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED); 403} 404 405void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 406void sdhci_set_bus_width(struct sdhci_host *host, int width); 407void sdhci_reset(struct sdhci_host *host, u8 mask); 408void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 409 410#ifdef CONFIG_PM 411extern int sdhci_suspend_host(struct sdhci_host *host); 412extern int sdhci_resume_host(struct sdhci_host *host); 413extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 414#endif 415 416#ifdef CONFIG_PM_RUNTIME 417extern int sdhci_runtime_suspend_host(struct sdhci_host *host); 418extern int sdhci_runtime_resume_host(struct sdhci_host *host); 419#endif 420 421#endif /* __SDHCI_HW_H */ 422