adv7604.c revision 454378923a9b44e26918893fac8bdeb43ae0f57b
1/* 2 * adv7604 - Analog Devices ADV7604 video decoder driver 3 * 4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 5 * 6 * This program is free software; you may redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 * SOFTWARE. 18 * 19 */ 20 21/* 22 * References (c = chapter, p = page): 23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations, 24 * Revision 2.5, June 2010 25 * REF_02 - Analog devices, Register map documentation, Documentation of 26 * the register maps, Software manual, Rev. F, June 2010 27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010 28 */ 29 30 31#include <linux/kernel.h> 32#include <linux/module.h> 33#include <linux/slab.h> 34#include <linux/i2c.h> 35#include <linux/delay.h> 36#include <linux/videodev2.h> 37#include <linux/workqueue.h> 38#include <linux/v4l2-dv-timings.h> 39#include <media/v4l2-device.h> 40#include <media/v4l2-ctrls.h> 41#include <media/v4l2-dv-timings.h> 42#include <media/adv7604.h> 43 44static int debug; 45module_param(debug, int, 0644); 46MODULE_PARM_DESC(debug, "debug level (0-2)"); 47 48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver"); 49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>"); 50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>"); 51MODULE_LICENSE("GPL"); 52 53/* ADV7604 system clock frequency */ 54#define ADV7604_fsc (28636360) 55 56enum adv7604_type { 57 ADV7604, 58 ADV7611, 59}; 60 61struct adv7604_reg_seq { 62 unsigned int reg; 63 u8 val; 64}; 65 66struct adv7604_chip_info { 67 enum adv7604_type type; 68 69 bool has_afe; 70 unsigned int max_port; 71 unsigned int num_dv_ports; 72 73 unsigned int edid_enable_reg; 74 unsigned int edid_status_reg; 75 unsigned int lcf_reg; 76 77 unsigned int cable_det_mask; 78 unsigned int tdms_lock_mask; 79 unsigned int fmt_change_digital_mask; 80 81 void (*set_termination)(struct v4l2_subdev *sd, bool enable); 82 void (*setup_irqs)(struct v4l2_subdev *sd); 83 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd); 84 unsigned int (*read_cable_det)(struct v4l2_subdev *sd); 85 86 /* 0 = AFE, 1 = HDMI */ 87 const struct adv7604_reg_seq *recommended_settings[2]; 88 unsigned int num_recommended_settings[2]; 89 90 unsigned long page_mask; 91}; 92 93/* 94 ********************************************************************** 95 * 96 * Arrays with configuration parameters for the ADV7604 97 * 98 ********************************************************************** 99 */ 100struct adv7604_state { 101 const struct adv7604_chip_info *info; 102 struct adv7604_platform_data pdata; 103 struct v4l2_subdev sd; 104 struct media_pad pad; 105 struct v4l2_ctrl_handler hdl; 106 enum adv7604_input_port selected_input; 107 struct v4l2_dv_timings timings; 108 struct { 109 u8 edid[256]; 110 u32 present; 111 unsigned blocks; 112 } edid; 113 u16 spa_port_a[2]; 114 struct v4l2_fract aspect_ratio; 115 u32 rgb_quantization_range; 116 struct workqueue_struct *work_queues; 117 struct delayed_work delayed_work_enable_hotplug; 118 bool restart_stdi_once; 119 120 /* i2c clients */ 121 struct i2c_client *i2c_avlink; 122 struct i2c_client *i2c_cec; 123 struct i2c_client *i2c_infoframe; 124 struct i2c_client *i2c_esdp; 125 struct i2c_client *i2c_dpp; 126 struct i2c_client *i2c_afe; 127 struct i2c_client *i2c_repeater; 128 struct i2c_client *i2c_edid; 129 struct i2c_client *i2c_hdmi; 130 struct i2c_client *i2c_test; 131 struct i2c_client *i2c_cp; 132 struct i2c_client *i2c_vdp; 133 134 /* controls */ 135 struct v4l2_ctrl *detect_tx_5v_ctrl; 136 struct v4l2_ctrl *analog_sampling_phase_ctrl; 137 struct v4l2_ctrl *free_run_color_manual_ctrl; 138 struct v4l2_ctrl *free_run_color_ctrl; 139 struct v4l2_ctrl *rgb_quantization_range_ctrl; 140}; 141 142static bool adv7604_has_afe(struct adv7604_state *state) 143{ 144 return state->info->has_afe; 145} 146 147/* Supported CEA and DMT timings */ 148static const struct v4l2_dv_timings adv7604_timings[] = { 149 V4L2_DV_BT_CEA_720X480P59_94, 150 V4L2_DV_BT_CEA_720X576P50, 151 V4L2_DV_BT_CEA_1280X720P24, 152 V4L2_DV_BT_CEA_1280X720P25, 153 V4L2_DV_BT_CEA_1280X720P50, 154 V4L2_DV_BT_CEA_1280X720P60, 155 V4L2_DV_BT_CEA_1920X1080P24, 156 V4L2_DV_BT_CEA_1920X1080P25, 157 V4L2_DV_BT_CEA_1920X1080P30, 158 V4L2_DV_BT_CEA_1920X1080P50, 159 V4L2_DV_BT_CEA_1920X1080P60, 160 161 /* sorted by DMT ID */ 162 V4L2_DV_BT_DMT_640X350P85, 163 V4L2_DV_BT_DMT_640X400P85, 164 V4L2_DV_BT_DMT_720X400P85, 165 V4L2_DV_BT_DMT_640X480P60, 166 V4L2_DV_BT_DMT_640X480P72, 167 V4L2_DV_BT_DMT_640X480P75, 168 V4L2_DV_BT_DMT_640X480P85, 169 V4L2_DV_BT_DMT_800X600P56, 170 V4L2_DV_BT_DMT_800X600P60, 171 V4L2_DV_BT_DMT_800X600P72, 172 V4L2_DV_BT_DMT_800X600P75, 173 V4L2_DV_BT_DMT_800X600P85, 174 V4L2_DV_BT_DMT_848X480P60, 175 V4L2_DV_BT_DMT_1024X768P60, 176 V4L2_DV_BT_DMT_1024X768P70, 177 V4L2_DV_BT_DMT_1024X768P75, 178 V4L2_DV_BT_DMT_1024X768P85, 179 V4L2_DV_BT_DMT_1152X864P75, 180 V4L2_DV_BT_DMT_1280X768P60_RB, 181 V4L2_DV_BT_DMT_1280X768P60, 182 V4L2_DV_BT_DMT_1280X768P75, 183 V4L2_DV_BT_DMT_1280X768P85, 184 V4L2_DV_BT_DMT_1280X800P60_RB, 185 V4L2_DV_BT_DMT_1280X800P60, 186 V4L2_DV_BT_DMT_1280X800P75, 187 V4L2_DV_BT_DMT_1280X800P85, 188 V4L2_DV_BT_DMT_1280X960P60, 189 V4L2_DV_BT_DMT_1280X960P85, 190 V4L2_DV_BT_DMT_1280X1024P60, 191 V4L2_DV_BT_DMT_1280X1024P75, 192 V4L2_DV_BT_DMT_1280X1024P85, 193 V4L2_DV_BT_DMT_1360X768P60, 194 V4L2_DV_BT_DMT_1400X1050P60_RB, 195 V4L2_DV_BT_DMT_1400X1050P60, 196 V4L2_DV_BT_DMT_1400X1050P75, 197 V4L2_DV_BT_DMT_1400X1050P85, 198 V4L2_DV_BT_DMT_1440X900P60_RB, 199 V4L2_DV_BT_DMT_1440X900P60, 200 V4L2_DV_BT_DMT_1600X1200P60, 201 V4L2_DV_BT_DMT_1680X1050P60_RB, 202 V4L2_DV_BT_DMT_1680X1050P60, 203 V4L2_DV_BT_DMT_1792X1344P60, 204 V4L2_DV_BT_DMT_1856X1392P60, 205 V4L2_DV_BT_DMT_1920X1200P60_RB, 206 V4L2_DV_BT_DMT_1366X768P60_RB, 207 V4L2_DV_BT_DMT_1366X768P60, 208 V4L2_DV_BT_DMT_1920X1080P60, 209 { }, 210}; 211 212struct adv7604_video_standards { 213 struct v4l2_dv_timings timings; 214 u8 vid_std; 215 u8 v_freq; 216}; 217 218/* sorted by number of lines */ 219static const struct adv7604_video_standards adv7604_prim_mode_comp[] = { 220 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */ 221 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 222 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 }, 223 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 }, 224 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 225 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 226 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 227 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 228 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 229 /* TODO add 1920x1080P60_RB (CVT timing) */ 230 { }, 231}; 232 233/* sorted by number of lines */ 234static const struct adv7604_video_standards adv7604_prim_mode_gr[] = { 235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 250 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 }, 251 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 }, 252 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 }, 253 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 }, 254 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */ 255 /* TODO add 1600X1200P60_RB (not a DMT timing) */ 256 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 }, 257 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */ 258 { }, 259}; 260 261/* sorted by number of lines */ 262static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = { 263 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, 264 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 }, 265 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 }, 266 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 }, 267 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 }, 268 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 }, 269 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 }, 270 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 }, 271 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 }, 272 { }, 273}; 274 275/* sorted by number of lines */ 276static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = { 277 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 }, 278 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 }, 279 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 }, 280 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 }, 281 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 }, 282 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 }, 283 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 }, 284 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 }, 285 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 }, 286 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 }, 287 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 }, 288 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 }, 289 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 }, 290 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 }, 291 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 }, 292 { }, 293}; 294 295/* ----------------------------------------------------------------------- */ 296 297static inline struct adv7604_state *to_state(struct v4l2_subdev *sd) 298{ 299 return container_of(sd, struct adv7604_state, sd); 300} 301 302static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) 303{ 304 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd; 305} 306 307static inline unsigned hblanking(const struct v4l2_bt_timings *t) 308{ 309 return V4L2_DV_BT_BLANKING_WIDTH(t); 310} 311 312static inline unsigned htotal(const struct v4l2_bt_timings *t) 313{ 314 return V4L2_DV_BT_FRAME_WIDTH(t); 315} 316 317static inline unsigned vblanking(const struct v4l2_bt_timings *t) 318{ 319 return V4L2_DV_BT_BLANKING_HEIGHT(t); 320} 321 322static inline unsigned vtotal(const struct v4l2_bt_timings *t) 323{ 324 return V4L2_DV_BT_FRAME_HEIGHT(t); 325} 326 327/* ----------------------------------------------------------------------- */ 328 329static s32 adv_smbus_read_byte_data_check(struct i2c_client *client, 330 u8 command, bool check) 331{ 332 union i2c_smbus_data data; 333 334 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags, 335 I2C_SMBUS_READ, command, 336 I2C_SMBUS_BYTE_DATA, &data)) 337 return data.byte; 338 if (check) 339 v4l_err(client, "error reading %02x, %02x\n", 340 client->addr, command); 341 return -EIO; 342} 343 344static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command) 345{ 346 return adv_smbus_read_byte_data_check(client, command, true); 347} 348 349static s32 adv_smbus_write_byte_data(struct i2c_client *client, 350 u8 command, u8 value) 351{ 352 union i2c_smbus_data data; 353 int err; 354 int i; 355 356 data.byte = value; 357 for (i = 0; i < 3; i++) { 358 err = i2c_smbus_xfer(client->adapter, client->addr, 359 client->flags, 360 I2C_SMBUS_WRITE, command, 361 I2C_SMBUS_BYTE_DATA, &data); 362 if (!err) 363 break; 364 } 365 if (err < 0) 366 v4l_err(client, "error writing %02x, %02x, %02x\n", 367 client->addr, command, value); 368 return err; 369} 370 371static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client, 372 u8 command, unsigned length, const u8 *values) 373{ 374 union i2c_smbus_data data; 375 376 if (length > I2C_SMBUS_BLOCK_MAX) 377 length = I2C_SMBUS_BLOCK_MAX; 378 data.block[0] = length; 379 memcpy(data.block + 1, values, length); 380 return i2c_smbus_xfer(client->adapter, client->addr, client->flags, 381 I2C_SMBUS_WRITE, command, 382 I2C_SMBUS_I2C_BLOCK_DATA, &data); 383} 384 385/* ----------------------------------------------------------------------- */ 386 387static inline int io_read(struct v4l2_subdev *sd, u8 reg) 388{ 389 struct i2c_client *client = v4l2_get_subdevdata(sd); 390 391 return adv_smbus_read_byte_data(client, reg); 392} 393 394static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) 395{ 396 struct i2c_client *client = v4l2_get_subdevdata(sd); 397 398 return adv_smbus_write_byte_data(client, reg, val); 399} 400 401static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 402{ 403 return io_write(sd, reg, (io_read(sd, reg) & mask) | val); 404} 405 406static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) 407{ 408 struct adv7604_state *state = to_state(sd); 409 410 return adv_smbus_read_byte_data(state->i2c_avlink, reg); 411} 412 413static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) 414{ 415 struct adv7604_state *state = to_state(sd); 416 417 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); 418} 419 420static inline int cec_read(struct v4l2_subdev *sd, u8 reg) 421{ 422 struct adv7604_state *state = to_state(sd); 423 424 return adv_smbus_read_byte_data(state->i2c_cec, reg); 425} 426 427static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) 428{ 429 struct adv7604_state *state = to_state(sd); 430 431 return adv_smbus_write_byte_data(state->i2c_cec, reg, val); 432} 433 434static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 435{ 436 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val); 437} 438 439static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) 440{ 441 struct adv7604_state *state = to_state(sd); 442 443 return adv_smbus_read_byte_data(state->i2c_infoframe, reg); 444} 445 446static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 447{ 448 struct adv7604_state *state = to_state(sd); 449 450 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); 451} 452 453static inline int esdp_read(struct v4l2_subdev *sd, u8 reg) 454{ 455 struct adv7604_state *state = to_state(sd); 456 457 return adv_smbus_read_byte_data(state->i2c_esdp, reg); 458} 459 460static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 461{ 462 struct adv7604_state *state = to_state(sd); 463 464 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val); 465} 466 467static inline int dpp_read(struct v4l2_subdev *sd, u8 reg) 468{ 469 struct adv7604_state *state = to_state(sd); 470 471 return adv_smbus_read_byte_data(state->i2c_dpp, reg); 472} 473 474static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 475{ 476 struct adv7604_state *state = to_state(sd); 477 478 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val); 479} 480 481static inline int afe_read(struct v4l2_subdev *sd, u8 reg) 482{ 483 struct adv7604_state *state = to_state(sd); 484 485 return adv_smbus_read_byte_data(state->i2c_afe, reg); 486} 487 488static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) 489{ 490 struct adv7604_state *state = to_state(sd); 491 492 return adv_smbus_write_byte_data(state->i2c_afe, reg, val); 493} 494 495static inline int rep_read(struct v4l2_subdev *sd, u8 reg) 496{ 497 struct adv7604_state *state = to_state(sd); 498 499 return adv_smbus_read_byte_data(state->i2c_repeater, reg); 500} 501 502static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) 503{ 504 struct adv7604_state *state = to_state(sd); 505 506 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); 507} 508 509static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 510{ 511 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); 512} 513 514static inline int edid_read(struct v4l2_subdev *sd, u8 reg) 515{ 516 struct adv7604_state *state = to_state(sd); 517 518 return adv_smbus_read_byte_data(state->i2c_edid, reg); 519} 520 521static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) 522{ 523 struct adv7604_state *state = to_state(sd); 524 525 return adv_smbus_write_byte_data(state->i2c_edid, reg, val); 526} 527 528static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val) 529{ 530 struct adv7604_state *state = to_state(sd); 531 struct i2c_client *client = state->i2c_edid; 532 u8 msgbuf0[1] = { 0 }; 533 u8 msgbuf1[256]; 534 struct i2c_msg msg[2] = { 535 { 536 .addr = client->addr, 537 .len = 1, 538 .buf = msgbuf0 539 }, 540 { 541 .addr = client->addr, 542 .flags = I2C_M_RD, 543 .len = len, 544 .buf = msgbuf1 545 }, 546 }; 547 548 if (i2c_transfer(client->adapter, msg, 2) < 0) 549 return -EIO; 550 memcpy(val, msgbuf1, len); 551 return 0; 552} 553 554static inline int edid_write_block(struct v4l2_subdev *sd, 555 unsigned len, const u8 *val) 556{ 557 struct adv7604_state *state = to_state(sd); 558 int err = 0; 559 int i; 560 561 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len); 562 563 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX) 564 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i, 565 I2C_SMBUS_BLOCK_MAX, val + i); 566 return err; 567} 568 569static void adv7604_delayed_work_enable_hotplug(struct work_struct *work) 570{ 571 struct delayed_work *dwork = to_delayed_work(work); 572 struct adv7604_state *state = container_of(dwork, struct adv7604_state, 573 delayed_work_enable_hotplug); 574 struct v4l2_subdev *sd = &state->sd; 575 576 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); 577 578 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 579} 580 581static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) 582{ 583 struct adv7604_state *state = to_state(sd); 584 585 return adv_smbus_read_byte_data(state->i2c_hdmi, reg); 586} 587 588static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 589{ 590 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; 591} 592 593static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) 594{ 595 struct adv7604_state *state = to_state(sd); 596 597 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); 598} 599 600static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 601{ 602 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); 603} 604 605static inline int test_read(struct v4l2_subdev *sd, u8 reg) 606{ 607 struct adv7604_state *state = to_state(sd); 608 609 return adv_smbus_read_byte_data(state->i2c_test, reg); 610} 611 612static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) 613{ 614 struct adv7604_state *state = to_state(sd); 615 616 return adv_smbus_write_byte_data(state->i2c_test, reg, val); 617} 618 619static inline int cp_read(struct v4l2_subdev *sd, u8 reg) 620{ 621 struct adv7604_state *state = to_state(sd); 622 623 return adv_smbus_read_byte_data(state->i2c_cp, reg); 624} 625 626static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) 627{ 628 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; 629} 630 631static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 632{ 633 struct adv7604_state *state = to_state(sd); 634 635 return adv_smbus_write_byte_data(state->i2c_cp, reg, val); 636} 637 638static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) 639{ 640 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); 641} 642 643static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) 644{ 645 struct adv7604_state *state = to_state(sd); 646 647 return adv_smbus_read_byte_data(state->i2c_vdp, reg); 648} 649 650static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) 651{ 652 struct adv7604_state *state = to_state(sd); 653 654 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); 655} 656 657enum { 658 ADV7604_PAGE_IO, 659 ADV7604_PAGE_AVLINK, 660 ADV7604_PAGE_CEC, 661 ADV7604_PAGE_INFOFRAME, 662 ADV7604_PAGE_ESDP, 663 ADV7604_PAGE_DPP, 664 ADV7604_PAGE_AFE, 665 ADV7604_PAGE_REP, 666 ADV7604_PAGE_EDID, 667 ADV7604_PAGE_HDMI, 668 ADV7604_PAGE_TEST, 669 ADV7604_PAGE_CP, 670 ADV7604_PAGE_VDP, 671 ADV7604_PAGE_TERM, 672}; 673 674#define ADV7604_REG(page, offset) (((page) << 8) | (offset)) 675#define ADV7604_REG_SEQ_TERM 0xffff 676 677#ifdef CONFIG_VIDEO_ADV_DEBUG 678static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg) 679{ 680 struct adv7604_state *state = to_state(sd); 681 unsigned int page = reg >> 8; 682 683 if (!(BIT(page) & state->info->page_mask)) 684 return -EINVAL; 685 686 reg &= 0xff; 687 688 switch (page) { 689 case ADV7604_PAGE_IO: 690 return io_read(sd, reg); 691 case ADV7604_PAGE_AVLINK: 692 return avlink_read(sd, reg); 693 case ADV7604_PAGE_CEC: 694 return cec_read(sd, reg); 695 case ADV7604_PAGE_INFOFRAME: 696 return infoframe_read(sd, reg); 697 case ADV7604_PAGE_ESDP: 698 return esdp_read(sd, reg); 699 case ADV7604_PAGE_DPP: 700 return dpp_read(sd, reg); 701 case ADV7604_PAGE_AFE: 702 return afe_read(sd, reg); 703 case ADV7604_PAGE_REP: 704 return rep_read(sd, reg); 705 case ADV7604_PAGE_EDID: 706 return edid_read(sd, reg); 707 case ADV7604_PAGE_HDMI: 708 return hdmi_read(sd, reg); 709 case ADV7604_PAGE_TEST: 710 return test_read(sd, reg); 711 case ADV7604_PAGE_CP: 712 return cp_read(sd, reg); 713 case ADV7604_PAGE_VDP: 714 return vdp_read(sd, reg); 715 } 716 717 return -EINVAL; 718} 719#endif 720 721static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) 722{ 723 struct adv7604_state *state = to_state(sd); 724 unsigned int page = reg >> 8; 725 726 if (!(BIT(page) & state->info->page_mask)) 727 return -EINVAL; 728 729 reg &= 0xff; 730 731 switch (page) { 732 case ADV7604_PAGE_IO: 733 return io_write(sd, reg, val); 734 case ADV7604_PAGE_AVLINK: 735 return avlink_write(sd, reg, val); 736 case ADV7604_PAGE_CEC: 737 return cec_write(sd, reg, val); 738 case ADV7604_PAGE_INFOFRAME: 739 return infoframe_write(sd, reg, val); 740 case ADV7604_PAGE_ESDP: 741 return esdp_write(sd, reg, val); 742 case ADV7604_PAGE_DPP: 743 return dpp_write(sd, reg, val); 744 case ADV7604_PAGE_AFE: 745 return afe_write(sd, reg, val); 746 case ADV7604_PAGE_REP: 747 return rep_write(sd, reg, val); 748 case ADV7604_PAGE_EDID: 749 return edid_write(sd, reg, val); 750 case ADV7604_PAGE_HDMI: 751 return hdmi_write(sd, reg, val); 752 case ADV7604_PAGE_TEST: 753 return test_write(sd, reg, val); 754 case ADV7604_PAGE_CP: 755 return cp_write(sd, reg, val); 756 case ADV7604_PAGE_VDP: 757 return vdp_write(sd, reg, val); 758 } 759 760 return -EINVAL; 761} 762 763static void adv7604_write_reg_seq(struct v4l2_subdev *sd, 764 const struct adv7604_reg_seq *reg_seq) 765{ 766 unsigned int i; 767 768 for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++) 769 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); 770} 771 772/* ----------------------------------------------------------------------- */ 773 774static inline bool is_analog_input(struct v4l2_subdev *sd) 775{ 776 struct adv7604_state *state = to_state(sd); 777 778 return state->selected_input == ADV7604_INPUT_VGA_RGB || 779 state->selected_input == ADV7604_INPUT_VGA_COMP; 780} 781 782static inline bool is_digital_input(struct v4l2_subdev *sd) 783{ 784 struct adv7604_state *state = to_state(sd); 785 786 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A || 787 state->selected_input == ADV7604_INPUT_HDMI_PORT_B || 788 state->selected_input == ADV7604_INPUT_HDMI_PORT_C || 789 state->selected_input == ADV7604_INPUT_HDMI_PORT_D; 790} 791 792/* ----------------------------------------------------------------------- */ 793 794#ifdef CONFIG_VIDEO_ADV_DEBUG 795static void adv7604_inv_register(struct v4l2_subdev *sd) 796{ 797 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); 798 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); 799 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); 800 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); 801 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); 802 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); 803 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); 804 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); 805 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); 806 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); 807 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); 808 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); 809 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); 810} 811 812static int adv7604_g_register(struct v4l2_subdev *sd, 813 struct v4l2_dbg_register *reg) 814{ 815 int ret; 816 817 ret = adv7604_read_reg(sd, reg->reg); 818 if (ret < 0) { 819 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 820 adv7604_inv_register(sd); 821 return ret; 822 } 823 824 reg->size = 1; 825 reg->val = ret; 826 827 return 0; 828} 829 830static int adv7604_s_register(struct v4l2_subdev *sd, 831 const struct v4l2_dbg_register *reg) 832{ 833 int ret; 834 835 ret = adv7604_write_reg(sd, reg->reg, reg->val); 836 if (ret < 0) { 837 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); 838 adv7604_inv_register(sd); 839 return ret; 840 } 841 842 return 0; 843} 844#endif 845 846static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) 847{ 848 u8 value = io_read(sd, 0x6f); 849 850 return ((value & 0x10) >> 4) 851 | ((value & 0x08) >> 2) 852 | ((value & 0x04) << 0) 853 | ((value & 0x02) << 2); 854} 855 856static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) 857{ 858 u8 value = io_read(sd, 0x6f); 859 860 return value & 1; 861} 862 863static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) 864{ 865 struct adv7604_state *state = to_state(sd); 866 const struct adv7604_chip_info *info = state->info; 867 868 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, 869 info->read_cable_det(sd)); 870} 871 872static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, 873 u8 prim_mode, 874 const struct adv7604_video_standards *predef_vid_timings, 875 const struct v4l2_dv_timings *timings) 876{ 877 int i; 878 879 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) { 880 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings, 881 is_digital_input(sd) ? 250000 : 1000000)) 882 continue; 883 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ 884 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + 885 prim_mode); /* v_freq and prim mode */ 886 return 0; 887 } 888 889 return -1; 890} 891 892static int configure_predefined_video_timings(struct v4l2_subdev *sd, 893 struct v4l2_dv_timings *timings) 894{ 895 struct adv7604_state *state = to_state(sd); 896 int err; 897 898 v4l2_dbg(1, debug, sd, "%s", __func__); 899 900 if (adv7604_has_afe(state)) { 901 /* reset to default values */ 902 io_write(sd, 0x16, 0x43); 903 io_write(sd, 0x17, 0x5a); 904 } 905 /* disable embedded syncs for auto graphics mode */ 906 cp_write_and_or(sd, 0x81, 0xef, 0x00); 907 cp_write(sd, 0x8f, 0x00); 908 cp_write(sd, 0x90, 0x00); 909 cp_write(sd, 0xa2, 0x00); 910 cp_write(sd, 0xa3, 0x00); 911 cp_write(sd, 0xa4, 0x00); 912 cp_write(sd, 0xa5, 0x00); 913 cp_write(sd, 0xa6, 0x00); 914 cp_write(sd, 0xa7, 0x00); 915 cp_write(sd, 0xab, 0x00); 916 cp_write(sd, 0xac, 0x00); 917 918 if (is_analog_input(sd)) { 919 err = find_and_set_predefined_video_timings(sd, 920 0x01, adv7604_prim_mode_comp, timings); 921 if (err) 922 err = find_and_set_predefined_video_timings(sd, 923 0x02, adv7604_prim_mode_gr, timings); 924 } else if (is_digital_input(sd)) { 925 err = find_and_set_predefined_video_timings(sd, 926 0x05, adv7604_prim_mode_hdmi_comp, timings); 927 if (err) 928 err = find_and_set_predefined_video_timings(sd, 929 0x06, adv7604_prim_mode_hdmi_gr, timings); 930 } else { 931 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 932 __func__, state->selected_input); 933 err = -1; 934 } 935 936 937 return err; 938} 939 940static void configure_custom_video_timings(struct v4l2_subdev *sd, 941 const struct v4l2_bt_timings *bt) 942{ 943 struct adv7604_state *state = to_state(sd); 944 struct i2c_client *client = v4l2_get_subdevdata(sd); 945 u32 width = htotal(bt); 946 u32 height = vtotal(bt); 947 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; 948 u16 cp_start_eav = width - bt->hfrontporch; 949 u16 cp_start_vbi = height - bt->vfrontporch; 950 u16 cp_end_vbi = bt->vsync + bt->vbackporch; 951 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? 952 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0; 953 const u8 pll[2] = { 954 0xc0 | ((width >> 8) & 0x1f), 955 width & 0xff 956 }; 957 958 v4l2_dbg(2, debug, sd, "%s\n", __func__); 959 960 if (is_analog_input(sd)) { 961 /* auto graphics */ 962 io_write(sd, 0x00, 0x07); /* video std */ 963 io_write(sd, 0x01, 0x02); /* prim mode */ 964 /* enable embedded syncs for auto graphics mode */ 965 cp_write_and_or(sd, 0x81, 0xef, 0x10); 966 967 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ 968 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */ 969 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ 970 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) 971 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); 972 973 /* active video - horizontal timing */ 974 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); 975 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | 976 ((cp_start_eav >> 8) & 0x0f)); 977 cp_write(sd, 0xa4, cp_start_eav & 0xff); 978 979 /* active video - vertical timing */ 980 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); 981 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | 982 ((cp_end_vbi >> 8) & 0xf)); 983 cp_write(sd, 0xa7, cp_end_vbi & 0xff); 984 } else if (is_digital_input(sd)) { 985 /* set default prim_mode/vid_std for HDMI 986 according to [REF_03, c. 4.2] */ 987 io_write(sd, 0x00, 0x02); /* video std */ 988 io_write(sd, 0x01, 0x06); /* prim mode */ 989 } else { 990 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 991 __func__, state->selected_input); 992 } 993 994 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); 995 cp_write(sd, 0x90, ch1_fr_ll & 0xff); 996 cp_write(sd, 0xab, (height >> 4) & 0xff); 997 cp_write(sd, 0xac, (height & 0x0f) << 4); 998} 999 1000static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c) 1001{ 1002 struct adv7604_state *state = to_state(sd); 1003 u8 offset_buf[4]; 1004 1005 if (auto_offset) { 1006 offset_a = 0x3ff; 1007 offset_b = 0x3ff; 1008 offset_c = 0x3ff; 1009 } 1010 1011 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", 1012 __func__, auto_offset ? "Auto" : "Manual", 1013 offset_a, offset_b, offset_c); 1014 1015 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); 1016 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); 1017 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8); 1018 offset_buf[3] = offset_c & 0x0ff; 1019 1020 /* Registers must be written in this order with no i2c access in between */ 1021 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf)) 1022 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); 1023} 1024 1025static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c) 1026{ 1027 struct adv7604_state *state = to_state(sd); 1028 u8 gain_buf[4]; 1029 u8 gain_man = 1; 1030 u8 agc_mode_man = 1; 1031 1032 if (auto_gain) { 1033 gain_man = 0; 1034 agc_mode_man = 0; 1035 gain_a = 0x100; 1036 gain_b = 0x100; 1037 gain_c = 0x100; 1038 } 1039 1040 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", 1041 __func__, auto_gain ? "Auto" : "Manual", 1042 gain_a, gain_b, gain_c); 1043 1044 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4)); 1045 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); 1046 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8)); 1047 gain_buf[3] = ((gain_c & 0x0ff)); 1048 1049 /* Registers must be written in this order with no i2c access in between */ 1050 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf)) 1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); 1052} 1053 1054static void set_rgb_quantization_range(struct v4l2_subdev *sd) 1055{ 1056 struct adv7604_state *state = to_state(sd); 1057 bool rgb_output = io_read(sd, 0x02) & 0x02; 1058 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; 1059 1060 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", 1061 __func__, state->rgb_quantization_range, 1062 rgb_output, hdmi_signal); 1063 1064 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0); 1065 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0); 1066 1067 switch (state->rgb_quantization_range) { 1068 case V4L2_DV_RGB_RANGE_AUTO: 1069 if (state->selected_input == ADV7604_INPUT_VGA_RGB) { 1070 /* Receiving analog RGB signal 1071 * Set RGB full range (0-255) */ 1072 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1073 break; 1074 } 1075 1076 if (state->selected_input == ADV7604_INPUT_VGA_COMP) { 1077 /* Receiving analog YPbPr signal 1078 * Set automode */ 1079 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1080 break; 1081 } 1082 1083 if (hdmi_signal) { 1084 /* Receiving HDMI signal 1085 * Set automode */ 1086 io_write_and_or(sd, 0x02, 0x0f, 0xf0); 1087 break; 1088 } 1089 1090 /* Receiving DVI-D signal 1091 * ADV7604 selects RGB limited range regardless of 1092 * input format (CE/IT) in automatic mode */ 1093 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1094 /* RGB limited range (16-235) */ 1095 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1096 } else { 1097 /* RGB full range (0-255) */ 1098 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1099 1100 if (is_digital_input(sd) && rgb_output) { 1101 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1102 } else { 1103 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1104 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1105 } 1106 } 1107 break; 1108 case V4L2_DV_RGB_RANGE_LIMITED: 1109 if (state->selected_input == ADV7604_INPUT_VGA_COMP) { 1110 /* YCrCb limited range (16-235) */ 1111 io_write_and_or(sd, 0x02, 0x0f, 0x20); 1112 break; 1113 } 1114 1115 /* RGB limited range (16-235) */ 1116 io_write_and_or(sd, 0x02, 0x0f, 0x00); 1117 1118 break; 1119 case V4L2_DV_RGB_RANGE_FULL: 1120 if (state->selected_input == ADV7604_INPUT_VGA_COMP) { 1121 /* YCrCb full range (0-255) */ 1122 io_write_and_or(sd, 0x02, 0x0f, 0x60); 1123 break; 1124 } 1125 1126 /* RGB full range (0-255) */ 1127 io_write_and_or(sd, 0x02, 0x0f, 0x10); 1128 1129 if (is_analog_input(sd) || hdmi_signal) 1130 break; 1131 1132 /* Adjust gain/offset for DVI-D signals only */ 1133 if (rgb_output) { 1134 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40); 1135 } else { 1136 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0); 1137 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70); 1138 } 1139 break; 1140 } 1141} 1142 1143static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl) 1144{ 1145 struct v4l2_subdev *sd = to_sd(ctrl); 1146 struct adv7604_state *state = to_state(sd); 1147 1148 switch (ctrl->id) { 1149 case V4L2_CID_BRIGHTNESS: 1150 cp_write(sd, 0x3c, ctrl->val); 1151 return 0; 1152 case V4L2_CID_CONTRAST: 1153 cp_write(sd, 0x3a, ctrl->val); 1154 return 0; 1155 case V4L2_CID_SATURATION: 1156 cp_write(sd, 0x3b, ctrl->val); 1157 return 0; 1158 case V4L2_CID_HUE: 1159 cp_write(sd, 0x3d, ctrl->val); 1160 return 0; 1161 case V4L2_CID_DV_RX_RGB_RANGE: 1162 state->rgb_quantization_range = ctrl->val; 1163 set_rgb_quantization_range(sd); 1164 return 0; 1165 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE: 1166 if (!adv7604_has_afe(state)) 1167 return -EINVAL; 1168 /* Set the analog sampling phase. This is needed to find the 1169 best sampling phase for analog video: an application or 1170 driver has to try a number of phases and analyze the picture 1171 quality before settling on the best performing phase. */ 1172 afe_write(sd, 0xc8, ctrl->val); 1173 return 0; 1174 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL: 1175 /* Use the default blue color for free running mode, 1176 or supply your own. */ 1177 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2)); 1178 return 0; 1179 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: 1180 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); 1181 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); 1182 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); 1183 return 0; 1184 } 1185 return -EINVAL; 1186} 1187 1188/* ----------------------------------------------------------------------- */ 1189 1190static inline bool no_power(struct v4l2_subdev *sd) 1191{ 1192 /* Entire chip or CP powered off */ 1193 return io_read(sd, 0x0c) & 0x24; 1194} 1195 1196static inline bool no_signal_tmds(struct v4l2_subdev *sd) 1197{ 1198 struct adv7604_state *state = to_state(sd); 1199 1200 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); 1201} 1202 1203static inline bool no_lock_tmds(struct v4l2_subdev *sd) 1204{ 1205 struct adv7604_state *state = to_state(sd); 1206 const struct adv7604_chip_info *info = state->info; 1207 1208 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; 1209} 1210 1211static inline bool is_hdmi(struct v4l2_subdev *sd) 1212{ 1213 return hdmi_read(sd, 0x05) & 0x80; 1214} 1215 1216static inline bool no_lock_sspd(struct v4l2_subdev *sd) 1217{ 1218 struct adv7604_state *state = to_state(sd); 1219 1220 /* 1221 * Chips without a AFE don't expose registers for the SSPD, so just assume 1222 * that we have a lock. 1223 */ 1224 if (adv7604_has_afe(state)) 1225 return false; 1226 1227 /* TODO channel 2 */ 1228 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); 1229} 1230 1231static inline bool no_lock_stdi(struct v4l2_subdev *sd) 1232{ 1233 /* TODO channel 2 */ 1234 return !(cp_read(sd, 0xb1) & 0x80); 1235} 1236 1237static inline bool no_signal(struct v4l2_subdev *sd) 1238{ 1239 bool ret; 1240 1241 ret = no_power(sd); 1242 1243 ret |= no_lock_stdi(sd); 1244 ret |= no_lock_sspd(sd); 1245 1246 if (is_digital_input(sd)) { 1247 ret |= no_lock_tmds(sd); 1248 ret |= no_signal_tmds(sd); 1249 } 1250 1251 return ret; 1252} 1253 1254static inline bool no_lock_cp(struct v4l2_subdev *sd) 1255{ 1256 struct adv7604_state *state = to_state(sd); 1257 1258 if (!adv7604_has_afe(state)) 1259 return false; 1260 1261 /* CP has detected a non standard number of lines on the incoming 1262 video compared to what it is configured to receive by s_dv_timings */ 1263 return io_read(sd, 0x12) & 0x01; 1264} 1265 1266static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status) 1267{ 1268 *status = 0; 1269 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; 1270 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; 1271 if (no_lock_cp(sd)) 1272 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK; 1273 1274 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); 1275 1276 return 0; 1277} 1278 1279/* ----------------------------------------------------------------------- */ 1280 1281struct stdi_readback { 1282 u16 bl, lcf, lcvs; 1283 u8 hs_pol, vs_pol; 1284 bool interlaced; 1285}; 1286 1287static int stdi2dv_timings(struct v4l2_subdev *sd, 1288 struct stdi_readback *stdi, 1289 struct v4l2_dv_timings *timings) 1290{ 1291 struct adv7604_state *state = to_state(sd); 1292 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl; 1293 u32 pix_clk; 1294 int i; 1295 1296 for (i = 0; adv7604_timings[i].bt.height; i++) { 1297 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1) 1298 continue; 1299 if (adv7604_timings[i].bt.vsync != stdi->lcvs) 1300 continue; 1301 1302 pix_clk = hfreq * htotal(&adv7604_timings[i].bt); 1303 1304 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) && 1305 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) { 1306 *timings = adv7604_timings[i]; 1307 return 0; 1308 } 1309 } 1310 1311 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 1312 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1313 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1314 timings)) 1315 return 0; 1316 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, 1317 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | 1318 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), 1319 state->aspect_ratio, timings)) 1320 return 0; 1321 1322 v4l2_dbg(2, debug, sd, 1323 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n", 1324 __func__, stdi->lcvs, stdi->lcf, stdi->bl, 1325 stdi->hs_pol, stdi->vs_pol); 1326 return -1; 1327} 1328 1329 1330static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) 1331{ 1332 struct adv7604_state *state = to_state(sd); 1333 const struct adv7604_chip_info *info = state->info; 1334 u8 polarity; 1335 1336 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1337 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); 1338 return -1; 1339 } 1340 1341 /* read STDI */ 1342 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); 1343 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); 1344 stdi->lcvs = cp_read(sd, 0xb3) >> 3; 1345 stdi->interlaced = io_read(sd, 0x12) & 0x10; 1346 1347 if (adv7604_has_afe(state)) { 1348 /* read SSPD */ 1349 polarity = cp_read(sd, 0xb5); 1350 if ((polarity & 0x03) == 0x01) { 1351 stdi->hs_pol = polarity & 0x10 1352 ? (polarity & 0x08 ? '+' : '-') : 'x'; 1353 stdi->vs_pol = polarity & 0x40 1354 ? (polarity & 0x20 ? '+' : '-') : 'x'; 1355 } else { 1356 stdi->hs_pol = 'x'; 1357 stdi->vs_pol = 'x'; 1358 } 1359 } else { 1360 polarity = hdmi_read(sd, 0x05); 1361 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; 1362 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; 1363 } 1364 1365 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { 1366 v4l2_dbg(2, debug, sd, 1367 "%s: signal lost during readout of STDI/SSPD\n", __func__); 1368 return -1; 1369 } 1370 1371 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { 1372 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); 1373 memset(stdi, 0, sizeof(struct stdi_readback)); 1374 return -1; 1375 } 1376 1377 v4l2_dbg(2, debug, sd, 1378 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", 1379 __func__, stdi->lcf, stdi->bl, stdi->lcvs, 1380 stdi->hs_pol, stdi->vs_pol, 1381 stdi->interlaced ? "interlaced" : "progressive"); 1382 1383 return 0; 1384} 1385 1386static int adv7604_enum_dv_timings(struct v4l2_subdev *sd, 1387 struct v4l2_enum_dv_timings *timings) 1388{ 1389 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1) 1390 return -EINVAL; 1391 memset(timings->reserved, 0, sizeof(timings->reserved)); 1392 timings->timings = adv7604_timings[timings->index]; 1393 return 0; 1394} 1395 1396static int adv7604_dv_timings_cap(struct v4l2_subdev *sd, 1397 struct v4l2_dv_timings_cap *cap) 1398{ 1399 cap->type = V4L2_DV_BT_656_1120; 1400 cap->bt.max_width = 1920; 1401 cap->bt.max_height = 1200; 1402 cap->bt.min_pixelclock = 25000000; 1403 if (is_digital_input(sd)) 1404 cap->bt.max_pixelclock = 225000000; 1405 else 1406 cap->bt.max_pixelclock = 170000000; 1407 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | 1408 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT; 1409 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | 1410 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM; 1411 return 0; 1412} 1413 1414/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings 1415 if the format is listed in adv7604_timings[] */ 1416static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, 1417 struct v4l2_dv_timings *timings) 1418{ 1419 int i; 1420 1421 for (i = 0; adv7604_timings[i].bt.width; i++) { 1422 if (v4l2_match_dv_timings(timings, &adv7604_timings[i], 1423 is_digital_input(sd) ? 250000 : 1000000)) { 1424 *timings = adv7604_timings[i]; 1425 break; 1426 } 1427 } 1428} 1429 1430static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1431{ 1432 unsigned int freq; 1433 int a, b; 1434 1435 a = hdmi_read(sd, 0x06); 1436 b = hdmi_read(sd, 0x3b); 1437 if (a < 0 || b < 0) 1438 return 0; 1439 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000; 1440 1441 if (is_hdmi(sd)) { 1442 /* adjust for deep color mode */ 1443 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; 1444 1445 freq = freq * 8 / bits_per_channel; 1446 } 1447 1448 return freq; 1449} 1450 1451static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) 1452{ 1453 int a, b; 1454 1455 a = hdmi_read(sd, 0x51); 1456 b = hdmi_read(sd, 0x52); 1457 if (a < 0 || b < 0) 1458 return 0; 1459 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; 1460} 1461 1462static int adv7604_query_dv_timings(struct v4l2_subdev *sd, 1463 struct v4l2_dv_timings *timings) 1464{ 1465 struct adv7604_state *state = to_state(sd); 1466 const struct adv7604_chip_info *info = state->info; 1467 struct v4l2_bt_timings *bt = &timings->bt; 1468 struct stdi_readback stdi; 1469 1470 if (!timings) 1471 return -EINVAL; 1472 1473 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1474 1475 if (no_signal(sd)) { 1476 state->restart_stdi_once = true; 1477 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); 1478 return -ENOLINK; 1479 } 1480 1481 /* read STDI */ 1482 if (read_stdi(sd, &stdi)) { 1483 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); 1484 return -ENOLINK; 1485 } 1486 bt->interlaced = stdi.interlaced ? 1487 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE; 1488 1489 if (is_digital_input(sd)) { 1490 timings->type = V4L2_DV_BT_656_1120; 1491 1492 /* FIXME: All masks are incorrect for ADV7611 */ 1493 bt->width = hdmi_read16(sd, 0x07, 0xfff); 1494 bt->height = hdmi_read16(sd, 0x09, 0xfff); 1495 bt->pixelclock = info->read_hdmi_pixelclock(sd); 1496 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff); 1497 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff); 1498 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff); 1499 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2; 1500 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2; 1501 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2; 1502 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | 1503 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); 1504 if (bt->interlaced == V4L2_DV_INTERLACED) { 1505 bt->height += hdmi_read16(sd, 0x0b, 0xfff); 1506 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2; 1507 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2; 1508 bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2; 1509 } 1510 adv7604_fill_optional_dv_timings_fields(sd, timings); 1511 } else { 1512 /* find format 1513 * Since LCVS values are inaccurate [REF_03, p. 275-276], 1514 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. 1515 */ 1516 if (!stdi2dv_timings(sd, &stdi, timings)) 1517 goto found; 1518 stdi.lcvs += 1; 1519 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); 1520 if (!stdi2dv_timings(sd, &stdi, timings)) 1521 goto found; 1522 stdi.lcvs -= 2; 1523 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); 1524 if (stdi2dv_timings(sd, &stdi, timings)) { 1525 /* 1526 * The STDI block may measure wrong values, especially 1527 * for lcvs and lcf. If the driver can not find any 1528 * valid timing, the STDI block is restarted to measure 1529 * the video timings again. The function will return an 1530 * error, but the restart of STDI will generate a new 1531 * STDI interrupt and the format detection process will 1532 * restart. 1533 */ 1534 if (state->restart_stdi_once) { 1535 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); 1536 /* TODO restart STDI for Sync Channel 2 */ 1537 /* enter one-shot mode */ 1538 cp_write_and_or(sd, 0x86, 0xf9, 0x00); 1539 /* trigger STDI restart */ 1540 cp_write_and_or(sd, 0x86, 0xf9, 0x04); 1541 /* reset to continuous mode */ 1542 cp_write_and_or(sd, 0x86, 0xf9, 0x02); 1543 state->restart_stdi_once = false; 1544 return -ENOLINK; 1545 } 1546 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); 1547 return -ERANGE; 1548 } 1549 state->restart_stdi_once = true; 1550 } 1551found: 1552 1553 if (no_signal(sd)) { 1554 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); 1555 memset(timings, 0, sizeof(struct v4l2_dv_timings)); 1556 return -ENOLINK; 1557 } 1558 1559 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1560 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1561 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1562 __func__, (u32)bt->pixelclock); 1563 return -ERANGE; 1564 } 1565 1566 if (debug > 1) 1567 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ", 1568 timings, true); 1569 1570 return 0; 1571} 1572 1573static int adv7604_s_dv_timings(struct v4l2_subdev *sd, 1574 struct v4l2_dv_timings *timings) 1575{ 1576 struct adv7604_state *state = to_state(sd); 1577 struct v4l2_bt_timings *bt; 1578 int err; 1579 1580 if (!timings) 1581 return -EINVAL; 1582 1583 if (v4l2_match_dv_timings(&state->timings, timings, 0)) { 1584 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); 1585 return 0; 1586 } 1587 1588 bt = &timings->bt; 1589 1590 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || 1591 (is_digital_input(sd) && bt->pixelclock > 225000000)) { 1592 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", 1593 __func__, (u32)bt->pixelclock); 1594 return -ERANGE; 1595 } 1596 1597 adv7604_fill_optional_dv_timings_fields(sd, timings); 1598 1599 state->timings = *timings; 1600 1601 cp_write_and_or(sd, 0x91, 0xbf, bt->interlaced ? 0x40 : 0x00); 1602 1603 /* Use prim_mode and vid_std when available */ 1604 err = configure_predefined_video_timings(sd, timings); 1605 if (err) { 1606 /* custom settings when the video format 1607 does not have prim_mode/vid_std */ 1608 configure_custom_video_timings(sd, bt); 1609 } 1610 1611 set_rgb_quantization_range(sd); 1612 1613 if (debug > 1) 1614 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ", 1615 timings, true); 1616 return 0; 1617} 1618 1619static int adv7604_g_dv_timings(struct v4l2_subdev *sd, 1620 struct v4l2_dv_timings *timings) 1621{ 1622 struct adv7604_state *state = to_state(sd); 1623 1624 *timings = state->timings; 1625 return 0; 1626} 1627 1628static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) 1629{ 1630 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); 1631} 1632 1633static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) 1634{ 1635 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); 1636} 1637 1638static void enable_input(struct v4l2_subdev *sd) 1639{ 1640 struct adv7604_state *state = to_state(sd); 1641 1642 if (is_analog_input(sd)) { 1643 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ 1644 } else if (is_digital_input(sd)) { 1645 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input); 1646 state->info->set_termination(sd, true); 1647 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ 1648 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */ 1649 } else { 1650 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1651 __func__, state->selected_input); 1652 } 1653} 1654 1655static void disable_input(struct v4l2_subdev *sd) 1656{ 1657 struct adv7604_state *state = to_state(sd); 1658 1659 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */ 1660 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */ 1661 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ 1662 state->info->set_termination(sd, false); 1663} 1664 1665static void select_input(struct v4l2_subdev *sd) 1666{ 1667 struct adv7604_state *state = to_state(sd); 1668 const struct adv7604_chip_info *info = state->info; 1669 1670 if (is_analog_input(sd)) { 1671 adv7604_write_reg_seq(sd, info->recommended_settings[0]); 1672 1673 afe_write(sd, 0x00, 0x08); /* power up ADC */ 1674 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ 1675 afe_write(sd, 0xc8, 0x00); /* phase control */ 1676 } else if (is_digital_input(sd)) { 1677 hdmi_write(sd, 0x00, state->selected_input & 0x03); 1678 1679 adv7604_write_reg_seq(sd, info->recommended_settings[1]); 1680 1681 if (adv7604_has_afe(state)) { 1682 afe_write(sd, 0x00, 0xff); /* power down ADC */ 1683 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ 1684 afe_write(sd, 0xc8, 0x40); /* phase control */ 1685 } 1686 1687 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ 1688 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ 1689 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ 1690 } else { 1691 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", 1692 __func__, state->selected_input); 1693 } 1694} 1695 1696static int adv7604_s_routing(struct v4l2_subdev *sd, 1697 u32 input, u32 output, u32 config) 1698{ 1699 struct adv7604_state *state = to_state(sd); 1700 1701 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", 1702 __func__, input, state->selected_input); 1703 1704 if (input == state->selected_input) 1705 return 0; 1706 1707 if (input > state->info->max_port) 1708 return -EINVAL; 1709 1710 state->selected_input = input; 1711 1712 disable_input(sd); 1713 1714 select_input(sd); 1715 1716 enable_input(sd); 1717 1718 return 0; 1719} 1720 1721static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index, 1722 enum v4l2_mbus_pixelcode *code) 1723{ 1724 if (index) 1725 return -EINVAL; 1726 /* Good enough for now */ 1727 *code = V4L2_MBUS_FMT_FIXED; 1728 return 0; 1729} 1730 1731static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd, 1732 struct v4l2_mbus_framefmt *fmt) 1733{ 1734 struct adv7604_state *state = to_state(sd); 1735 1736 fmt->width = state->timings.bt.width; 1737 fmt->height = state->timings.bt.height; 1738 fmt->code = V4L2_MBUS_FMT_FIXED; 1739 fmt->field = V4L2_FIELD_NONE; 1740 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) { 1741 fmt->colorspace = (state->timings.bt.height <= 576) ? 1742 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709; 1743 } 1744 return 0; 1745} 1746 1747static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled) 1748{ 1749 struct adv7604_state *state = to_state(sd); 1750 const struct adv7604_chip_info *info = state->info; 1751 const u8 irq_reg_0x43 = io_read(sd, 0x43); 1752 const u8 irq_reg_0x6b = io_read(sd, 0x6b); 1753 const u8 irq_reg_0x70 = io_read(sd, 0x70); 1754 u8 fmt_change_digital; 1755 u8 fmt_change; 1756 u8 tx_5v; 1757 1758 if (irq_reg_0x43) 1759 io_write(sd, 0x44, irq_reg_0x43); 1760 if (irq_reg_0x70) 1761 io_write(sd, 0x71, irq_reg_0x70); 1762 if (irq_reg_0x6b) 1763 io_write(sd, 0x6c, irq_reg_0x6b); 1764 1765 v4l2_dbg(2, debug, sd, "%s: ", __func__); 1766 1767 /* format change */ 1768 fmt_change = irq_reg_0x43 & 0x98; 1769 fmt_change_digital = is_digital_input(sd) 1770 ? irq_reg_0x6b & info->fmt_change_digital_mask 1771 : 0; 1772 1773 if (fmt_change || fmt_change_digital) { 1774 v4l2_dbg(1, debug, sd, 1775 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n", 1776 __func__, fmt_change, fmt_change_digital); 1777 1778 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL); 1779 1780 if (handled) 1781 *handled = true; 1782 } 1783 /* HDMI/DVI mode */ 1784 if (irq_reg_0x6b & 0x01) { 1785 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, 1786 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); 1787 set_rgb_quantization_range(sd); 1788 if (handled) 1789 *handled = true; 1790 } 1791 1792 /* tx 5v detect */ 1793 tx_5v = io_read(sd, 0x70) & info->cable_det_mask; 1794 if (tx_5v) { 1795 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); 1796 io_write(sd, 0x71, tx_5v); 1797 adv7604_s_detect_tx_5v_ctrl(sd); 1798 if (handled) 1799 *handled = true; 1800 } 1801 return 0; 1802} 1803 1804static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1805{ 1806 struct adv7604_state *state = to_state(sd); 1807 u8 *data = NULL; 1808 1809 if (edid->pad > ADV7604_EDID_PORT_D) 1810 return -EINVAL; 1811 if (edid->blocks == 0) 1812 return -EINVAL; 1813 if (edid->blocks > 2) 1814 return -EINVAL; 1815 if (edid->start_block > 1) 1816 return -EINVAL; 1817 if (edid->start_block == 1) 1818 edid->blocks = 1; 1819 1820 if (edid->blocks > state->edid.blocks) 1821 edid->blocks = state->edid.blocks; 1822 1823 switch (edid->pad) { 1824 case ADV7604_EDID_PORT_A: 1825 case ADV7604_EDID_PORT_B: 1826 case ADV7604_EDID_PORT_C: 1827 case ADV7604_EDID_PORT_D: 1828 if (state->edid.present & (1 << edid->pad)) 1829 data = state->edid.edid; 1830 break; 1831 default: 1832 return -EINVAL; 1833 break; 1834 } 1835 if (!data) 1836 return -ENODATA; 1837 1838 memcpy(edid->edid, 1839 data + edid->start_block * 128, 1840 edid->blocks * 128); 1841 return 0; 1842} 1843 1844static int get_edid_spa_location(const u8 *edid) 1845{ 1846 u8 d; 1847 1848 if ((edid[0x7e] != 1) || 1849 (edid[0x80] != 0x02) || 1850 (edid[0x81] != 0x03)) { 1851 return -1; 1852 } 1853 1854 /* search Vendor Specific Data Block (tag 3) */ 1855 d = edid[0x82] & 0x7f; 1856 if (d > 4) { 1857 int i = 0x84; 1858 int end = 0x80 + d; 1859 1860 do { 1861 u8 tag = edid[i] >> 5; 1862 u8 len = edid[i] & 0x1f; 1863 1864 if ((tag == 3) && (len >= 5)) 1865 return i + 4; 1866 i += len + 1; 1867 } while (i < end); 1868 } 1869 return -1; 1870} 1871 1872static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) 1873{ 1874 struct adv7604_state *state = to_state(sd); 1875 const struct adv7604_chip_info *info = state->info; 1876 int spa_loc; 1877 int tmp = 0; 1878 int err; 1879 int i; 1880 1881 if (edid->pad > ADV7604_EDID_PORT_D) 1882 return -EINVAL; 1883 if (edid->start_block != 0) 1884 return -EINVAL; 1885 if (edid->blocks == 0) { 1886 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 1887 state->edid.present &= ~(1 << edid->pad); 1888 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present); 1889 rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present); 1890 1891 /* Fall back to a 16:9 aspect ratio */ 1892 state->aspect_ratio.numerator = 16; 1893 state->aspect_ratio.denominator = 9; 1894 1895 if (!state->edid.present) 1896 state->edid.blocks = 0; 1897 1898 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", 1899 __func__, edid->pad, state->edid.present); 1900 return 0; 1901 } 1902 if (edid->blocks > 2) { 1903 edid->blocks = 2; 1904 return -E2BIG; 1905 } 1906 1907 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", 1908 __func__, edid->pad, state->edid.present); 1909 1910 /* Disable hotplug and I2C access to EDID RAM from DDC port */ 1911 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); 1912 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp); 1913 rep_write_and_or(sd, info->edid_enable_reg, 0xf0, 0x00); 1914 1915 spa_loc = get_edid_spa_location(edid->edid); 1916 if (spa_loc < 0) 1917 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */ 1918 1919 switch (edid->pad) { 1920 case ADV7604_EDID_PORT_A: 1921 state->spa_port_a[0] = edid->edid[spa_loc]; 1922 state->spa_port_a[1] = edid->edid[spa_loc + 1]; 1923 break; 1924 case ADV7604_EDID_PORT_B: 1925 rep_write(sd, 0x70, edid->edid[spa_loc]); 1926 rep_write(sd, 0x71, edid->edid[spa_loc + 1]); 1927 break; 1928 case ADV7604_EDID_PORT_C: 1929 rep_write(sd, 0x72, edid->edid[spa_loc]); 1930 rep_write(sd, 0x73, edid->edid[spa_loc + 1]); 1931 break; 1932 case ADV7604_EDID_PORT_D: 1933 rep_write(sd, 0x74, edid->edid[spa_loc]); 1934 rep_write(sd, 0x75, edid->edid[spa_loc + 1]); 1935 break; 1936 default: 1937 return -EINVAL; 1938 } 1939 1940 if (info->type == ADV7604) { 1941 rep_write(sd, 0x76, spa_loc & 0xff); 1942 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc & 0x100) >> 2); 1943 } else { 1944 /* FIXME: Where is the SPA location LSB register ? */ 1945 rep_write_and_or(sd, 0x71, 0xfe, (spa_loc & 0x100) >> 8); 1946 } 1947 1948 edid->edid[spa_loc] = state->spa_port_a[0]; 1949 edid->edid[spa_loc + 1] = state->spa_port_a[1]; 1950 1951 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); 1952 state->edid.blocks = edid->blocks; 1953 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], 1954 edid->edid[0x16]); 1955 state->edid.present |= 1 << edid->pad; 1956 1957 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); 1958 if (err < 0) { 1959 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); 1960 return err; 1961 } 1962 1963 /* adv7604 calculates the checksums and enables I2C access to internal 1964 EDID RAM from DDC port. */ 1965 rep_write_and_or(sd, info->edid_enable_reg, 0xf0, state->edid.present); 1966 1967 for (i = 0; i < 1000; i++) { 1968 if (rep_read(sd, info->edid_status_reg) & state->edid.present) 1969 break; 1970 mdelay(1); 1971 } 1972 if (i == 1000) { 1973 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); 1974 return -EIO; 1975 } 1976 1977 1978 /* enable hotplug after 100 ms */ 1979 queue_delayed_work(state->work_queues, 1980 &state->delayed_work_enable_hotplug, HZ / 10); 1981 return 0; 1982} 1983 1984/*********** avi info frame CEA-861-E **************/ 1985 1986static void print_avi_infoframe(struct v4l2_subdev *sd) 1987{ 1988 int i; 1989 u8 buf[14]; 1990 u8 avi_len; 1991 u8 avi_ver; 1992 1993 if (!is_hdmi(sd)) { 1994 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n"); 1995 return; 1996 } 1997 if (!(io_read(sd, 0x60) & 0x01)) { 1998 v4l2_info(sd, "AVI infoframe not received\n"); 1999 return; 2000 } 2001 2002 if (io_read(sd, 0x83) & 0x01) { 2003 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n"); 2004 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 2005 if (io_read(sd, 0x83) & 0x01) { 2006 v4l2_info(sd, "AVI infoframe checksum error still present\n"); 2007 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */ 2008 } 2009 } 2010 2011 avi_len = infoframe_read(sd, 0xe2); 2012 avi_ver = infoframe_read(sd, 0xe1); 2013 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", 2014 avi_ver, avi_len); 2015 2016 if (avi_ver != 0x02) 2017 return; 2018 2019 for (i = 0; i < 14; i++) 2020 buf[i] = infoframe_read(sd, i); 2021 2022 v4l2_info(sd, 2023 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 2024 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7], 2025 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]); 2026} 2027 2028static int adv7604_log_status(struct v4l2_subdev *sd) 2029{ 2030 struct adv7604_state *state = to_state(sd); 2031 const struct adv7604_chip_info *info = state->info; 2032 struct v4l2_dv_timings timings; 2033 struct stdi_readback stdi; 2034 u8 reg_io_0x02 = io_read(sd, 0x02); 2035 u8 edid_enabled; 2036 u8 cable_det; 2037 2038 static const char * const csc_coeff_sel_rb[16] = { 2039 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", 2040 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", 2041 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", 2042 "reserved", "reserved", "reserved", "reserved", "manual" 2043 }; 2044 static const char * const input_color_space_txt[16] = { 2045 "RGB limited range (16-235)", "RGB full range (0-255)", 2046 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", 2047 "xvYCC Bt.601", "xvYCC Bt.709", 2048 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", 2049 "invalid", "invalid", "invalid", "invalid", "invalid", 2050 "invalid", "invalid", "automatic" 2051 }; 2052 static const char * const rgb_quantization_range_txt[] = { 2053 "Automatic", 2054 "RGB limited range (16-235)", 2055 "RGB full range (0-255)", 2056 }; 2057 static const char * const deep_color_mode_txt[4] = { 2058 "8-bits per channel", 2059 "10-bits per channel", 2060 "12-bits per channel", 2061 "16-bits per channel (not supported)" 2062 }; 2063 2064 v4l2_info(sd, "-----Chip status-----\n"); 2065 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); 2066 edid_enabled = rep_read(sd, info->edid_status_reg); 2067 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", 2068 ((edid_enabled & 0x01) ? "Yes" : "No"), 2069 ((edid_enabled & 0x02) ? "Yes" : "No"), 2070 ((edid_enabled & 0x04) ? "Yes" : "No"), 2071 ((edid_enabled & 0x08) ? "Yes" : "No")); 2072 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ? 2073 "enabled" : "disabled"); 2074 2075 v4l2_info(sd, "-----Signal status-----\n"); 2076 cable_det = info->read_cable_det(sd); 2077 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", 2078 ((cable_det & 0x01) ? "Yes" : "No"), 2079 ((cable_det & 0x02) ? "Yes" : "No"), 2080 ((cable_det & 0x04) ? "Yes" : "No"), 2081 ((cable_det & 0x08) ? "Yes" : "No")); 2082 v4l2_info(sd, "TMDS signal detected: %s\n", 2083 no_signal_tmds(sd) ? "false" : "true"); 2084 v4l2_info(sd, "TMDS signal locked: %s\n", 2085 no_lock_tmds(sd) ? "false" : "true"); 2086 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); 2087 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); 2088 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); 2089 v4l2_info(sd, "CP free run: %s\n", 2090 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off")); 2091 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", 2092 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, 2093 (io_read(sd, 0x01) & 0x70) >> 4); 2094 2095 v4l2_info(sd, "-----Video Timings-----\n"); 2096 if (read_stdi(sd, &stdi)) 2097 v4l2_info(sd, "STDI: not locked\n"); 2098 else 2099 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n", 2100 stdi.lcf, stdi.bl, stdi.lcvs, 2101 stdi.interlaced ? "interlaced" : "progressive", 2102 stdi.hs_pol, stdi.vs_pol); 2103 if (adv7604_query_dv_timings(sd, &timings)) 2104 v4l2_info(sd, "No video detected\n"); 2105 else 2106 v4l2_print_dv_timings(sd->name, "Detected format: ", 2107 &timings, true); 2108 v4l2_print_dv_timings(sd->name, "Configured format: ", 2109 &state->timings, true); 2110 2111 if (no_signal(sd)) 2112 return 0; 2113 2114 v4l2_info(sd, "-----Color space-----\n"); 2115 v4l2_info(sd, "RGB quantization range ctrl: %s\n", 2116 rgb_quantization_range_txt[state->rgb_quantization_range]); 2117 v4l2_info(sd, "Input color space: %s\n", 2118 input_color_space_txt[reg_io_0x02 >> 4]); 2119 v4l2_info(sd, "Output color space: %s %s, saturator %s\n", 2120 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr", 2121 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)", 2122 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ? 2123 "enabled" : "disabled"); 2124 v4l2_info(sd, "Color space conversion: %s\n", 2125 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]); 2126 2127 if (!is_digital_input(sd)) 2128 return 0; 2129 2130 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); 2131 v4l2_info(sd, "Digital video port selected: %c\n", 2132 (hdmi_read(sd, 0x00) & 0x03) + 'A'); 2133 v4l2_info(sd, "HDCP encrypted content: %s\n", 2134 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); 2135 v4l2_info(sd, "HDCP keys read: %s%s\n", 2136 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", 2137 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); 2138 if (!is_hdmi(sd)) { 2139 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; 2140 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; 2141 bool audio_mute = io_read(sd, 0x65) & 0x40; 2142 2143 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", 2144 audio_pll_locked ? "locked" : "not locked", 2145 audio_sample_packet_detect ? "detected" : "not detected", 2146 audio_mute ? "muted" : "enabled"); 2147 if (audio_pll_locked && audio_sample_packet_detect) { 2148 v4l2_info(sd, "Audio format: %s\n", 2149 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); 2150 } 2151 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + 2152 (hdmi_read(sd, 0x5c) << 8) + 2153 (hdmi_read(sd, 0x5d) & 0xf0)); 2154 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + 2155 (hdmi_read(sd, 0x5e) << 8) + 2156 hdmi_read(sd, 0x5f)); 2157 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); 2158 2159 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); 2160 2161 print_avi_infoframe(sd); 2162 } 2163 2164 return 0; 2165} 2166 2167/* ----------------------------------------------------------------------- */ 2168 2169static const struct v4l2_ctrl_ops adv7604_ctrl_ops = { 2170 .s_ctrl = adv7604_s_ctrl, 2171}; 2172 2173static const struct v4l2_subdev_core_ops adv7604_core_ops = { 2174 .log_status = adv7604_log_status, 2175 .interrupt_service_routine = adv7604_isr, 2176#ifdef CONFIG_VIDEO_ADV_DEBUG 2177 .g_register = adv7604_g_register, 2178 .s_register = adv7604_s_register, 2179#endif 2180}; 2181 2182static const struct v4l2_subdev_video_ops adv7604_video_ops = { 2183 .s_routing = adv7604_s_routing, 2184 .g_input_status = adv7604_g_input_status, 2185 .s_dv_timings = adv7604_s_dv_timings, 2186 .g_dv_timings = adv7604_g_dv_timings, 2187 .query_dv_timings = adv7604_query_dv_timings, 2188 .enum_dv_timings = adv7604_enum_dv_timings, 2189 .dv_timings_cap = adv7604_dv_timings_cap, 2190 .enum_mbus_fmt = adv7604_enum_mbus_fmt, 2191 .g_mbus_fmt = adv7604_g_mbus_fmt, 2192 .try_mbus_fmt = adv7604_g_mbus_fmt, 2193 .s_mbus_fmt = adv7604_g_mbus_fmt, 2194}; 2195 2196static const struct v4l2_subdev_pad_ops adv7604_pad_ops = { 2197 .get_edid = adv7604_get_edid, 2198 .set_edid = adv7604_set_edid, 2199}; 2200 2201static const struct v4l2_subdev_ops adv7604_ops = { 2202 .core = &adv7604_core_ops, 2203 .video = &adv7604_video_ops, 2204 .pad = &adv7604_pad_ops, 2205}; 2206 2207/* -------------------------- custom ctrls ---------------------------------- */ 2208 2209static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = { 2210 .ops = &adv7604_ctrl_ops, 2211 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE, 2212 .name = "Analog Sampling Phase", 2213 .type = V4L2_CTRL_TYPE_INTEGER, 2214 .min = 0, 2215 .max = 0x1f, 2216 .step = 1, 2217 .def = 0, 2218}; 2219 2220static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = { 2221 .ops = &adv7604_ctrl_ops, 2222 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL, 2223 .name = "Free Running Color, Manual", 2224 .type = V4L2_CTRL_TYPE_BOOLEAN, 2225 .min = false, 2226 .max = true, 2227 .step = 1, 2228 .def = false, 2229}; 2230 2231static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = { 2232 .ops = &adv7604_ctrl_ops, 2233 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR, 2234 .name = "Free Running Color", 2235 .type = V4L2_CTRL_TYPE_INTEGER, 2236 .min = 0x0, 2237 .max = 0xffffff, 2238 .step = 0x1, 2239 .def = 0x0, 2240}; 2241 2242/* ----------------------------------------------------------------------- */ 2243 2244static int adv7604_core_init(struct v4l2_subdev *sd) 2245{ 2246 struct adv7604_state *state = to_state(sd); 2247 const struct adv7604_chip_info *info = state->info; 2248 struct adv7604_platform_data *pdata = &state->pdata; 2249 2250 hdmi_write(sd, 0x48, 2251 (pdata->disable_pwrdnb ? 0x80 : 0) | 2252 (pdata->disable_cable_det_rst ? 0x40 : 0)); 2253 2254 disable_input(sd); 2255 2256 /* power */ 2257 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ 2258 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ 2259 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ 2260 2261 /* video format */ 2262 io_write_and_or(sd, 0x02, 0xf0, 2263 pdata->alt_gamma << 3 | 2264 pdata->op_656_range << 2 | 2265 pdata->rgb_out << 1 | 2266 pdata->alt_data_sat << 0); 2267 io_write(sd, 0x03, pdata->op_format_sel); 2268 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5); 2269 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 | 2270 pdata->insert_av_codes << 2 | 2271 pdata->replicate_av_codes << 1 | 2272 pdata->invert_cbcr << 0); 2273 2274 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ 2275 2276 /* VS, HS polarities */ 2277 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1); 2278 2279 /* Adjust drive strength */ 2280 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | 2281 pdata->dr_str_clk << 2 | 2282 pdata->dr_str_sync); 2283 2284 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ 2285 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ 2286 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - 2287 ADI recommended setting [REF_01, c. 2.3.3] */ 2288 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - 2289 ADI recommended setting [REF_01, c. 2.3.3] */ 2290 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution 2291 for digital formats */ 2292 2293 /* HDMI audio */ 2294 hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ 2295 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */ 2296 hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ 2297 2298 /* TODO from platform data */ 2299 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ 2300 2301 if (adv7604_has_afe(state)) { 2302 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ 2303 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4); 2304 } 2305 2306 /* interrupts */ 2307 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ 2308 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ 2309 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */ 2310 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ 2311 info->setup_irqs(sd); 2312 2313 return v4l2_ctrl_handler_setup(sd->ctrl_handler); 2314} 2315 2316static void adv7604_setup_irqs(struct v4l2_subdev *sd) 2317{ 2318 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ 2319} 2320 2321static void adv7611_setup_irqs(struct v4l2_subdev *sd) 2322{ 2323 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ 2324} 2325 2326static void adv7604_unregister_clients(struct adv7604_state *state) 2327{ 2328 if (state->i2c_avlink) 2329 i2c_unregister_device(state->i2c_avlink); 2330 if (state->i2c_cec) 2331 i2c_unregister_device(state->i2c_cec); 2332 if (state->i2c_infoframe) 2333 i2c_unregister_device(state->i2c_infoframe); 2334 if (state->i2c_esdp) 2335 i2c_unregister_device(state->i2c_esdp); 2336 if (state->i2c_dpp) 2337 i2c_unregister_device(state->i2c_dpp); 2338 if (state->i2c_afe) 2339 i2c_unregister_device(state->i2c_afe); 2340 if (state->i2c_repeater) 2341 i2c_unregister_device(state->i2c_repeater); 2342 if (state->i2c_edid) 2343 i2c_unregister_device(state->i2c_edid); 2344 if (state->i2c_hdmi) 2345 i2c_unregister_device(state->i2c_hdmi); 2346 if (state->i2c_test) 2347 i2c_unregister_device(state->i2c_test); 2348 if (state->i2c_cp) 2349 i2c_unregister_device(state->i2c_cp); 2350 if (state->i2c_vdp) 2351 i2c_unregister_device(state->i2c_vdp); 2352} 2353 2354static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd, 2355 u8 addr, u8 io_reg) 2356{ 2357 struct i2c_client *client = v4l2_get_subdevdata(sd); 2358 2359 if (addr) 2360 io_write(sd, io_reg, addr << 1); 2361 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1); 2362} 2363 2364static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = { 2365 /* reset ADI recommended settings for HDMI: */ 2366 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2367 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2368 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */ 2369 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */ 2370 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */ 2371 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2372 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */ 2373 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */ 2374 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2375 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2376 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */ 2377 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */ 2378 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */ 2379 2380 /* set ADI recommended settings for digitizer */ 2381 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2382 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */ 2383 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */ 2384 { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */ 2385 { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */ 2386 { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */ 2387 2388 { ADV7604_REG_SEQ_TERM, 0 }, 2389}; 2390 2391static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = { 2392 /* set ADI recommended settings for HDMI: */ 2393 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */ 2394 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */ 2395 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */ 2396 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */ 2397 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */ 2398 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */ 2399 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */ 2400 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */ 2401 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */ 2402 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */ 2403 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */ 2404 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */ 2405 2406 /* reset ADI recommended settings for digitizer */ 2407 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */ 2408 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */ 2409 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */ 2410 2411 { ADV7604_REG_SEQ_TERM, 0 }, 2412}; 2413 2414static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = { 2415 { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 }, 2416 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c }, 2417 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 }, 2418 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda }, 2419 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 }, 2420 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 }, 2421 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 }, 2422 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 }, 2423 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e }, 2424 2425 { ADV7604_REG_SEQ_TERM, 0 }, 2426}; 2427 2428static const struct adv7604_chip_info adv7604_chip_info[] = { 2429 [ADV7604] = { 2430 .type = ADV7604, 2431 .has_afe = true, 2432 .max_port = ADV7604_INPUT_VGA_COMP, 2433 .num_dv_ports = 4, 2434 .edid_enable_reg = 0x77, 2435 .edid_status_reg = 0x7d, 2436 .lcf_reg = 0xb3, 2437 .tdms_lock_mask = 0xe0, 2438 .cable_det_mask = 0x1e, 2439 .fmt_change_digital_mask = 0xc1, 2440 .set_termination = adv7604_set_termination, 2441 .setup_irqs = adv7604_setup_irqs, 2442 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock, 2443 .read_cable_det = adv7604_read_cable_det, 2444 .recommended_settings = { 2445 [0] = adv7604_recommended_settings_afe, 2446 [1] = adv7604_recommended_settings_hdmi, 2447 }, 2448 .num_recommended_settings = { 2449 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe), 2450 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi), 2451 }, 2452 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) | 2453 BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) | 2454 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) | 2455 BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) | 2456 BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) | 2457 BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) | 2458 BIT(ADV7604_PAGE_VDP), 2459 }, 2460 [ADV7611] = { 2461 .type = ADV7611, 2462 .has_afe = false, 2463 .max_port = ADV7604_INPUT_HDMI_PORT_A, 2464 .num_dv_ports = 1, 2465 .edid_enable_reg = 0x74, 2466 .edid_status_reg = 0x76, 2467 .lcf_reg = 0xa3, 2468 .tdms_lock_mask = 0x43, 2469 .cable_det_mask = 0x01, 2470 .fmt_change_digital_mask = 0x03, 2471 .set_termination = adv7611_set_termination, 2472 .setup_irqs = adv7611_setup_irqs, 2473 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock, 2474 .read_cable_det = adv7611_read_cable_det, 2475 .recommended_settings = { 2476 [1] = adv7611_recommended_settings_hdmi, 2477 }, 2478 .num_recommended_settings = { 2479 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi), 2480 }, 2481 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) | 2482 BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) | 2483 BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) | 2484 BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP), 2485 }, 2486}; 2487 2488static int adv7604_probe(struct i2c_client *client, 2489 const struct i2c_device_id *id) 2490{ 2491 static const struct v4l2_dv_timings cea640x480 = 2492 V4L2_DV_BT_CEA_640X480P59_94; 2493 struct adv7604_state *state; 2494 struct adv7604_platform_data *pdata = client->dev.platform_data; 2495 struct v4l2_ctrl_handler *hdl; 2496 struct v4l2_subdev *sd; 2497 u16 val; 2498 int err; 2499 2500 /* Check if the adapter supports the needed features */ 2501 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 2502 return -EIO; 2503 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n", 2504 client->addr << 1); 2505 2506 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); 2507 if (!state) { 2508 v4l_err(client, "Could not allocate adv7604_state memory!\n"); 2509 return -ENOMEM; 2510 } 2511 2512 state->info = &adv7604_chip_info[id->driver_data]; 2513 2514 /* initialize variables */ 2515 state->restart_stdi_once = true; 2516 state->selected_input = ~0; 2517 2518 /* platform data */ 2519 if (!pdata) { 2520 v4l_err(client, "No platform data!\n"); 2521 return -ENODEV; 2522 } 2523 state->pdata = *pdata; 2524 state->timings = cea640x480; 2525 2526 sd = &state->sd; 2527 v4l2_i2c_subdev_init(sd, client, &adv7604_ops); 2528 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", 2529 id->name, i2c_adapter_id(client->adapter), 2530 client->addr); 2531 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 2532 2533 /* 2534 * Verify that the chip is present. On ADV7604 the RD_INFO register only 2535 * identifies the revision, while on ADV7611 it identifies the model as 2536 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611. 2537 */ 2538 if (state->info->type == ADV7604) { 2539 val = adv_smbus_read_byte_data_check(client, 0xfb, false); 2540 if (val != 0x68) { 2541 v4l2_info(sd, "not an adv7604 on address 0x%x\n", 2542 client->addr << 1); 2543 return -ENODEV; 2544 } 2545 } else { 2546 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8) 2547 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0); 2548 if (val != 0x2051) { 2549 v4l2_info(sd, "not an adv7611 on address 0x%x\n", 2550 client->addr << 1); 2551 return -ENODEV; 2552 } 2553 } 2554 2555 /* control handlers */ 2556 hdl = &state->hdl; 2557 v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8); 2558 2559 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2560 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); 2561 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2562 V4L2_CID_CONTRAST, 0, 255, 1, 128); 2563 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2564 V4L2_CID_SATURATION, 0, 255, 1, 128); 2565 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops, 2566 V4L2_CID_HUE, 0, 128, 1, 0); 2567 2568 /* private controls */ 2569 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, 2570 V4L2_CID_DV_RX_POWER_PRESENT, 0, 2571 (1 << state->info->num_dv_ports) - 1, 0, 0); 2572 state->rgb_quantization_range_ctrl = 2573 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops, 2574 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL, 2575 0, V4L2_DV_RGB_RANGE_AUTO); 2576 2577 /* custom controls */ 2578 if (adv7604_has_afe(state)) 2579 state->analog_sampling_phase_ctrl = 2580 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL); 2581 state->free_run_color_manual_ctrl = 2582 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL); 2583 state->free_run_color_ctrl = 2584 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL); 2585 2586 sd->ctrl_handler = hdl; 2587 if (hdl->error) { 2588 err = hdl->error; 2589 goto err_hdl; 2590 } 2591 state->detect_tx_5v_ctrl->is_private = true; 2592 state->rgb_quantization_range_ctrl->is_private = true; 2593 if (adv7604_has_afe(state)) 2594 state->analog_sampling_phase_ctrl->is_private = true; 2595 state->free_run_color_manual_ctrl->is_private = true; 2596 state->free_run_color_ctrl->is_private = true; 2597 2598 if (adv7604_s_detect_tx_5v_ctrl(sd)) { 2599 err = -ENODEV; 2600 goto err_hdl; 2601 } 2602 2603 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4); 2604 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5); 2605 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8); 2606 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9); 2607 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa); 2608 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb); 2609 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd); 2610 if (!state->i2c_cec || !state->i2c_infoframe || !state->i2c_afe || 2611 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi || 2612 !state->i2c_cp) { 2613 err = -ENOMEM; 2614 v4l2_err(sd, "failed to create digital i2c clients\n"); 2615 goto err_i2c; 2616 } 2617 2618 if (adv7604_has_afe(state)) { 2619 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3); 2620 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6); 2621 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7); 2622 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc); 2623 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe); 2624 if (!state->i2c_avlink || !state->i2c_esdp || !state->i2c_dpp || 2625 !state->i2c_test || !state->i2c_vdp) { 2626 err = -ENOMEM; 2627 v4l2_err(sd, "failed to create analog i2c clients\n"); 2628 goto err_i2c; 2629 } 2630 } 2631 /* work queues */ 2632 state->work_queues = create_singlethread_workqueue(client->name); 2633 if (!state->work_queues) { 2634 v4l2_err(sd, "Could not create work queue\n"); 2635 err = -ENOMEM; 2636 goto err_i2c; 2637 } 2638 2639 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, 2640 adv7604_delayed_work_enable_hotplug); 2641 2642 state->pad.flags = MEDIA_PAD_FL_SOURCE; 2643 err = media_entity_init(&sd->entity, 1, &state->pad, 0); 2644 if (err) 2645 goto err_work_queues; 2646 2647 err = adv7604_core_init(sd); 2648 if (err) 2649 goto err_entity; 2650 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, 2651 client->addr << 1, client->adapter->name); 2652 2653 err = v4l2_async_register_subdev(sd); 2654 if (err) 2655 goto err_entity; 2656 2657 return 0; 2658 2659err_entity: 2660 media_entity_cleanup(&sd->entity); 2661err_work_queues: 2662 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2663 destroy_workqueue(state->work_queues); 2664err_i2c: 2665 adv7604_unregister_clients(state); 2666err_hdl: 2667 v4l2_ctrl_handler_free(hdl); 2668 return err; 2669} 2670 2671/* ----------------------------------------------------------------------- */ 2672 2673static int adv7604_remove(struct i2c_client *client) 2674{ 2675 struct v4l2_subdev *sd = i2c_get_clientdata(client); 2676 struct adv7604_state *state = to_state(sd); 2677 2678 cancel_delayed_work(&state->delayed_work_enable_hotplug); 2679 destroy_workqueue(state->work_queues); 2680 v4l2_async_unregister_subdev(sd); 2681 v4l2_device_unregister_subdev(sd); 2682 media_entity_cleanup(&sd->entity); 2683 adv7604_unregister_clients(to_state(sd)); 2684 v4l2_ctrl_handler_free(sd->ctrl_handler); 2685 return 0; 2686} 2687 2688/* ----------------------------------------------------------------------- */ 2689 2690static struct i2c_device_id adv7604_id[] = { 2691 { "adv7604", ADV7604 }, 2692 { "adv7611", ADV7611 }, 2693 { } 2694}; 2695MODULE_DEVICE_TABLE(i2c, adv7604_id); 2696 2697static struct i2c_driver adv7604_driver = { 2698 .driver = { 2699 .owner = THIS_MODULE, 2700 .name = "adv7604", 2701 }, 2702 .probe = adv7604_probe, 2703 .remove = adv7604_remove, 2704 .id_table = adv7604_id, 2705}; 2706 2707module_i2c_driver(adv7604_driver); 2708