1/* 2 * tw68-core.c 3 * Core functions for the Techwell 68xx driver 4 * 5 * Much of this code is derived from the cx88 and sa7134 drivers, which 6 * were in turn derived from the bt87x driver. The original work was by 7 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab, 8 * Hans Verkuil, Andy Walls and many others. Their work is gratefully 9 * acknowledged. Full credit goes to them - any problems within this code 10 * are mine. 11 * 12 * Copyright (C) 2009 William M. Brack 13 * 14 * Refactored and updated to the latest v4l core frameworks: 15 * 16 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl> 17 * 18 * This program is free software; you can redistribute it and/or modify 19 * it under the terms of the GNU General Public License as published by 20 * the Free Software Foundation; either version 2 of the License, or 21 * (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 */ 28 29#include <linux/init.h> 30#include <linux/list.h> 31#include <linux/module.h> 32#include <linux/kernel.h> 33#include <linux/slab.h> 34#include <linux/kmod.h> 35#include <linux/sound.h> 36#include <linux/interrupt.h> 37#include <linux/delay.h> 38#include <linux/mutex.h> 39#include <linux/dma-mapping.h> 40#include <linux/pm.h> 41 42#include <media/v4l2-dev.h> 43#include "tw68.h" 44#include "tw68-reg.h" 45 46MODULE_DESCRIPTION("v4l2 driver module for tw6800 based video capture cards"); 47MODULE_AUTHOR("William M. Brack"); 48MODULE_AUTHOR("Hans Verkuil <hverkuil@xs4all.nl>"); 49MODULE_LICENSE("GPL"); 50 51static unsigned int latency = UNSET; 52module_param(latency, int, 0444); 53MODULE_PARM_DESC(latency, "pci latency timer"); 54 55static unsigned int video_nr[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; 56module_param_array(video_nr, int, NULL, 0444); 57MODULE_PARM_DESC(video_nr, "video device number"); 58 59static unsigned int card[] = {[0 ... (TW68_MAXBOARDS - 1)] = UNSET }; 60module_param_array(card, int, NULL, 0444); 61MODULE_PARM_DESC(card, "card type"); 62 63static atomic_t tw68_instance = ATOMIC_INIT(0); 64 65/* ------------------------------------------------------------------ */ 66 67/* 68 * Please add any new PCI IDs to: http://pci-ids.ucw.cz. This keeps 69 * the PCI ID database up to date. Note that the entries must be 70 * added under vendor 0x1797 (Techwell Inc.) as subsystem IDs. 71 */ 72static const struct pci_device_id tw68_pci_tbl[] = { 73 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6800)}, 74 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6801)}, 75 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6804)}, 76 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6816_1)}, 77 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6816_2)}, 78 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6816_3)}, 79 {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6816_4)}, 80 {0,} 81}; 82 83/* ------------------------------------------------------------------ */ 84 85 86/* 87 * The device is given a "soft reset". According to the specifications, 88 * after this "all register content remain unchanged", so we also write 89 * to all specified registers manually as well (mostly to manufacturer's 90 * specified reset values) 91 */ 92static int tw68_hw_init1(struct tw68_dev *dev) 93{ 94 /* Assure all interrupts are disabled */ 95 tw_writel(TW68_INTMASK, 0); /* 020 */ 96 /* Clear any pending interrupts */ 97 tw_writel(TW68_INTSTAT, 0xffffffff); /* 01C */ 98 /* Stop risc processor, set default buffer level */ 99 tw_writel(TW68_DMAC, 0x1600); 100 101 tw_writeb(TW68_ACNTL, 0x80); /* 218 soft reset */ 102 msleep(100); 103 104 tw_writeb(TW68_INFORM, 0x40); /* 208 mux0, 27mhz xtal */ 105 tw_writeb(TW68_OPFORM, 0x04); /* 20C analog line-lock */ 106 tw_writeb(TW68_HSYNC, 0); /* 210 color-killer high sens */ 107 tw_writeb(TW68_ACNTL, 0x42); /* 218 int vref #2, chroma adc off */ 108 109 tw_writeb(TW68_CROP_HI, 0x02); /* 21C Hactive m.s. bits */ 110 tw_writeb(TW68_VDELAY_LO, 0x12);/* 220 Mfg specified reset value */ 111 tw_writeb(TW68_VACTIVE_LO, 0xf0); 112 tw_writeb(TW68_HDELAY_LO, 0x0f); 113 tw_writeb(TW68_HACTIVE_LO, 0xd0); 114 115 tw_writeb(TW68_CNTRL1, 0xcd); /* 230 Wide Chroma BPF B/W 116 * Secam reduction, Adap comb for 117 * NTSC, Op Mode 1 */ 118 119 tw_writeb(TW68_VSCALE_LO, 0); /* 234 */ 120 tw_writeb(TW68_SCALE_HI, 0x11); /* 238 */ 121 tw_writeb(TW68_HSCALE_LO, 0); /* 23c */ 122 tw_writeb(TW68_BRIGHT, 0); /* 240 */ 123 tw_writeb(TW68_CONTRAST, 0x5c); /* 244 */ 124 tw_writeb(TW68_SHARPNESS, 0x51);/* 248 */ 125 tw_writeb(TW68_SAT_U, 0x80); /* 24C */ 126 tw_writeb(TW68_SAT_V, 0x80); /* 250 */ 127 tw_writeb(TW68_HUE, 0x00); /* 254 */ 128 129 /* TODO - Check that none of these are set by control defaults */ 130 tw_writeb(TW68_SHARP2, 0x53); /* 258 Mfg specified reset val */ 131 tw_writeb(TW68_VSHARP, 0x80); /* 25C Sharpness Coring val 8 */ 132 tw_writeb(TW68_CORING, 0x44); /* 260 CTI and Vert Peak coring */ 133 tw_writeb(TW68_CNTRL2, 0x00); /* 268 No power saving enabled */ 134 tw_writeb(TW68_SDT, 0x07); /* 270 Enable shadow reg, auto-det */ 135 tw_writeb(TW68_SDTR, 0x7f); /* 274 All stds recog, don't start */ 136 tw_writeb(TW68_CLMPG, 0x50); /* 280 Clamp end at 40 sys clocks */ 137 tw_writeb(TW68_IAGC, 0x22); /* 284 Mfg specified reset val */ 138 tw_writeb(TW68_AGCGAIN, 0xf0); /* 288 AGC gain when loop disabled */ 139 tw_writeb(TW68_PEAKWT, 0xd8); /* 28C White peak threshold */ 140 tw_writeb(TW68_CLMPL, 0x3c); /* 290 Y channel clamp level */ 141/* tw_writeb(TW68_SYNCT, 0x38);*/ /* 294 Sync amplitude */ 142 tw_writeb(TW68_SYNCT, 0x30); /* 294 Sync amplitude */ 143 tw_writeb(TW68_MISSCNT, 0x44); /* 298 Horiz sync, VCR detect sens */ 144 tw_writeb(TW68_PCLAMP, 0x28); /* 29C Clamp pos from PLL sync */ 145 /* Bit DETV of VCNTL1 helps sync multi cams/chip board */ 146 tw_writeb(TW68_VCNTL1, 0x04); /* 2A0 */ 147 tw_writeb(TW68_VCNTL2, 0); /* 2A4 */ 148 tw_writeb(TW68_CKILL, 0x68); /* 2A8 Mfg specified reset val */ 149 tw_writeb(TW68_COMB, 0x44); /* 2AC Mfg specified reset val */ 150 tw_writeb(TW68_LDLY, 0x30); /* 2B0 Max positive luma delay */ 151 tw_writeb(TW68_MISC1, 0x14); /* 2B4 Mfg specified reset val */ 152 tw_writeb(TW68_LOOP, 0xa5); /* 2B8 Mfg specified reset val */ 153 tw_writeb(TW68_MISC2, 0xe0); /* 2BC Enable colour killer */ 154 tw_writeb(TW68_MVSN, 0); /* 2C0 */ 155 tw_writeb(TW68_CLMD, 0x05); /* 2CC slice level auto, clamp med. */ 156 tw_writeb(TW68_IDCNTL, 0); /* 2D0 Writing zero to this register 157 * selects NTSC ID detection, 158 * but doesn't change the 159 * sensitivity (which has a reset 160 * value of 1E). Since we are 161 * not doing auto-detection, it 162 * has no real effect */ 163 tw_writeb(TW68_CLCNTL1, 0); /* 2D4 */ 164 tw_writel(TW68_VBIC, 0x03); /* 010 */ 165 tw_writel(TW68_CAP_CTL, 0x03); /* 040 Enable both even & odd flds */ 166 tw_writel(TW68_DMAC, 0x2000); /* patch set had 0x2080 */ 167 tw_writel(TW68_TESTREG, 0); /* 02C */ 168 169 /* 170 * Some common boards, especially inexpensive single-chip models, 171 * use the GPIO bits 0-3 to control an on-board video-output mux. 172 * For these boards, we need to set up the GPIO register into 173 * "normal" mode, set bits 0-3 as output, and then set those bits 174 * zero. 175 * 176 * Eventually, it would be nice if we could identify these boards 177 * uniquely, and only do this initialisation if the board has been 178 * identify. For the moment, however, it shouldn't hurt anything 179 * to do these steps. 180 */ 181 tw_writel(TW68_GPIOC, 0); /* Set the GPIO to "normal", no ints */ 182 tw_writel(TW68_GPOE, 0x0f); /* Set bits 0-3 to "output" */ 183 tw_writel(TW68_GPDATA, 0); /* Set all bits to low state */ 184 185 /* Initialize the device control structures */ 186 mutex_init(&dev->lock); 187 spin_lock_init(&dev->slock); 188 189 /* Initialize any subsystems */ 190 tw68_video_init1(dev); 191 return 0; 192} 193 194static irqreturn_t tw68_irq(int irq, void *dev_id) 195{ 196 struct tw68_dev *dev = dev_id; 197 u32 status, orig; 198 int loop; 199 200 status = orig = tw_readl(TW68_INTSTAT) & dev->pci_irqmask; 201 /* Check if anything to do */ 202 if (0 == status) 203 return IRQ_NONE; /* Nope - return */ 204 for (loop = 0; loop < 10; loop++) { 205 if (status & dev->board_virqmask) /* video interrupt */ 206 tw68_irq_video_done(dev, status); 207 status = tw_readl(TW68_INTSTAT) & dev->pci_irqmask; 208 if (0 == status) 209 return IRQ_HANDLED; 210 } 211 dev_dbg(&dev->pci->dev, "%s: **** INTERRUPT NOT HANDLED - clearing mask (orig 0x%08x, cur 0x%08x)", 212 dev->name, orig, tw_readl(TW68_INTSTAT)); 213 dev_dbg(&dev->pci->dev, "%s: pci_irqmask 0x%08x; board_virqmask 0x%08x ****\n", 214 dev->name, dev->pci_irqmask, dev->board_virqmask); 215 tw_clearl(TW68_INTMASK, dev->pci_irqmask); 216 return IRQ_HANDLED; 217} 218 219static int tw68_initdev(struct pci_dev *pci_dev, 220 const struct pci_device_id *pci_id) 221{ 222 struct tw68_dev *dev; 223 int vidnr = -1; 224 int err; 225 226 dev = devm_kzalloc(&pci_dev->dev, sizeof(*dev), GFP_KERNEL); 227 if (NULL == dev) 228 return -ENOMEM; 229 230 dev->instance = v4l2_device_set_name(&dev->v4l2_dev, "tw68", 231 &tw68_instance); 232 233 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); 234 if (err) 235 return err; 236 237 /* pci init */ 238 dev->pci = pci_dev; 239 if (pci_enable_device(pci_dev)) { 240 err = -EIO; 241 goto fail1; 242 } 243 244 dev->name = dev->v4l2_dev.name; 245 246 if (UNSET != latency) { 247 pr_info("%s: setting pci latency timer to %d\n", 248 dev->name, latency); 249 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency); 250 } 251 252 /* print pci info */ 253 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); 254 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); 255 pr_info("%s: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n", 256 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 257 dev->pci_lat, (u64)pci_resource_start(pci_dev, 0)); 258 pci_set_master(pci_dev); 259 if (!pci_dma_supported(pci_dev, DMA_BIT_MASK(32))) { 260 pr_info("%s: Oops: no 32bit PCI DMA ???\n", dev->name); 261 err = -EIO; 262 goto fail1; 263 } 264 265 switch (pci_id->device) { 266 case PCI_DEVICE_ID_6800: /* TW6800 */ 267 dev->vdecoder = TW6800; 268 dev->board_virqmask = TW68_VID_INTS; 269 break; 270 case PCI_DEVICE_ID_6801: /* Video decoder for TW6802 */ 271 dev->vdecoder = TW6801; 272 dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; 273 break; 274 case PCI_DEVICE_ID_6804: /* Video decoder for TW6804 */ 275 dev->vdecoder = TW6804; 276 dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; 277 break; 278 default: 279 dev->vdecoder = TWXXXX; /* To be announced */ 280 dev->board_virqmask = TW68_VID_INTS | TW68_VID_INTSX; 281 break; 282 } 283 284 /* get mmio */ 285 if (!request_mem_region(pci_resource_start(pci_dev, 0), 286 pci_resource_len(pci_dev, 0), 287 dev->name)) { 288 err = -EBUSY; 289 pr_err("%s: can't get MMIO memory @ 0x%llx\n", 290 dev->name, 291 (unsigned long long)pci_resource_start(pci_dev, 0)); 292 goto fail1; 293 } 294 dev->lmmio = ioremap(pci_resource_start(pci_dev, 0), 295 pci_resource_len(pci_dev, 0)); 296 dev->bmmio = (__u8 __iomem *)dev->lmmio; 297 if (NULL == dev->lmmio) { 298 err = -EIO; 299 pr_err("%s: can't ioremap() MMIO memory\n", 300 dev->name); 301 goto fail2; 302 } 303 /* initialize hardware #1 */ 304 /* Then do any initialisation wanted before interrupts are on */ 305 tw68_hw_init1(dev); 306 307 /* get irq */ 308 err = devm_request_irq(&pci_dev->dev, pci_dev->irq, tw68_irq, 309 IRQF_SHARED, dev->name, dev); 310 if (err < 0) { 311 pr_err("%s: can't get IRQ %d\n", 312 dev->name, pci_dev->irq); 313 goto fail3; 314 } 315 316 /* 317 * Now do remainder of initialisation, first for 318 * things unique for this card, then for general board 319 */ 320 if (dev->instance < TW68_MAXBOARDS) 321 vidnr = video_nr[dev->instance]; 322 /* initialise video function first */ 323 err = tw68_video_init2(dev, vidnr); 324 if (err < 0) { 325 pr_err("%s: can't register video device\n", 326 dev->name); 327 goto fail4; 328 } 329 tw_setl(TW68_INTMASK, dev->pci_irqmask); 330 331 pr_info("%s: registered device %s\n", 332 dev->name, video_device_node_name(&dev->vdev)); 333 334 return 0; 335 336fail4: 337 video_unregister_device(&dev->vdev); 338fail3: 339 iounmap(dev->lmmio); 340fail2: 341 release_mem_region(pci_resource_start(pci_dev, 0), 342 pci_resource_len(pci_dev, 0)); 343fail1: 344 v4l2_device_unregister(&dev->v4l2_dev); 345 return err; 346} 347 348static void tw68_finidev(struct pci_dev *pci_dev) 349{ 350 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 351 struct tw68_dev *dev = 352 container_of(v4l2_dev, struct tw68_dev, v4l2_dev); 353 354 /* shutdown subsystems */ 355 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); 356 tw_writel(TW68_INTMASK, 0); 357 358 /* unregister */ 359 video_unregister_device(&dev->vdev); 360 v4l2_ctrl_handler_free(&dev->hdl); 361 362 /* release resources */ 363 iounmap(dev->lmmio); 364 release_mem_region(pci_resource_start(pci_dev, 0), 365 pci_resource_len(pci_dev, 0)); 366 367 v4l2_device_unregister(&dev->v4l2_dev); 368} 369 370#ifdef CONFIG_PM 371 372static int tw68_suspend(struct pci_dev *pci_dev , pm_message_t state) 373{ 374 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 375 struct tw68_dev *dev = container_of(v4l2_dev, 376 struct tw68_dev, v4l2_dev); 377 378 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN); 379 dev->pci_irqmask &= ~TW68_VID_INTS; 380 tw_writel(TW68_INTMASK, 0); 381 382 synchronize_irq(pci_dev->irq); 383 384 pci_save_state(pci_dev); 385 pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state)); 386 vb2_discard_done(&dev->vidq); 387 388 return 0; 389} 390 391static int tw68_resume(struct pci_dev *pci_dev) 392{ 393 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev); 394 struct tw68_dev *dev = container_of(v4l2_dev, 395 struct tw68_dev, v4l2_dev); 396 struct tw68_buf *buf; 397 unsigned long flags; 398 399 pci_set_power_state(pci_dev, PCI_D0); 400 pci_restore_state(pci_dev); 401 402 /* Do things that are done in tw68_initdev , 403 except of initializing memory structures.*/ 404 405 msleep(100); 406 407 tw68_set_tvnorm_hw(dev); 408 409 /*resume unfinished buffer(s)*/ 410 spin_lock_irqsave(&dev->slock, flags); 411 buf = container_of(dev->active.next, struct tw68_buf, list); 412 413 tw68_video_start_dma(dev, buf); 414 415 spin_unlock_irqrestore(&dev->slock, flags); 416 417 return 0; 418} 419#endif 420 421/* ----------------------------------------------------------- */ 422 423static struct pci_driver tw68_pci_driver = { 424 .name = "tw68", 425 .id_table = tw68_pci_tbl, 426 .probe = tw68_initdev, 427 .remove = tw68_finidev, 428#ifdef CONFIG_PM 429 .suspend = tw68_suspend, 430 .resume = tw68_resume 431#endif 432}; 433 434module_pci_driver(tw68_pci_driver); 435