1/* 2 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * Samsung EXYNOS5 SoC series G-Scaler driver 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published 9 * by the Free Software Foundation, either version 2 of the License, 10 * or (at your option) any later version. 11 */ 12 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/types.h> 16#include <linux/errno.h> 17#include <linux/bug.h> 18#include <linux/interrupt.h> 19#include <linux/workqueue.h> 20#include <linux/device.h> 21#include <linux/platform_device.h> 22#include <linux/list.h> 23#include <linux/io.h> 24#include <linux/slab.h> 25#include <linux/clk.h> 26#include <linux/of.h> 27#include <media/v4l2-ioctl.h> 28 29#include "gsc-core.h" 30 31#define GSC_CLOCK_GATE_NAME "gscl" 32 33static const struct gsc_fmt gsc_formats[] = { 34 { 35 .name = "RGB565", 36 .pixelformat = V4L2_PIX_FMT_RGB565X, 37 .depth = { 16 }, 38 .color = GSC_RGB, 39 .num_planes = 1, 40 .num_comp = 1, 41 }, { 42 .name = "XRGB-8-8-8-8, 32 bpp", 43 .pixelformat = V4L2_PIX_FMT_RGB32, 44 .depth = { 32 }, 45 .color = GSC_RGB, 46 .num_planes = 1, 47 .num_comp = 1, 48 }, { 49 .name = "YUV 4:2:2 packed, YCbYCr", 50 .pixelformat = V4L2_PIX_FMT_YUYV, 51 .depth = { 16 }, 52 .color = GSC_YUV422, 53 .yorder = GSC_LSB_Y, 54 .corder = GSC_CBCR, 55 .num_planes = 1, 56 .num_comp = 1, 57 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, 58 }, { 59 .name = "YUV 4:2:2 packed, CbYCrY", 60 .pixelformat = V4L2_PIX_FMT_UYVY, 61 .depth = { 16 }, 62 .color = GSC_YUV422, 63 .yorder = GSC_LSB_C, 64 .corder = GSC_CBCR, 65 .num_planes = 1, 66 .num_comp = 1, 67 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, 68 }, { 69 .name = "YUV 4:2:2 packed, CrYCbY", 70 .pixelformat = V4L2_PIX_FMT_VYUY, 71 .depth = { 16 }, 72 .color = GSC_YUV422, 73 .yorder = GSC_LSB_C, 74 .corder = GSC_CRCB, 75 .num_planes = 1, 76 .num_comp = 1, 77 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, 78 }, { 79 .name = "YUV 4:2:2 packed, YCrYCb", 80 .pixelformat = V4L2_PIX_FMT_YVYU, 81 .depth = { 16 }, 82 .color = GSC_YUV422, 83 .yorder = GSC_LSB_Y, 84 .corder = GSC_CRCB, 85 .num_planes = 1, 86 .num_comp = 1, 87 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, 88 }, { 89 .name = "YUV 4:4:4 planar, YCbYCr", 90 .pixelformat = V4L2_PIX_FMT_YUV32, 91 .depth = { 32 }, 92 .color = GSC_YUV444, 93 .yorder = GSC_LSB_Y, 94 .corder = GSC_CBCR, 95 .num_planes = 1, 96 .num_comp = 1, 97 }, { 98 .name = "YUV 4:2:2 planar, Y/Cb/Cr", 99 .pixelformat = V4L2_PIX_FMT_YUV422P, 100 .depth = { 16 }, 101 .color = GSC_YUV422, 102 .yorder = GSC_LSB_Y, 103 .corder = GSC_CBCR, 104 .num_planes = 1, 105 .num_comp = 3, 106 }, { 107 .name = "YUV 4:2:2 planar, Y/CbCr", 108 .pixelformat = V4L2_PIX_FMT_NV16, 109 .depth = { 16 }, 110 .color = GSC_YUV422, 111 .yorder = GSC_LSB_Y, 112 .corder = GSC_CBCR, 113 .num_planes = 1, 114 .num_comp = 2, 115 }, { 116 .name = "YUV 4:2:2 planar, Y/CrCb", 117 .pixelformat = V4L2_PIX_FMT_NV61, 118 .depth = { 16 }, 119 .color = GSC_YUV422, 120 .yorder = GSC_LSB_Y, 121 .corder = GSC_CRCB, 122 .num_planes = 1, 123 .num_comp = 2, 124 }, { 125 .name = "YUV 4:2:0 planar, YCbCr", 126 .pixelformat = V4L2_PIX_FMT_YUV420, 127 .depth = { 12 }, 128 .color = GSC_YUV420, 129 .yorder = GSC_LSB_Y, 130 .corder = GSC_CBCR, 131 .num_planes = 1, 132 .num_comp = 3, 133 }, { 134 .name = "YUV 4:2:0 planar, YCrCb", 135 .pixelformat = V4L2_PIX_FMT_YVU420, 136 .depth = { 12 }, 137 .color = GSC_YUV420, 138 .yorder = GSC_LSB_Y, 139 .corder = GSC_CRCB, 140 .num_planes = 1, 141 .num_comp = 3, 142 143 }, { 144 .name = "YUV 4:2:0 planar, Y/CbCr", 145 .pixelformat = V4L2_PIX_FMT_NV12, 146 .depth = { 12 }, 147 .color = GSC_YUV420, 148 .yorder = GSC_LSB_Y, 149 .corder = GSC_CBCR, 150 .num_planes = 1, 151 .num_comp = 2, 152 }, { 153 .name = "YUV 4:2:0 planar, Y/CrCb", 154 .pixelformat = V4L2_PIX_FMT_NV21, 155 .depth = { 12 }, 156 .color = GSC_YUV420, 157 .yorder = GSC_LSB_Y, 158 .corder = GSC_CRCB, 159 .num_planes = 1, 160 .num_comp = 2, 161 }, { 162 .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr", 163 .pixelformat = V4L2_PIX_FMT_NV12M, 164 .depth = { 8, 4 }, 165 .color = GSC_YUV420, 166 .yorder = GSC_LSB_Y, 167 .corder = GSC_CBCR, 168 .num_planes = 2, 169 .num_comp = 2, 170 }, { 171 .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr", 172 .pixelformat = V4L2_PIX_FMT_YUV420M, 173 .depth = { 8, 2, 2 }, 174 .color = GSC_YUV420, 175 .yorder = GSC_LSB_Y, 176 .corder = GSC_CBCR, 177 .num_planes = 3, 178 .num_comp = 3, 179 }, { 180 .name = "YUV 4:2:0 non-contig. 3p, Y/Cr/Cb", 181 .pixelformat = V4L2_PIX_FMT_YVU420M, 182 .depth = { 8, 2, 2 }, 183 .color = GSC_YUV420, 184 .yorder = GSC_LSB_Y, 185 .corder = GSC_CRCB, 186 .num_planes = 3, 187 .num_comp = 3, 188 }, { 189 .name = "YUV 4:2:0 n.c. 2p, Y/CbCr tiled", 190 .pixelformat = V4L2_PIX_FMT_NV12MT_16X16, 191 .depth = { 8, 4 }, 192 .color = GSC_YUV420, 193 .yorder = GSC_LSB_Y, 194 .corder = GSC_CBCR, 195 .num_planes = 2, 196 .num_comp = 2, 197 } 198}; 199 200const struct gsc_fmt *get_format(int index) 201{ 202 if (index >= ARRAY_SIZE(gsc_formats)) 203 return NULL; 204 205 return (struct gsc_fmt *)&gsc_formats[index]; 206} 207 208const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index) 209{ 210 const struct gsc_fmt *fmt, *def_fmt = NULL; 211 unsigned int i; 212 213 if (index >= ARRAY_SIZE(gsc_formats)) 214 return NULL; 215 216 for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) { 217 fmt = get_format(i); 218 if (pixelformat && fmt->pixelformat == *pixelformat) 219 return fmt; 220 if (mbus_code && fmt->mbus_code == *mbus_code) 221 return fmt; 222 if (index == i) 223 def_fmt = fmt; 224 } 225 return def_fmt; 226 227} 228 229void gsc_set_frame_size(struct gsc_frame *frame, int width, int height) 230{ 231 frame->f_width = width; 232 frame->f_height = height; 233 frame->crop.width = width; 234 frame->crop.height = height; 235 frame->crop.left = 0; 236 frame->crop.top = 0; 237} 238 239int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst, 240 u32 *ratio) 241{ 242 if ((dst > src) || (dst >= src / var->poly_sc_down_max)) { 243 *ratio = 1; 244 return 0; 245 } 246 247 if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) { 248 pr_err("Exceeded maximum downscaling ratio (1/16))"); 249 return -EINVAL; 250 } 251 252 *ratio = (dst > (src / 8)) ? 2 : 4; 253 254 return 0; 255} 256 257void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh) 258{ 259 if (hratio == 4 && vratio == 4) 260 *sh = 4; 261 else if ((hratio == 4 && vratio == 2) || 262 (hratio == 2 && vratio == 4)) 263 *sh = 3; 264 else if ((hratio == 4 && vratio == 1) || 265 (hratio == 1 && vratio == 4) || 266 (hratio == 2 && vratio == 2)) 267 *sh = 2; 268 else if (hratio == 1 && vratio == 1) 269 *sh = 0; 270 else 271 *sh = 1; 272} 273 274void gsc_check_src_scale_info(struct gsc_variant *var, 275 struct gsc_frame *s_frame, u32 *wratio, 276 u32 tx, u32 ty, u32 *hratio) 277{ 278 int remainder = 0, walign, halign; 279 280 if (is_yuv420(s_frame->fmt->color)) { 281 walign = GSC_SC_ALIGN_4; 282 halign = GSC_SC_ALIGN_4; 283 } else if (is_yuv422(s_frame->fmt->color)) { 284 walign = GSC_SC_ALIGN_4; 285 halign = GSC_SC_ALIGN_2; 286 } else { 287 walign = GSC_SC_ALIGN_2; 288 halign = GSC_SC_ALIGN_2; 289 } 290 291 remainder = s_frame->crop.width % (*wratio * walign); 292 if (remainder) { 293 s_frame->crop.width -= remainder; 294 gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio); 295 pr_info("cropped src width size is recalculated from %d to %d", 296 s_frame->crop.width + remainder, s_frame->crop.width); 297 } 298 299 remainder = s_frame->crop.height % (*hratio * halign); 300 if (remainder) { 301 s_frame->crop.height -= remainder; 302 gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio); 303 pr_info("cropped src height size is recalculated from %d to %d", 304 s_frame->crop.height + remainder, s_frame->crop.height); 305 } 306} 307 308int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f) 309{ 310 const struct gsc_fmt *fmt; 311 312 fmt = find_fmt(NULL, NULL, f->index); 313 if (!fmt) 314 return -EINVAL; 315 316 strlcpy(f->description, fmt->name, sizeof(f->description)); 317 f->pixelformat = fmt->pixelformat; 318 319 return 0; 320} 321 322static u32 get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index) 323{ 324 if (frm->addr.y == addr) { 325 *index = 0; 326 return frm->addr.y; 327 } else if (frm->addr.cb == addr) { 328 *index = 1; 329 return frm->addr.cb; 330 } else if (frm->addr.cr == addr) { 331 *index = 2; 332 return frm->addr.cr; 333 } else { 334 pr_err("Plane address is wrong"); 335 return -EINVAL; 336 } 337} 338 339void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm) 340{ 341 u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len; 342 f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0; 343 344 f_chk_addr = frm->addr.y; 345 f_chk_len = frm->payload[0]; 346 if (frm->fmt->num_planes == 2) { 347 s_chk_addr = frm->addr.cb; 348 s_chk_len = frm->payload[1]; 349 } else if (frm->fmt->num_planes == 3) { 350 u32 low_addr, low_plane, mid_addr, mid_plane; 351 u32 high_addr, high_plane; 352 u32 t_min, t_max; 353 354 t_min = min3(frm->addr.y, frm->addr.cb, frm->addr.cr); 355 low_addr = get_plane_info(frm, t_min, &low_plane); 356 t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr); 357 high_addr = get_plane_info(frm, t_max, &high_plane); 358 359 mid_plane = 3 - (low_plane + high_plane); 360 if (mid_plane == 0) 361 mid_addr = frm->addr.y; 362 else if (mid_plane == 1) 363 mid_addr = frm->addr.cb; 364 else if (mid_plane == 2) 365 mid_addr = frm->addr.cr; 366 else 367 return; 368 369 f_chk_addr = low_addr; 370 if (mid_addr + frm->payload[mid_plane] - low_addr > 371 high_addr + frm->payload[high_plane] - mid_addr) { 372 f_chk_len = frm->payload[low_plane]; 373 s_chk_addr = mid_addr; 374 s_chk_len = high_addr + 375 frm->payload[high_plane] - mid_addr; 376 } else { 377 f_chk_len = mid_addr + 378 frm->payload[mid_plane] - low_addr; 379 s_chk_addr = high_addr; 380 s_chk_len = frm->payload[high_plane]; 381 } 382 } 383 pr_debug("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n", 384 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len); 385} 386 387int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f) 388{ 389 struct gsc_dev *gsc = ctx->gsc_dev; 390 struct gsc_variant *variant = gsc->variant; 391 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; 392 const struct gsc_fmt *fmt; 393 u32 max_w, max_h, mod_x, mod_y; 394 u32 min_w, min_h, tmp_w, tmp_h; 395 int i; 396 397 pr_debug("user put w: %d, h: %d", pix_mp->width, pix_mp->height); 398 399 fmt = find_fmt(&pix_mp->pixelformat, NULL, 0); 400 if (!fmt) { 401 pr_err("pixelformat format (0x%X) invalid\n", 402 pix_mp->pixelformat); 403 return -EINVAL; 404 } 405 406 if (pix_mp->field == V4L2_FIELD_ANY) 407 pix_mp->field = V4L2_FIELD_NONE; 408 else if (pix_mp->field != V4L2_FIELD_NONE) { 409 pr_err("Not supported field order(%d)\n", pix_mp->field); 410 return -EINVAL; 411 } 412 413 max_w = variant->pix_max->target_rot_dis_w; 414 max_h = variant->pix_max->target_rot_dis_h; 415 416 mod_x = ffs(variant->pix_align->org_w) - 1; 417 if (is_yuv420(fmt->color)) 418 mod_y = ffs(variant->pix_align->org_h) - 1; 419 else 420 mod_y = ffs(variant->pix_align->org_h) - 2; 421 422 if (V4L2_TYPE_IS_OUTPUT(f->type)) { 423 min_w = variant->pix_min->org_w; 424 min_h = variant->pix_min->org_h; 425 } else { 426 min_w = variant->pix_min->target_rot_dis_w; 427 min_h = variant->pix_min->target_rot_dis_h; 428 } 429 430 pr_debug("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d", 431 mod_x, mod_y, max_w, max_h); 432 433 /* To check if image size is modified to adjust parameter against 434 hardware abilities */ 435 tmp_w = pix_mp->width; 436 tmp_h = pix_mp->height; 437 438 v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x, 439 &pix_mp->height, min_h, max_h, mod_y, 0); 440 if (tmp_w != pix_mp->width || tmp_h != pix_mp->height) 441 pr_info("Image size has been modified from %dx%d to %dx%d", 442 tmp_w, tmp_h, pix_mp->width, pix_mp->height); 443 444 pix_mp->num_planes = fmt->num_planes; 445 446 if (pix_mp->width >= 1280) /* HD */ 447 pix_mp->colorspace = V4L2_COLORSPACE_REC709; 448 else /* SD */ 449 pix_mp->colorspace = V4L2_COLORSPACE_SMPTE170M; 450 451 452 for (i = 0; i < pix_mp->num_planes; ++i) { 453 int bpl = (pix_mp->width * fmt->depth[i]) >> 3; 454 pix_mp->plane_fmt[i].bytesperline = bpl; 455 pix_mp->plane_fmt[i].sizeimage = bpl * pix_mp->height; 456 457 pr_debug("[%d]: bpl: %d, sizeimage: %d", 458 i, bpl, pix_mp->plane_fmt[i].sizeimage); 459 } 460 461 return 0; 462} 463 464int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f) 465{ 466 struct gsc_frame *frame; 467 struct v4l2_pix_format_mplane *pix_mp; 468 int i; 469 470 frame = ctx_get_frame(ctx, f->type); 471 if (IS_ERR(frame)) 472 return PTR_ERR(frame); 473 474 pix_mp = &f->fmt.pix_mp; 475 476 pix_mp->width = frame->f_width; 477 pix_mp->height = frame->f_height; 478 pix_mp->field = V4L2_FIELD_NONE; 479 pix_mp->pixelformat = frame->fmt->pixelformat; 480 pix_mp->colorspace = V4L2_COLORSPACE_REC709; 481 pix_mp->num_planes = frame->fmt->num_planes; 482 483 for (i = 0; i < pix_mp->num_planes; ++i) { 484 pix_mp->plane_fmt[i].bytesperline = (frame->f_width * 485 frame->fmt->depth[i]) / 8; 486 pix_mp->plane_fmt[i].sizeimage = 487 pix_mp->plane_fmt[i].bytesperline * frame->f_height; 488 } 489 490 return 0; 491} 492 493void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h) 494{ 495 if (tmp_w != *w || tmp_h != *h) { 496 pr_info("Cropped size has been modified from %dx%d to %dx%d", 497 *w, *h, tmp_w, tmp_h); 498 *w = tmp_w; 499 *h = tmp_h; 500 } 501} 502 503int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) 504{ 505 struct gsc_frame *frame; 506 507 frame = ctx_get_frame(ctx, cr->type); 508 if (IS_ERR(frame)) 509 return PTR_ERR(frame); 510 511 cr->c = frame->crop; 512 513 return 0; 514} 515 516int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr) 517{ 518 struct gsc_frame *f; 519 struct gsc_dev *gsc = ctx->gsc_dev; 520 struct gsc_variant *variant = gsc->variant; 521 u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h; 522 u32 min_w, min_h, max_w, max_h; 523 524 if (cr->c.top < 0 || cr->c.left < 0) { 525 pr_err("doesn't support negative values for top & left\n"); 526 return -EINVAL; 527 } 528 pr_debug("user put w: %d, h: %d", cr->c.width, cr->c.height); 529 530 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) 531 f = &ctx->d_frame; 532 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 533 f = &ctx->s_frame; 534 else 535 return -EINVAL; 536 537 max_w = f->f_width; 538 max_h = f->f_height; 539 tmp_w = cr->c.width; 540 tmp_h = cr->c.height; 541 542 if (V4L2_TYPE_IS_OUTPUT(cr->type)) { 543 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) || 544 is_rgb(f->fmt->color)) 545 min_w = 32; 546 else 547 min_w = 64; 548 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 3) || 549 is_yuv420(f->fmt->color)) 550 min_h = 32; 551 else 552 min_h = 16; 553 } else { 554 if (is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) 555 mod_x = ffs(variant->pix_align->target_w) - 1; 556 if (is_yuv420(f->fmt->color)) 557 mod_y = ffs(variant->pix_align->target_h) - 1; 558 if (ctx->gsc_ctrls.rotate->val == 90 || 559 ctx->gsc_ctrls.rotate->val == 270) { 560 max_w = f->f_height; 561 max_h = f->f_width; 562 min_w = variant->pix_min->target_rot_en_w; 563 min_h = variant->pix_min->target_rot_en_h; 564 tmp_w = cr->c.height; 565 tmp_h = cr->c.width; 566 } else { 567 min_w = variant->pix_min->target_rot_dis_w; 568 min_h = variant->pix_min->target_rot_dis_h; 569 } 570 } 571 pr_debug("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d", 572 mod_x, mod_y, min_w, min_h); 573 pr_debug("tmp_w : %d, tmp_h : %d", tmp_w, tmp_h); 574 575 v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x, 576 &tmp_h, min_h, max_h, mod_y, 0); 577 578 if (!V4L2_TYPE_IS_OUTPUT(cr->type) && 579 (ctx->gsc_ctrls.rotate->val == 90 || 580 ctx->gsc_ctrls.rotate->val == 270)) 581 gsc_check_crop_change(tmp_h, tmp_w, 582 &cr->c.width, &cr->c.height); 583 else 584 gsc_check_crop_change(tmp_w, tmp_h, 585 &cr->c.width, &cr->c.height); 586 587 588 /* adjust left/top if cropping rectangle is out of bounds */ 589 /* Need to add code to algin left value with 2's multiple */ 590 if (cr->c.left + tmp_w > max_w) 591 cr->c.left = max_w - tmp_w; 592 if (cr->c.top + tmp_h > max_h) 593 cr->c.top = max_h - tmp_h; 594 595 if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) && 596 cr->c.left & 1) 597 cr->c.left -= 1; 598 599 pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d", 600 cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h); 601 602 return 0; 603} 604 605int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw, 606 int dh, int rot, int out_path) 607{ 608 int tmp_w, tmp_h, sc_down_max; 609 610 if (out_path == GSC_DMA) 611 sc_down_max = var->sc_down_max; 612 else 613 sc_down_max = var->local_sc_down; 614 615 if (rot == 90 || rot == 270) { 616 tmp_w = dh; 617 tmp_h = dw; 618 } else { 619 tmp_w = dw; 620 tmp_h = dh; 621 } 622 623 if ((sw / tmp_w) > sc_down_max || 624 (sh / tmp_h) > sc_down_max || 625 (tmp_w / sw) > var->sc_up_max || 626 (tmp_h / sh) > var->sc_up_max) 627 return -EINVAL; 628 629 return 0; 630} 631 632int gsc_set_scaler_info(struct gsc_ctx *ctx) 633{ 634 struct gsc_scaler *sc = &ctx->scaler; 635 struct gsc_frame *s_frame = &ctx->s_frame; 636 struct gsc_frame *d_frame = &ctx->d_frame; 637 struct gsc_variant *variant = ctx->gsc_dev->variant; 638 struct device *dev = &ctx->gsc_dev->pdev->dev; 639 int tx, ty; 640 int ret; 641 642 ret = gsc_check_scaler_ratio(variant, s_frame->crop.width, 643 s_frame->crop.height, d_frame->crop.width, d_frame->crop.height, 644 ctx->gsc_ctrls.rotate->val, ctx->out_path); 645 if (ret) { 646 pr_err("out of scaler range"); 647 return ret; 648 } 649 650 if (ctx->gsc_ctrls.rotate->val == 90 || 651 ctx->gsc_ctrls.rotate->val == 270) { 652 ty = d_frame->crop.width; 653 tx = d_frame->crop.height; 654 } else { 655 tx = d_frame->crop.width; 656 ty = d_frame->crop.height; 657 } 658 659 if (tx <= 0 || ty <= 0) { 660 dev_err(dev, "Invalid target size: %dx%d", tx, ty); 661 return -EINVAL; 662 } 663 664 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width, 665 tx, &sc->pre_hratio); 666 if (ret) { 667 pr_err("Horizontal scale ratio is out of range"); 668 return ret; 669 } 670 671 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height, 672 ty, &sc->pre_vratio); 673 if (ret) { 674 pr_err("Vertical scale ratio is out of range"); 675 return ret; 676 } 677 678 gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio, 679 tx, ty, &sc->pre_vratio); 680 681 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio, 682 &sc->pre_shfactor); 683 684 sc->main_hratio = (s_frame->crop.width << 16) / tx; 685 sc->main_vratio = (s_frame->crop.height << 16) / ty; 686 687 pr_debug("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d", 688 s_frame->crop.width, s_frame->crop.height, tx, ty); 689 pr_debug("scaler ratio info : pre_shfactor : %d, pre_h : %d", 690 sc->pre_shfactor, sc->pre_hratio); 691 pr_debug("pre_v :%d, main_h : %d, main_v : %d", 692 sc->pre_vratio, sc->main_hratio, sc->main_vratio); 693 694 return 0; 695} 696 697static int __gsc_s_ctrl(struct gsc_ctx *ctx, struct v4l2_ctrl *ctrl) 698{ 699 struct gsc_dev *gsc = ctx->gsc_dev; 700 struct gsc_variant *variant = gsc->variant; 701 unsigned int flags = GSC_DST_FMT | GSC_SRC_FMT; 702 int ret = 0; 703 704 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) 705 return 0; 706 707 switch (ctrl->id) { 708 case V4L2_CID_HFLIP: 709 ctx->hflip = ctrl->val; 710 break; 711 712 case V4L2_CID_VFLIP: 713 ctx->vflip = ctrl->val; 714 break; 715 716 case V4L2_CID_ROTATE: 717 if ((ctx->state & flags) == flags) { 718 ret = gsc_check_scaler_ratio(variant, 719 ctx->s_frame.crop.width, 720 ctx->s_frame.crop.height, 721 ctx->d_frame.crop.width, 722 ctx->d_frame.crop.height, 723 ctx->gsc_ctrls.rotate->val, 724 ctx->out_path); 725 726 if (ret) 727 return -EINVAL; 728 } 729 730 ctx->rotation = ctrl->val; 731 break; 732 733 case V4L2_CID_ALPHA_COMPONENT: 734 ctx->d_frame.alpha = ctrl->val; 735 break; 736 } 737 738 ctx->state |= GSC_PARAMS; 739 return 0; 740} 741 742static int gsc_s_ctrl(struct v4l2_ctrl *ctrl) 743{ 744 struct gsc_ctx *ctx = ctrl_to_ctx(ctrl); 745 unsigned long flags; 746 int ret; 747 748 spin_lock_irqsave(&ctx->gsc_dev->slock, flags); 749 ret = __gsc_s_ctrl(ctx, ctrl); 750 spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags); 751 752 return ret; 753} 754 755static const struct v4l2_ctrl_ops gsc_ctrl_ops = { 756 .s_ctrl = gsc_s_ctrl, 757}; 758 759int gsc_ctrls_create(struct gsc_ctx *ctx) 760{ 761 if (ctx->ctrls_rdy) { 762 pr_err("Control handler of this context was created already"); 763 return 0; 764 } 765 766 v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM); 767 768 ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, 769 &gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0); 770 ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, 771 &gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 772 ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, 773 &gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 774 ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler, 775 &gsc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0); 776 777 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0; 778 779 if (ctx->ctrl_handler.error) { 780 int err = ctx->ctrl_handler.error; 781 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 782 pr_err("Failed to create G-Scaler control handlers"); 783 return err; 784 } 785 786 return 0; 787} 788 789void gsc_ctrls_delete(struct gsc_ctx *ctx) 790{ 791 if (ctx->ctrls_rdy) { 792 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 793 ctx->ctrls_rdy = false; 794 } 795} 796 797/* The color format (num_comp, num_planes) must be already configured. */ 798int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb, 799 struct gsc_frame *frame, struct gsc_addr *addr) 800{ 801 int ret = 0; 802 u32 pix_size; 803 804 if ((vb == NULL) || (frame == NULL)) 805 return -EINVAL; 806 807 pix_size = frame->f_width * frame->f_height; 808 809 pr_debug("num_planes= %d, num_comp= %d, pix_size= %d", 810 frame->fmt->num_planes, frame->fmt->num_comp, pix_size); 811 812 addr->y = vb2_dma_contig_plane_dma_addr(vb, 0); 813 814 if (frame->fmt->num_planes == 1) { 815 switch (frame->fmt->num_comp) { 816 case 1: 817 addr->cb = 0; 818 addr->cr = 0; 819 break; 820 case 2: 821 /* decompose Y into Y/Cb */ 822 addr->cb = (dma_addr_t)(addr->y + pix_size); 823 addr->cr = 0; 824 break; 825 case 3: 826 /* decompose Y into Y/Cb/Cr */ 827 addr->cb = (dma_addr_t)(addr->y + pix_size); 828 if (GSC_YUV420 == frame->fmt->color) 829 addr->cr = (dma_addr_t)(addr->cb 830 + (pix_size >> 2)); 831 else /* 422 */ 832 addr->cr = (dma_addr_t)(addr->cb 833 + (pix_size >> 1)); 834 break; 835 default: 836 pr_err("Invalid the number of color planes"); 837 return -EINVAL; 838 } 839 } else { 840 if (frame->fmt->num_planes >= 2) 841 addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1); 842 843 if (frame->fmt->num_planes == 3) 844 addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2); 845 } 846 847 if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) || 848 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) || 849 (frame->fmt->pixelformat == V4L2_PIX_FMT_NV61) || 850 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) || 851 (frame->fmt->pixelformat == V4L2_PIX_FMT_NV21) || 852 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M)) 853 swap(addr->cb, addr->cr); 854 855 pr_debug("ADDR: y= %pad cb= %pad cr= %pad ret= %d", 856 &addr->y, &addr->cb, &addr->cr, ret); 857 858 return ret; 859} 860 861static irqreturn_t gsc_irq_handler(int irq, void *priv) 862{ 863 struct gsc_dev *gsc = priv; 864 struct gsc_ctx *ctx; 865 int gsc_irq; 866 867 gsc_irq = gsc_hw_get_irq_status(gsc); 868 gsc_hw_clear_irq(gsc, gsc_irq); 869 870 if (gsc_irq == GSC_IRQ_OVERRUN) { 871 pr_err("Local path input over-run interrupt has occurred!\n"); 872 return IRQ_HANDLED; 873 } 874 875 spin_lock(&gsc->slock); 876 877 if (test_and_clear_bit(ST_M2M_PEND, &gsc->state)) { 878 879 gsc_hw_enable_control(gsc, false); 880 881 if (test_and_clear_bit(ST_M2M_SUSPENDING, &gsc->state)) { 882 set_bit(ST_M2M_SUSPENDED, &gsc->state); 883 wake_up(&gsc->irq_queue); 884 goto isr_unlock; 885 } 886 ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev); 887 888 if (!ctx || !ctx->m2m_ctx) 889 goto isr_unlock; 890 891 spin_unlock(&gsc->slock); 892 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE); 893 894 /* wake_up job_abort, stop_streaming */ 895 if (ctx->state & GSC_CTX_STOP_REQ) { 896 ctx->state &= ~GSC_CTX_STOP_REQ; 897 wake_up(&gsc->irq_queue); 898 } 899 return IRQ_HANDLED; 900 } 901 902isr_unlock: 903 spin_unlock(&gsc->slock); 904 return IRQ_HANDLED; 905} 906 907static struct gsc_pix_max gsc_v_100_max = { 908 .org_scaler_bypass_w = 8192, 909 .org_scaler_bypass_h = 8192, 910 .org_scaler_input_w = 4800, 911 .org_scaler_input_h = 3344, 912 .real_rot_dis_w = 4800, 913 .real_rot_dis_h = 3344, 914 .real_rot_en_w = 2047, 915 .real_rot_en_h = 2047, 916 .target_rot_dis_w = 4800, 917 .target_rot_dis_h = 3344, 918 .target_rot_en_w = 2016, 919 .target_rot_en_h = 2016, 920}; 921 922static struct gsc_pix_min gsc_v_100_min = { 923 .org_w = 64, 924 .org_h = 32, 925 .real_w = 64, 926 .real_h = 32, 927 .target_rot_dis_w = 64, 928 .target_rot_dis_h = 32, 929 .target_rot_en_w = 32, 930 .target_rot_en_h = 16, 931}; 932 933static struct gsc_pix_align gsc_v_100_align = { 934 .org_h = 16, 935 .org_w = 16, /* yuv420 : 16, others : 8 */ 936 .offset_h = 2, /* yuv420/422 : 2, others : 1 */ 937 .real_w = 16, /* yuv420/422 : 4~16, others : 2~8 */ 938 .real_h = 16, /* yuv420 : 4~16, others : 1 */ 939 .target_w = 2, /* yuv420/422 : 2, others : 1 */ 940 .target_h = 2, /* yuv420 : 2, others : 1 */ 941}; 942 943static struct gsc_variant gsc_v_100_variant = { 944 .pix_max = &gsc_v_100_max, 945 .pix_min = &gsc_v_100_min, 946 .pix_align = &gsc_v_100_align, 947 .in_buf_cnt = 32, 948 .out_buf_cnt = 32, 949 .sc_up_max = 8, 950 .sc_down_max = 16, 951 .poly_sc_down_max = 4, 952 .pre_sc_down_max = 4, 953 .local_sc_down = 2, 954}; 955 956static struct gsc_driverdata gsc_v_100_drvdata = { 957 .variant = { 958 [0] = &gsc_v_100_variant, 959 [1] = &gsc_v_100_variant, 960 [2] = &gsc_v_100_variant, 961 [3] = &gsc_v_100_variant, 962 }, 963 .num_entities = 4, 964 .lclk_frequency = 266000000UL, 965}; 966 967static struct platform_device_id gsc_driver_ids[] = { 968 { 969 .name = "exynos-gsc", 970 .driver_data = (unsigned long)&gsc_v_100_drvdata, 971 }, 972 {}, 973}; 974MODULE_DEVICE_TABLE(platform, gsc_driver_ids); 975 976static const struct of_device_id exynos_gsc_match[] = { 977 { 978 .compatible = "samsung,exynos5-gsc", 979 .data = &gsc_v_100_drvdata, 980 }, 981 {}, 982}; 983MODULE_DEVICE_TABLE(of, exynos_gsc_match); 984 985static void *gsc_get_drv_data(struct platform_device *pdev) 986{ 987 struct gsc_driverdata *driver_data = NULL; 988 989 if (pdev->dev.of_node) { 990 const struct of_device_id *match; 991 match = of_match_node(exynos_gsc_match, 992 pdev->dev.of_node); 993 if (match) 994 driver_data = (struct gsc_driverdata *)match->data; 995 } else { 996 driver_data = (struct gsc_driverdata *) 997 platform_get_device_id(pdev)->driver_data; 998 } 999 1000 return driver_data; 1001} 1002 1003static void gsc_clk_put(struct gsc_dev *gsc) 1004{ 1005 if (!IS_ERR(gsc->clock)) 1006 clk_unprepare(gsc->clock); 1007} 1008 1009static int gsc_clk_get(struct gsc_dev *gsc) 1010{ 1011 int ret; 1012 1013 dev_dbg(&gsc->pdev->dev, "gsc_clk_get Called\n"); 1014 1015 gsc->clock = devm_clk_get(&gsc->pdev->dev, GSC_CLOCK_GATE_NAME); 1016 if (IS_ERR(gsc->clock)) { 1017 dev_err(&gsc->pdev->dev, "failed to get clock~~~: %s\n", 1018 GSC_CLOCK_GATE_NAME); 1019 return PTR_ERR(gsc->clock); 1020 } 1021 1022 ret = clk_prepare(gsc->clock); 1023 if (ret < 0) { 1024 dev_err(&gsc->pdev->dev, "clock prepare failed for clock: %s\n", 1025 GSC_CLOCK_GATE_NAME); 1026 gsc->clock = ERR_PTR(-EINVAL); 1027 return ret; 1028 } 1029 1030 return 0; 1031} 1032 1033static int gsc_m2m_suspend(struct gsc_dev *gsc) 1034{ 1035 unsigned long flags; 1036 int timeout; 1037 1038 spin_lock_irqsave(&gsc->slock, flags); 1039 if (!gsc_m2m_pending(gsc)) { 1040 spin_unlock_irqrestore(&gsc->slock, flags); 1041 return 0; 1042 } 1043 clear_bit(ST_M2M_SUSPENDED, &gsc->state); 1044 set_bit(ST_M2M_SUSPENDING, &gsc->state); 1045 spin_unlock_irqrestore(&gsc->slock, flags); 1046 1047 timeout = wait_event_timeout(gsc->irq_queue, 1048 test_bit(ST_M2M_SUSPENDED, &gsc->state), 1049 GSC_SHUTDOWN_TIMEOUT); 1050 1051 clear_bit(ST_M2M_SUSPENDING, &gsc->state); 1052 return timeout == 0 ? -EAGAIN : 0; 1053} 1054 1055static int gsc_m2m_resume(struct gsc_dev *gsc) 1056{ 1057 struct gsc_ctx *ctx; 1058 unsigned long flags; 1059 1060 spin_lock_irqsave(&gsc->slock, flags); 1061 /* Clear for full H/W setup in first run after resume */ 1062 ctx = gsc->m2m.ctx; 1063 gsc->m2m.ctx = NULL; 1064 spin_unlock_irqrestore(&gsc->slock, flags); 1065 1066 if (test_and_clear_bit(ST_M2M_SUSPENDED, &gsc->state)) 1067 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR); 1068 1069 return 0; 1070} 1071 1072static int gsc_probe(struct platform_device *pdev) 1073{ 1074 struct gsc_dev *gsc; 1075 struct resource *res; 1076 struct gsc_driverdata *drv_data = gsc_get_drv_data(pdev); 1077 struct device *dev = &pdev->dev; 1078 int ret = 0; 1079 1080 gsc = devm_kzalloc(dev, sizeof(struct gsc_dev), GFP_KERNEL); 1081 if (!gsc) 1082 return -ENOMEM; 1083 1084 if (dev->of_node) 1085 gsc->id = of_alias_get_id(pdev->dev.of_node, "gsc"); 1086 else 1087 gsc->id = pdev->id; 1088 1089 if (gsc->id >= drv_data->num_entities) { 1090 dev_err(dev, "Invalid platform device id: %d\n", gsc->id); 1091 return -EINVAL; 1092 } 1093 1094 gsc->variant = drv_data->variant[gsc->id]; 1095 gsc->pdev = pdev; 1096 gsc->pdata = dev->platform_data; 1097 1098 init_waitqueue_head(&gsc->irq_queue); 1099 spin_lock_init(&gsc->slock); 1100 mutex_init(&gsc->lock); 1101 gsc->clock = ERR_PTR(-EINVAL); 1102 1103 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1104 gsc->regs = devm_ioremap_resource(dev, res); 1105 if (IS_ERR(gsc->regs)) 1106 return PTR_ERR(gsc->regs); 1107 1108 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1109 if (!res) { 1110 dev_err(dev, "failed to get IRQ resource\n"); 1111 return -ENXIO; 1112 } 1113 1114 ret = gsc_clk_get(gsc); 1115 if (ret) 1116 return ret; 1117 1118 ret = devm_request_irq(dev, res->start, gsc_irq_handler, 1119 0, pdev->name, gsc); 1120 if (ret) { 1121 dev_err(dev, "failed to install irq (%d)\n", ret); 1122 goto err_clk; 1123 } 1124 1125 ret = v4l2_device_register(dev, &gsc->v4l2_dev); 1126 if (ret) 1127 goto err_clk; 1128 1129 ret = gsc_register_m2m_device(gsc); 1130 if (ret) 1131 goto err_v4l2; 1132 1133 platform_set_drvdata(pdev, gsc); 1134 pm_runtime_enable(dev); 1135 ret = pm_runtime_get_sync(&pdev->dev); 1136 if (ret < 0) 1137 goto err_m2m; 1138 1139 /* Initialize continious memory allocator */ 1140 gsc->alloc_ctx = vb2_dma_contig_init_ctx(dev); 1141 if (IS_ERR(gsc->alloc_ctx)) { 1142 ret = PTR_ERR(gsc->alloc_ctx); 1143 goto err_pm; 1144 } 1145 1146 dev_dbg(dev, "gsc-%d registered successfully\n", gsc->id); 1147 1148 pm_runtime_put(dev); 1149 return 0; 1150err_pm: 1151 pm_runtime_put(dev); 1152err_m2m: 1153 gsc_unregister_m2m_device(gsc); 1154err_v4l2: 1155 v4l2_device_unregister(&gsc->v4l2_dev); 1156err_clk: 1157 gsc_clk_put(gsc); 1158 return ret; 1159} 1160 1161static int gsc_remove(struct platform_device *pdev) 1162{ 1163 struct gsc_dev *gsc = platform_get_drvdata(pdev); 1164 1165 gsc_unregister_m2m_device(gsc); 1166 v4l2_device_unregister(&gsc->v4l2_dev); 1167 1168 vb2_dma_contig_cleanup_ctx(gsc->alloc_ctx); 1169 pm_runtime_disable(&pdev->dev); 1170 gsc_clk_put(gsc); 1171 1172 dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name); 1173 return 0; 1174} 1175 1176static int gsc_runtime_resume(struct device *dev) 1177{ 1178 struct gsc_dev *gsc = dev_get_drvdata(dev); 1179 int ret = 0; 1180 1181 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state); 1182 1183 ret = clk_enable(gsc->clock); 1184 if (ret) 1185 return ret; 1186 1187 gsc_hw_set_sw_reset(gsc); 1188 gsc_wait_reset(gsc); 1189 1190 return gsc_m2m_resume(gsc); 1191} 1192 1193static int gsc_runtime_suspend(struct device *dev) 1194{ 1195 struct gsc_dev *gsc = dev_get_drvdata(dev); 1196 int ret = 0; 1197 1198 ret = gsc_m2m_suspend(gsc); 1199 if (!ret) 1200 clk_disable(gsc->clock); 1201 1202 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state); 1203 return ret; 1204} 1205 1206static int gsc_resume(struct device *dev) 1207{ 1208 struct gsc_dev *gsc = dev_get_drvdata(dev); 1209 unsigned long flags; 1210 1211 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state); 1212 1213 /* Do not resume if the device was idle before system suspend */ 1214 spin_lock_irqsave(&gsc->slock, flags); 1215 if (!test_and_clear_bit(ST_SUSPEND, &gsc->state) || 1216 !gsc_m2m_opened(gsc)) { 1217 spin_unlock_irqrestore(&gsc->slock, flags); 1218 return 0; 1219 } 1220 spin_unlock_irqrestore(&gsc->slock, flags); 1221 1222 if (!pm_runtime_suspended(dev)) 1223 return gsc_runtime_resume(dev); 1224 1225 return 0; 1226} 1227 1228static int gsc_suspend(struct device *dev) 1229{ 1230 struct gsc_dev *gsc = dev_get_drvdata(dev); 1231 1232 pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state); 1233 1234 if (test_and_set_bit(ST_SUSPEND, &gsc->state)) 1235 return 0; 1236 1237 if (!pm_runtime_suspended(dev)) 1238 return gsc_runtime_suspend(dev); 1239 1240 return 0; 1241} 1242 1243static const struct dev_pm_ops gsc_pm_ops = { 1244 .suspend = gsc_suspend, 1245 .resume = gsc_resume, 1246 .runtime_suspend = gsc_runtime_suspend, 1247 .runtime_resume = gsc_runtime_resume, 1248}; 1249 1250static struct platform_driver gsc_driver = { 1251 .probe = gsc_probe, 1252 .remove = gsc_remove, 1253 .id_table = gsc_driver_ids, 1254 .driver = { 1255 .name = GSC_MODULE_NAME, 1256 .owner = THIS_MODULE, 1257 .pm = &gsc_pm_ops, 1258 .of_match_table = exynos_gsc_match, 1259 } 1260}; 1261 1262module_platform_driver(gsc_driver); 1263 1264MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>"); 1265MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver"); 1266MODULE_LICENSE("GPL"); 1267