1/* 2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c 3 * 4 * Samsung MFC (Multi Function Codec - FIMV) driver 5 * This file contains hw related functions. 6 * 7 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 8 * http://www.samsung.com/ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#undef DEBUG 16 17#include <linux/delay.h> 18#include <linux/mm.h> 19#include <linux/io.h> 20#include <linux/jiffies.h> 21#include <linux/firmware.h> 22#include <linux/err.h> 23#include <linux/sched.h> 24#include <linux/dma-mapping.h> 25 26#include <asm/cacheflush.h> 27 28#include "s5p_mfc_common.h" 29#include "s5p_mfc_cmd.h" 30#include "s5p_mfc_intr.h" 31#include "s5p_mfc_pm.h" 32#include "s5p_mfc_debug.h" 33#include "s5p_mfc_opr.h" 34#include "s5p_mfc_opr_v6.h" 35 36/* #define S5P_MFC_DEBUG_REGWRITE */ 37#ifdef S5P_MFC_DEBUG_REGWRITE 38#undef writel 39#define writel(v, r) \ 40 do { \ 41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \ 42 __raw_writel(v, r); \ 43 } while (0) 44#endif /* S5P_MFC_DEBUG_REGWRITE */ 45 46#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2) 47 48/* Allocate temporary buffers for decoding */ 49static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx) 50{ 51 /* NOP */ 52 53 return 0; 54} 55 56/* Release temproary buffers for decoding */ 57static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx) 58{ 59 /* NOP */ 60} 61 62/* Allocate codec buffers */ 63static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 64{ 65 struct s5p_mfc_dev *dev = ctx->dev; 66 unsigned int mb_width, mb_height; 67 int ret; 68 69 mb_width = MB_WIDTH(ctx->img_width); 70 mb_height = MB_HEIGHT(ctx->img_height); 71 72 if (ctx->type == MFCINST_DECODER) { 73 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", 74 ctx->luma_size, ctx->chroma_size, ctx->mv_size); 75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); 76 } else if (ctx->type == MFCINST_ENCODER) { 77 if (IS_MFCV8(dev)) 78 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * 79 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height), 80 S5P_FIMV_TMV_BUFFER_ALIGN_V6); 81 else 82 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * 83 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), 84 S5P_FIMV_TMV_BUFFER_ALIGN_V6); 85 86 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * 87 S5P_FIMV_LUMA_MB_TO_PIXEL_V6, 88 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); 89 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * 90 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, 91 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); 92 if (IS_MFCV8(dev)) 93 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8( 94 ctx->img_width, ctx->img_height, 95 mb_width, mb_height), 96 S5P_FIMV_ME_BUFFER_ALIGN_V6); 97 else 98 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6( 99 ctx->img_width, ctx->img_height, 100 mb_width, mb_height), 101 S5P_FIMV_ME_BUFFER_ALIGN_V6); 102 103 mfc_debug(2, "recon luma size: %zu chroma size: %zu\n", 104 ctx->luma_dpb_size, ctx->chroma_dpb_size); 105 } else { 106 return -EINVAL; 107 } 108 109 /* Codecs have different memory requirements */ 110 switch (ctx->codec_mode) { 111 case S5P_MFC_CODEC_H264_DEC: 112 case S5P_MFC_CODEC_H264_MVC_DEC: 113 if (IS_MFCV8(dev)) 114 ctx->scratch_buf_size = 115 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8( 116 mb_width, 117 mb_height); 118 else 119 ctx->scratch_buf_size = 120 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6( 121 mb_width, 122 mb_height); 123 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 124 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 125 ctx->bank1.size = 126 ctx->scratch_buf_size + 127 (ctx->mv_count * ctx->mv_size); 128 break; 129 case S5P_MFC_CODEC_MPEG4_DEC: 130 if (IS_MFCV7_PLUS(dev)) { 131 ctx->scratch_buf_size = 132 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7( 133 mb_width, 134 mb_height); 135 } else { 136 ctx->scratch_buf_size = 137 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6( 138 mb_width, 139 mb_height); 140 } 141 142 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 143 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 144 ctx->bank1.size = ctx->scratch_buf_size; 145 break; 146 case S5P_MFC_CODEC_VC1RCV_DEC: 147 case S5P_MFC_CODEC_VC1_DEC: 148 ctx->scratch_buf_size = 149 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6( 150 mb_width, 151 mb_height); 152 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 153 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 154 ctx->bank1.size = ctx->scratch_buf_size; 155 break; 156 case S5P_MFC_CODEC_MPEG2_DEC: 157 ctx->bank1.size = 0; 158 ctx->bank2.size = 0; 159 break; 160 case S5P_MFC_CODEC_H263_DEC: 161 ctx->scratch_buf_size = 162 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6( 163 mb_width, 164 mb_height); 165 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 166 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 167 ctx->bank1.size = ctx->scratch_buf_size; 168 break; 169 case S5P_MFC_CODEC_VP8_DEC: 170 if (IS_MFCV8(dev)) 171 ctx->scratch_buf_size = 172 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8( 173 mb_width, 174 mb_height); 175 else 176 ctx->scratch_buf_size = 177 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6( 178 mb_width, 179 mb_height); 180 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 181 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 182 ctx->bank1.size = ctx->scratch_buf_size; 183 break; 184 case S5P_MFC_CODEC_H264_ENC: 185 if (IS_MFCV8(dev)) 186 ctx->scratch_buf_size = 187 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8( 188 mb_width, 189 mb_height); 190 else 191 ctx->scratch_buf_size = 192 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6( 193 mb_width, 194 mb_height); 195 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 196 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 197 ctx->bank1.size = 198 ctx->scratch_buf_size + ctx->tmv_buffer_size + 199 (ctx->pb_count * (ctx->luma_dpb_size + 200 ctx->chroma_dpb_size + ctx->me_buffer_size)); 201 ctx->bank2.size = 0; 202 break; 203 case S5P_MFC_CODEC_MPEG4_ENC: 204 case S5P_MFC_CODEC_H263_ENC: 205 ctx->scratch_buf_size = 206 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( 207 mb_width, 208 mb_height); 209 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 210 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 211 ctx->bank1.size = 212 ctx->scratch_buf_size + ctx->tmv_buffer_size + 213 (ctx->pb_count * (ctx->luma_dpb_size + 214 ctx->chroma_dpb_size + ctx->me_buffer_size)); 215 ctx->bank2.size = 0; 216 break; 217 case S5P_MFC_CODEC_VP8_ENC: 218 if (IS_MFCV8(dev)) 219 ctx->scratch_buf_size = 220 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8( 221 mb_width, 222 mb_height); 223 else 224 ctx->scratch_buf_size = 225 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7( 226 mb_width, 227 mb_height); 228 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 229 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); 230 ctx->bank1.size = 231 ctx->scratch_buf_size + ctx->tmv_buffer_size + 232 (ctx->pb_count * (ctx->luma_dpb_size + 233 ctx->chroma_dpb_size + ctx->me_buffer_size)); 234 ctx->bank2.size = 0; 235 break; 236 default: 237 break; 238 } 239 240 /* Allocate only if memory from bank 1 is necessary */ 241 if (ctx->bank1.size > 0) { 242 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1); 243 if (ret) { 244 mfc_err("Failed to allocate Bank1 memory\n"); 245 return ret; 246 } 247 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 248 } 249 return 0; 250} 251 252/* Release buffers allocated for codec */ 253static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx) 254{ 255 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); 256} 257 258/* Allocate memory for instance data buffer */ 259static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx) 260{ 261 struct s5p_mfc_dev *dev = ctx->dev; 262 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; 263 int ret; 264 265 mfc_debug_enter(); 266 267 switch (ctx->codec_mode) { 268 case S5P_MFC_CODEC_H264_DEC: 269 case S5P_MFC_CODEC_H264_MVC_DEC: 270 ctx->ctx.size = buf_size->h264_dec_ctx; 271 break; 272 case S5P_MFC_CODEC_MPEG4_DEC: 273 case S5P_MFC_CODEC_H263_DEC: 274 case S5P_MFC_CODEC_VC1RCV_DEC: 275 case S5P_MFC_CODEC_VC1_DEC: 276 case S5P_MFC_CODEC_MPEG2_DEC: 277 case S5P_MFC_CODEC_VP8_DEC: 278 ctx->ctx.size = buf_size->other_dec_ctx; 279 break; 280 case S5P_MFC_CODEC_H264_ENC: 281 ctx->ctx.size = buf_size->h264_enc_ctx; 282 break; 283 case S5P_MFC_CODEC_MPEG4_ENC: 284 case S5P_MFC_CODEC_H263_ENC: 285 case S5P_MFC_CODEC_VP8_ENC: 286 ctx->ctx.size = buf_size->other_enc_ctx; 287 break; 288 default: 289 ctx->ctx.size = 0; 290 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode); 291 break; 292 } 293 294 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx); 295 if (ret) { 296 mfc_err("Failed to allocate instance buffer\n"); 297 return ret; 298 } 299 300 memset(ctx->ctx.virt, 0, ctx->ctx.size); 301 wmb(); 302 303 mfc_debug_leave(); 304 305 return 0; 306} 307 308/* Release instance buffer */ 309static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx) 310{ 311 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx); 312} 313 314/* Allocate context buffers for SYS_INIT */ 315static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev) 316{ 317 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; 318 int ret; 319 320 mfc_debug_enter(); 321 322 dev->ctx_buf.size = buf_size->dev_ctx; 323 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &dev->ctx_buf); 324 if (ret) { 325 mfc_err("Failed to allocate device context buffer\n"); 326 return ret; 327 } 328 329 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx); 330 wmb(); 331 332 mfc_debug_leave(); 333 334 return 0; 335} 336 337/* Release context buffers for SYS_INIT */ 338static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev) 339{ 340 s5p_mfc_release_priv_buf(dev->mem_dev_l, &dev->ctx_buf); 341} 342 343static int calc_plane(int width, int height) 344{ 345 int mbX, mbY; 346 347 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6); 348 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6); 349 350 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6) 351 mbY = (mbY + 1) / 2 * 2; 352 353 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) * 354 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6); 355} 356 357static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) 358{ 359 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6); 360 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6); 361 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n" 362 "buffer dimensions: %dx%d\n", ctx->img_width, 363 ctx->img_height, ctx->buf_width, ctx->buf_height); 364 365 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height); 366 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1)); 367 if (IS_MFCV8(ctx->dev)) { 368 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/ 369 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8; 370 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8; 371 } 372 373 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 374 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { 375 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, 376 ctx->img_height); 377 ctx->mv_size = ALIGN(ctx->mv_size, 16); 378 } else { 379 ctx->mv_size = 0; 380 } 381} 382 383static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx) 384{ 385 unsigned int mb_width, mb_height; 386 387 mb_width = MB_WIDTH(ctx->img_width); 388 mb_height = MB_HEIGHT(ctx->img_height); 389 390 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6); 391 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256); 392 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256); 393 394 /* MFCv7 needs pad bytes for Luma and Chroma */ 395 if (IS_MFCV7_PLUS(ctx->dev)) { 396 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7; 397 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7; 398 } 399} 400 401/* Set registers for decoding stream buffer */ 402static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx, 403 int buf_addr, unsigned int start_num_byte, 404 unsigned int strm_size) 405{ 406 struct s5p_mfc_dev *dev = ctx->dev; 407 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 408 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size; 409 410 mfc_debug_enter(); 411 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n" 412 "buf_size: 0x%08x (%d)\n", 413 ctx->inst_no, buf_addr, strm_size, strm_size); 414 writel(strm_size, mfc_regs->d_stream_data_size); 415 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); 416 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); 417 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); 418 419 mfc_debug_leave(); 420 return 0; 421} 422 423/* Set decoding frame buffer */ 424static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) 425{ 426 unsigned int frame_size, i; 427 unsigned int frame_size_ch, frame_size_mv; 428 struct s5p_mfc_dev *dev = ctx->dev; 429 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 430 size_t buf_addr1; 431 int buf_size1; 432 int align_gap; 433 434 buf_addr1 = ctx->bank1.dma; 435 buf_size1 = ctx->bank1.size; 436 437 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); 438 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count); 439 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay); 440 441 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); 442 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); 443 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); 444 445 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); 446 writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); 447 448 if (IS_MFCV8(dev)) { 449 writel(ctx->img_width, 450 mfc_regs->d_first_plane_dpb_stride_size); 451 writel(ctx->img_width, 452 mfc_regs->d_second_plane_dpb_stride_size); 453 } 454 455 buf_addr1 += ctx->scratch_buf_size; 456 buf_size1 -= ctx->scratch_buf_size; 457 458 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || 459 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){ 460 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size); 461 writel(ctx->mv_count, mfc_regs->d_num_mv); 462 } 463 464 frame_size = ctx->luma_size; 465 frame_size_ch = ctx->chroma_size; 466 frame_size_mv = ctx->mv_size; 467 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n", 468 frame_size, frame_size_ch, frame_size_mv); 469 470 for (i = 0; i < ctx->total_dpb_count; i++) { 471 /* Bank2 */ 472 mfc_debug(2, "Luma %d: %zx\n", i, 473 ctx->dst_bufs[i].cookie.raw.luma); 474 writel(ctx->dst_bufs[i].cookie.raw.luma, 475 mfc_regs->d_first_plane_dpb + i * 4); 476 mfc_debug(2, "\tChroma %d: %zx\n", i, 477 ctx->dst_bufs[i].cookie.raw.chroma); 478 writel(ctx->dst_bufs[i].cookie.raw.chroma, 479 mfc_regs->d_second_plane_dpb + i * 4); 480 } 481 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 482 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { 483 for (i = 0; i < ctx->mv_count; i++) { 484 /* To test alignment */ 485 align_gap = buf_addr1; 486 buf_addr1 = ALIGN(buf_addr1, 16); 487 align_gap = buf_addr1 - align_gap; 488 buf_size1 -= align_gap; 489 490 mfc_debug(2, "\tBuf1: %zx, size: %d\n", 491 buf_addr1, buf_size1); 492 writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4); 493 buf_addr1 += frame_size_mv; 494 buf_size1 -= frame_size_mv; 495 } 496 } 497 498 mfc_debug(2, "Buf1: %zu, buf_size1: %d (frames %d)\n", 499 buf_addr1, buf_size1, ctx->total_dpb_count); 500 if (buf_size1 < 0) { 501 mfc_debug(2, "Not enough memory has been allocated.\n"); 502 return -ENOMEM; 503 } 504 505 writel(ctx->inst_no, mfc_regs->instance_id); 506 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 507 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 508 509 mfc_debug(2, "After setting buffers.\n"); 510 return 0; 511} 512 513/* Set registers for encoding stream buffer */ 514static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx, 515 unsigned long addr, unsigned int size) 516{ 517 struct s5p_mfc_dev *dev = ctx->dev; 518 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 519 520 writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */ 521 writel(size, mfc_regs->e_stream_buffer_size); 522 523 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n", 524 addr, size); 525 526 return 0; 527} 528 529static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, 530 unsigned long y_addr, unsigned long c_addr) 531{ 532 struct s5p_mfc_dev *dev = ctx->dev; 533 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 534 535 writel(y_addr, mfc_regs->e_source_first_plane_addr); 536 writel(c_addr, mfc_regs->e_source_second_plane_addr); 537 538 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr); 539 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr); 540} 541 542static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, 543 unsigned long *y_addr, unsigned long *c_addr) 544{ 545 struct s5p_mfc_dev *dev = ctx->dev; 546 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 547 unsigned long enc_recon_y_addr, enc_recon_c_addr; 548 549 *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr); 550 *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr); 551 552 enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr); 553 enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr); 554 555 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr); 556 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr); 557} 558 559/* Set encoding ref & codec buffer */ 560static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) 561{ 562 struct s5p_mfc_dev *dev = ctx->dev; 563 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 564 size_t buf_addr1; 565 int i, buf_size1; 566 567 mfc_debug_enter(); 568 569 buf_addr1 = ctx->bank1.dma; 570 buf_size1 = ctx->bank1.size; 571 572 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); 573 574 for (i = 0; i < ctx->pb_count; i++) { 575 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); 576 buf_addr1 += ctx->luma_dpb_size; 577 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); 578 buf_addr1 += ctx->chroma_dpb_size; 579 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); 580 buf_addr1 += ctx->me_buffer_size; 581 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + 582 ctx->me_buffer_size); 583 } 584 585 writel(buf_addr1, mfc_regs->e_scratch_buffer_addr); 586 writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size); 587 buf_addr1 += ctx->scratch_buf_size; 588 buf_size1 -= ctx->scratch_buf_size; 589 590 writel(buf_addr1, mfc_regs->e_tmv_buffer0); 591 buf_addr1 += ctx->tmv_buffer_size >> 1; 592 writel(buf_addr1, mfc_regs->e_tmv_buffer1); 593 buf_addr1 += ctx->tmv_buffer_size >> 1; 594 buf_size1 -= ctx->tmv_buffer_size; 595 596 mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n", 597 buf_addr1, buf_size1, ctx->pb_count); 598 if (buf_size1 < 0) { 599 mfc_debug(2, "Not enough memory has been allocated.\n"); 600 return -ENOMEM; 601 } 602 603 writel(ctx->inst_no, mfc_regs->instance_id); 604 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 605 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 606 607 mfc_debug_leave(); 608 609 return 0; 610} 611 612static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx) 613{ 614 struct s5p_mfc_dev *dev = ctx->dev; 615 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 616 617 /* multi-slice control */ 618 /* multi-slice MB number or bit size */ 619 writel(ctx->slice_mode, mfc_regs->e_mslice_mode); 620 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 621 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb); 622 } else if (ctx->slice_mode == 623 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 624 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits); 625 } else { 626 writel(0x0, mfc_regs->e_mslice_size_mb); 627 writel(0x0, mfc_regs->e_mslice_size_bits); 628 } 629 630 return 0; 631} 632 633static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) 634{ 635 struct s5p_mfc_dev *dev = ctx->dev; 636 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 637 struct s5p_mfc_enc_params *p = &ctx->enc_params; 638 unsigned int reg = 0; 639 640 mfc_debug_enter(); 641 642 /* width */ 643 writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */ 644 /* height */ 645 writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */ 646 647 /* cropped width */ 648 writel(ctx->img_width, mfc_regs->e_cropped_frame_width); 649 /* cropped height */ 650 writel(ctx->img_height, mfc_regs->e_cropped_frame_height); 651 /* cropped offset */ 652 writel(0x0, mfc_regs->e_frame_crop_offset); 653 654 /* pictype : IDR period */ 655 reg = 0; 656 reg |= p->gop_size & 0xFFFF; 657 writel(reg, mfc_regs->e_gop_config); 658 659 /* multi-slice control */ 660 /* multi-slice MB number or bit size */ 661 ctx->slice_mode = p->slice_mode; 662 reg = 0; 663 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 664 reg |= (0x1 << 3); 665 writel(reg, mfc_regs->e_enc_options); 666 ctx->slice_size.mb = p->slice_mb; 667 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 668 reg |= (0x1 << 3); 669 writel(reg, mfc_regs->e_enc_options); 670 ctx->slice_size.bits = p->slice_bit; 671 } else { 672 reg &= ~(0x1 << 3); 673 writel(reg, mfc_regs->e_enc_options); 674 } 675 676 s5p_mfc_set_slice_mode(ctx); 677 678 /* cyclic intra refresh */ 679 writel(p->intra_refresh_mb, mfc_regs->e_ir_size); 680 reg = readl(mfc_regs->e_enc_options); 681 if (p->intra_refresh_mb == 0) 682 reg &= ~(0x1 << 4); 683 else 684 reg |= (0x1 << 4); 685 writel(reg, mfc_regs->e_enc_options); 686 687 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ 688 reg = readl(mfc_regs->e_enc_options); 689 reg &= ~(0x1 << 9); 690 writel(reg, mfc_regs->e_enc_options); 691 692 /* memory structure cur. frame */ 693 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 694 /* 0: Linear, 1: 2D tiled*/ 695 reg = readl(mfc_regs->e_enc_options); 696 reg &= ~(0x1 << 7); 697 writel(reg, mfc_regs->e_enc_options); 698 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 699 writel(0x0, mfc_regs->pixel_format); 700 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) { 701 /* 0: Linear, 1: 2D tiled*/ 702 reg = readl(mfc_regs->e_enc_options); 703 reg &= ~(0x1 << 7); 704 writel(reg, mfc_regs->e_enc_options); 705 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 706 writel(0x1, mfc_regs->pixel_format); 707 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) { 708 /* 0: Linear, 1: 2D tiled*/ 709 reg = readl(mfc_regs->e_enc_options); 710 reg |= (0x1 << 7); 711 writel(reg, mfc_regs->e_enc_options); 712 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 713 writel(0x0, mfc_regs->pixel_format); 714 } 715 716 /* memory structure recon. frame */ 717 /* 0: Linear, 1: 2D tiled */ 718 reg = readl(mfc_regs->e_enc_options); 719 reg |= (0x1 << 8); 720 writel(reg, mfc_regs->e_enc_options); 721 722 /* padding control & value */ 723 writel(0x0, mfc_regs->e_padding_ctrl); 724 if (p->pad) { 725 reg = 0; 726 /** enable */ 727 reg |= (1 << 31); 728 /** cr value */ 729 reg |= ((p->pad_cr & 0xFF) << 16); 730 /** cb value */ 731 reg |= ((p->pad_cb & 0xFF) << 8); 732 /** y value */ 733 reg |= p->pad_luma & 0xFF; 734 writel(reg, mfc_regs->e_padding_ctrl); 735 } 736 737 /* rate control config. */ 738 reg = 0; 739 /* frame-level rate control */ 740 reg |= ((p->rc_frame & 0x1) << 9); 741 writel(reg, mfc_regs->e_rc_config); 742 743 /* bit rate */ 744 if (p->rc_frame) 745 writel(p->rc_bitrate, 746 mfc_regs->e_rc_bit_rate); 747 else 748 writel(1, mfc_regs->e_rc_bit_rate); 749 750 /* reaction coefficient */ 751 if (p->rc_frame) { 752 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ 753 writel(1, mfc_regs->e_rc_mode); 754 else /* loose CBR */ 755 writel(2, mfc_regs->e_rc_mode); 756 } 757 758 /* seq header ctrl */ 759 reg = readl(mfc_regs->e_enc_options); 760 reg &= ~(0x1 << 2); 761 reg |= ((p->seq_hdr_mode & 0x1) << 2); 762 763 /* frame skip mode */ 764 reg &= ~(0x3); 765 reg |= (p->frame_skip_mode & 0x3); 766 writel(reg, mfc_regs->e_enc_options); 767 768 /* 'DROP_CONTROL_ENABLE', disable */ 769 reg = readl(mfc_regs->e_rc_config); 770 reg &= ~(0x1 << 10); 771 writel(reg, mfc_regs->e_rc_config); 772 773 /* setting for MV range [16, 256] */ 774 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 775 writel(reg, mfc_regs->e_mv_hor_range); 776 777 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 778 writel(reg, mfc_regs->e_mv_ver_range); 779 780 writel(0x0, mfc_regs->e_frame_insertion); 781 writel(0x0, mfc_regs->e_roi_buffer_addr); 782 writel(0x0, mfc_regs->e_param_change); 783 writel(0x0, mfc_regs->e_rc_roi_ctrl); 784 writel(0x0, mfc_regs->e_picture_tag); 785 786 writel(0x0, mfc_regs->e_bit_count_enable); 787 writel(0x0, mfc_regs->e_max_bit_count); 788 writel(0x0, mfc_regs->e_min_bit_count); 789 790 writel(0x0, mfc_regs->e_metadata_buffer_addr); 791 writel(0x0, mfc_regs->e_metadata_buffer_size); 792 793 mfc_debug_leave(); 794 795 return 0; 796} 797 798static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 799{ 800 struct s5p_mfc_dev *dev = ctx->dev; 801 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 802 struct s5p_mfc_enc_params *p = &ctx->enc_params; 803 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; 804 unsigned int reg = 0; 805 int i; 806 807 mfc_debug_enter(); 808 809 s5p_mfc_set_enc_params(ctx); 810 811 /* pictype : number of B */ 812 reg = readl(mfc_regs->e_gop_config); 813 reg &= ~(0x3 << 16); 814 reg |= ((p->num_b_frame & 0x3) << 16); 815 writel(reg, mfc_regs->e_gop_config); 816 817 /* profile & level */ 818 reg = 0; 819 /** level */ 820 reg |= ((p_h264->level & 0xFF) << 8); 821 /** profile - 0 ~ 3 */ 822 reg |= p_h264->profile & 0x3F; 823 writel(reg, mfc_regs->e_picture_profile); 824 825 /* rate control config. */ 826 reg = readl(mfc_regs->e_rc_config); 827 /** macroblock level rate control */ 828 reg &= ~(0x1 << 8); 829 reg |= ((p->rc_mb & 0x1) << 8); 830 writel(reg, mfc_regs->e_rc_config); 831 832 /** frame QP */ 833 reg &= ~(0x3F); 834 reg |= p_h264->rc_frame_qp & 0x3F; 835 writel(reg, mfc_regs->e_rc_config); 836 837 /* max & min value of QP */ 838 reg = 0; 839 /** max QP */ 840 reg |= ((p_h264->rc_max_qp & 0x3F) << 8); 841 /** min QP */ 842 reg |= p_h264->rc_min_qp & 0x3F; 843 writel(reg, mfc_regs->e_rc_qp_bound); 844 845 /* other QPs */ 846 writel(0x0, mfc_regs->e_fixed_picture_qp); 847 if (!p->rc_frame && !p->rc_mb) { 848 reg = 0; 849 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); 850 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); 851 reg |= p_h264->rc_frame_qp & 0x3F; 852 writel(reg, mfc_regs->e_fixed_picture_qp); 853 } 854 855 /* frame rate */ 856 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 857 reg = 0; 858 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 859 reg |= p->rc_framerate_denom & 0xFFFF; 860 writel(reg, mfc_regs->e_rc_frame_rate); 861 } 862 863 /* vbv buffer size */ 864 if (p->frame_skip_mode == 865 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 866 writel(p_h264->cpb_size & 0xFFFF, 867 mfc_regs->e_vbv_buffer_size); 868 869 if (p->rc_frame) 870 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); 871 } 872 873 /* interlace */ 874 reg = 0; 875 reg |= ((p_h264->interlace & 0x1) << 3); 876 writel(reg, mfc_regs->e_h264_options); 877 878 /* height */ 879 if (p_h264->interlace) { 880 writel(ctx->img_height >> 1, 881 mfc_regs->e_frame_height); /* 32 align */ 882 /* cropped height */ 883 writel(ctx->img_height >> 1, 884 mfc_regs->e_cropped_frame_height); 885 } 886 887 /* loop filter ctrl */ 888 reg = readl(mfc_regs->e_h264_options); 889 reg &= ~(0x3 << 1); 890 reg |= ((p_h264->loop_filter_mode & 0x3) << 1); 891 writel(reg, mfc_regs->e_h264_options); 892 893 /* loopfilter alpha offset */ 894 if (p_h264->loop_filter_alpha < 0) { 895 reg = 0x10; 896 reg |= (0xFF - p_h264->loop_filter_alpha) + 1; 897 } else { 898 reg = 0x00; 899 reg |= (p_h264->loop_filter_alpha & 0xF); 900 } 901 writel(reg, mfc_regs->e_h264_lf_alpha_offset); 902 903 /* loopfilter beta offset */ 904 if (p_h264->loop_filter_beta < 0) { 905 reg = 0x10; 906 reg |= (0xFF - p_h264->loop_filter_beta) + 1; 907 } else { 908 reg = 0x00; 909 reg |= (p_h264->loop_filter_beta & 0xF); 910 } 911 writel(reg, mfc_regs->e_h264_lf_beta_offset); 912 913 /* entropy coding mode */ 914 reg = readl(mfc_regs->e_h264_options); 915 reg &= ~(0x1); 916 reg |= p_h264->entropy_mode & 0x1; 917 writel(reg, mfc_regs->e_h264_options); 918 919 /* number of ref. picture */ 920 reg = readl(mfc_regs->e_h264_options); 921 reg &= ~(0x1 << 7); 922 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); 923 writel(reg, mfc_regs->e_h264_options); 924 925 /* 8x8 transform enable */ 926 reg = readl(mfc_regs->e_h264_options); 927 reg &= ~(0x3 << 12); 928 reg |= ((p_h264->_8x8_transform & 0x3) << 12); 929 writel(reg, mfc_regs->e_h264_options); 930 931 /* macroblock adaptive scaling features */ 932 writel(0x0, mfc_regs->e_mb_rc_config); 933 if (p->rc_mb) { 934 reg = 0; 935 /** dark region */ 936 reg |= ((p_h264->rc_mb_dark & 0x1) << 3); 937 /** smooth region */ 938 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2); 939 /** static region */ 940 reg |= ((p_h264->rc_mb_static & 0x1) << 1); 941 /** high activity region */ 942 reg |= p_h264->rc_mb_activity & 0x1; 943 writel(reg, mfc_regs->e_mb_rc_config); 944 } 945 946 /* aspect ratio VUI */ 947 readl(mfc_regs->e_h264_options); 948 reg &= ~(0x1 << 5); 949 reg |= ((p_h264->vui_sar & 0x1) << 5); 950 writel(reg, mfc_regs->e_h264_options); 951 952 writel(0x0, mfc_regs->e_aspect_ratio); 953 writel(0x0, mfc_regs->e_extended_sar); 954 if (p_h264->vui_sar) { 955 /* aspect ration IDC */ 956 reg = 0; 957 reg |= p_h264->vui_sar_idc & 0xFF; 958 writel(reg, mfc_regs->e_aspect_ratio); 959 if (p_h264->vui_sar_idc == 0xFF) { 960 /* extended SAR */ 961 reg = 0; 962 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; 963 reg |= p_h264->vui_ext_sar_height & 0xFFFF; 964 writel(reg, mfc_regs->e_extended_sar); 965 } 966 } 967 968 /* intra picture period for H.264 open GOP */ 969 /* control */ 970 readl(mfc_regs->e_h264_options); 971 reg &= ~(0x1 << 4); 972 reg |= ((p_h264->open_gop & 0x1) << 4); 973 writel(reg, mfc_regs->e_h264_options); 974 975 /* value */ 976 writel(0x0, mfc_regs->e_h264_i_period); 977 if (p_h264->open_gop) { 978 reg = 0; 979 reg |= p_h264->open_gop_size & 0xFFFF; 980 writel(reg, mfc_regs->e_h264_i_period); 981 } 982 983 /* 'WEIGHTED_BI_PREDICTION' for B is disable */ 984 readl(mfc_regs->e_h264_options); 985 reg &= ~(0x3 << 9); 986 writel(reg, mfc_regs->e_h264_options); 987 988 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ 989 readl(mfc_regs->e_h264_options); 990 reg &= ~(0x1 << 14); 991 writel(reg, mfc_regs->e_h264_options); 992 993 /* ASO */ 994 readl(mfc_regs->e_h264_options); 995 reg &= ~(0x1 << 6); 996 reg |= ((p_h264->aso & 0x1) << 6); 997 writel(reg, mfc_regs->e_h264_options); 998 999 /* hier qp enable */ 1000 readl(mfc_regs->e_h264_options); 1001 reg &= ~(0x1 << 8); 1002 reg |= ((p_h264->open_gop & 0x1) << 8); 1003 writel(reg, mfc_regs->e_h264_options); 1004 reg = 0; 1005 if (p_h264->hier_qp && p_h264->hier_qp_layer) { 1006 reg |= (p_h264->hier_qp_type & 0x1) << 0x3; 1007 reg |= p_h264->hier_qp_layer & 0x7; 1008 writel(reg, mfc_regs->e_h264_num_t_layer); 1009 /* QP value for each layer */ 1010 for (i = 0; i < p_h264->hier_qp_layer && 1011 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) { 1012 writel(p_h264->hier_qp_layer_qp[i], 1013 mfc_regs->e_h264_hierarchical_qp_layer0 1014 + i * 4); 1015 } 1016 } 1017 /* number of coding layer should be zero when hierarchical is disable */ 1018 writel(reg, mfc_regs->e_h264_num_t_layer); 1019 1020 /* frame packing SEI generation */ 1021 readl(mfc_regs->e_h264_options); 1022 reg &= ~(0x1 << 25); 1023 reg |= ((p_h264->sei_frame_packing & 0x1) << 25); 1024 writel(reg, mfc_regs->e_h264_options); 1025 if (p_h264->sei_frame_packing) { 1026 reg = 0; 1027 /** current frame0 flag */ 1028 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); 1029 /** arrangement type */ 1030 reg |= p_h264->sei_fp_arrangement_type & 0x3; 1031 writel(reg, mfc_regs->e_h264_frame_packing_sei_info); 1032 } 1033 1034 if (p_h264->fmo) { 1035 switch (p_h264->fmo_map_type) { 1036 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES: 1037 if (p_h264->fmo_slice_grp > 4) 1038 p_h264->fmo_slice_grp = 4; 1039 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++) 1040 writel(p_h264->fmo_run_len[i] - 1, 1041 mfc_regs->e_h264_fmo_run_length_minus1_0 1042 + i * 4); 1043 break; 1044 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: 1045 if (p_h264->fmo_slice_grp > 4) 1046 p_h264->fmo_slice_grp = 4; 1047 break; 1048 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN: 1049 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: 1050 if (p_h264->fmo_slice_grp > 2) 1051 p_h264->fmo_slice_grp = 2; 1052 writel(p_h264->fmo_chg_dir & 0x1, 1053 mfc_regs->e_h264_fmo_slice_grp_change_dir); 1054 /* the valid range is 0 ~ number of macroblocks -1 */ 1055 writel(p_h264->fmo_chg_rate, 1056 mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1); 1057 break; 1058 default: 1059 mfc_err("Unsupported map type for FMO: %d\n", 1060 p_h264->fmo_map_type); 1061 p_h264->fmo_map_type = 0; 1062 p_h264->fmo_slice_grp = 1; 1063 break; 1064 } 1065 1066 writel(p_h264->fmo_map_type, 1067 mfc_regs->e_h264_fmo_slice_grp_map_type); 1068 writel(p_h264->fmo_slice_grp - 1, 1069 mfc_regs->e_h264_fmo_num_slice_grp_minus1); 1070 } else { 1071 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1); 1072 } 1073 1074 mfc_debug_leave(); 1075 1076 return 0; 1077} 1078 1079static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) 1080{ 1081 struct s5p_mfc_dev *dev = ctx->dev; 1082 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1083 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1084 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; 1085 unsigned int reg = 0; 1086 1087 mfc_debug_enter(); 1088 1089 s5p_mfc_set_enc_params(ctx); 1090 1091 /* pictype : number of B */ 1092 reg = readl(mfc_regs->e_gop_config); 1093 reg &= ~(0x3 << 16); 1094 reg |= ((p->num_b_frame & 0x3) << 16); 1095 writel(reg, mfc_regs->e_gop_config); 1096 1097 /* profile & level */ 1098 reg = 0; 1099 /** level */ 1100 reg |= ((p_mpeg4->level & 0xFF) << 8); 1101 /** profile - 0 ~ 1 */ 1102 reg |= p_mpeg4->profile & 0x3F; 1103 writel(reg, mfc_regs->e_picture_profile); 1104 1105 /* rate control config. */ 1106 reg = readl(mfc_regs->e_rc_config); 1107 /** macroblock level rate control */ 1108 reg &= ~(0x1 << 8); 1109 reg |= ((p->rc_mb & 0x1) << 8); 1110 writel(reg, mfc_regs->e_rc_config); 1111 1112 /** frame QP */ 1113 reg &= ~(0x3F); 1114 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1115 writel(reg, mfc_regs->e_rc_config); 1116 1117 /* max & min value of QP */ 1118 reg = 0; 1119 /** max QP */ 1120 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); 1121 /** min QP */ 1122 reg |= p_mpeg4->rc_min_qp & 0x3F; 1123 writel(reg, mfc_regs->e_rc_qp_bound); 1124 1125 /* other QPs */ 1126 writel(0x0, mfc_regs->e_fixed_picture_qp); 1127 if (!p->rc_frame && !p->rc_mb) { 1128 reg = 0; 1129 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); 1130 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); 1131 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1132 writel(reg, mfc_regs->e_fixed_picture_qp); 1133 } 1134 1135 /* frame rate */ 1136 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 1137 reg = 0; 1138 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1139 reg |= p->rc_framerate_denom & 0xFFFF; 1140 writel(reg, mfc_regs->e_rc_frame_rate); 1141 } 1142 1143 /* vbv buffer size */ 1144 if (p->frame_skip_mode == 1145 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1146 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1147 1148 if (p->rc_frame) 1149 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1150 } 1151 1152 /* Disable HEC */ 1153 writel(0x0, mfc_regs->e_mpeg4_options); 1154 writel(0x0, mfc_regs->e_mpeg4_hec_period); 1155 1156 mfc_debug_leave(); 1157 1158 return 0; 1159} 1160 1161static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) 1162{ 1163 struct s5p_mfc_dev *dev = ctx->dev; 1164 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1165 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1166 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; 1167 unsigned int reg = 0; 1168 1169 mfc_debug_enter(); 1170 1171 s5p_mfc_set_enc_params(ctx); 1172 1173 /* profile & level */ 1174 reg = 0; 1175 /** profile */ 1176 reg |= (0x1 << 4); 1177 writel(reg, mfc_regs->e_picture_profile); 1178 1179 /* rate control config. */ 1180 reg = readl(mfc_regs->e_rc_config); 1181 /** macroblock level rate control */ 1182 reg &= ~(0x1 << 8); 1183 reg |= ((p->rc_mb & 0x1) << 8); 1184 writel(reg, mfc_regs->e_rc_config); 1185 1186 /** frame QP */ 1187 reg &= ~(0x3F); 1188 reg |= p_h263->rc_frame_qp & 0x3F; 1189 writel(reg, mfc_regs->e_rc_config); 1190 1191 /* max & min value of QP */ 1192 reg = 0; 1193 /** max QP */ 1194 reg |= ((p_h263->rc_max_qp & 0x3F) << 8); 1195 /** min QP */ 1196 reg |= p_h263->rc_min_qp & 0x3F; 1197 writel(reg, mfc_regs->e_rc_qp_bound); 1198 1199 /* other QPs */ 1200 writel(0x0, mfc_regs->e_fixed_picture_qp); 1201 if (!p->rc_frame && !p->rc_mb) { 1202 reg = 0; 1203 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); 1204 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); 1205 reg |= p_h263->rc_frame_qp & 0x3F; 1206 writel(reg, mfc_regs->e_fixed_picture_qp); 1207 } 1208 1209 /* frame rate */ 1210 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 1211 reg = 0; 1212 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1213 reg |= p->rc_framerate_denom & 0xFFFF; 1214 writel(reg, mfc_regs->e_rc_frame_rate); 1215 } 1216 1217 /* vbv buffer size */ 1218 if (p->frame_skip_mode == 1219 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1220 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1221 1222 if (p->rc_frame) 1223 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1224 } 1225 1226 mfc_debug_leave(); 1227 1228 return 0; 1229} 1230 1231static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) 1232{ 1233 struct s5p_mfc_dev *dev = ctx->dev; 1234 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1235 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1236 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8; 1237 unsigned int reg = 0; 1238 unsigned int val = 0; 1239 1240 mfc_debug_enter(); 1241 1242 s5p_mfc_set_enc_params(ctx); 1243 1244 /* pictype : number of B */ 1245 reg = readl(mfc_regs->e_gop_config); 1246 reg &= ~(0x3 << 16); 1247 reg |= ((p->num_b_frame & 0x3) << 16); 1248 writel(reg, mfc_regs->e_gop_config); 1249 1250 /* profile - 0 ~ 3 */ 1251 reg = p_vp8->profile & 0x3; 1252 writel(reg, mfc_regs->e_picture_profile); 1253 1254 /* rate control config. */ 1255 reg = readl(mfc_regs->e_rc_config); 1256 /** macroblock level rate control */ 1257 reg &= ~(0x1 << 8); 1258 reg |= ((p->rc_mb & 0x1) << 8); 1259 writel(reg, mfc_regs->e_rc_config); 1260 1261 /* frame rate */ 1262 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 1263 reg = 0; 1264 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1265 reg |= p->rc_framerate_denom & 0xFFFF; 1266 writel(reg, mfc_regs->e_rc_frame_rate); 1267 } 1268 1269 /* frame QP */ 1270 reg &= ~(0x7F); 1271 reg |= p_vp8->rc_frame_qp & 0x7F; 1272 writel(reg, mfc_regs->e_rc_config); 1273 1274 /* other QPs */ 1275 writel(0x0, mfc_regs->e_fixed_picture_qp); 1276 if (!p->rc_frame && !p->rc_mb) { 1277 reg = 0; 1278 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); 1279 reg |= p_vp8->rc_frame_qp & 0x7F; 1280 writel(reg, mfc_regs->e_fixed_picture_qp); 1281 } 1282 1283 /* max QP */ 1284 reg = ((p_vp8->rc_max_qp & 0x7F) << 8); 1285 /* min QP */ 1286 reg |= p_vp8->rc_min_qp & 0x7F; 1287 writel(reg, mfc_regs->e_rc_qp_bound); 1288 1289 /* vbv buffer size */ 1290 if (p->frame_skip_mode == 1291 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1292 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1293 1294 if (p->rc_frame) 1295 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1296 } 1297 1298 /* VP8 specific params */ 1299 reg = 0; 1300 reg |= (p_vp8->imd_4x4 & 0x1) << 10; 1301 switch (p_vp8->num_partitions) { 1302 case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION: 1303 val = 0; 1304 break; 1305 case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS: 1306 val = 2; 1307 break; 1308 case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS: 1309 val = 4; 1310 break; 1311 case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS: 1312 val = 8; 1313 break; 1314 } 1315 reg |= (val & 0xF) << 3; 1316 reg |= (p_vp8->num_ref & 0x2); 1317 writel(reg, mfc_regs->e_vp8_options); 1318 1319 mfc_debug_leave(); 1320 1321 return 0; 1322} 1323 1324/* Initialize decoding */ 1325static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) 1326{ 1327 struct s5p_mfc_dev *dev = ctx->dev; 1328 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1329 unsigned int reg = 0; 1330 int fmo_aso_ctrl = 0; 1331 1332 mfc_debug_enter(); 1333 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, 1334 S5P_FIMV_CH_SEQ_HEADER_V6); 1335 mfc_debug(2, "BUFs: %08x %08x %08x\n", 1336 readl(mfc_regs->d_cpb_buffer_addr), 1337 readl(mfc_regs->d_cpb_buffer_addr), 1338 readl(mfc_regs->d_cpb_buffer_addr)); 1339 1340 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ 1341 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); 1342 1343 /* When user sets desplay_delay to 0, 1344 * It works as "display_delay enable" and delay set to 0. 1345 * If user wants display_delay disable, It should be 1346 * set to negative value. */ 1347 if (ctx->display_delay >= 0) { 1348 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); 1349 writel(ctx->display_delay, mfc_regs->d_display_delay); 1350 } 1351 1352 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) { 1353 writel(reg, mfc_regs->d_dec_options); 1354 reg = 0; 1355 } 1356 1357 /* Setup loop filter, for decoding this is only valid for MPEG4 */ 1358 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) { 1359 mfc_debug(2, "Set loop filter to: %d\n", 1360 ctx->loop_filter_mpeg4); 1361 reg |= (ctx->loop_filter_mpeg4 << 1362 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6); 1363 } 1364 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) 1365 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); 1366 1367 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) 1368 writel(reg, mfc_regs->d_init_buffer_options); 1369 else 1370 writel(reg, mfc_regs->d_dec_options); 1371 1372 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 1373 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) 1374 writel(0x1, mfc_regs->pixel_format); 1375 else 1376 writel(0x0, mfc_regs->pixel_format); 1377 1378 1379 /* sei parse */ 1380 writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable); 1381 1382 writel(ctx->inst_no, mfc_regs->instance_id); 1383 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1384 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1385 1386 mfc_debug_leave(); 1387 return 0; 1388} 1389 1390static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) 1391{ 1392 struct s5p_mfc_dev *dev = ctx->dev; 1393 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1394 1395 if (flush) { 1396 dev->curr_ctx = ctx->num; 1397 s5p_mfc_clean_ctx_int_flags(ctx); 1398 writel(ctx->inst_no, mfc_regs->instance_id); 1399 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1400 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL); 1401 } 1402} 1403 1404/* Decode a single frame */ 1405static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx, 1406 enum s5p_mfc_decode_arg last_frame) 1407{ 1408 struct s5p_mfc_dev *dev = ctx->dev; 1409 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1410 1411 writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower); 1412 writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable); 1413 1414 writel(ctx->inst_no, mfc_regs->instance_id); 1415 /* Issue different commands to instance basing on whether it 1416 * is the last frame or not. */ 1417 switch (last_frame) { 1418 case 0: 1419 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1420 S5P_FIMV_CH_FRAME_START_V6, NULL); 1421 break; 1422 case 1: 1423 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1424 S5P_FIMV_CH_LAST_FRAME_V6, NULL); 1425 break; 1426 default: 1427 mfc_err("Unsupported last frame arg.\n"); 1428 return -EINVAL; 1429 } 1430 1431 mfc_debug(2, "Decoding a usual frame.\n"); 1432 return 0; 1433} 1434 1435static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) 1436{ 1437 struct s5p_mfc_dev *dev = ctx->dev; 1438 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1439 1440 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 1441 s5p_mfc_set_enc_params_h264(ctx); 1442 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) 1443 s5p_mfc_set_enc_params_mpeg4(ctx); 1444 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) 1445 s5p_mfc_set_enc_params_h263(ctx); 1446 else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC) 1447 s5p_mfc_set_enc_params_vp8(ctx); 1448 else { 1449 mfc_err("Unknown codec for encoding (%x).\n", 1450 ctx->codec_mode); 1451 return -EINVAL; 1452 } 1453 1454 /* Set stride lengths for v7 & above */ 1455 if (IS_MFCV7_PLUS(dev)) { 1456 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride); 1457 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride); 1458 } 1459 1460 writel(ctx->inst_no, mfc_regs->instance_id); 1461 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1462 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1463 1464 return 0; 1465} 1466 1467static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx) 1468{ 1469 struct s5p_mfc_dev *dev = ctx->dev; 1470 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1471 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1472 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264; 1473 int i; 1474 1475 if (p_h264->aso) { 1476 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) { 1477 writel(p_h264->aso_slice_order[i], 1478 mfc_regs->e_h264_aso_slice_order_0 + i * 4); 1479 } 1480 } 1481 return 0; 1482} 1483 1484/* Encode a single frame */ 1485static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx) 1486{ 1487 struct s5p_mfc_dev *dev = ctx->dev; 1488 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1489 1490 mfc_debug(2, "++\n"); 1491 1492 /* memory structure cur. frame */ 1493 1494 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 1495 s5p_mfc_h264_set_aso_slice_order_v6(ctx); 1496 1497 s5p_mfc_set_slice_mode(ctx); 1498 1499 writel(ctx->inst_no, mfc_regs->instance_id); 1500 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev, 1501 S5P_FIMV_CH_FRAME_START_V6, NULL); 1502 1503 mfc_debug(2, "--\n"); 1504 1505 return 0; 1506} 1507 1508static inline int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) 1509{ 1510 unsigned long flags; 1511 int new_ctx; 1512 int cnt; 1513 1514 spin_lock_irqsave(&dev->condlock, flags); 1515 mfc_debug(2, "Previous context: %d (bits %08lx)\n", dev->curr_ctx, 1516 dev->ctx_work_bits); 1517 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; 1518 cnt = 0; 1519 while (!test_bit(new_ctx, &dev->ctx_work_bits)) { 1520 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; 1521 cnt++; 1522 if (cnt > MFC_NUM_CONTEXTS) { 1523 /* No contexts to run */ 1524 spin_unlock_irqrestore(&dev->condlock, flags); 1525 return -EAGAIN; 1526 } 1527 } 1528 spin_unlock_irqrestore(&dev->condlock, flags); 1529 return new_ctx; 1530} 1531 1532static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx) 1533{ 1534 struct s5p_mfc_dev *dev = ctx->dev; 1535 struct s5p_mfc_buf *temp_vb; 1536 unsigned long flags; 1537 1538 spin_lock_irqsave(&dev->irqlock, flags); 1539 1540 /* Frames are being decoded */ 1541 if (list_empty(&ctx->src_queue)) { 1542 mfc_debug(2, "No src buffers.\n"); 1543 spin_unlock_irqrestore(&dev->irqlock, flags); 1544 return; 1545 } 1546 /* Get the next source buffer */ 1547 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1548 temp_vb->flags |= MFC_BUF_FLAG_USED; 1549 s5p_mfc_set_dec_stream_buffer_v6(ctx, 1550 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 0); 1551 spin_unlock_irqrestore(&dev->irqlock, flags); 1552 1553 dev->curr_ctx = ctx->num; 1554 s5p_mfc_clean_ctx_int_flags(ctx); 1555 s5p_mfc_decode_one_frame_v6(ctx, 1); 1556} 1557 1558static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) 1559{ 1560 struct s5p_mfc_dev *dev = ctx->dev; 1561 struct s5p_mfc_buf *temp_vb; 1562 unsigned long flags; 1563 int last_frame = 0; 1564 1565 if (ctx->state == MFCINST_FINISHING) { 1566 last_frame = MFC_DEC_LAST_FRAME; 1567 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0); 1568 dev->curr_ctx = ctx->num; 1569 s5p_mfc_clean_ctx_int_flags(ctx); 1570 s5p_mfc_decode_one_frame_v6(ctx, last_frame); 1571 return 0; 1572 } 1573 1574 spin_lock_irqsave(&dev->irqlock, flags); 1575 /* Frames are being decoded */ 1576 if (list_empty(&ctx->src_queue)) { 1577 mfc_debug(2, "No src buffers.\n"); 1578 spin_unlock_irqrestore(&dev->irqlock, flags); 1579 return -EAGAIN; 1580 } 1581 /* Get the next source buffer */ 1582 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1583 temp_vb->flags |= MFC_BUF_FLAG_USED; 1584 s5p_mfc_set_dec_stream_buffer_v6(ctx, 1585 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1586 ctx->consumed_stream, 1587 temp_vb->b->v4l2_planes[0].bytesused); 1588 spin_unlock_irqrestore(&dev->irqlock, flags); 1589 1590 dev->curr_ctx = ctx->num; 1591 s5p_mfc_clean_ctx_int_flags(ctx); 1592 if (temp_vb->b->v4l2_planes[0].bytesused == 0) { 1593 last_frame = 1; 1594 mfc_debug(2, "Setting ctx->state to FINISHING\n"); 1595 ctx->state = MFCINST_FINISHING; 1596 } 1597 s5p_mfc_decode_one_frame_v6(ctx, last_frame); 1598 1599 return 0; 1600} 1601 1602static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) 1603{ 1604 struct s5p_mfc_dev *dev = ctx->dev; 1605 unsigned long flags; 1606 struct s5p_mfc_buf *dst_mb; 1607 struct s5p_mfc_buf *src_mb; 1608 unsigned long src_y_addr, src_c_addr, dst_addr; 1609 /* 1610 unsigned int src_y_size, src_c_size; 1611 */ 1612 unsigned int dst_size; 1613 1614 spin_lock_irqsave(&dev->irqlock, flags); 1615 1616 if (list_empty(&ctx->src_queue)) { 1617 mfc_debug(2, "no src buffers.\n"); 1618 spin_unlock_irqrestore(&dev->irqlock, flags); 1619 return -EAGAIN; 1620 } 1621 1622 if (list_empty(&ctx->dst_queue)) { 1623 mfc_debug(2, "no dst buffers.\n"); 1624 spin_unlock_irqrestore(&dev->irqlock, flags); 1625 return -EAGAIN; 1626 } 1627 1628 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1629 src_mb->flags |= MFC_BUF_FLAG_USED; 1630 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0); 1631 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1); 1632 1633 mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr); 1634 mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr); 1635 1636 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr); 1637 1638 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1639 dst_mb->flags |= MFC_BUF_FLAG_USED; 1640 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1641 dst_size = vb2_plane_size(dst_mb->b, 0); 1642 1643 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size); 1644 1645 spin_unlock_irqrestore(&dev->irqlock, flags); 1646 1647 dev->curr_ctx = ctx->num; 1648 s5p_mfc_clean_ctx_int_flags(ctx); 1649 s5p_mfc_encode_one_frame_v6(ctx); 1650 1651 return 0; 1652} 1653 1654static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) 1655{ 1656 struct s5p_mfc_dev *dev = ctx->dev; 1657 unsigned long flags; 1658 struct s5p_mfc_buf *temp_vb; 1659 1660 /* Initializing decoding - parsing header */ 1661 spin_lock_irqsave(&dev->irqlock, flags); 1662 mfc_debug(2, "Preparing to init decoding.\n"); 1663 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1664 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); 1665 s5p_mfc_set_dec_stream_buffer_v6(ctx, 1666 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 0, 1667 temp_vb->b->v4l2_planes[0].bytesused); 1668 spin_unlock_irqrestore(&dev->irqlock, flags); 1669 dev->curr_ctx = ctx->num; 1670 s5p_mfc_clean_ctx_int_flags(ctx); 1671 s5p_mfc_init_decode_v6(ctx); 1672} 1673 1674static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) 1675{ 1676 struct s5p_mfc_dev *dev = ctx->dev; 1677 unsigned long flags; 1678 struct s5p_mfc_buf *dst_mb; 1679 unsigned long dst_addr; 1680 unsigned int dst_size; 1681 1682 spin_lock_irqsave(&dev->irqlock, flags); 1683 1684 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1685 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1686 dst_size = vb2_plane_size(dst_mb->b, 0); 1687 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size); 1688 spin_unlock_irqrestore(&dev->irqlock, flags); 1689 dev->curr_ctx = ctx->num; 1690 s5p_mfc_clean_ctx_int_flags(ctx); 1691 s5p_mfc_init_encode_v6(ctx); 1692} 1693 1694static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) 1695{ 1696 struct s5p_mfc_dev *dev = ctx->dev; 1697 int ret; 1698 /* Header was parsed now start processing 1699 * First set the output frame buffers 1700 * s5p_mfc_alloc_dec_buffers(ctx); */ 1701 1702 if (ctx->capture_state != QUEUE_BUFS_MMAPED) { 1703 mfc_err("It seems that not all destionation buffers were\n" 1704 "mmaped.MFC requires that all destination are mmaped\n" 1705 "before starting processing.\n"); 1706 return -EAGAIN; 1707 } 1708 1709 dev->curr_ctx = ctx->num; 1710 s5p_mfc_clean_ctx_int_flags(ctx); 1711 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx); 1712 if (ret) { 1713 mfc_err("Failed to alloc frame mem.\n"); 1714 ctx->state = MFCINST_ERROR; 1715 } 1716 return ret; 1717} 1718 1719static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx) 1720{ 1721 struct s5p_mfc_dev *dev = ctx->dev; 1722 int ret; 1723 1724 dev->curr_ctx = ctx->num; 1725 s5p_mfc_clean_ctx_int_flags(ctx); 1726 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx); 1727 if (ret) { 1728 mfc_err("Failed to alloc frame mem.\n"); 1729 ctx->state = MFCINST_ERROR; 1730 } 1731 return ret; 1732} 1733 1734/* Try running an operation on hardware */ 1735static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev) 1736{ 1737 struct s5p_mfc_ctx *ctx; 1738 int new_ctx; 1739 unsigned int ret = 0; 1740 1741 mfc_debug(1, "Try run dev: %p\n", dev); 1742 1743 /* Check whether hardware is not running */ 1744 if (test_and_set_bit(0, &dev->hw_lock) != 0) { 1745 /* This is perfectly ok, the scheduled ctx should wait */ 1746 mfc_debug(1, "Couldn't lock HW.\n"); 1747 return; 1748 } 1749 1750 /* Choose the context to run */ 1751 new_ctx = s5p_mfc_get_new_ctx(dev); 1752 if (new_ctx < 0) { 1753 /* No contexts to run */ 1754 if (test_and_clear_bit(0, &dev->hw_lock) == 0) { 1755 mfc_err("Failed to unlock hardware.\n"); 1756 return; 1757 } 1758 1759 mfc_debug(1, "No ctx is scheduled to be run.\n"); 1760 return; 1761 } 1762 1763 mfc_debug(1, "New context: %d\n", new_ctx); 1764 ctx = dev->ctx[new_ctx]; 1765 mfc_debug(1, "Seting new context to %p\n", ctx); 1766 /* Got context to run in ctx */ 1767 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n", 1768 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt); 1769 mfc_debug(1, "ctx->state=%d\n", ctx->state); 1770 /* Last frame has already been sent to MFC 1771 * Now obtaining frames from MFC buffer */ 1772 1773 s5p_mfc_clock_on(); 1774 if (ctx->type == MFCINST_DECODER) { 1775 switch (ctx->state) { 1776 case MFCINST_FINISHING: 1777 s5p_mfc_run_dec_last_frames(ctx); 1778 break; 1779 case MFCINST_RUNNING: 1780 ret = s5p_mfc_run_dec_frame(ctx); 1781 break; 1782 case MFCINST_INIT: 1783 s5p_mfc_clean_ctx_int_flags(ctx); 1784 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1785 ctx); 1786 break; 1787 case MFCINST_RETURN_INST: 1788 s5p_mfc_clean_ctx_int_flags(ctx); 1789 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1790 ctx); 1791 break; 1792 case MFCINST_GOT_INST: 1793 s5p_mfc_run_init_dec(ctx); 1794 break; 1795 case MFCINST_HEAD_PARSED: 1796 ret = s5p_mfc_run_init_dec_buffers(ctx); 1797 break; 1798 case MFCINST_FLUSH: 1799 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); 1800 break; 1801 case MFCINST_RES_CHANGE_INIT: 1802 s5p_mfc_run_dec_last_frames(ctx); 1803 break; 1804 case MFCINST_RES_CHANGE_FLUSH: 1805 s5p_mfc_run_dec_last_frames(ctx); 1806 break; 1807 case MFCINST_RES_CHANGE_END: 1808 mfc_debug(2, "Finished remaining frames after resolution change.\n"); 1809 ctx->capture_state = QUEUE_FREE; 1810 mfc_debug(2, "Will re-init the codec`.\n"); 1811 s5p_mfc_run_init_dec(ctx); 1812 break; 1813 default: 1814 ret = -EAGAIN; 1815 } 1816 } else if (ctx->type == MFCINST_ENCODER) { 1817 switch (ctx->state) { 1818 case MFCINST_FINISHING: 1819 case MFCINST_RUNNING: 1820 ret = s5p_mfc_run_enc_frame(ctx); 1821 break; 1822 case MFCINST_INIT: 1823 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1824 ctx); 1825 break; 1826 case MFCINST_RETURN_INST: 1827 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1828 ctx); 1829 break; 1830 case MFCINST_GOT_INST: 1831 s5p_mfc_run_init_enc(ctx); 1832 break; 1833 case MFCINST_HEAD_PRODUCED: 1834 ret = s5p_mfc_run_init_enc_buffers(ctx); 1835 break; 1836 default: 1837 ret = -EAGAIN; 1838 } 1839 } else { 1840 mfc_err("invalid context type: %d\n", ctx->type); 1841 ret = -EAGAIN; 1842 } 1843 1844 if (ret) { 1845 /* Free hardware lock */ 1846 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 1847 mfc_err("Failed to unlock hardware.\n"); 1848 1849 /* This is in deed imporant, as no operation has been 1850 * scheduled, reduce the clock count as no one will 1851 * ever do this, because no interrupt related to this try_run 1852 * will ever come from hardware. */ 1853 s5p_mfc_clock_off(); 1854 } 1855} 1856 1857 1858static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq) 1859{ 1860 struct s5p_mfc_buf *b; 1861 int i; 1862 1863 while (!list_empty(lh)) { 1864 b = list_entry(lh->next, struct s5p_mfc_buf, list); 1865 for (i = 0; i < b->b->num_planes; i++) 1866 vb2_set_plane_payload(b->b, i, 0); 1867 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); 1868 list_del(&b->list); 1869 } 1870} 1871 1872static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev) 1873{ 1874 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1875 writel(0, mfc_regs->risc2host_command); 1876 writel(0, mfc_regs->risc2host_int); 1877} 1878 1879static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data, 1880 unsigned int ofs) 1881{ 1882 s5p_mfc_clock_on(); 1883 writel(data, (volatile void __iomem *)((unsigned long)ofs)); 1884 s5p_mfc_clock_off(); 1885} 1886 1887static unsigned int 1888s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs) 1889{ 1890 int ret; 1891 1892 s5p_mfc_clock_on(); 1893 ret = readl((volatile void __iomem *)((unsigned long)ofs)); 1894 s5p_mfc_clock_off(); 1895 1896 return ret; 1897} 1898 1899static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev) 1900{ 1901 return readl(dev->mfc_regs->d_display_first_plane_addr); 1902} 1903 1904static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev) 1905{ 1906 return readl(dev->mfc_regs->d_decoded_first_plane_addr); 1907} 1908 1909static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev) 1910{ 1911 return readl(dev->mfc_regs->d_display_status); 1912} 1913 1914static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev) 1915{ 1916 return readl(dev->mfc_regs->d_decoded_status); 1917} 1918 1919static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev) 1920{ 1921 return readl(dev->mfc_regs->d_decoded_frame_type) & 1922 S5P_FIMV_DECODE_FRAME_MASK_V6; 1923} 1924 1925static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx) 1926{ 1927 struct s5p_mfc_dev *dev = ctx->dev; 1928 return readl(dev->mfc_regs->d_display_frame_type) & 1929 S5P_FIMV_DECODE_FRAME_MASK_V6; 1930} 1931 1932static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev) 1933{ 1934 return readl(dev->mfc_regs->d_decoded_nal_size); 1935} 1936 1937static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev) 1938{ 1939 return readl(dev->mfc_regs->risc2host_command) & 1940 S5P_FIMV_RISC2HOST_CMD_MASK; 1941} 1942 1943static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev) 1944{ 1945 return readl(dev->mfc_regs->error_code); 1946} 1947 1948static int s5p_mfc_err_dec_v6(unsigned int err) 1949{ 1950 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6; 1951} 1952 1953static int s5p_mfc_err_dspl_v6(unsigned int err) 1954{ 1955 return (err & S5P_FIMV_ERR_DSPL_MASK_V6) >> S5P_FIMV_ERR_DSPL_SHIFT_V6; 1956} 1957 1958static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev) 1959{ 1960 return readl(dev->mfc_regs->d_display_frame_width); 1961} 1962 1963static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev) 1964{ 1965 return readl(dev->mfc_regs->d_display_frame_height); 1966} 1967 1968static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev) 1969{ 1970 return readl(dev->mfc_regs->d_min_num_dpb); 1971} 1972 1973static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) 1974{ 1975 return readl(dev->mfc_regs->d_min_num_mv); 1976} 1977 1978static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) 1979{ 1980 return readl(dev->mfc_regs->ret_instance_id); 1981} 1982 1983static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev) 1984{ 1985 return readl(dev->mfc_regs->e_num_dpb); 1986} 1987 1988static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev) 1989{ 1990 return readl(dev->mfc_regs->e_stream_size); 1991} 1992 1993static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev) 1994{ 1995 return readl(dev->mfc_regs->e_slice_type); 1996} 1997 1998static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev) 1999{ 2000 return readl(dev->mfc_regs->e_picture_count); 2001} 2002 2003static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx) 2004{ 2005 struct s5p_mfc_dev *dev = ctx->dev; 2006 return readl(dev->mfc_regs->d_frame_pack_sei_avail); 2007} 2008 2009static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev) 2010{ 2011 return readl(dev->mfc_regs->d_mvc_num_views); 2012} 2013 2014static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev) 2015{ 2016 return readl(dev->mfc_regs->d_mvc_view_id); 2017} 2018 2019static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx) 2020{ 2021 return s5p_mfc_read_info_v6(ctx, 2022 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top); 2023} 2024 2025static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx) 2026{ 2027 return s5p_mfc_read_info_v6(ctx, 2028 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot); 2029} 2030 2031static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx) 2032{ 2033 return s5p_mfc_read_info_v6(ctx, 2034 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1); 2035} 2036 2037static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx) 2038{ 2039 return s5p_mfc_read_info_v6(ctx, 2040 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2); 2041} 2042 2043static struct s5p_mfc_regs mfc_regs; 2044 2045/* Initialize registers for MFC v6 onwards */ 2046const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) 2047{ 2048 memset(&mfc_regs, 0, sizeof(mfc_regs)); 2049 2050#define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg)) 2051#define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r) 2052 /* codec common registers */ 2053 R(risc_on, S5P_FIMV_RISC_ON_V6); 2054 R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6); 2055 R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6); 2056 R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6); 2057 R(mfc_reset, S5P_FIMV_MFC_RESET_V6); 2058 R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6); 2059 R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6); 2060 R(firmware_version, S5P_FIMV_FW_VERSION_V6); 2061 R(instance_id, S5P_FIMV_INSTANCE_ID_V6); 2062 R(codec_type, S5P_FIMV_CODEC_TYPE_V6); 2063 R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6); 2064 R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6); 2065 R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6); 2066 R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6); 2067 R(error_code, S5P_FIMV_ERROR_CODE_V6); 2068 2069 /* decoder registers */ 2070 R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6); 2071 R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6); 2072 R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6); 2073 R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6); 2074 R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6); 2075 R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6); 2076 R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6); 2077 R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6); 2078 R(d_num_mv, S5P_FIMV_D_NUM_MV_V6); 2079 R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6); 2080 R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6); 2081 R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6); 2082 R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6); 2083 R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6); 2084 R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6); 2085 R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6); 2086 R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6); 2087 R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6); 2088 R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6); 2089 R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6); 2090 R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6); 2091 R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6); 2092 R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6); 2093 R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6); 2094 R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6); 2095 R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6); 2096 R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6); 2097 R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6); 2098 R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6); 2099 R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6); 2100 R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6); 2101 R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6); 2102 R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6); 2103 R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6); 2104 R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6); 2105 R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6); 2106 R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6); 2107 R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6); 2108 R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6); 2109 R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6); 2110 R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6); 2111 R(d_h264_info, S5P_FIMV_D_H264_INFO_V6); 2112 R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6); 2113 R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6); 2114 2115 /* encoder registers */ 2116 R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6); 2117 R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6); 2118 R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6); 2119 R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6); 2120 R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6); 2121 R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6); 2122 R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6); 2123 R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6); 2124 R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6); 2125 R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6); 2126 R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6); 2127 R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6); 2128 R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6); 2129 R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6); 2130 R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6); 2131 R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6); 2132 R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6); 2133 R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6); 2134 R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6); 2135 R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6); 2136 R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6); 2137 R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6); 2138 R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6); 2139 R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6); 2140 R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6); 2141 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6); 2142 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6); 2143 R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6); 2144 R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6); 2145 R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6); 2146 R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6); 2147 R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6); 2148 R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6); 2149 R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6); 2150 R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6); 2151 R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6); 2152 R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6); 2153 R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6); 2154 R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6); 2155 R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6); 2156 R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6); 2157 R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6); 2158 R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6); 2159 R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6); 2160 R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6); 2161 R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6); 2162 R(e_encoded_source_first_plane_addr, 2163 S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6); 2164 R(e_encoded_source_second_plane_addr, 2165 S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6); 2166 R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6); 2167 R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6); 2168 R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6); 2169 R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6); 2170 R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6); 2171 R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6); 2172 R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6); 2173 R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6); 2174 R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6); 2175 R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6); 2176 R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6); 2177 R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6); 2178 R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6); 2179 R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6); 2180 R(e_h264_fmo_slice_grp_map_type, 2181 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6); 2182 R(e_h264_fmo_num_slice_grp_minus1, 2183 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6); 2184 R(e_h264_fmo_slice_grp_change_dir, 2185 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6); 2186 R(e_h264_fmo_slice_grp_change_rate_minus1, 2187 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6); 2188 R(e_h264_fmo_run_length_minus1_0, 2189 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6); 2190 R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6); 2191 R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6); 2192 R(e_h264_hierarchical_qp_layer0, 2193 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6); 2194 R(e_h264_frame_packing_sei_info, 2195 S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6); 2196 2197 if (!IS_MFCV7_PLUS(dev)) 2198 goto done; 2199 2200 /* Initialize registers used in MFC v7+ */ 2201 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7); 2202 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7); 2203 R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7); 2204 R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7); 2205 R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7); 2206 R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7); 2207 R(e_encoded_source_first_plane_addr, 2208 S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7); 2209 R(e_encoded_source_second_plane_addr, 2210 S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7); 2211 R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7); 2212 2213 if (!IS_MFCV8(dev)) 2214 goto done; 2215 2216 /* Initialize registers used in MFC v8 only. 2217 * Also, over-write the registers which have 2218 * a different offset for MFC v8. */ 2219 R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8); 2220 R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8); 2221 R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8); 2222 R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8); 2223 R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8); 2224 R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8); 2225 R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8); 2226 R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8); 2227 R(d_first_plane_dpb_stride_size, 2228 S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8); 2229 R(d_second_plane_dpb_stride_size, 2230 S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8); 2231 R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8); 2232 R(d_num_mv, S5P_FIMV_D_NUM_MV_V8); 2233 R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8); 2234 R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8); 2235 R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8); 2236 R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8); 2237 R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8); 2238 R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8); 2239 R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8); 2240 R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8); 2241 R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8); 2242 R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8); 2243 R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8); 2244 R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8); 2245 R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8); 2246 R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8); 2247 R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8); 2248 R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8); 2249 R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8); 2250 R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8); 2251 R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8); 2252 R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8); 2253 R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8); 2254 R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8); 2255 R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8); 2256 R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8); 2257 2258 /* encoder registers */ 2259 R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8); 2260 R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8); 2261 R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8); 2262 R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8); 2263 R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8); 2264 R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8); 2265 R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8); 2266 R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8); 2267 R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8); 2268 R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8); 2269 R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8); 2270 R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8); 2271 R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8); 2272 2273done: 2274 return &mfc_regs; 2275#undef S5P_MFC_REG_ADDR 2276#undef R 2277} 2278 2279/* Initialize opr function pointers for MFC v6 */ 2280static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = { 2281 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6, 2282 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6, 2283 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6, 2284 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6, 2285 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6, 2286 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6, 2287 .alloc_dev_context_buffer = 2288 s5p_mfc_alloc_dev_context_buffer_v6, 2289 .release_dev_context_buffer = 2290 s5p_mfc_release_dev_context_buffer_v6, 2291 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6, 2292 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6, 2293 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v6, 2294 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v6, 2295 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6, 2296 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6, 2297 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6, 2298 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v6, 2299 .init_decode = s5p_mfc_init_decode_v6, 2300 .init_encode = s5p_mfc_init_encode_v6, 2301 .encode_one_frame = s5p_mfc_encode_one_frame_v6, 2302 .try_run = s5p_mfc_try_run_v6, 2303 .cleanup_queue = s5p_mfc_cleanup_queue_v6, 2304 .clear_int_flags = s5p_mfc_clear_int_flags_v6, 2305 .write_info = s5p_mfc_write_info_v6, 2306 .read_info = s5p_mfc_read_info_v6, 2307 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6, 2308 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6, 2309 .get_dspl_status = s5p_mfc_get_dspl_status_v6, 2310 .get_dec_status = s5p_mfc_get_dec_status_v6, 2311 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6, 2312 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6, 2313 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6, 2314 .get_int_reason = s5p_mfc_get_int_reason_v6, 2315 .get_int_err = s5p_mfc_get_int_err_v6, 2316 .err_dec = s5p_mfc_err_dec_v6, 2317 .err_dspl = s5p_mfc_err_dspl_v6, 2318 .get_img_width = s5p_mfc_get_img_width_v6, 2319 .get_img_height = s5p_mfc_get_img_height_v6, 2320 .get_dpb_count = s5p_mfc_get_dpb_count_v6, 2321 .get_mv_count = s5p_mfc_get_mv_count_v6, 2322 .get_inst_no = s5p_mfc_get_inst_no_v6, 2323 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6, 2324 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6, 2325 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6, 2326 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v6, 2327 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v6, 2328 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v6, 2329 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v6, 2330 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6, 2331 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6, 2332 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6, 2333 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6, 2334}; 2335 2336struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void) 2337{ 2338 return &s5p_mfc_ops_v6; 2339} 2340