1/* 2 * drivers/mtd/nand.c 3 * 4 * Overview: 5 * This is the generic MTD driver for NAND flash devices. It should be 6 * capable of working with almost all NAND chips currently available. 7 * 8 * Additional technical information is available on 9 * http://www.linux-mtd.infradead.org/doc/nand.html 10 * 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 13 * 14 * Credits: 15 * David Woodhouse for adding multichip support 16 * 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 18 * rework for 2K page size chips 19 * 20 * TODO: 21 * Enable cached programming for 2k page size chips 22 * Check, if mtd->ecctype should be set to MTD_ECC_HW 23 * if we have HW ECC support. 24 * BBT table is not serialized, has to be fixed 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License version 2 as 28 * published by the Free Software Foundation. 29 * 30 */ 31 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34#include <linux/module.h> 35#include <linux/delay.h> 36#include <linux/errno.h> 37#include <linux/err.h> 38#include <linux/sched.h> 39#include <linux/slab.h> 40#include <linux/mm.h> 41#include <linux/types.h> 42#include <linux/mtd/mtd.h> 43#include <linux/mtd/nand.h> 44#include <linux/mtd/nand_ecc.h> 45#include <linux/mtd/nand_bch.h> 46#include <linux/interrupt.h> 47#include <linux/bitops.h> 48#include <linux/leds.h> 49#include <linux/io.h> 50#include <linux/mtd/partitions.h> 51 52/* Define default oob placement schemes for large and small page devices */ 53static struct nand_ecclayout nand_oob_8 = { 54 .eccbytes = 3, 55 .eccpos = {0, 1, 2}, 56 .oobfree = { 57 {.offset = 3, 58 .length = 2}, 59 {.offset = 6, 60 .length = 2} } 61}; 62 63static struct nand_ecclayout nand_oob_16 = { 64 .eccbytes = 6, 65 .eccpos = {0, 1, 2, 3, 6, 7}, 66 .oobfree = { 67 {.offset = 8, 68 . length = 8} } 69}; 70 71static struct nand_ecclayout nand_oob_64 = { 72 .eccbytes = 24, 73 .eccpos = { 74 40, 41, 42, 43, 44, 45, 46, 47, 75 48, 49, 50, 51, 52, 53, 54, 55, 76 56, 57, 58, 59, 60, 61, 62, 63}, 77 .oobfree = { 78 {.offset = 2, 79 .length = 38} } 80}; 81 82static struct nand_ecclayout nand_oob_128 = { 83 .eccbytes = 48, 84 .eccpos = { 85 80, 81, 82, 83, 84, 85, 86, 87, 86 88, 89, 90, 91, 92, 93, 94, 95, 87 96, 97, 98, 99, 100, 101, 102, 103, 88 104, 105, 106, 107, 108, 109, 110, 111, 89 112, 113, 114, 115, 116, 117, 118, 119, 90 120, 121, 122, 123, 124, 125, 126, 127}, 91 .oobfree = { 92 {.offset = 2, 93 .length = 78} } 94}; 95 96static int nand_get_device(struct mtd_info *mtd, int new_state); 97 98static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 99 struct mtd_oob_ops *ops); 100 101/* 102 * For devices which display every fart in the system on a separate LED. Is 103 * compiled away when LED support is disabled. 104 */ 105DEFINE_LED_TRIGGER(nand_led_trigger); 106 107static int check_offs_len(struct mtd_info *mtd, 108 loff_t ofs, uint64_t len) 109{ 110 struct nand_chip *chip = mtd->priv; 111 int ret = 0; 112 113 /* Start address must align on block boundary */ 114 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 115 pr_debug("%s: unaligned address\n", __func__); 116 ret = -EINVAL; 117 } 118 119 /* Length must align on block boundary */ 120 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 121 pr_debug("%s: length not block aligned\n", __func__); 122 ret = -EINVAL; 123 } 124 125 return ret; 126} 127 128/** 129 * nand_release_device - [GENERIC] release chip 130 * @mtd: MTD device structure 131 * 132 * Release chip lock and wake up anyone waiting on the device. 133 */ 134static void nand_release_device(struct mtd_info *mtd) 135{ 136 struct nand_chip *chip = mtd->priv; 137 138 /* Release the controller and the chip */ 139 spin_lock(&chip->controller->lock); 140 chip->controller->active = NULL; 141 chip->state = FL_READY; 142 wake_up(&chip->controller->wq); 143 spin_unlock(&chip->controller->lock); 144} 145 146/** 147 * nand_read_byte - [DEFAULT] read one byte from the chip 148 * @mtd: MTD device structure 149 * 150 * Default read function for 8bit buswidth 151 */ 152static uint8_t nand_read_byte(struct mtd_info *mtd) 153{ 154 struct nand_chip *chip = mtd->priv; 155 return readb(chip->IO_ADDR_R); 156} 157 158/** 159 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip 160 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip 161 * @mtd: MTD device structure 162 * 163 * Default read function for 16bit buswidth with endianness conversion. 164 * 165 */ 166static uint8_t nand_read_byte16(struct mtd_info *mtd) 167{ 168 struct nand_chip *chip = mtd->priv; 169 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); 170} 171 172/** 173 * nand_read_word - [DEFAULT] read one word from the chip 174 * @mtd: MTD device structure 175 * 176 * Default read function for 16bit buswidth without endianness conversion. 177 */ 178static u16 nand_read_word(struct mtd_info *mtd) 179{ 180 struct nand_chip *chip = mtd->priv; 181 return readw(chip->IO_ADDR_R); 182} 183 184/** 185 * nand_select_chip - [DEFAULT] control CE line 186 * @mtd: MTD device structure 187 * @chipnr: chipnumber to select, -1 for deselect 188 * 189 * Default select function for 1 chip devices. 190 */ 191static void nand_select_chip(struct mtd_info *mtd, int chipnr) 192{ 193 struct nand_chip *chip = mtd->priv; 194 195 switch (chipnr) { 196 case -1: 197 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 198 break; 199 case 0: 200 break; 201 202 default: 203 BUG(); 204 } 205} 206 207/** 208 * nand_write_byte - [DEFAULT] write single byte to chip 209 * @mtd: MTD device structure 210 * @byte: value to write 211 * 212 * Default function to write a byte to I/O[7:0] 213 */ 214static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) 215{ 216 struct nand_chip *chip = mtd->priv; 217 218 chip->write_buf(mtd, &byte, 1); 219} 220 221/** 222 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 223 * @mtd: MTD device structure 224 * @byte: value to write 225 * 226 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. 227 */ 228static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) 229{ 230 struct nand_chip *chip = mtd->priv; 231 uint16_t word = byte; 232 233 /* 234 * It's not entirely clear what should happen to I/O[15:8] when writing 235 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: 236 * 237 * When the host supports a 16-bit bus width, only data is 238 * transferred at the 16-bit width. All address and command line 239 * transfers shall use only the lower 8-bits of the data bus. During 240 * command transfers, the host may place any value on the upper 241 * 8-bits of the data bus. During address transfers, the host shall 242 * set the upper 8-bits of the data bus to 00h. 243 * 244 * One user of the write_byte callback is nand_onfi_set_features. The 245 * four parameters are specified to be written to I/O[7:0], but this is 246 * neither an address nor a command transfer. Let's assume a 0 on the 247 * upper I/O lines is OK. 248 */ 249 chip->write_buf(mtd, (uint8_t *)&word, 2); 250} 251 252/** 253 * nand_write_buf - [DEFAULT] write buffer to chip 254 * @mtd: MTD device structure 255 * @buf: data buffer 256 * @len: number of bytes to write 257 * 258 * Default write function for 8bit buswidth. 259 */ 260static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 261{ 262 struct nand_chip *chip = mtd->priv; 263 264 iowrite8_rep(chip->IO_ADDR_W, buf, len); 265} 266 267/** 268 * nand_read_buf - [DEFAULT] read chip data into buffer 269 * @mtd: MTD device structure 270 * @buf: buffer to store date 271 * @len: number of bytes to read 272 * 273 * Default read function for 8bit buswidth. 274 */ 275static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 276{ 277 struct nand_chip *chip = mtd->priv; 278 279 ioread8_rep(chip->IO_ADDR_R, buf, len); 280} 281 282/** 283 * nand_write_buf16 - [DEFAULT] write buffer to chip 284 * @mtd: MTD device structure 285 * @buf: data buffer 286 * @len: number of bytes to write 287 * 288 * Default write function for 16bit buswidth. 289 */ 290static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 291{ 292 struct nand_chip *chip = mtd->priv; 293 u16 *p = (u16 *) buf; 294 295 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); 296} 297 298/** 299 * nand_read_buf16 - [DEFAULT] read chip data into buffer 300 * @mtd: MTD device structure 301 * @buf: buffer to store date 302 * @len: number of bytes to read 303 * 304 * Default read function for 16bit buswidth. 305 */ 306static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 307{ 308 struct nand_chip *chip = mtd->priv; 309 u16 *p = (u16 *) buf; 310 311 ioread16_rep(chip->IO_ADDR_R, p, len >> 1); 312} 313 314/** 315 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 316 * @mtd: MTD device structure 317 * @ofs: offset from device start 318 * @getchip: 0, if the chip is already selected 319 * 320 * Check, if the block is bad. 321 */ 322static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 323{ 324 int page, chipnr, res = 0, i = 0; 325 struct nand_chip *chip = mtd->priv; 326 u16 bad; 327 328 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 329 ofs += mtd->erasesize - mtd->writesize; 330 331 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 332 333 if (getchip) { 334 chipnr = (int)(ofs >> chip->chip_shift); 335 336 nand_get_device(mtd, FL_READING); 337 338 /* Select the NAND device */ 339 chip->select_chip(mtd, chipnr); 340 } 341 342 do { 343 if (chip->options & NAND_BUSWIDTH_16) { 344 chip->cmdfunc(mtd, NAND_CMD_READOOB, 345 chip->badblockpos & 0xFE, page); 346 bad = cpu_to_le16(chip->read_word(mtd)); 347 if (chip->badblockpos & 0x1) 348 bad >>= 8; 349 else 350 bad &= 0xFF; 351 } else { 352 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, 353 page); 354 bad = chip->read_byte(mtd); 355 } 356 357 if (likely(chip->badblockbits == 8)) 358 res = bad != 0xFF; 359 else 360 res = hweight8(bad) < chip->badblockbits; 361 ofs += mtd->writesize; 362 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 363 i++; 364 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); 365 366 if (getchip) { 367 chip->select_chip(mtd, -1); 368 nand_release_device(mtd); 369 } 370 371 return res; 372} 373 374/** 375 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 376 * @mtd: MTD device structure 377 * @ofs: offset from device start 378 * 379 * This is the default implementation, which can be overridden by a hardware 380 * specific driver. It provides the details for writing a bad block marker to a 381 * block. 382 */ 383static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 384{ 385 struct nand_chip *chip = mtd->priv; 386 struct mtd_oob_ops ops; 387 uint8_t buf[2] = { 0, 0 }; 388 int ret = 0, res, i = 0; 389 390 ops.datbuf = NULL; 391 ops.oobbuf = buf; 392 ops.ooboffs = chip->badblockpos; 393 if (chip->options & NAND_BUSWIDTH_16) { 394 ops.ooboffs &= ~0x01; 395 ops.len = ops.ooblen = 2; 396 } else { 397 ops.len = ops.ooblen = 1; 398 } 399 ops.mode = MTD_OPS_PLACE_OOB; 400 401 /* Write to first/last page(s) if necessary */ 402 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 403 ofs += mtd->erasesize - mtd->writesize; 404 do { 405 res = nand_do_write_oob(mtd, ofs, &ops); 406 if (!ret) 407 ret = res; 408 409 i++; 410 ofs += mtd->writesize; 411 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); 412 413 return ret; 414} 415 416/** 417 * nand_block_markbad_lowlevel - mark a block bad 418 * @mtd: MTD device structure 419 * @ofs: offset from device start 420 * 421 * This function performs the generic NAND bad block marking steps (i.e., bad 422 * block table(s) and/or marker(s)). We only allow the hardware driver to 423 * specify how to write bad block markers to OOB (chip->block_markbad). 424 * 425 * We try operations in the following order: 426 * (1) erase the affected block, to allow OOB marker to be written cleanly 427 * (2) write bad block marker to OOB area of affected block (unless flag 428 * NAND_BBT_NO_OOB_BBM is present) 429 * (3) update the BBT 430 * Note that we retain the first error encountered in (2) or (3), finish the 431 * procedures, and dump the error in the end. 432*/ 433static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) 434{ 435 struct nand_chip *chip = mtd->priv; 436 int res, ret = 0; 437 438 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 439 struct erase_info einfo; 440 441 /* Attempt erase before marking OOB */ 442 memset(&einfo, 0, sizeof(einfo)); 443 einfo.mtd = mtd; 444 einfo.addr = ofs; 445 einfo.len = 1ULL << chip->phys_erase_shift; 446 nand_erase_nand(mtd, &einfo, 0); 447 448 /* Write bad block marker to OOB */ 449 nand_get_device(mtd, FL_WRITING); 450 ret = chip->block_markbad(mtd, ofs); 451 nand_release_device(mtd); 452 } 453 454 /* Mark block bad in BBT */ 455 if (chip->bbt) { 456 res = nand_markbad_bbt(mtd, ofs); 457 if (!ret) 458 ret = res; 459 } 460 461 if (!ret) 462 mtd->ecc_stats.badblocks++; 463 464 return ret; 465} 466 467/** 468 * nand_check_wp - [GENERIC] check if the chip is write protected 469 * @mtd: MTD device structure 470 * 471 * Check, if the device is write protected. The function expects, that the 472 * device is already selected. 473 */ 474static int nand_check_wp(struct mtd_info *mtd) 475{ 476 struct nand_chip *chip = mtd->priv; 477 478 /* Broken xD cards report WP despite being writable */ 479 if (chip->options & NAND_BROKEN_XD) 480 return 0; 481 482 /* Check the WP bit */ 483 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 484 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; 485} 486 487/** 488 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 489 * @mtd: MTD device structure 490 * @ofs: offset from device start 491 * 492 * Check if the block is mark as reserved. 493 */ 494static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 495{ 496 struct nand_chip *chip = mtd->priv; 497 498 if (!chip->bbt) 499 return 0; 500 /* Return info from the table */ 501 return nand_isreserved_bbt(mtd, ofs); 502} 503 504/** 505 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 506 * @mtd: MTD device structure 507 * @ofs: offset from device start 508 * @getchip: 0, if the chip is already selected 509 * @allowbbt: 1, if its allowed to access the bbt area 510 * 511 * Check, if the block is bad. Either by reading the bad block table or 512 * calling of the scan function. 513 */ 514static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, 515 int allowbbt) 516{ 517 struct nand_chip *chip = mtd->priv; 518 519 if (!chip->bbt) 520 return chip->block_bad(mtd, ofs, getchip); 521 522 /* Return info from the table */ 523 return nand_isbad_bbt(mtd, ofs, allowbbt); 524} 525 526/** 527 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 528 * @mtd: MTD device structure 529 * @timeo: Timeout 530 * 531 * Helper function for nand_wait_ready used when needing to wait in interrupt 532 * context. 533 */ 534static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) 535{ 536 struct nand_chip *chip = mtd->priv; 537 int i; 538 539 /* Wait for the device to get ready */ 540 for (i = 0; i < timeo; i++) { 541 if (chip->dev_ready(mtd)) 542 break; 543 touch_softlockup_watchdog(); 544 mdelay(1); 545 } 546} 547 548/* Wait for the ready pin, after a command. The timeout is caught later. */ 549void nand_wait_ready(struct mtd_info *mtd) 550{ 551 struct nand_chip *chip = mtd->priv; 552 unsigned long timeo = jiffies + msecs_to_jiffies(20); 553 554 /* 400ms timeout */ 555 if (in_interrupt() || oops_in_progress) 556 return panic_nand_wait_ready(mtd, 400); 557 558 led_trigger_event(nand_led_trigger, LED_FULL); 559 /* Wait until command is processed or timeout occurs */ 560 do { 561 if (chip->dev_ready(mtd)) 562 break; 563 touch_softlockup_watchdog(); 564 } while (time_before(jiffies, timeo)); 565 led_trigger_event(nand_led_trigger, LED_OFF); 566} 567EXPORT_SYMBOL_GPL(nand_wait_ready); 568 569/** 570 * nand_command - [DEFAULT] Send command to NAND device 571 * @mtd: MTD device structure 572 * @command: the command to be sent 573 * @column: the column address for this command, -1 if none 574 * @page_addr: the page address for this command, -1 if none 575 * 576 * Send command to NAND device. This function is used for small page devices 577 * (512 Bytes per page). 578 */ 579static void nand_command(struct mtd_info *mtd, unsigned int command, 580 int column, int page_addr) 581{ 582 register struct nand_chip *chip = mtd->priv; 583 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 584 585 /* Write out the command to the device */ 586 if (command == NAND_CMD_SEQIN) { 587 int readcmd; 588 589 if (column >= mtd->writesize) { 590 /* OOB area */ 591 column -= mtd->writesize; 592 readcmd = NAND_CMD_READOOB; 593 } else if (column < 256) { 594 /* First 256 bytes --> READ0 */ 595 readcmd = NAND_CMD_READ0; 596 } else { 597 column -= 256; 598 readcmd = NAND_CMD_READ1; 599 } 600 chip->cmd_ctrl(mtd, readcmd, ctrl); 601 ctrl &= ~NAND_CTRL_CHANGE; 602 } 603 chip->cmd_ctrl(mtd, command, ctrl); 604 605 /* Address cycle, when necessary */ 606 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 607 /* Serially input address */ 608 if (column != -1) { 609 /* Adjust columns for 16 bit buswidth */ 610 if (chip->options & NAND_BUSWIDTH_16 && 611 !nand_opcode_8bits(command)) 612 column >>= 1; 613 chip->cmd_ctrl(mtd, column, ctrl); 614 ctrl &= ~NAND_CTRL_CHANGE; 615 } 616 if (page_addr != -1) { 617 chip->cmd_ctrl(mtd, page_addr, ctrl); 618 ctrl &= ~NAND_CTRL_CHANGE; 619 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); 620 /* One more address cycle for devices > 32MiB */ 621 if (chip->chipsize > (32 << 20)) 622 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); 623 } 624 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 625 626 /* 627 * Program and erase have their own busy handlers status and sequential 628 * in needs no delay 629 */ 630 switch (command) { 631 632 case NAND_CMD_PAGEPROG: 633 case NAND_CMD_ERASE1: 634 case NAND_CMD_ERASE2: 635 case NAND_CMD_SEQIN: 636 case NAND_CMD_STATUS: 637 return; 638 639 case NAND_CMD_RESET: 640 if (chip->dev_ready) 641 break; 642 udelay(chip->chip_delay); 643 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 644 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 645 chip->cmd_ctrl(mtd, 646 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 647 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) 648 ; 649 return; 650 651 /* This applies to read commands */ 652 default: 653 /* 654 * If we don't have access to the busy pin, we apply the given 655 * command delay 656 */ 657 if (!chip->dev_ready) { 658 udelay(chip->chip_delay); 659 return; 660 } 661 } 662 /* 663 * Apply this short delay always to ensure that we do wait tWB in 664 * any case on any machine. 665 */ 666 ndelay(100); 667 668 nand_wait_ready(mtd); 669} 670 671/** 672 * nand_command_lp - [DEFAULT] Send command to NAND large page device 673 * @mtd: MTD device structure 674 * @command: the command to be sent 675 * @column: the column address for this command, -1 if none 676 * @page_addr: the page address for this command, -1 if none 677 * 678 * Send command to NAND device. This is the version for the new large page 679 * devices. We don't have the separate regions as we have in the small page 680 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 681 */ 682static void nand_command_lp(struct mtd_info *mtd, unsigned int command, 683 int column, int page_addr) 684{ 685 register struct nand_chip *chip = mtd->priv; 686 687 /* Emulate NAND_CMD_READOOB */ 688 if (command == NAND_CMD_READOOB) { 689 column += mtd->writesize; 690 command = NAND_CMD_READ0; 691 } 692 693 /* Command latch cycle */ 694 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 695 696 if (column != -1 || page_addr != -1) { 697 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 698 699 /* Serially input address */ 700 if (column != -1) { 701 /* Adjust columns for 16 bit buswidth */ 702 if (chip->options & NAND_BUSWIDTH_16 && 703 !nand_opcode_8bits(command)) 704 column >>= 1; 705 chip->cmd_ctrl(mtd, column, ctrl); 706 ctrl &= ~NAND_CTRL_CHANGE; 707 chip->cmd_ctrl(mtd, column >> 8, ctrl); 708 } 709 if (page_addr != -1) { 710 chip->cmd_ctrl(mtd, page_addr, ctrl); 711 chip->cmd_ctrl(mtd, page_addr >> 8, 712 NAND_NCE | NAND_ALE); 713 /* One more address cycle for devices > 128MiB */ 714 if (chip->chipsize > (128 << 20)) 715 chip->cmd_ctrl(mtd, page_addr >> 16, 716 NAND_NCE | NAND_ALE); 717 } 718 } 719 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 720 721 /* 722 * Program and erase have their own busy handlers status, sequential 723 * in, and deplete1 need no delay. 724 */ 725 switch (command) { 726 727 case NAND_CMD_CACHEDPROG: 728 case NAND_CMD_PAGEPROG: 729 case NAND_CMD_ERASE1: 730 case NAND_CMD_ERASE2: 731 case NAND_CMD_SEQIN: 732 case NAND_CMD_RNDIN: 733 case NAND_CMD_STATUS: 734 return; 735 736 case NAND_CMD_RESET: 737 if (chip->dev_ready) 738 break; 739 udelay(chip->chip_delay); 740 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 741 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 742 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 743 NAND_NCE | NAND_CTRL_CHANGE); 744 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) 745 ; 746 return; 747 748 case NAND_CMD_RNDOUT: 749 /* No ready / busy check necessary */ 750 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, 751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 752 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 753 NAND_NCE | NAND_CTRL_CHANGE); 754 return; 755 756 case NAND_CMD_READ0: 757 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, 758 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 759 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 760 NAND_NCE | NAND_CTRL_CHANGE); 761 762 /* This applies to read commands */ 763 default: 764 /* 765 * If we don't have access to the busy pin, we apply the given 766 * command delay. 767 */ 768 if (!chip->dev_ready) { 769 udelay(chip->chip_delay); 770 return; 771 } 772 } 773 774 /* 775 * Apply this short delay always to ensure that we do wait tWB in 776 * any case on any machine. 777 */ 778 ndelay(100); 779 780 nand_wait_ready(mtd); 781} 782 783/** 784 * panic_nand_get_device - [GENERIC] Get chip for selected access 785 * @chip: the nand chip descriptor 786 * @mtd: MTD device structure 787 * @new_state: the state which is requested 788 * 789 * Used when in panic, no locks are taken. 790 */ 791static void panic_nand_get_device(struct nand_chip *chip, 792 struct mtd_info *mtd, int new_state) 793{ 794 /* Hardware controller shared among independent devices */ 795 chip->controller->active = chip; 796 chip->state = new_state; 797} 798 799/** 800 * nand_get_device - [GENERIC] Get chip for selected access 801 * @mtd: MTD device structure 802 * @new_state: the state which is requested 803 * 804 * Get the device and lock it for exclusive access 805 */ 806static int 807nand_get_device(struct mtd_info *mtd, int new_state) 808{ 809 struct nand_chip *chip = mtd->priv; 810 spinlock_t *lock = &chip->controller->lock; 811 wait_queue_head_t *wq = &chip->controller->wq; 812 DECLARE_WAITQUEUE(wait, current); 813retry: 814 spin_lock(lock); 815 816 /* Hardware controller shared among independent devices */ 817 if (!chip->controller->active) 818 chip->controller->active = chip; 819 820 if (chip->controller->active == chip && chip->state == FL_READY) { 821 chip->state = new_state; 822 spin_unlock(lock); 823 return 0; 824 } 825 if (new_state == FL_PM_SUSPENDED) { 826 if (chip->controller->active->state == FL_PM_SUSPENDED) { 827 chip->state = FL_PM_SUSPENDED; 828 spin_unlock(lock); 829 return 0; 830 } 831 } 832 set_current_state(TASK_UNINTERRUPTIBLE); 833 add_wait_queue(wq, &wait); 834 spin_unlock(lock); 835 schedule(); 836 remove_wait_queue(wq, &wait); 837 goto retry; 838} 839 840/** 841 * panic_nand_wait - [GENERIC] wait until the command is done 842 * @mtd: MTD device structure 843 * @chip: NAND chip structure 844 * @timeo: timeout 845 * 846 * Wait for command done. This is a helper function for nand_wait used when 847 * we are in interrupt context. May happen when in panic and trying to write 848 * an oops through mtdoops. 849 */ 850static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, 851 unsigned long timeo) 852{ 853 int i; 854 for (i = 0; i < timeo; i++) { 855 if (chip->dev_ready) { 856 if (chip->dev_ready(mtd)) 857 break; 858 } else { 859 if (chip->read_byte(mtd) & NAND_STATUS_READY) 860 break; 861 } 862 mdelay(1); 863 } 864} 865 866/** 867 * nand_wait - [DEFAULT] wait until the command is done 868 * @mtd: MTD device structure 869 * @chip: NAND chip structure 870 * 871 * Wait for command done. This applies to erase and program only. Erase can 872 * take up to 400ms and program up to 20ms according to general NAND and 873 * SmartMedia specs. 874 */ 875static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) 876{ 877 878 int status, state = chip->state; 879 unsigned long timeo = (state == FL_ERASING ? 400 : 20); 880 881 led_trigger_event(nand_led_trigger, LED_FULL); 882 883 /* 884 * Apply this short delay always to ensure that we do wait tWB in any 885 * case on any machine. 886 */ 887 ndelay(100); 888 889 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 890 891 if (in_interrupt() || oops_in_progress) 892 panic_nand_wait(mtd, chip, timeo); 893 else { 894 timeo = jiffies + msecs_to_jiffies(timeo); 895 while (time_before(jiffies, timeo)) { 896 if (chip->dev_ready) { 897 if (chip->dev_ready(mtd)) 898 break; 899 } else { 900 if (chip->read_byte(mtd) & NAND_STATUS_READY) 901 break; 902 } 903 cond_resched(); 904 } 905 } 906 led_trigger_event(nand_led_trigger, LED_OFF); 907 908 status = (int)chip->read_byte(mtd); 909 /* This can happen if in case of timeout or buggy dev_ready */ 910 WARN_ON(!(status & NAND_STATUS_READY)); 911 return status; 912} 913 914/** 915 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks 916 * @mtd: mtd info 917 * @ofs: offset to start unlock from 918 * @len: length to unlock 919 * @invert: when = 0, unlock the range of blocks within the lower and 920 * upper boundary address 921 * when = 1, unlock the range of blocks outside the boundaries 922 * of the lower and upper boundary address 923 * 924 * Returs unlock status. 925 */ 926static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, 927 uint64_t len, int invert) 928{ 929 int ret = 0; 930 int status, page; 931 struct nand_chip *chip = mtd->priv; 932 933 /* Submit address of first page to unlock */ 934 page = ofs >> chip->page_shift; 935 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); 936 937 /* Submit address of last page to unlock */ 938 page = (ofs + len) >> chip->page_shift; 939 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, 940 (page | invert) & chip->pagemask); 941 942 /* Call wait ready function */ 943 status = chip->waitfunc(mtd, chip); 944 /* See if device thinks it succeeded */ 945 if (status & NAND_STATUS_FAIL) { 946 pr_debug("%s: error status = 0x%08x\n", 947 __func__, status); 948 ret = -EIO; 949 } 950 951 return ret; 952} 953 954/** 955 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks 956 * @mtd: mtd info 957 * @ofs: offset to start unlock from 958 * @len: length to unlock 959 * 960 * Returns unlock status. 961 */ 962int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 963{ 964 int ret = 0; 965 int chipnr; 966 struct nand_chip *chip = mtd->priv; 967 968 pr_debug("%s: start = 0x%012llx, len = %llu\n", 969 __func__, (unsigned long long)ofs, len); 970 971 if (check_offs_len(mtd, ofs, len)) 972 ret = -EINVAL; 973 974 /* Align to last block address if size addresses end of the device */ 975 if (ofs + len == mtd->size) 976 len -= mtd->erasesize; 977 978 nand_get_device(mtd, FL_UNLOCKING); 979 980 /* Shift to get chip number */ 981 chipnr = ofs >> chip->chip_shift; 982 983 chip->select_chip(mtd, chipnr); 984 985 /* 986 * Reset the chip. 987 * If we want to check the WP through READ STATUS and check the bit 7 988 * we must reset the chip 989 * some operation can also clear the bit 7 of status register 990 * eg. erase/program a locked block 991 */ 992 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 993 994 /* Check, if it is write protected */ 995 if (nand_check_wp(mtd)) { 996 pr_debug("%s: device is write protected!\n", 997 __func__); 998 ret = -EIO; 999 goto out; 1000 } 1001 1002 ret = __nand_unlock(mtd, ofs, len, 0); 1003 1004out: 1005 chip->select_chip(mtd, -1); 1006 nand_release_device(mtd); 1007 1008 return ret; 1009} 1010EXPORT_SYMBOL(nand_unlock); 1011 1012/** 1013 * nand_lock - [REPLACEABLE] locks all blocks present in the device 1014 * @mtd: mtd info 1015 * @ofs: offset to start unlock from 1016 * @len: length to unlock 1017 * 1018 * This feature is not supported in many NAND parts. 'Micron' NAND parts do 1019 * have this feature, but it allows only to lock all blocks, not for specified 1020 * range for block. Implementing 'lock' feature by making use of 'unlock', for 1021 * now. 1022 * 1023 * Returns lock status. 1024 */ 1025int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 1026{ 1027 int ret = 0; 1028 int chipnr, status, page; 1029 struct nand_chip *chip = mtd->priv; 1030 1031 pr_debug("%s: start = 0x%012llx, len = %llu\n", 1032 __func__, (unsigned long long)ofs, len); 1033 1034 if (check_offs_len(mtd, ofs, len)) 1035 ret = -EINVAL; 1036 1037 nand_get_device(mtd, FL_LOCKING); 1038 1039 /* Shift to get chip number */ 1040 chipnr = ofs >> chip->chip_shift; 1041 1042 chip->select_chip(mtd, chipnr); 1043 1044 /* 1045 * Reset the chip. 1046 * If we want to check the WP through READ STATUS and check the bit 7 1047 * we must reset the chip 1048 * some operation can also clear the bit 7 of status register 1049 * eg. erase/program a locked block 1050 */ 1051 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1052 1053 /* Check, if it is write protected */ 1054 if (nand_check_wp(mtd)) { 1055 pr_debug("%s: device is write protected!\n", 1056 __func__); 1057 status = MTD_ERASE_FAILED; 1058 ret = -EIO; 1059 goto out; 1060 } 1061 1062 /* Submit address of first page to lock */ 1063 page = ofs >> chip->page_shift; 1064 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); 1065 1066 /* Call wait ready function */ 1067 status = chip->waitfunc(mtd, chip); 1068 /* See if device thinks it succeeded */ 1069 if (status & NAND_STATUS_FAIL) { 1070 pr_debug("%s: error status = 0x%08x\n", 1071 __func__, status); 1072 ret = -EIO; 1073 goto out; 1074 } 1075 1076 ret = __nand_unlock(mtd, ofs, len, 0x1); 1077 1078out: 1079 chip->select_chip(mtd, -1); 1080 nand_release_device(mtd); 1081 1082 return ret; 1083} 1084EXPORT_SYMBOL(nand_lock); 1085 1086/** 1087 * nand_read_page_raw - [INTERN] read raw page data without ecc 1088 * @mtd: mtd info structure 1089 * @chip: nand chip info structure 1090 * @buf: buffer to store read data 1091 * @oob_required: caller requires OOB data read to chip->oob_poi 1092 * @page: page number to read 1093 * 1094 * Not for syndrome calculating ECC controllers, which use a special oob layout. 1095 */ 1096static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1097 uint8_t *buf, int oob_required, int page) 1098{ 1099 chip->read_buf(mtd, buf, mtd->writesize); 1100 if (oob_required) 1101 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1102 return 0; 1103} 1104 1105/** 1106 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 1107 * @mtd: mtd info structure 1108 * @chip: nand chip info structure 1109 * @buf: buffer to store read data 1110 * @oob_required: caller requires OOB data read to chip->oob_poi 1111 * @page: page number to read 1112 * 1113 * We need a special oob layout and handling even when OOB isn't used. 1114 */ 1115static int nand_read_page_raw_syndrome(struct mtd_info *mtd, 1116 struct nand_chip *chip, uint8_t *buf, 1117 int oob_required, int page) 1118{ 1119 int eccsize = chip->ecc.size; 1120 int eccbytes = chip->ecc.bytes; 1121 uint8_t *oob = chip->oob_poi; 1122 int steps, size; 1123 1124 for (steps = chip->ecc.steps; steps > 0; steps--) { 1125 chip->read_buf(mtd, buf, eccsize); 1126 buf += eccsize; 1127 1128 if (chip->ecc.prepad) { 1129 chip->read_buf(mtd, oob, chip->ecc.prepad); 1130 oob += chip->ecc.prepad; 1131 } 1132 1133 chip->read_buf(mtd, oob, eccbytes); 1134 oob += eccbytes; 1135 1136 if (chip->ecc.postpad) { 1137 chip->read_buf(mtd, oob, chip->ecc.postpad); 1138 oob += chip->ecc.postpad; 1139 } 1140 } 1141 1142 size = mtd->oobsize - (oob - chip->oob_poi); 1143 if (size) 1144 chip->read_buf(mtd, oob, size); 1145 1146 return 0; 1147} 1148 1149/** 1150 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 1151 * @mtd: mtd info structure 1152 * @chip: nand chip info structure 1153 * @buf: buffer to store read data 1154 * @oob_required: caller requires OOB data read to chip->oob_poi 1155 * @page: page number to read 1156 */ 1157static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1158 uint8_t *buf, int oob_required, int page) 1159{ 1160 int i, eccsize = chip->ecc.size; 1161 int eccbytes = chip->ecc.bytes; 1162 int eccsteps = chip->ecc.steps; 1163 uint8_t *p = buf; 1164 uint8_t *ecc_calc = chip->buffers->ecccalc; 1165 uint8_t *ecc_code = chip->buffers->ecccode; 1166 uint32_t *eccpos = chip->ecc.layout->eccpos; 1167 unsigned int max_bitflips = 0; 1168 1169 chip->ecc.read_page_raw(mtd, chip, buf, 1, page); 1170 1171 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1172 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1173 1174 for (i = 0; i < chip->ecc.total; i++) 1175 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1176 1177 eccsteps = chip->ecc.steps; 1178 p = buf; 1179 1180 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1181 int stat; 1182 1183 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1184 if (stat < 0) { 1185 mtd->ecc_stats.failed++; 1186 } else { 1187 mtd->ecc_stats.corrected += stat; 1188 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1189 } 1190 } 1191 return max_bitflips; 1192} 1193 1194/** 1195 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 1196 * @mtd: mtd info structure 1197 * @chip: nand chip info structure 1198 * @data_offs: offset of requested data within the page 1199 * @readlen: data length 1200 * @bufpoi: buffer to store read data 1201 * @page: page number to read 1202 */ 1203static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 1204 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, 1205 int page) 1206{ 1207 int start_step, end_step, num_steps; 1208 uint32_t *eccpos = chip->ecc.layout->eccpos; 1209 uint8_t *p; 1210 int data_col_addr, i, gaps = 0; 1211 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 1212 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 1213 int index; 1214 unsigned int max_bitflips = 0; 1215 1216 /* Column address within the page aligned to ECC size (256bytes) */ 1217 start_step = data_offs / chip->ecc.size; 1218 end_step = (data_offs + readlen - 1) / chip->ecc.size; 1219 num_steps = end_step - start_step + 1; 1220 index = start_step * chip->ecc.bytes; 1221 1222 /* Data size aligned to ECC ecc.size */ 1223 datafrag_len = num_steps * chip->ecc.size; 1224 eccfrag_len = num_steps * chip->ecc.bytes; 1225 1226 data_col_addr = start_step * chip->ecc.size; 1227 /* If we read not a page aligned data */ 1228 if (data_col_addr != 0) 1229 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); 1230 1231 p = bufpoi + data_col_addr; 1232 chip->read_buf(mtd, p, datafrag_len); 1233 1234 /* Calculate ECC */ 1235 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 1236 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); 1237 1238 /* 1239 * The performance is faster if we position offsets according to 1240 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 1241 */ 1242 for (i = 0; i < eccfrag_len - 1; i++) { 1243 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { 1244 gaps = 1; 1245 break; 1246 } 1247 } 1248 if (gaps) { 1249 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 1250 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1251 } else { 1252 /* 1253 * Send the command to read the particular ECC bytes take care 1254 * about buswidth alignment in read_buf. 1255 */ 1256 aligned_pos = eccpos[index] & ~(busw - 1); 1257 aligned_len = eccfrag_len; 1258 if (eccpos[index] & (busw - 1)) 1259 aligned_len++; 1260 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) 1261 aligned_len++; 1262 1263 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 1264 mtd->writesize + aligned_pos, -1); 1265 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); 1266 } 1267 1268 for (i = 0; i < eccfrag_len; i++) 1269 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; 1270 1271 p = bufpoi + data_col_addr; 1272 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 1273 int stat; 1274 1275 stat = chip->ecc.correct(mtd, p, 1276 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); 1277 if (stat < 0) { 1278 mtd->ecc_stats.failed++; 1279 } else { 1280 mtd->ecc_stats.corrected += stat; 1281 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1282 } 1283 } 1284 return max_bitflips; 1285} 1286 1287/** 1288 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 1289 * @mtd: mtd info structure 1290 * @chip: nand chip info structure 1291 * @buf: buffer to store read data 1292 * @oob_required: caller requires OOB data read to chip->oob_poi 1293 * @page: page number to read 1294 * 1295 * Not for syndrome calculating ECC controllers which need a special oob layout. 1296 */ 1297static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 1298 uint8_t *buf, int oob_required, int page) 1299{ 1300 int i, eccsize = chip->ecc.size; 1301 int eccbytes = chip->ecc.bytes; 1302 int eccsteps = chip->ecc.steps; 1303 uint8_t *p = buf; 1304 uint8_t *ecc_calc = chip->buffers->ecccalc; 1305 uint8_t *ecc_code = chip->buffers->ecccode; 1306 uint32_t *eccpos = chip->ecc.layout->eccpos; 1307 unsigned int max_bitflips = 0; 1308 1309 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1310 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1311 chip->read_buf(mtd, p, eccsize); 1312 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1313 } 1314 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1315 1316 for (i = 0; i < chip->ecc.total; i++) 1317 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1318 1319 eccsteps = chip->ecc.steps; 1320 p = buf; 1321 1322 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1323 int stat; 1324 1325 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1326 if (stat < 0) { 1327 mtd->ecc_stats.failed++; 1328 } else { 1329 mtd->ecc_stats.corrected += stat; 1330 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1331 } 1332 } 1333 return max_bitflips; 1334} 1335 1336/** 1337 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first 1338 * @mtd: mtd info structure 1339 * @chip: nand chip info structure 1340 * @buf: buffer to store read data 1341 * @oob_required: caller requires OOB data read to chip->oob_poi 1342 * @page: page number to read 1343 * 1344 * Hardware ECC for large page chips, require OOB to be read first. For this 1345 * ECC mode, the write_page method is re-used from ECC_HW. These methods 1346 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with 1347 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from 1348 * the data area, by overwriting the NAND manufacturer bad block markings. 1349 */ 1350static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, 1351 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 1352{ 1353 int i, eccsize = chip->ecc.size; 1354 int eccbytes = chip->ecc.bytes; 1355 int eccsteps = chip->ecc.steps; 1356 uint8_t *p = buf; 1357 uint8_t *ecc_code = chip->buffers->ecccode; 1358 uint32_t *eccpos = chip->ecc.layout->eccpos; 1359 uint8_t *ecc_calc = chip->buffers->ecccalc; 1360 unsigned int max_bitflips = 0; 1361 1362 /* Read the OOB area first */ 1363 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1364 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1365 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 1366 1367 for (i = 0; i < chip->ecc.total; i++) 1368 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1369 1370 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1371 int stat; 1372 1373 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1374 chip->read_buf(mtd, p, eccsize); 1375 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1376 1377 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); 1378 if (stat < 0) { 1379 mtd->ecc_stats.failed++; 1380 } else { 1381 mtd->ecc_stats.corrected += stat; 1382 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1383 } 1384 } 1385 return max_bitflips; 1386} 1387 1388/** 1389 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 1390 * @mtd: mtd info structure 1391 * @chip: nand chip info structure 1392 * @buf: buffer to store read data 1393 * @oob_required: caller requires OOB data read to chip->oob_poi 1394 * @page: page number to read 1395 * 1396 * The hw generator calculates the error syndrome automatically. Therefore we 1397 * need a special oob layout and handling. 1398 */ 1399static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1400 uint8_t *buf, int oob_required, int page) 1401{ 1402 int i, eccsize = chip->ecc.size; 1403 int eccbytes = chip->ecc.bytes; 1404 int eccsteps = chip->ecc.steps; 1405 uint8_t *p = buf; 1406 uint8_t *oob = chip->oob_poi; 1407 unsigned int max_bitflips = 0; 1408 1409 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1410 int stat; 1411 1412 chip->ecc.hwctl(mtd, NAND_ECC_READ); 1413 chip->read_buf(mtd, p, eccsize); 1414 1415 if (chip->ecc.prepad) { 1416 chip->read_buf(mtd, oob, chip->ecc.prepad); 1417 oob += chip->ecc.prepad; 1418 } 1419 1420 chip->ecc.hwctl(mtd, NAND_ECC_READSYN); 1421 chip->read_buf(mtd, oob, eccbytes); 1422 stat = chip->ecc.correct(mtd, p, oob, NULL); 1423 1424 if (stat < 0) { 1425 mtd->ecc_stats.failed++; 1426 } else { 1427 mtd->ecc_stats.corrected += stat; 1428 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1429 } 1430 1431 oob += eccbytes; 1432 1433 if (chip->ecc.postpad) { 1434 chip->read_buf(mtd, oob, chip->ecc.postpad); 1435 oob += chip->ecc.postpad; 1436 } 1437 } 1438 1439 /* Calculate remaining oob bytes */ 1440 i = mtd->oobsize - (oob - chip->oob_poi); 1441 if (i) 1442 chip->read_buf(mtd, oob, i); 1443 1444 return max_bitflips; 1445} 1446 1447/** 1448 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 1449 * @chip: nand chip structure 1450 * @oob: oob destination address 1451 * @ops: oob ops structure 1452 * @len: size of oob to transfer 1453 */ 1454static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 1455 struct mtd_oob_ops *ops, size_t len) 1456{ 1457 switch (ops->mode) { 1458 1459 case MTD_OPS_PLACE_OOB: 1460 case MTD_OPS_RAW: 1461 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 1462 return oob + len; 1463 1464 case MTD_OPS_AUTO_OOB: { 1465 struct nand_oobfree *free = chip->ecc.layout->oobfree; 1466 uint32_t boffs = 0, roffs = ops->ooboffs; 1467 size_t bytes = 0; 1468 1469 for (; free->length && len; free++, len -= bytes) { 1470 /* Read request not from offset 0? */ 1471 if (unlikely(roffs)) { 1472 if (roffs >= free->length) { 1473 roffs -= free->length; 1474 continue; 1475 } 1476 boffs = free->offset + roffs; 1477 bytes = min_t(size_t, len, 1478 (free->length - roffs)); 1479 roffs = 0; 1480 } else { 1481 bytes = min_t(size_t, len, free->length); 1482 boffs = free->offset; 1483 } 1484 memcpy(oob, chip->oob_poi + boffs, bytes); 1485 oob += bytes; 1486 } 1487 return oob; 1488 } 1489 default: 1490 BUG(); 1491 } 1492 return NULL; 1493} 1494 1495/** 1496 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 1497 * @mtd: MTD device structure 1498 * @retry_mode: the retry mode to use 1499 * 1500 * Some vendors supply a special command to shift the Vt threshold, to be used 1501 * when there are too many bitflips in a page (i.e., ECC error). After setting 1502 * a new threshold, the host should retry reading the page. 1503 */ 1504static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) 1505{ 1506 struct nand_chip *chip = mtd->priv; 1507 1508 pr_debug("setting READ RETRY mode %d\n", retry_mode); 1509 1510 if (retry_mode >= chip->read_retries) 1511 return -EINVAL; 1512 1513 if (!chip->setup_read_retry) 1514 return -EOPNOTSUPP; 1515 1516 return chip->setup_read_retry(mtd, retry_mode); 1517} 1518 1519/** 1520 * nand_do_read_ops - [INTERN] Read data with ECC 1521 * @mtd: MTD device structure 1522 * @from: offset to read from 1523 * @ops: oob ops structure 1524 * 1525 * Internal function. Called with chip held. 1526 */ 1527static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 1528 struct mtd_oob_ops *ops) 1529{ 1530 int chipnr, page, realpage, col, bytes, aligned, oob_required; 1531 struct nand_chip *chip = mtd->priv; 1532 int ret = 0; 1533 uint32_t readlen = ops->len; 1534 uint32_t oobreadlen = ops->ooblen; 1535 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? 1536 mtd->oobavail : mtd->oobsize; 1537 1538 uint8_t *bufpoi, *oob, *buf; 1539 int use_bufpoi; 1540 unsigned int max_bitflips = 0; 1541 int retry_mode = 0; 1542 bool ecc_fail = false; 1543 1544 chipnr = (int)(from >> chip->chip_shift); 1545 chip->select_chip(mtd, chipnr); 1546 1547 realpage = (int)(from >> chip->page_shift); 1548 page = realpage & chip->pagemask; 1549 1550 col = (int)(from & (mtd->writesize - 1)); 1551 1552 buf = ops->datbuf; 1553 oob = ops->oobbuf; 1554 oob_required = oob ? 1 : 0; 1555 1556 while (1) { 1557 unsigned int ecc_failures = mtd->ecc_stats.failed; 1558 1559 bytes = min(mtd->writesize - col, readlen); 1560 aligned = (bytes == mtd->writesize); 1561 1562 if (!aligned) 1563 use_bufpoi = 1; 1564 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 1565 use_bufpoi = !virt_addr_valid(buf); 1566 else 1567 use_bufpoi = 0; 1568 1569 /* Is the current page in the buffer? */ 1570 if (realpage != chip->pagebuf || oob) { 1571 bufpoi = use_bufpoi ? chip->buffers->databuf : buf; 1572 1573 if (use_bufpoi && aligned) 1574 pr_debug("%s: using read bounce buffer for buf@%p\n", 1575 __func__, buf); 1576 1577read_retry: 1578 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 1579 1580 /* 1581 * Now read the page into the buffer. Absent an error, 1582 * the read methods return max bitflips per ecc step. 1583 */ 1584 if (unlikely(ops->mode == MTD_OPS_RAW)) 1585 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, 1586 oob_required, 1587 page); 1588 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 1589 !oob) 1590 ret = chip->ecc.read_subpage(mtd, chip, 1591 col, bytes, bufpoi, 1592 page); 1593 else 1594 ret = chip->ecc.read_page(mtd, chip, bufpoi, 1595 oob_required, page); 1596 if (ret < 0) { 1597 if (use_bufpoi) 1598 /* Invalidate page cache */ 1599 chip->pagebuf = -1; 1600 break; 1601 } 1602 1603 max_bitflips = max_t(unsigned int, max_bitflips, ret); 1604 1605 /* Transfer not aligned data */ 1606 if (use_bufpoi) { 1607 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 1608 !(mtd->ecc_stats.failed - ecc_failures) && 1609 (ops->mode != MTD_OPS_RAW)) { 1610 chip->pagebuf = realpage; 1611 chip->pagebuf_bitflips = ret; 1612 } else { 1613 /* Invalidate page cache */ 1614 chip->pagebuf = -1; 1615 } 1616 memcpy(buf, chip->buffers->databuf + col, bytes); 1617 } 1618 1619 if (unlikely(oob)) { 1620 int toread = min(oobreadlen, max_oobsize); 1621 1622 if (toread) { 1623 oob = nand_transfer_oob(chip, 1624 oob, ops, toread); 1625 oobreadlen -= toread; 1626 } 1627 } 1628 1629 if (chip->options & NAND_NEED_READRDY) { 1630 /* Apply delay or wait for ready/busy pin */ 1631 if (!chip->dev_ready) 1632 udelay(chip->chip_delay); 1633 else 1634 nand_wait_ready(mtd); 1635 } 1636 1637 if (mtd->ecc_stats.failed - ecc_failures) { 1638 if (retry_mode + 1 < chip->read_retries) { 1639 retry_mode++; 1640 ret = nand_setup_read_retry(mtd, 1641 retry_mode); 1642 if (ret < 0) 1643 break; 1644 1645 /* Reset failures; retry */ 1646 mtd->ecc_stats.failed = ecc_failures; 1647 goto read_retry; 1648 } else { 1649 /* No more retry modes; real failure */ 1650 ecc_fail = true; 1651 } 1652 } 1653 1654 buf += bytes; 1655 } else { 1656 memcpy(buf, chip->buffers->databuf + col, bytes); 1657 buf += bytes; 1658 max_bitflips = max_t(unsigned int, max_bitflips, 1659 chip->pagebuf_bitflips); 1660 } 1661 1662 readlen -= bytes; 1663 1664 /* Reset to retry mode 0 */ 1665 if (retry_mode) { 1666 ret = nand_setup_read_retry(mtd, 0); 1667 if (ret < 0) 1668 break; 1669 retry_mode = 0; 1670 } 1671 1672 if (!readlen) 1673 break; 1674 1675 /* For subsequent reads align to page boundary */ 1676 col = 0; 1677 /* Increment page address */ 1678 realpage++; 1679 1680 page = realpage & chip->pagemask; 1681 /* Check, if we cross a chip boundary */ 1682 if (!page) { 1683 chipnr++; 1684 chip->select_chip(mtd, -1); 1685 chip->select_chip(mtd, chipnr); 1686 } 1687 } 1688 chip->select_chip(mtd, -1); 1689 1690 ops->retlen = ops->len - (size_t) readlen; 1691 if (oob) 1692 ops->oobretlen = ops->ooblen - oobreadlen; 1693 1694 if (ret < 0) 1695 return ret; 1696 1697 if (ecc_fail) 1698 return -EBADMSG; 1699 1700 return max_bitflips; 1701} 1702 1703/** 1704 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc 1705 * @mtd: MTD device structure 1706 * @from: offset to read from 1707 * @len: number of bytes to read 1708 * @retlen: pointer to variable to store the number of read bytes 1709 * @buf: the databuffer to put data 1710 * 1711 * Get hold of the chip and call nand_do_read. 1712 */ 1713static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, 1714 size_t *retlen, uint8_t *buf) 1715{ 1716 struct mtd_oob_ops ops; 1717 int ret; 1718 1719 nand_get_device(mtd, FL_READING); 1720 ops.len = len; 1721 ops.datbuf = buf; 1722 ops.oobbuf = NULL; 1723 ops.mode = MTD_OPS_PLACE_OOB; 1724 ret = nand_do_read_ops(mtd, from, &ops); 1725 *retlen = ops.retlen; 1726 nand_release_device(mtd); 1727 return ret; 1728} 1729 1730/** 1731 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 1732 * @mtd: mtd info structure 1733 * @chip: nand chip info structure 1734 * @page: page number to read 1735 */ 1736static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1737 int page) 1738{ 1739 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 1740 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1741 return 0; 1742} 1743 1744/** 1745 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 1746 * with syndromes 1747 * @mtd: mtd info structure 1748 * @chip: nand chip info structure 1749 * @page: page number to read 1750 */ 1751static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 1752 int page) 1753{ 1754 uint8_t *buf = chip->oob_poi; 1755 int length = mtd->oobsize; 1756 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1757 int eccsize = chip->ecc.size; 1758 uint8_t *bufpoi = buf; 1759 int i, toread, sndrnd = 0, pos; 1760 1761 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); 1762 for (i = 0; i < chip->ecc.steps; i++) { 1763 if (sndrnd) { 1764 pos = eccsize + i * (eccsize + chunk); 1765 if (mtd->writesize > 512) 1766 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); 1767 else 1768 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); 1769 } else 1770 sndrnd = 1; 1771 toread = min_t(int, length, chunk); 1772 chip->read_buf(mtd, bufpoi, toread); 1773 bufpoi += toread; 1774 length -= toread; 1775 } 1776 if (length > 0) 1777 chip->read_buf(mtd, bufpoi, length); 1778 1779 return 0; 1780} 1781 1782/** 1783 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 1784 * @mtd: mtd info structure 1785 * @chip: nand chip info structure 1786 * @page: page number to write 1787 */ 1788static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 1789 int page) 1790{ 1791 int status = 0; 1792 const uint8_t *buf = chip->oob_poi; 1793 int length = mtd->oobsize; 1794 1795 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 1796 chip->write_buf(mtd, buf, length); 1797 /* Send command to program the OOB data */ 1798 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1799 1800 status = chip->waitfunc(mtd, chip); 1801 1802 return status & NAND_STATUS_FAIL ? -EIO : 0; 1803} 1804 1805/** 1806 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 1807 * with syndrome - only for large page flash 1808 * @mtd: mtd info structure 1809 * @chip: nand chip info structure 1810 * @page: page number to write 1811 */ 1812static int nand_write_oob_syndrome(struct mtd_info *mtd, 1813 struct nand_chip *chip, int page) 1814{ 1815 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 1816 int eccsize = chip->ecc.size, length = mtd->oobsize; 1817 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; 1818 const uint8_t *bufpoi = chip->oob_poi; 1819 1820 /* 1821 * data-ecc-data-ecc ... ecc-oob 1822 * or 1823 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 1824 */ 1825 if (!chip->ecc.prepad && !chip->ecc.postpad) { 1826 pos = steps * (eccsize + chunk); 1827 steps = 0; 1828 } else 1829 pos = eccsize; 1830 1831 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); 1832 for (i = 0; i < steps; i++) { 1833 if (sndcmd) { 1834 if (mtd->writesize <= 512) { 1835 uint32_t fill = 0xFFFFFFFF; 1836 1837 len = eccsize; 1838 while (len > 0) { 1839 int num = min_t(int, len, 4); 1840 chip->write_buf(mtd, (uint8_t *)&fill, 1841 num); 1842 len -= num; 1843 } 1844 } else { 1845 pos = eccsize + i * (eccsize + chunk); 1846 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); 1847 } 1848 } else 1849 sndcmd = 1; 1850 len = min_t(int, length, chunk); 1851 chip->write_buf(mtd, bufpoi, len); 1852 bufpoi += len; 1853 length -= len; 1854 } 1855 if (length > 0) 1856 chip->write_buf(mtd, bufpoi, length); 1857 1858 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1859 status = chip->waitfunc(mtd, chip); 1860 1861 return status & NAND_STATUS_FAIL ? -EIO : 0; 1862} 1863 1864/** 1865 * nand_do_read_oob - [INTERN] NAND read out-of-band 1866 * @mtd: MTD device structure 1867 * @from: offset to read from 1868 * @ops: oob operations description structure 1869 * 1870 * NAND read out-of-band data from the spare area. 1871 */ 1872static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 1873 struct mtd_oob_ops *ops) 1874{ 1875 int page, realpage, chipnr; 1876 struct nand_chip *chip = mtd->priv; 1877 struct mtd_ecc_stats stats; 1878 int readlen = ops->ooblen; 1879 int len; 1880 uint8_t *buf = ops->oobbuf; 1881 int ret = 0; 1882 1883 pr_debug("%s: from = 0x%08Lx, len = %i\n", 1884 __func__, (unsigned long long)from, readlen); 1885 1886 stats = mtd->ecc_stats; 1887 1888 if (ops->mode == MTD_OPS_AUTO_OOB) 1889 len = chip->ecc.layout->oobavail; 1890 else 1891 len = mtd->oobsize; 1892 1893 if (unlikely(ops->ooboffs >= len)) { 1894 pr_debug("%s: attempt to start read outside oob\n", 1895 __func__); 1896 return -EINVAL; 1897 } 1898 1899 /* Do not allow reads past end of device */ 1900 if (unlikely(from >= mtd->size || 1901 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - 1902 (from >> chip->page_shift)) * len)) { 1903 pr_debug("%s: attempt to read beyond end of device\n", 1904 __func__); 1905 return -EINVAL; 1906 } 1907 1908 chipnr = (int)(from >> chip->chip_shift); 1909 chip->select_chip(mtd, chipnr); 1910 1911 /* Shift to get page */ 1912 realpage = (int)(from >> chip->page_shift); 1913 page = realpage & chip->pagemask; 1914 1915 while (1) { 1916 if (ops->mode == MTD_OPS_RAW) 1917 ret = chip->ecc.read_oob_raw(mtd, chip, page); 1918 else 1919 ret = chip->ecc.read_oob(mtd, chip, page); 1920 1921 if (ret < 0) 1922 break; 1923 1924 len = min(len, readlen); 1925 buf = nand_transfer_oob(chip, buf, ops, len); 1926 1927 if (chip->options & NAND_NEED_READRDY) { 1928 /* Apply delay or wait for ready/busy pin */ 1929 if (!chip->dev_ready) 1930 udelay(chip->chip_delay); 1931 else 1932 nand_wait_ready(mtd); 1933 } 1934 1935 readlen -= len; 1936 if (!readlen) 1937 break; 1938 1939 /* Increment page address */ 1940 realpage++; 1941 1942 page = realpage & chip->pagemask; 1943 /* Check, if we cross a chip boundary */ 1944 if (!page) { 1945 chipnr++; 1946 chip->select_chip(mtd, -1); 1947 chip->select_chip(mtd, chipnr); 1948 } 1949 } 1950 chip->select_chip(mtd, -1); 1951 1952 ops->oobretlen = ops->ooblen - readlen; 1953 1954 if (ret < 0) 1955 return ret; 1956 1957 if (mtd->ecc_stats.failed - stats.failed) 1958 return -EBADMSG; 1959 1960 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; 1961} 1962 1963/** 1964 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 1965 * @mtd: MTD device structure 1966 * @from: offset to read from 1967 * @ops: oob operation description structure 1968 * 1969 * NAND read data and/or out-of-band data. 1970 */ 1971static int nand_read_oob(struct mtd_info *mtd, loff_t from, 1972 struct mtd_oob_ops *ops) 1973{ 1974 int ret = -ENOTSUPP; 1975 1976 ops->retlen = 0; 1977 1978 /* Do not allow reads past end of device */ 1979 if (ops->datbuf && (from + ops->len) > mtd->size) { 1980 pr_debug("%s: attempt to read beyond end of device\n", 1981 __func__); 1982 return -EINVAL; 1983 } 1984 1985 nand_get_device(mtd, FL_READING); 1986 1987 switch (ops->mode) { 1988 case MTD_OPS_PLACE_OOB: 1989 case MTD_OPS_AUTO_OOB: 1990 case MTD_OPS_RAW: 1991 break; 1992 1993 default: 1994 goto out; 1995 } 1996 1997 if (!ops->datbuf) 1998 ret = nand_do_read_oob(mtd, from, ops); 1999 else 2000 ret = nand_do_read_ops(mtd, from, ops); 2001 2002out: 2003 nand_release_device(mtd); 2004 return ret; 2005} 2006 2007 2008/** 2009 * nand_write_page_raw - [INTERN] raw page write function 2010 * @mtd: mtd info structure 2011 * @chip: nand chip info structure 2012 * @buf: data buffer 2013 * @oob_required: must write chip->oob_poi to OOB 2014 * 2015 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2016 */ 2017static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 2018 const uint8_t *buf, int oob_required) 2019{ 2020 chip->write_buf(mtd, buf, mtd->writesize); 2021 if (oob_required) 2022 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2023 2024 return 0; 2025} 2026 2027/** 2028 * nand_write_page_raw_syndrome - [INTERN] raw page write function 2029 * @mtd: mtd info structure 2030 * @chip: nand chip info structure 2031 * @buf: data buffer 2032 * @oob_required: must write chip->oob_poi to OOB 2033 * 2034 * We need a special oob layout and handling even when ECC isn't checked. 2035 */ 2036static int nand_write_page_raw_syndrome(struct mtd_info *mtd, 2037 struct nand_chip *chip, 2038 const uint8_t *buf, int oob_required) 2039{ 2040 int eccsize = chip->ecc.size; 2041 int eccbytes = chip->ecc.bytes; 2042 uint8_t *oob = chip->oob_poi; 2043 int steps, size; 2044 2045 for (steps = chip->ecc.steps; steps > 0; steps--) { 2046 chip->write_buf(mtd, buf, eccsize); 2047 buf += eccsize; 2048 2049 if (chip->ecc.prepad) { 2050 chip->write_buf(mtd, oob, chip->ecc.prepad); 2051 oob += chip->ecc.prepad; 2052 } 2053 2054 chip->write_buf(mtd, oob, eccbytes); 2055 oob += eccbytes; 2056 2057 if (chip->ecc.postpad) { 2058 chip->write_buf(mtd, oob, chip->ecc.postpad); 2059 oob += chip->ecc.postpad; 2060 } 2061 } 2062 2063 size = mtd->oobsize - (oob - chip->oob_poi); 2064 if (size) 2065 chip->write_buf(mtd, oob, size); 2066 2067 return 0; 2068} 2069/** 2070 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 2071 * @mtd: mtd info structure 2072 * @chip: nand chip info structure 2073 * @buf: data buffer 2074 * @oob_required: must write chip->oob_poi to OOB 2075 */ 2076static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 2077 const uint8_t *buf, int oob_required) 2078{ 2079 int i, eccsize = chip->ecc.size; 2080 int eccbytes = chip->ecc.bytes; 2081 int eccsteps = chip->ecc.steps; 2082 uint8_t *ecc_calc = chip->buffers->ecccalc; 2083 const uint8_t *p = buf; 2084 uint32_t *eccpos = chip->ecc.layout->eccpos; 2085 2086 /* Software ECC calculation */ 2087 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 2088 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2089 2090 for (i = 0; i < chip->ecc.total; i++) 2091 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2092 2093 return chip->ecc.write_page_raw(mtd, chip, buf, 1); 2094} 2095 2096/** 2097 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 2098 * @mtd: mtd info structure 2099 * @chip: nand chip info structure 2100 * @buf: data buffer 2101 * @oob_required: must write chip->oob_poi to OOB 2102 */ 2103static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 2104 const uint8_t *buf, int oob_required) 2105{ 2106 int i, eccsize = chip->ecc.size; 2107 int eccbytes = chip->ecc.bytes; 2108 int eccsteps = chip->ecc.steps; 2109 uint8_t *ecc_calc = chip->buffers->ecccalc; 2110 const uint8_t *p = buf; 2111 uint32_t *eccpos = chip->ecc.layout->eccpos; 2112 2113 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2114 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2115 chip->write_buf(mtd, p, eccsize); 2116 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2117 } 2118 2119 for (i = 0; i < chip->ecc.total; i++) 2120 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2121 2122 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2123 2124 return 0; 2125} 2126 2127 2128/** 2129 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write 2130 * @mtd: mtd info structure 2131 * @chip: nand chip info structure 2132 * @offset: column address of subpage within the page 2133 * @data_len: data length 2134 * @buf: data buffer 2135 * @oob_required: must write chip->oob_poi to OOB 2136 */ 2137static int nand_write_subpage_hwecc(struct mtd_info *mtd, 2138 struct nand_chip *chip, uint32_t offset, 2139 uint32_t data_len, const uint8_t *buf, 2140 int oob_required) 2141{ 2142 uint8_t *oob_buf = chip->oob_poi; 2143 uint8_t *ecc_calc = chip->buffers->ecccalc; 2144 int ecc_size = chip->ecc.size; 2145 int ecc_bytes = chip->ecc.bytes; 2146 int ecc_steps = chip->ecc.steps; 2147 uint32_t *eccpos = chip->ecc.layout->eccpos; 2148 uint32_t start_step = offset / ecc_size; 2149 uint32_t end_step = (offset + data_len - 1) / ecc_size; 2150 int oob_bytes = mtd->oobsize / ecc_steps; 2151 int step, i; 2152 2153 for (step = 0; step < ecc_steps; step++) { 2154 /* configure controller for WRITE access */ 2155 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2156 2157 /* write data (untouched subpages already masked by 0xFF) */ 2158 chip->write_buf(mtd, buf, ecc_size); 2159 2160 /* mask ECC of un-touched subpages by padding 0xFF */ 2161 if ((step < start_step) || (step > end_step)) 2162 memset(ecc_calc, 0xff, ecc_bytes); 2163 else 2164 chip->ecc.calculate(mtd, buf, ecc_calc); 2165 2166 /* mask OOB of un-touched subpages by padding 0xFF */ 2167 /* if oob_required, preserve OOB metadata of written subpage */ 2168 if (!oob_required || (step < start_step) || (step > end_step)) 2169 memset(oob_buf, 0xff, oob_bytes); 2170 2171 buf += ecc_size; 2172 ecc_calc += ecc_bytes; 2173 oob_buf += oob_bytes; 2174 } 2175 2176 /* copy calculated ECC for whole page to chip->buffer->oob */ 2177 /* this include masked-value(0xFF) for unwritten subpages */ 2178 ecc_calc = chip->buffers->ecccalc; 2179 for (i = 0; i < chip->ecc.total; i++) 2180 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2181 2182 /* write OOB buffer to NAND device */ 2183 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 2184 2185 return 0; 2186} 2187 2188 2189/** 2190 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 2191 * @mtd: mtd info structure 2192 * @chip: nand chip info structure 2193 * @buf: data buffer 2194 * @oob_required: must write chip->oob_poi to OOB 2195 * 2196 * The hw generator calculates the error syndrome automatically. Therefore we 2197 * need a special oob layout and handling. 2198 */ 2199static int nand_write_page_syndrome(struct mtd_info *mtd, 2200 struct nand_chip *chip, 2201 const uint8_t *buf, int oob_required) 2202{ 2203 int i, eccsize = chip->ecc.size; 2204 int eccbytes = chip->ecc.bytes; 2205 int eccsteps = chip->ecc.steps; 2206 const uint8_t *p = buf; 2207 uint8_t *oob = chip->oob_poi; 2208 2209 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2210 2211 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2212 chip->write_buf(mtd, p, eccsize); 2213 2214 if (chip->ecc.prepad) { 2215 chip->write_buf(mtd, oob, chip->ecc.prepad); 2216 oob += chip->ecc.prepad; 2217 } 2218 2219 chip->ecc.calculate(mtd, p, oob); 2220 chip->write_buf(mtd, oob, eccbytes); 2221 oob += eccbytes; 2222 2223 if (chip->ecc.postpad) { 2224 chip->write_buf(mtd, oob, chip->ecc.postpad); 2225 oob += chip->ecc.postpad; 2226 } 2227 } 2228 2229 /* Calculate remaining oob bytes */ 2230 i = mtd->oobsize - (oob - chip->oob_poi); 2231 if (i) 2232 chip->write_buf(mtd, oob, i); 2233 2234 return 0; 2235} 2236 2237/** 2238 * nand_write_page - [REPLACEABLE] write one page 2239 * @mtd: MTD device structure 2240 * @chip: NAND chip descriptor 2241 * @offset: address offset within the page 2242 * @data_len: length of actual data to be written 2243 * @buf: the data to write 2244 * @oob_required: must write chip->oob_poi to OOB 2245 * @page: page number to write 2246 * @cached: cached programming 2247 * @raw: use _raw version of write_page 2248 */ 2249static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 2250 uint32_t offset, int data_len, const uint8_t *buf, 2251 int oob_required, int page, int cached, int raw) 2252{ 2253 int status, subpage; 2254 2255 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 2256 chip->ecc.write_subpage) 2257 subpage = offset || (data_len < mtd->writesize); 2258 else 2259 subpage = 0; 2260 2261 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); 2262 2263 if (unlikely(raw)) 2264 status = chip->ecc.write_page_raw(mtd, chip, buf, 2265 oob_required); 2266 else if (subpage) 2267 status = chip->ecc.write_subpage(mtd, chip, offset, data_len, 2268 buf, oob_required); 2269 else 2270 status = chip->ecc.write_page(mtd, chip, buf, oob_required); 2271 2272 if (status < 0) 2273 return status; 2274 2275 /* 2276 * Cached progamming disabled for now. Not sure if it's worth the 2277 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). 2278 */ 2279 cached = 0; 2280 2281 if (!cached || !NAND_HAS_CACHEPROG(chip)) { 2282 2283 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 2284 status = chip->waitfunc(mtd, chip); 2285 /* 2286 * See if operation failed and additional status checks are 2287 * available. 2288 */ 2289 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 2290 status = chip->errstat(mtd, chip, FL_WRITING, status, 2291 page); 2292 2293 if (status & NAND_STATUS_FAIL) 2294 return -EIO; 2295 } else { 2296 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); 2297 status = chip->waitfunc(mtd, chip); 2298 } 2299 2300 return 0; 2301} 2302 2303/** 2304 * nand_fill_oob - [INTERN] Transfer client buffer to oob 2305 * @mtd: MTD device structure 2306 * @oob: oob data buffer 2307 * @len: oob data write length 2308 * @ops: oob ops structure 2309 */ 2310static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, 2311 struct mtd_oob_ops *ops) 2312{ 2313 struct nand_chip *chip = mtd->priv; 2314 2315 /* 2316 * Initialise to all 0xFF, to avoid the possibility of left over OOB 2317 * data from a previous OOB read. 2318 */ 2319 memset(chip->oob_poi, 0xff, mtd->oobsize); 2320 2321 switch (ops->mode) { 2322 2323 case MTD_OPS_PLACE_OOB: 2324 case MTD_OPS_RAW: 2325 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 2326 return oob + len; 2327 2328 case MTD_OPS_AUTO_OOB: { 2329 struct nand_oobfree *free = chip->ecc.layout->oobfree; 2330 uint32_t boffs = 0, woffs = ops->ooboffs; 2331 size_t bytes = 0; 2332 2333 for (; free->length && len; free++, len -= bytes) { 2334 /* Write request not from offset 0? */ 2335 if (unlikely(woffs)) { 2336 if (woffs >= free->length) { 2337 woffs -= free->length; 2338 continue; 2339 } 2340 boffs = free->offset + woffs; 2341 bytes = min_t(size_t, len, 2342 (free->length - woffs)); 2343 woffs = 0; 2344 } else { 2345 bytes = min_t(size_t, len, free->length); 2346 boffs = free->offset; 2347 } 2348 memcpy(chip->oob_poi + boffs, oob, bytes); 2349 oob += bytes; 2350 } 2351 return oob; 2352 } 2353 default: 2354 BUG(); 2355 } 2356 return NULL; 2357} 2358 2359#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 2360 2361/** 2362 * nand_do_write_ops - [INTERN] NAND write with ECC 2363 * @mtd: MTD device structure 2364 * @to: offset to write to 2365 * @ops: oob operations description structure 2366 * 2367 * NAND write with ECC. 2368 */ 2369static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, 2370 struct mtd_oob_ops *ops) 2371{ 2372 int chipnr, realpage, page, blockmask, column; 2373 struct nand_chip *chip = mtd->priv; 2374 uint32_t writelen = ops->len; 2375 2376 uint32_t oobwritelen = ops->ooblen; 2377 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? 2378 mtd->oobavail : mtd->oobsize; 2379 2380 uint8_t *oob = ops->oobbuf; 2381 uint8_t *buf = ops->datbuf; 2382 int ret; 2383 int oob_required = oob ? 1 : 0; 2384 2385 ops->retlen = 0; 2386 if (!writelen) 2387 return 0; 2388 2389 /* Reject writes, which are not page aligned */ 2390 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 2391 pr_notice("%s: attempt to write non page aligned data\n", 2392 __func__); 2393 return -EINVAL; 2394 } 2395 2396 column = to & (mtd->writesize - 1); 2397 2398 chipnr = (int)(to >> chip->chip_shift); 2399 chip->select_chip(mtd, chipnr); 2400 2401 /* Check, if it is write protected */ 2402 if (nand_check_wp(mtd)) { 2403 ret = -EIO; 2404 goto err_out; 2405 } 2406 2407 realpage = (int)(to >> chip->page_shift); 2408 page = realpage & chip->pagemask; 2409 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; 2410 2411 /* Invalidate the page cache, when we write to the cached page */ 2412 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && 2413 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) 2414 chip->pagebuf = -1; 2415 2416 /* Don't allow multipage oob writes with offset */ 2417 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 2418 ret = -EINVAL; 2419 goto err_out; 2420 } 2421 2422 while (1) { 2423 int bytes = mtd->writesize; 2424 int cached = writelen > bytes && page != blockmask; 2425 uint8_t *wbuf = buf; 2426 int use_bufpoi; 2427 int part_pagewr = (column || writelen < (mtd->writesize - 1)); 2428 2429 if (part_pagewr) 2430 use_bufpoi = 1; 2431 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 2432 use_bufpoi = !virt_addr_valid(buf); 2433 else 2434 use_bufpoi = 0; 2435 2436 /* Partial page write?, or need to use bounce buffer */ 2437 if (use_bufpoi) { 2438 pr_debug("%s: using write bounce buffer for buf@%p\n", 2439 __func__, buf); 2440 cached = 0; 2441 if (part_pagewr) 2442 bytes = min_t(int, bytes - column, writelen); 2443 chip->pagebuf = -1; 2444 memset(chip->buffers->databuf, 0xff, mtd->writesize); 2445 memcpy(&chip->buffers->databuf[column], buf, bytes); 2446 wbuf = chip->buffers->databuf; 2447 } 2448 2449 if (unlikely(oob)) { 2450 size_t len = min(oobwritelen, oobmaxlen); 2451 oob = nand_fill_oob(mtd, oob, len, ops); 2452 oobwritelen -= len; 2453 } else { 2454 /* We still need to erase leftover OOB data */ 2455 memset(chip->oob_poi, 0xff, mtd->oobsize); 2456 } 2457 ret = chip->write_page(mtd, chip, column, bytes, wbuf, 2458 oob_required, page, cached, 2459 (ops->mode == MTD_OPS_RAW)); 2460 if (ret) 2461 break; 2462 2463 writelen -= bytes; 2464 if (!writelen) 2465 break; 2466 2467 column = 0; 2468 buf += bytes; 2469 realpage++; 2470 2471 page = realpage & chip->pagemask; 2472 /* Check, if we cross a chip boundary */ 2473 if (!page) { 2474 chipnr++; 2475 chip->select_chip(mtd, -1); 2476 chip->select_chip(mtd, chipnr); 2477 } 2478 } 2479 2480 ops->retlen = ops->len - writelen; 2481 if (unlikely(oob)) 2482 ops->oobretlen = ops->ooblen; 2483 2484err_out: 2485 chip->select_chip(mtd, -1); 2486 return ret; 2487} 2488 2489/** 2490 * panic_nand_write - [MTD Interface] NAND write with ECC 2491 * @mtd: MTD device structure 2492 * @to: offset to write to 2493 * @len: number of bytes to write 2494 * @retlen: pointer to variable to store the number of written bytes 2495 * @buf: the data to write 2496 * 2497 * NAND write with ECC. Used when performing writes in interrupt context, this 2498 * may for example be called by mtdoops when writing an oops while in panic. 2499 */ 2500static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 2501 size_t *retlen, const uint8_t *buf) 2502{ 2503 struct nand_chip *chip = mtd->priv; 2504 struct mtd_oob_ops ops; 2505 int ret; 2506 2507 /* Wait for the device to get ready */ 2508 panic_nand_wait(mtd, chip, 400); 2509 2510 /* Grab the device */ 2511 panic_nand_get_device(chip, mtd, FL_WRITING); 2512 2513 ops.len = len; 2514 ops.datbuf = (uint8_t *)buf; 2515 ops.oobbuf = NULL; 2516 ops.mode = MTD_OPS_PLACE_OOB; 2517 2518 ret = nand_do_write_ops(mtd, to, &ops); 2519 2520 *retlen = ops.retlen; 2521 return ret; 2522} 2523 2524/** 2525 * nand_write - [MTD Interface] NAND write with ECC 2526 * @mtd: MTD device structure 2527 * @to: offset to write to 2528 * @len: number of bytes to write 2529 * @retlen: pointer to variable to store the number of written bytes 2530 * @buf: the data to write 2531 * 2532 * NAND write with ECC. 2533 */ 2534static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, 2535 size_t *retlen, const uint8_t *buf) 2536{ 2537 struct mtd_oob_ops ops; 2538 int ret; 2539 2540 nand_get_device(mtd, FL_WRITING); 2541 ops.len = len; 2542 ops.datbuf = (uint8_t *)buf; 2543 ops.oobbuf = NULL; 2544 ops.mode = MTD_OPS_PLACE_OOB; 2545 ret = nand_do_write_ops(mtd, to, &ops); 2546 *retlen = ops.retlen; 2547 nand_release_device(mtd); 2548 return ret; 2549} 2550 2551/** 2552 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 2553 * @mtd: MTD device structure 2554 * @to: offset to write to 2555 * @ops: oob operation description structure 2556 * 2557 * NAND write out-of-band. 2558 */ 2559static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 2560 struct mtd_oob_ops *ops) 2561{ 2562 int chipnr, page, status, len; 2563 struct nand_chip *chip = mtd->priv; 2564 2565 pr_debug("%s: to = 0x%08x, len = %i\n", 2566 __func__, (unsigned int)to, (int)ops->ooblen); 2567 2568 if (ops->mode == MTD_OPS_AUTO_OOB) 2569 len = chip->ecc.layout->oobavail; 2570 else 2571 len = mtd->oobsize; 2572 2573 /* Do not allow write past end of page */ 2574 if ((ops->ooboffs + ops->ooblen) > len) { 2575 pr_debug("%s: attempt to write past end of page\n", 2576 __func__); 2577 return -EINVAL; 2578 } 2579 2580 if (unlikely(ops->ooboffs >= len)) { 2581 pr_debug("%s: attempt to start write outside oob\n", 2582 __func__); 2583 return -EINVAL; 2584 } 2585 2586 /* Do not allow write past end of device */ 2587 if (unlikely(to >= mtd->size || 2588 ops->ooboffs + ops->ooblen > 2589 ((mtd->size >> chip->page_shift) - 2590 (to >> chip->page_shift)) * len)) { 2591 pr_debug("%s: attempt to write beyond end of device\n", 2592 __func__); 2593 return -EINVAL; 2594 } 2595 2596 chipnr = (int)(to >> chip->chip_shift); 2597 chip->select_chip(mtd, chipnr); 2598 2599 /* Shift to get page */ 2600 page = (int)(to >> chip->page_shift); 2601 2602 /* 2603 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 2604 * of my DiskOnChip 2000 test units) will clear the whole data page too 2605 * if we don't do this. I have no clue why, but I seem to have 'fixed' 2606 * it in the doc2000 driver in August 1999. dwmw2. 2607 */ 2608 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 2609 2610 /* Check, if it is write protected */ 2611 if (nand_check_wp(mtd)) { 2612 chip->select_chip(mtd, -1); 2613 return -EROFS; 2614 } 2615 2616 /* Invalidate the page cache, if we write to the cached page */ 2617 if (page == chip->pagebuf) 2618 chip->pagebuf = -1; 2619 2620 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); 2621 2622 if (ops->mode == MTD_OPS_RAW) 2623 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); 2624 else 2625 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); 2626 2627 chip->select_chip(mtd, -1); 2628 2629 if (status) 2630 return status; 2631 2632 ops->oobretlen = ops->ooblen; 2633 2634 return 0; 2635} 2636 2637/** 2638 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 2639 * @mtd: MTD device structure 2640 * @to: offset to write to 2641 * @ops: oob operation description structure 2642 */ 2643static int nand_write_oob(struct mtd_info *mtd, loff_t to, 2644 struct mtd_oob_ops *ops) 2645{ 2646 int ret = -ENOTSUPP; 2647 2648 ops->retlen = 0; 2649 2650 /* Do not allow writes past end of device */ 2651 if (ops->datbuf && (to + ops->len) > mtd->size) { 2652 pr_debug("%s: attempt to write beyond end of device\n", 2653 __func__); 2654 return -EINVAL; 2655 } 2656 2657 nand_get_device(mtd, FL_WRITING); 2658 2659 switch (ops->mode) { 2660 case MTD_OPS_PLACE_OOB: 2661 case MTD_OPS_AUTO_OOB: 2662 case MTD_OPS_RAW: 2663 break; 2664 2665 default: 2666 goto out; 2667 } 2668 2669 if (!ops->datbuf) 2670 ret = nand_do_write_oob(mtd, to, ops); 2671 else 2672 ret = nand_do_write_ops(mtd, to, ops); 2673 2674out: 2675 nand_release_device(mtd); 2676 return ret; 2677} 2678 2679/** 2680 * single_erase - [GENERIC] NAND standard block erase command function 2681 * @mtd: MTD device structure 2682 * @page: the page address of the block which will be erased 2683 * 2684 * Standard erase command for NAND chips. Returns NAND status. 2685 */ 2686static int single_erase(struct mtd_info *mtd, int page) 2687{ 2688 struct nand_chip *chip = mtd->priv; 2689 /* Send commands to erase a block */ 2690 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 2691 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 2692 2693 return chip->waitfunc(mtd, chip); 2694} 2695 2696/** 2697 * nand_erase - [MTD Interface] erase block(s) 2698 * @mtd: MTD device structure 2699 * @instr: erase instruction 2700 * 2701 * Erase one ore more blocks. 2702 */ 2703static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 2704{ 2705 return nand_erase_nand(mtd, instr, 0); 2706} 2707 2708/** 2709 * nand_erase_nand - [INTERN] erase block(s) 2710 * @mtd: MTD device structure 2711 * @instr: erase instruction 2712 * @allowbbt: allow erasing the bbt area 2713 * 2714 * Erase one ore more blocks. 2715 */ 2716int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 2717 int allowbbt) 2718{ 2719 int page, status, pages_per_block, ret, chipnr; 2720 struct nand_chip *chip = mtd->priv; 2721 loff_t len; 2722 2723 pr_debug("%s: start = 0x%012llx, len = %llu\n", 2724 __func__, (unsigned long long)instr->addr, 2725 (unsigned long long)instr->len); 2726 2727 if (check_offs_len(mtd, instr->addr, instr->len)) 2728 return -EINVAL; 2729 2730 /* Grab the lock and see if the device is available */ 2731 nand_get_device(mtd, FL_ERASING); 2732 2733 /* Shift to get first page */ 2734 page = (int)(instr->addr >> chip->page_shift); 2735 chipnr = (int)(instr->addr >> chip->chip_shift); 2736 2737 /* Calculate pages in each block */ 2738 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 2739 2740 /* Select the NAND device */ 2741 chip->select_chip(mtd, chipnr); 2742 2743 /* Check, if it is write protected */ 2744 if (nand_check_wp(mtd)) { 2745 pr_debug("%s: device is write protected!\n", 2746 __func__); 2747 instr->state = MTD_ERASE_FAILED; 2748 goto erase_exit; 2749 } 2750 2751 /* Loop through the pages */ 2752 len = instr->len; 2753 2754 instr->state = MTD_ERASING; 2755 2756 while (len) { 2757 /* Check if we have a bad block, we do not erase bad blocks! */ 2758 if (nand_block_checkbad(mtd, ((loff_t) page) << 2759 chip->page_shift, 0, allowbbt)) { 2760 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", 2761 __func__, page); 2762 instr->state = MTD_ERASE_FAILED; 2763 goto erase_exit; 2764 } 2765 2766 /* 2767 * Invalidate the page cache, if we erase the block which 2768 * contains the current cached page. 2769 */ 2770 if (page <= chip->pagebuf && chip->pagebuf < 2771 (page + pages_per_block)) 2772 chip->pagebuf = -1; 2773 2774 status = chip->erase(mtd, page & chip->pagemask); 2775 2776 /* 2777 * See if operation failed and additional status checks are 2778 * available 2779 */ 2780 if ((status & NAND_STATUS_FAIL) && (chip->errstat)) 2781 status = chip->errstat(mtd, chip, FL_ERASING, 2782 status, page); 2783 2784 /* See if block erase succeeded */ 2785 if (status & NAND_STATUS_FAIL) { 2786 pr_debug("%s: failed erase, page 0x%08x\n", 2787 __func__, page); 2788 instr->state = MTD_ERASE_FAILED; 2789 instr->fail_addr = 2790 ((loff_t)page << chip->page_shift); 2791 goto erase_exit; 2792 } 2793 2794 /* Increment page address and decrement length */ 2795 len -= (1ULL << chip->phys_erase_shift); 2796 page += pages_per_block; 2797 2798 /* Check, if we cross a chip boundary */ 2799 if (len && !(page & chip->pagemask)) { 2800 chipnr++; 2801 chip->select_chip(mtd, -1); 2802 chip->select_chip(mtd, chipnr); 2803 } 2804 } 2805 instr->state = MTD_ERASE_DONE; 2806 2807erase_exit: 2808 2809 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; 2810 2811 /* Deselect and wake up anyone waiting on the device */ 2812 chip->select_chip(mtd, -1); 2813 nand_release_device(mtd); 2814 2815 /* Do call back function */ 2816 if (!ret) 2817 mtd_erase_callback(instr); 2818 2819 /* Return more or less happy */ 2820 return ret; 2821} 2822 2823/** 2824 * nand_sync - [MTD Interface] sync 2825 * @mtd: MTD device structure 2826 * 2827 * Sync is actually a wait for chip ready function. 2828 */ 2829static void nand_sync(struct mtd_info *mtd) 2830{ 2831 pr_debug("%s: called\n", __func__); 2832 2833 /* Grab the lock and see if the device is available */ 2834 nand_get_device(mtd, FL_SYNCING); 2835 /* Release it and go back */ 2836 nand_release_device(mtd); 2837} 2838 2839/** 2840 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 2841 * @mtd: MTD device structure 2842 * @offs: offset relative to mtd start 2843 */ 2844static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 2845{ 2846 return nand_block_checkbad(mtd, offs, 1, 0); 2847} 2848 2849/** 2850 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 2851 * @mtd: MTD device structure 2852 * @ofs: offset relative to mtd start 2853 */ 2854static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 2855{ 2856 int ret; 2857 2858 ret = nand_block_isbad(mtd, ofs); 2859 if (ret) { 2860 /* If it was bad already, return success and do nothing */ 2861 if (ret > 0) 2862 return 0; 2863 return ret; 2864 } 2865 2866 return nand_block_markbad_lowlevel(mtd, ofs); 2867} 2868 2869/** 2870 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand 2871 * @mtd: MTD device structure 2872 * @chip: nand chip info structure 2873 * @addr: feature address. 2874 * @subfeature_param: the subfeature parameters, a four bytes array. 2875 */ 2876static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, 2877 int addr, uint8_t *subfeature_param) 2878{ 2879 int status; 2880 int i; 2881 2882 if (!chip->onfi_version || 2883 !(le16_to_cpu(chip->onfi_params.opt_cmd) 2884 & ONFI_OPT_CMD_SET_GET_FEATURES)) 2885 return -EINVAL; 2886 2887 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); 2888 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2889 chip->write_byte(mtd, subfeature_param[i]); 2890 2891 status = chip->waitfunc(mtd, chip); 2892 if (status & NAND_STATUS_FAIL) 2893 return -EIO; 2894 return 0; 2895} 2896 2897/** 2898 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand 2899 * @mtd: MTD device structure 2900 * @chip: nand chip info structure 2901 * @addr: feature address. 2902 * @subfeature_param: the subfeature parameters, a four bytes array. 2903 */ 2904static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, 2905 int addr, uint8_t *subfeature_param) 2906{ 2907 int i; 2908 2909 if (!chip->onfi_version || 2910 !(le16_to_cpu(chip->onfi_params.opt_cmd) 2911 & ONFI_OPT_CMD_SET_GET_FEATURES)) 2912 return -EINVAL; 2913 2914 /* clear the sub feature parameters */ 2915 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); 2916 2917 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); 2918 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2919 *subfeature_param++ = chip->read_byte(mtd); 2920 return 0; 2921} 2922 2923/** 2924 * nand_suspend - [MTD Interface] Suspend the NAND flash 2925 * @mtd: MTD device structure 2926 */ 2927static int nand_suspend(struct mtd_info *mtd) 2928{ 2929 return nand_get_device(mtd, FL_PM_SUSPENDED); 2930} 2931 2932/** 2933 * nand_resume - [MTD Interface] Resume the NAND flash 2934 * @mtd: MTD device structure 2935 */ 2936static void nand_resume(struct mtd_info *mtd) 2937{ 2938 struct nand_chip *chip = mtd->priv; 2939 2940 if (chip->state == FL_PM_SUSPENDED) 2941 nand_release_device(mtd); 2942 else 2943 pr_err("%s called for a chip which is not in suspended state\n", 2944 __func__); 2945} 2946 2947/* Set default functions */ 2948static void nand_set_defaults(struct nand_chip *chip, int busw) 2949{ 2950 /* check for proper chip_delay setup, set 20us if not */ 2951 if (!chip->chip_delay) 2952 chip->chip_delay = 20; 2953 2954 /* check, if a user supplied command function given */ 2955 if (chip->cmdfunc == NULL) 2956 chip->cmdfunc = nand_command; 2957 2958 /* check, if a user supplied wait function given */ 2959 if (chip->waitfunc == NULL) 2960 chip->waitfunc = nand_wait; 2961 2962 if (!chip->select_chip) 2963 chip->select_chip = nand_select_chip; 2964 2965 /* set for ONFI nand */ 2966 if (!chip->onfi_set_features) 2967 chip->onfi_set_features = nand_onfi_set_features; 2968 if (!chip->onfi_get_features) 2969 chip->onfi_get_features = nand_onfi_get_features; 2970 2971 /* If called twice, pointers that depend on busw may need to be reset */ 2972 if (!chip->read_byte || chip->read_byte == nand_read_byte) 2973 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; 2974 if (!chip->read_word) 2975 chip->read_word = nand_read_word; 2976 if (!chip->block_bad) 2977 chip->block_bad = nand_block_bad; 2978 if (!chip->block_markbad) 2979 chip->block_markbad = nand_default_block_markbad; 2980 if (!chip->write_buf || chip->write_buf == nand_write_buf) 2981 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; 2982 if (!chip->write_byte || chip->write_byte == nand_write_byte) 2983 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; 2984 if (!chip->read_buf || chip->read_buf == nand_read_buf) 2985 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; 2986 if (!chip->scan_bbt) 2987 chip->scan_bbt = nand_default_bbt; 2988 2989 if (!chip->controller) { 2990 chip->controller = &chip->hwcontrol; 2991 spin_lock_init(&chip->controller->lock); 2992 init_waitqueue_head(&chip->controller->wq); 2993 } 2994 2995} 2996 2997/* Sanitize ONFI strings so we can safely print them */ 2998static void sanitize_string(uint8_t *s, size_t len) 2999{ 3000 ssize_t i; 3001 3002 /* Null terminate */ 3003 s[len - 1] = 0; 3004 3005 /* Remove non printable chars */ 3006 for (i = 0; i < len - 1; i++) { 3007 if (s[i] < ' ' || s[i] > 127) 3008 s[i] = '?'; 3009 } 3010 3011 /* Remove trailing spaces */ 3012 strim(s); 3013} 3014 3015static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) 3016{ 3017 int i; 3018 while (len--) { 3019 crc ^= *p++ << 8; 3020 for (i = 0; i < 8; i++) 3021 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); 3022 } 3023 3024 return crc; 3025} 3026 3027/* Parse the Extended Parameter Page. */ 3028static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, 3029 struct nand_chip *chip, struct nand_onfi_params *p) 3030{ 3031 struct onfi_ext_param_page *ep; 3032 struct onfi_ext_section *s; 3033 struct onfi_ext_ecc_info *ecc; 3034 uint8_t *cursor; 3035 int ret = -EINVAL; 3036 int len; 3037 int i; 3038 3039 len = le16_to_cpu(p->ext_param_page_length) * 16; 3040 ep = kmalloc(len, GFP_KERNEL); 3041 if (!ep) 3042 return -ENOMEM; 3043 3044 /* Send our own NAND_CMD_PARAM. */ 3045 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); 3046 3047 /* Use the Change Read Column command to skip the ONFI param pages. */ 3048 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 3049 sizeof(*p) * p->num_of_param_pages , -1); 3050 3051 /* Read out the Extended Parameter Page. */ 3052 chip->read_buf(mtd, (uint8_t *)ep, len); 3053 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) 3054 != le16_to_cpu(ep->crc))) { 3055 pr_debug("fail in the CRC.\n"); 3056 goto ext_out; 3057 } 3058 3059 /* 3060 * Check the signature. 3061 * Do not strictly follow the ONFI spec, maybe changed in future. 3062 */ 3063 if (strncmp(ep->sig, "EPPS", 4)) { 3064 pr_debug("The signature is invalid.\n"); 3065 goto ext_out; 3066 } 3067 3068 /* find the ECC section. */ 3069 cursor = (uint8_t *)(ep + 1); 3070 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { 3071 s = ep->sections + i; 3072 if (s->type == ONFI_SECTION_TYPE_2) 3073 break; 3074 cursor += s->length * 16; 3075 } 3076 if (i == ONFI_EXT_SECTION_MAX) { 3077 pr_debug("We can not find the ECC section.\n"); 3078 goto ext_out; 3079 } 3080 3081 /* get the info we want. */ 3082 ecc = (struct onfi_ext_ecc_info *)cursor; 3083 3084 if (!ecc->codeword_size) { 3085 pr_debug("Invalid codeword size\n"); 3086 goto ext_out; 3087 } 3088 3089 chip->ecc_strength_ds = ecc->ecc_bits; 3090 chip->ecc_step_ds = 1 << ecc->codeword_size; 3091 ret = 0; 3092 3093ext_out: 3094 kfree(ep); 3095 return ret; 3096} 3097 3098static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) 3099{ 3100 struct nand_chip *chip = mtd->priv; 3101 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; 3102 3103 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, 3104 feature); 3105} 3106 3107/* 3108 * Configure chip properties from Micron vendor-specific ONFI table 3109 */ 3110static void nand_onfi_detect_micron(struct nand_chip *chip, 3111 struct nand_onfi_params *p) 3112{ 3113 struct nand_onfi_vendor_micron *micron = (void *)p->vendor; 3114 3115 if (le16_to_cpu(p->vendor_revision) < 1) 3116 return; 3117 3118 chip->read_retries = micron->read_retry_options; 3119 chip->setup_read_retry = nand_setup_read_retry_micron; 3120} 3121 3122/* 3123 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. 3124 */ 3125static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, 3126 int *busw) 3127{ 3128 struct nand_onfi_params *p = &chip->onfi_params; 3129 int i, j; 3130 int val; 3131 3132 /* Try ONFI for unknown chip or LP */ 3133 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); 3134 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || 3135 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') 3136 return 0; 3137 3138 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); 3139 for (i = 0; i < 3; i++) { 3140 for (j = 0; j < sizeof(*p); j++) 3141 ((uint8_t *)p)[j] = chip->read_byte(mtd); 3142 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == 3143 le16_to_cpu(p->crc)) { 3144 break; 3145 } 3146 } 3147 3148 if (i == 3) { 3149 pr_err("Could not find valid ONFI parameter page; aborting\n"); 3150 return 0; 3151 } 3152 3153 /* Check version */ 3154 val = le16_to_cpu(p->revision); 3155 if (val & (1 << 5)) 3156 chip->onfi_version = 23; 3157 else if (val & (1 << 4)) 3158 chip->onfi_version = 22; 3159 else if (val & (1 << 3)) 3160 chip->onfi_version = 21; 3161 else if (val & (1 << 2)) 3162 chip->onfi_version = 20; 3163 else if (val & (1 << 1)) 3164 chip->onfi_version = 10; 3165 3166 if (!chip->onfi_version) { 3167 pr_info("unsupported ONFI version: %d\n", val); 3168 return 0; 3169 } 3170 3171 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 3172 sanitize_string(p->model, sizeof(p->model)); 3173 if (!mtd->name) 3174 mtd->name = p->model; 3175 3176 mtd->writesize = le32_to_cpu(p->byte_per_page); 3177 3178 /* 3179 * pages_per_block and blocks_per_lun may not be a power-of-2 size 3180 * (don't ask me who thought of this...). MTD assumes that these 3181 * dimensions will be power-of-2, so just truncate the remaining area. 3182 */ 3183 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 3184 mtd->erasesize *= mtd->writesize; 3185 3186 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 3187 3188 /* See erasesize comment */ 3189 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 3190 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 3191 chip->bits_per_cell = p->bits_per_cell; 3192 3193 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) 3194 *busw = NAND_BUSWIDTH_16; 3195 else 3196 *busw = 0; 3197 3198 if (p->ecc_bits != 0xff) { 3199 chip->ecc_strength_ds = p->ecc_bits; 3200 chip->ecc_step_ds = 512; 3201 } else if (chip->onfi_version >= 21 && 3202 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { 3203 3204 /* 3205 * The nand_flash_detect_ext_param_page() uses the 3206 * Change Read Column command which maybe not supported 3207 * by the chip->cmdfunc. So try to update the chip->cmdfunc 3208 * now. We do not replace user supplied command function. 3209 */ 3210 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3211 chip->cmdfunc = nand_command_lp; 3212 3213 /* The Extended Parameter Page is supported since ONFI 2.1. */ 3214 if (nand_flash_detect_ext_param_page(mtd, chip, p)) 3215 pr_warn("Failed to detect ONFI extended param page\n"); 3216 } else { 3217 pr_warn("Could not retrieve ONFI ECC requirements\n"); 3218 } 3219 3220 if (p->jedec_id == NAND_MFR_MICRON) 3221 nand_onfi_detect_micron(chip, p); 3222 3223 return 1; 3224} 3225 3226/* 3227 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. 3228 */ 3229static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, 3230 int *busw) 3231{ 3232 struct nand_jedec_params *p = &chip->jedec_params; 3233 struct jedec_ecc_info *ecc; 3234 int val; 3235 int i, j; 3236 3237 /* Try JEDEC for unknown chip or LP */ 3238 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); 3239 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || 3240 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || 3241 chip->read_byte(mtd) != 'C') 3242 return 0; 3243 3244 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); 3245 for (i = 0; i < 3; i++) { 3246 for (j = 0; j < sizeof(*p); j++) 3247 ((uint8_t *)p)[j] = chip->read_byte(mtd); 3248 3249 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == 3250 le16_to_cpu(p->crc)) 3251 break; 3252 } 3253 3254 if (i == 3) { 3255 pr_err("Could not find valid JEDEC parameter page; aborting\n"); 3256 return 0; 3257 } 3258 3259 /* Check version */ 3260 val = le16_to_cpu(p->revision); 3261 if (val & (1 << 2)) 3262 chip->jedec_version = 10; 3263 else if (val & (1 << 1)) 3264 chip->jedec_version = 1; /* vendor specific version */ 3265 3266 if (!chip->jedec_version) { 3267 pr_info("unsupported JEDEC version: %d\n", val); 3268 return 0; 3269 } 3270 3271 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 3272 sanitize_string(p->model, sizeof(p->model)); 3273 if (!mtd->name) 3274 mtd->name = p->model; 3275 3276 mtd->writesize = le32_to_cpu(p->byte_per_page); 3277 3278 /* Please reference to the comment for nand_flash_detect_onfi. */ 3279 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 3280 mtd->erasesize *= mtd->writesize; 3281 3282 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 3283 3284 /* Please reference to the comment for nand_flash_detect_onfi. */ 3285 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 3286 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 3287 chip->bits_per_cell = p->bits_per_cell; 3288 3289 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) 3290 *busw = NAND_BUSWIDTH_16; 3291 else 3292 *busw = 0; 3293 3294 /* ECC info */ 3295 ecc = &p->ecc_info[0]; 3296 3297 if (ecc->codeword_size >= 9) { 3298 chip->ecc_strength_ds = ecc->ecc_bits; 3299 chip->ecc_step_ds = 1 << ecc->codeword_size; 3300 } else { 3301 pr_warn("Invalid codeword size\n"); 3302 } 3303 3304 return 1; 3305} 3306 3307/* 3308 * nand_id_has_period - Check if an ID string has a given wraparound period 3309 * @id_data: the ID string 3310 * @arrlen: the length of the @id_data array 3311 * @period: the period of repitition 3312 * 3313 * Check if an ID string is repeated within a given sequence of bytes at 3314 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 3315 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 3316 * if the repetition has a period of @period; otherwise, returns zero. 3317 */ 3318static int nand_id_has_period(u8 *id_data, int arrlen, int period) 3319{ 3320 int i, j; 3321 for (i = 0; i < period; i++) 3322 for (j = i + period; j < arrlen; j += period) 3323 if (id_data[i] != id_data[j]) 3324 return 0; 3325 return 1; 3326} 3327 3328/* 3329 * nand_id_len - Get the length of an ID string returned by CMD_READID 3330 * @id_data: the ID string 3331 * @arrlen: the length of the @id_data array 3332 3333 * Returns the length of the ID string, according to known wraparound/trailing 3334 * zero patterns. If no pattern exists, returns the length of the array. 3335 */ 3336static int nand_id_len(u8 *id_data, int arrlen) 3337{ 3338 int last_nonzero, period; 3339 3340 /* Find last non-zero byte */ 3341 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 3342 if (id_data[last_nonzero]) 3343 break; 3344 3345 /* All zeros */ 3346 if (last_nonzero < 0) 3347 return 0; 3348 3349 /* Calculate wraparound period */ 3350 for (period = 1; period < arrlen; period++) 3351 if (nand_id_has_period(id_data, arrlen, period)) 3352 break; 3353 3354 /* There's a repeated pattern */ 3355 if (period < arrlen) 3356 return period; 3357 3358 /* There are trailing zeros */ 3359 if (last_nonzero < arrlen - 1) 3360 return last_nonzero + 1; 3361 3362 /* No pattern detected */ 3363 return arrlen; 3364} 3365 3366/* Extract the bits of per cell from the 3rd byte of the extended ID */ 3367static int nand_get_bits_per_cell(u8 cellinfo) 3368{ 3369 int bits; 3370 3371 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 3372 bits >>= NAND_CI_CELLTYPE_SHIFT; 3373 return bits + 1; 3374} 3375 3376/* 3377 * Many new NAND share similar device ID codes, which represent the size of the 3378 * chip. The rest of the parameters must be decoded according to generic or 3379 * manufacturer-specific "extended ID" decoding patterns. 3380 */ 3381static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, 3382 u8 id_data[8], int *busw) 3383{ 3384 int extid, id_len; 3385 /* The 3rd id byte holds MLC / multichip data */ 3386 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 3387 /* The 4th id byte is the important one */ 3388 extid = id_data[3]; 3389 3390 id_len = nand_id_len(id_data, 8); 3391 3392 /* 3393 * Field definitions are in the following datasheets: 3394 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) 3395 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) 3396 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) 3397 * 3398 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung 3399 * ID to decide what to do. 3400 */ 3401 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && 3402 !nand_is_slc(chip) && id_data[5] != 0x00) { 3403 /* Calc pagesize */ 3404 mtd->writesize = 2048 << (extid & 0x03); 3405 extid >>= 2; 3406 /* Calc oobsize */ 3407 switch (((extid >> 2) & 0x04) | (extid & 0x03)) { 3408 case 1: 3409 mtd->oobsize = 128; 3410 break; 3411 case 2: 3412 mtd->oobsize = 218; 3413 break; 3414 case 3: 3415 mtd->oobsize = 400; 3416 break; 3417 case 4: 3418 mtd->oobsize = 436; 3419 break; 3420 case 5: 3421 mtd->oobsize = 512; 3422 break; 3423 case 6: 3424 mtd->oobsize = 640; 3425 break; 3426 case 7: 3427 default: /* Other cases are "reserved" (unknown) */ 3428 mtd->oobsize = 1024; 3429 break; 3430 } 3431 extid >>= 2; 3432 /* Calc blocksize */ 3433 mtd->erasesize = (128 * 1024) << 3434 (((extid >> 1) & 0x04) | (extid & 0x03)); 3435 *busw = 0; 3436 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && 3437 !nand_is_slc(chip)) { 3438 unsigned int tmp; 3439 3440 /* Calc pagesize */ 3441 mtd->writesize = 2048 << (extid & 0x03); 3442 extid >>= 2; 3443 /* Calc oobsize */ 3444 switch (((extid >> 2) & 0x04) | (extid & 0x03)) { 3445 case 0: 3446 mtd->oobsize = 128; 3447 break; 3448 case 1: 3449 mtd->oobsize = 224; 3450 break; 3451 case 2: 3452 mtd->oobsize = 448; 3453 break; 3454 case 3: 3455 mtd->oobsize = 64; 3456 break; 3457 case 4: 3458 mtd->oobsize = 32; 3459 break; 3460 case 5: 3461 mtd->oobsize = 16; 3462 break; 3463 default: 3464 mtd->oobsize = 640; 3465 break; 3466 } 3467 extid >>= 2; 3468 /* Calc blocksize */ 3469 tmp = ((extid >> 1) & 0x04) | (extid & 0x03); 3470 if (tmp < 0x03) 3471 mtd->erasesize = (128 * 1024) << tmp; 3472 else if (tmp == 0x03) 3473 mtd->erasesize = 768 * 1024; 3474 else 3475 mtd->erasesize = (64 * 1024) << tmp; 3476 *busw = 0; 3477 } else { 3478 /* Calc pagesize */ 3479 mtd->writesize = 1024 << (extid & 0x03); 3480 extid >>= 2; 3481 /* Calc oobsize */ 3482 mtd->oobsize = (8 << (extid & 0x01)) * 3483 (mtd->writesize >> 9); 3484 extid >>= 2; 3485 /* Calc blocksize. Blocksize is multiples of 64KiB */ 3486 mtd->erasesize = (64 * 1024) << (extid & 0x03); 3487 extid >>= 2; 3488 /* Get buswidth information */ 3489 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; 3490 3491 /* 3492 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per 3493 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as 3494 * follows: 3495 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, 3496 * 110b -> 24nm 3497 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC 3498 */ 3499 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && 3500 nand_is_slc(chip) && 3501 (id_data[5] & 0x7) == 0x6 /* 24nm */ && 3502 !(id_data[4] & 0x80) /* !BENAND */) { 3503 mtd->oobsize = 32 * mtd->writesize >> 9; 3504 } 3505 3506 } 3507} 3508 3509/* 3510 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 3511 * decodes a matching ID table entry and assigns the MTD size parameters for 3512 * the chip. 3513 */ 3514static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, 3515 struct nand_flash_dev *type, u8 id_data[8], 3516 int *busw) 3517{ 3518 int maf_id = id_data[0]; 3519 3520 mtd->erasesize = type->erasesize; 3521 mtd->writesize = type->pagesize; 3522 mtd->oobsize = mtd->writesize / 32; 3523 *busw = type->options & NAND_BUSWIDTH_16; 3524 3525 /* All legacy ID NAND are small-page, SLC */ 3526 chip->bits_per_cell = 1; 3527 3528 /* 3529 * Check for Spansion/AMD ID + repeating 5th, 6th byte since 3530 * some Spansion chips have erasesize that conflicts with size 3531 * listed in nand_ids table. 3532 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) 3533 */ 3534 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 3535 && id_data[6] == 0x00 && id_data[7] == 0x00 3536 && mtd->writesize == 512) { 3537 mtd->erasesize = 128 * 1024; 3538 mtd->erasesize <<= ((id_data[3] & 0x03) << 1); 3539 } 3540} 3541 3542/* 3543 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 3544 * heuristic patterns using various detected parameters (e.g., manufacturer, 3545 * page size, cell-type information). 3546 */ 3547static void nand_decode_bbm_options(struct mtd_info *mtd, 3548 struct nand_chip *chip, u8 id_data[8]) 3549{ 3550 int maf_id = id_data[0]; 3551 3552 /* Set the bad block position */ 3553 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 3554 chip->badblockpos = NAND_LARGE_BADBLOCK_POS; 3555 else 3556 chip->badblockpos = NAND_SMALL_BADBLOCK_POS; 3557 3558 /* 3559 * Bad block marker is stored in the last page of each block on Samsung 3560 * and Hynix MLC devices; stored in first two pages of each block on 3561 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, 3562 * AMD/Spansion, and Macronix. All others scan only the first page. 3563 */ 3564 if (!nand_is_slc(chip) && 3565 (maf_id == NAND_MFR_SAMSUNG || 3566 maf_id == NAND_MFR_HYNIX)) 3567 chip->bbt_options |= NAND_BBT_SCANLASTPAGE; 3568 else if ((nand_is_slc(chip) && 3569 (maf_id == NAND_MFR_SAMSUNG || 3570 maf_id == NAND_MFR_HYNIX || 3571 maf_id == NAND_MFR_TOSHIBA || 3572 maf_id == NAND_MFR_AMD || 3573 maf_id == NAND_MFR_MACRONIX)) || 3574 (mtd->writesize == 2048 && 3575 maf_id == NAND_MFR_MICRON)) 3576 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; 3577} 3578 3579static inline bool is_full_id_nand(struct nand_flash_dev *type) 3580{ 3581 return type->id_len; 3582} 3583 3584static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, 3585 struct nand_flash_dev *type, u8 *id_data, int *busw) 3586{ 3587 if (!strncmp(type->id, id_data, type->id_len)) { 3588 mtd->writesize = type->pagesize; 3589 mtd->erasesize = type->erasesize; 3590 mtd->oobsize = type->oobsize; 3591 3592 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 3593 chip->chipsize = (uint64_t)type->chipsize << 20; 3594 chip->options |= type->options; 3595 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); 3596 chip->ecc_step_ds = NAND_ECC_STEP(type); 3597 chip->onfi_timing_mode_default = 3598 type->onfi_timing_mode_default; 3599 3600 *busw = type->options & NAND_BUSWIDTH_16; 3601 3602 if (!mtd->name) 3603 mtd->name = type->name; 3604 3605 return true; 3606 } 3607 return false; 3608} 3609 3610/* 3611 * Get the flash and manufacturer id and lookup if the type is supported. 3612 */ 3613static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, 3614 struct nand_chip *chip, 3615 int *maf_id, int *dev_id, 3616 struct nand_flash_dev *type) 3617{ 3618 int busw; 3619 int i, maf_idx; 3620 u8 id_data[8]; 3621 3622 /* Select the device */ 3623 chip->select_chip(mtd, 0); 3624 3625 /* 3626 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 3627 * after power-up. 3628 */ 3629 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 3630 3631 /* Send the command for reading device ID */ 3632 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3633 3634 /* Read manufacturer and device IDs */ 3635 *maf_id = chip->read_byte(mtd); 3636 *dev_id = chip->read_byte(mtd); 3637 3638 /* 3639 * Try again to make sure, as some systems the bus-hold or other 3640 * interface concerns can cause random data which looks like a 3641 * possibly credible NAND flash to appear. If the two results do 3642 * not match, ignore the device completely. 3643 */ 3644 3645 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3646 3647 /* Read entire ID string */ 3648 for (i = 0; i < 8; i++) 3649 id_data[i] = chip->read_byte(mtd); 3650 3651 if (id_data[0] != *maf_id || id_data[1] != *dev_id) { 3652 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 3653 *maf_id, *dev_id, id_data[0], id_data[1]); 3654 return ERR_PTR(-ENODEV); 3655 } 3656 3657 if (!type) 3658 type = nand_flash_ids; 3659 3660 for (; type->name != NULL; type++) { 3661 if (is_full_id_nand(type)) { 3662 if (find_full_id_nand(mtd, chip, type, id_data, &busw)) 3663 goto ident_done; 3664 } else if (*dev_id == type->dev_id) { 3665 break; 3666 } 3667 } 3668 3669 chip->onfi_version = 0; 3670 if (!type->name || !type->pagesize) { 3671 /* Check if the chip is ONFI compliant */ 3672 if (nand_flash_detect_onfi(mtd, chip, &busw)) 3673 goto ident_done; 3674 3675 /* Check if the chip is JEDEC compliant */ 3676 if (nand_flash_detect_jedec(mtd, chip, &busw)) 3677 goto ident_done; 3678 } 3679 3680 if (!type->name) 3681 return ERR_PTR(-ENODEV); 3682 3683 if (!mtd->name) 3684 mtd->name = type->name; 3685 3686 chip->chipsize = (uint64_t)type->chipsize << 20; 3687 3688 if (!type->pagesize && chip->init_size) { 3689 /* Set the pagesize, oobsize, erasesize by the driver */ 3690 busw = chip->init_size(mtd, chip, id_data); 3691 } else if (!type->pagesize) { 3692 /* Decode parameters from extended ID */ 3693 nand_decode_ext_id(mtd, chip, id_data, &busw); 3694 } else { 3695 nand_decode_id(mtd, chip, type, id_data, &busw); 3696 } 3697 /* Get chip options */ 3698 chip->options |= type->options; 3699 3700 /* 3701 * Check if chip is not a Samsung device. Do not clear the 3702 * options for chips which do not have an extended id. 3703 */ 3704 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) 3705 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; 3706ident_done: 3707 3708 /* Try to identify manufacturer */ 3709 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { 3710 if (nand_manuf_ids[maf_idx].id == *maf_id) 3711 break; 3712 } 3713 3714 if (chip->options & NAND_BUSWIDTH_AUTO) { 3715 WARN_ON(chip->options & NAND_BUSWIDTH_16); 3716 chip->options |= busw; 3717 nand_set_defaults(chip, busw); 3718 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 3719 /* 3720 * Check, if buswidth is correct. Hardware drivers should set 3721 * chip correct! 3722 */ 3723 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 3724 *maf_id, *dev_id); 3725 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); 3726 pr_warn("bus width %d instead %d bit\n", 3727 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, 3728 busw ? 16 : 8); 3729 return ERR_PTR(-EINVAL); 3730 } 3731 3732 nand_decode_bbm_options(mtd, chip, id_data); 3733 3734 /* Calculate the address shift from the page size */ 3735 chip->page_shift = ffs(mtd->writesize) - 1; 3736 /* Convert chipsize to number of pages per chip -1 */ 3737 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 3738 3739 chip->bbt_erase_shift = chip->phys_erase_shift = 3740 ffs(mtd->erasesize) - 1; 3741 if (chip->chipsize & 0xffffffff) 3742 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; 3743 else { 3744 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); 3745 chip->chip_shift += 32 - 1; 3746 } 3747 3748 chip->badblockbits = 8; 3749 chip->erase = single_erase; 3750 3751 /* Do not replace user supplied command function! */ 3752 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3753 chip->cmdfunc = nand_command_lp; 3754 3755 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 3756 *maf_id, *dev_id); 3757 3758 if (chip->onfi_version) 3759 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3760 chip->onfi_params.model); 3761 else if (chip->jedec_version) 3762 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3763 chip->jedec_params.model); 3764 else 3765 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, 3766 type->name); 3767 3768 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", 3769 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 3770 mtd->writesize, mtd->oobsize); 3771 return type; 3772} 3773 3774/** 3775 * nand_scan_ident - [NAND Interface] Scan for the NAND device 3776 * @mtd: MTD device structure 3777 * @maxchips: number of chips to scan for 3778 * @table: alternative NAND ID table 3779 * 3780 * This is the first phase of the normal nand_scan() function. It reads the 3781 * flash ID and sets up MTD fields accordingly. 3782 * 3783 * The mtd->owner field must be set to the module of the caller. 3784 */ 3785int nand_scan_ident(struct mtd_info *mtd, int maxchips, 3786 struct nand_flash_dev *table) 3787{ 3788 int i, nand_maf_id, nand_dev_id; 3789 struct nand_chip *chip = mtd->priv; 3790 struct nand_flash_dev *type; 3791 3792 /* Set the default functions */ 3793 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); 3794 3795 /* Read the flash type */ 3796 type = nand_get_flash_type(mtd, chip, &nand_maf_id, 3797 &nand_dev_id, table); 3798 3799 if (IS_ERR(type)) { 3800 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 3801 pr_warn("No NAND device found\n"); 3802 chip->select_chip(mtd, -1); 3803 return PTR_ERR(type); 3804 } 3805 3806 chip->select_chip(mtd, -1); 3807 3808 /* Check for a chip array */ 3809 for (i = 1; i < maxchips; i++) { 3810 chip->select_chip(mtd, i); 3811 /* See comment in nand_get_flash_type for reset */ 3812 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 3813 /* Send the command for reading device ID */ 3814 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 3815 /* Read manufacturer and device IDs */ 3816 if (nand_maf_id != chip->read_byte(mtd) || 3817 nand_dev_id != chip->read_byte(mtd)) { 3818 chip->select_chip(mtd, -1); 3819 break; 3820 } 3821 chip->select_chip(mtd, -1); 3822 } 3823 if (i > 1) 3824 pr_info("%d chips detected\n", i); 3825 3826 /* Store the number of chips and calc total size for mtd */ 3827 chip->numchips = i; 3828 mtd->size = i * chip->chipsize; 3829 3830 return 0; 3831} 3832EXPORT_SYMBOL(nand_scan_ident); 3833 3834/* 3835 * Check if the chip configuration meet the datasheet requirements. 3836 3837 * If our configuration corrects A bits per B bytes and the minimum 3838 * required correction level is X bits per Y bytes, then we must ensure 3839 * both of the following are true: 3840 * 3841 * (1) A / B >= X / Y 3842 * (2) A >= X 3843 * 3844 * Requirement (1) ensures we can correct for the required bitflip density. 3845 * Requirement (2) ensures we can correct even when all bitflips are clumped 3846 * in the same sector. 3847 */ 3848static bool nand_ecc_strength_good(struct mtd_info *mtd) 3849{ 3850 struct nand_chip *chip = mtd->priv; 3851 struct nand_ecc_ctrl *ecc = &chip->ecc; 3852 int corr, ds_corr; 3853 3854 if (ecc->size == 0 || chip->ecc_step_ds == 0) 3855 /* Not enough information */ 3856 return true; 3857 3858 /* 3859 * We get the number of corrected bits per page to compare 3860 * the correction density. 3861 */ 3862 corr = (mtd->writesize * ecc->strength) / ecc->size; 3863 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; 3864 3865 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; 3866} 3867 3868/** 3869 * nand_scan_tail - [NAND Interface] Scan for the NAND device 3870 * @mtd: MTD device structure 3871 * 3872 * This is the second phase of the normal nand_scan() function. It fills out 3873 * all the uninitialized function pointers with the defaults and scans for a 3874 * bad block table if appropriate. 3875 */ 3876int nand_scan_tail(struct mtd_info *mtd) 3877{ 3878 int i; 3879 struct nand_chip *chip = mtd->priv; 3880 struct nand_ecc_ctrl *ecc = &chip->ecc; 3881 struct nand_buffers *nbuf; 3882 3883 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 3884 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 3885 !(chip->bbt_options & NAND_BBT_USE_FLASH)); 3886 3887 if (!(chip->options & NAND_OWN_BUFFERS)) { 3888 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize 3889 + mtd->oobsize * 3, GFP_KERNEL); 3890 if (!nbuf) 3891 return -ENOMEM; 3892 nbuf->ecccalc = (uint8_t *)(nbuf + 1); 3893 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; 3894 nbuf->databuf = nbuf->ecccode + mtd->oobsize; 3895 3896 chip->buffers = nbuf; 3897 } else { 3898 if (!chip->buffers) 3899 return -ENOMEM; 3900 } 3901 3902 /* Set the internal oob buffer location, just after the page data */ 3903 chip->oob_poi = chip->buffers->databuf + mtd->writesize; 3904 3905 /* 3906 * If no default placement scheme is given, select an appropriate one. 3907 */ 3908 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { 3909 switch (mtd->oobsize) { 3910 case 8: 3911 ecc->layout = &nand_oob_8; 3912 break; 3913 case 16: 3914 ecc->layout = &nand_oob_16; 3915 break; 3916 case 64: 3917 ecc->layout = &nand_oob_64; 3918 break; 3919 case 128: 3920 ecc->layout = &nand_oob_128; 3921 break; 3922 default: 3923 pr_warn("No oob scheme defined for oobsize %d\n", 3924 mtd->oobsize); 3925 BUG(); 3926 } 3927 } 3928 3929 if (!chip->write_page) 3930 chip->write_page = nand_write_page; 3931 3932 /* 3933 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 3934 * selected and we have 256 byte pagesize fallback to software ECC 3935 */ 3936 3937 switch (ecc->mode) { 3938 case NAND_ECC_HW_OOB_FIRST: 3939 /* Similar to NAND_ECC_HW, but a separate read_page handle */ 3940 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { 3941 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 3942 BUG(); 3943 } 3944 if (!ecc->read_page) 3945 ecc->read_page = nand_read_page_hwecc_oob_first; 3946 3947 case NAND_ECC_HW: 3948 /* Use standard hwecc read page function? */ 3949 if (!ecc->read_page) 3950 ecc->read_page = nand_read_page_hwecc; 3951 if (!ecc->write_page) 3952 ecc->write_page = nand_write_page_hwecc; 3953 if (!ecc->read_page_raw) 3954 ecc->read_page_raw = nand_read_page_raw; 3955 if (!ecc->write_page_raw) 3956 ecc->write_page_raw = nand_write_page_raw; 3957 if (!ecc->read_oob) 3958 ecc->read_oob = nand_read_oob_std; 3959 if (!ecc->write_oob) 3960 ecc->write_oob = nand_write_oob_std; 3961 if (!ecc->read_subpage) 3962 ecc->read_subpage = nand_read_subpage; 3963 if (!ecc->write_subpage) 3964 ecc->write_subpage = nand_write_subpage_hwecc; 3965 3966 case NAND_ECC_HW_SYNDROME: 3967 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 3968 (!ecc->read_page || 3969 ecc->read_page == nand_read_page_hwecc || 3970 !ecc->write_page || 3971 ecc->write_page == nand_write_page_hwecc)) { 3972 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 3973 BUG(); 3974 } 3975 /* Use standard syndrome read/write page function? */ 3976 if (!ecc->read_page) 3977 ecc->read_page = nand_read_page_syndrome; 3978 if (!ecc->write_page) 3979 ecc->write_page = nand_write_page_syndrome; 3980 if (!ecc->read_page_raw) 3981 ecc->read_page_raw = nand_read_page_raw_syndrome; 3982 if (!ecc->write_page_raw) 3983 ecc->write_page_raw = nand_write_page_raw_syndrome; 3984 if (!ecc->read_oob) 3985 ecc->read_oob = nand_read_oob_syndrome; 3986 if (!ecc->write_oob) 3987 ecc->write_oob = nand_write_oob_syndrome; 3988 3989 if (mtd->writesize >= ecc->size) { 3990 if (!ecc->strength) { 3991 pr_warn("Driver must set ecc.strength when using hardware ECC\n"); 3992 BUG(); 3993 } 3994 break; 3995 } 3996 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 3997 ecc->size, mtd->writesize); 3998 ecc->mode = NAND_ECC_SOFT; 3999 4000 case NAND_ECC_SOFT: 4001 ecc->calculate = nand_calculate_ecc; 4002 ecc->correct = nand_correct_data; 4003 ecc->read_page = nand_read_page_swecc; 4004 ecc->read_subpage = nand_read_subpage; 4005 ecc->write_page = nand_write_page_swecc; 4006 ecc->read_page_raw = nand_read_page_raw; 4007 ecc->write_page_raw = nand_write_page_raw; 4008 ecc->read_oob = nand_read_oob_std; 4009 ecc->write_oob = nand_write_oob_std; 4010 if (!ecc->size) 4011 ecc->size = 256; 4012 ecc->bytes = 3; 4013 ecc->strength = 1; 4014 break; 4015 4016 case NAND_ECC_SOFT_BCH: 4017 if (!mtd_nand_has_bch()) { 4018 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); 4019 BUG(); 4020 } 4021 ecc->calculate = nand_bch_calculate_ecc; 4022 ecc->correct = nand_bch_correct_data; 4023 ecc->read_page = nand_read_page_swecc; 4024 ecc->read_subpage = nand_read_subpage; 4025 ecc->write_page = nand_write_page_swecc; 4026 ecc->read_page_raw = nand_read_page_raw; 4027 ecc->write_page_raw = nand_write_page_raw; 4028 ecc->read_oob = nand_read_oob_std; 4029 ecc->write_oob = nand_write_oob_std; 4030 /* 4031 * Board driver should supply ecc.size and ecc.bytes values to 4032 * select how many bits are correctable; see nand_bch_init() 4033 * for details. Otherwise, default to 4 bits for large page 4034 * devices. 4035 */ 4036 if (!ecc->size && (mtd->oobsize >= 64)) { 4037 ecc->size = 512; 4038 ecc->bytes = 7; 4039 } 4040 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, 4041 &ecc->layout); 4042 if (!ecc->priv) { 4043 pr_warn("BCH ECC initialization failed!\n"); 4044 BUG(); 4045 } 4046 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); 4047 break; 4048 4049 case NAND_ECC_NONE: 4050 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); 4051 ecc->read_page = nand_read_page_raw; 4052 ecc->write_page = nand_write_page_raw; 4053 ecc->read_oob = nand_read_oob_std; 4054 ecc->read_page_raw = nand_read_page_raw; 4055 ecc->write_page_raw = nand_write_page_raw; 4056 ecc->write_oob = nand_write_oob_std; 4057 ecc->size = mtd->writesize; 4058 ecc->bytes = 0; 4059 ecc->strength = 0; 4060 break; 4061 4062 default: 4063 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); 4064 BUG(); 4065 } 4066 4067 /* For many systems, the standard OOB write also works for raw */ 4068 if (!ecc->read_oob_raw) 4069 ecc->read_oob_raw = ecc->read_oob; 4070 if (!ecc->write_oob_raw) 4071 ecc->write_oob_raw = ecc->write_oob; 4072 4073 /* 4074 * The number of bytes available for a client to place data into 4075 * the out of band area. 4076 */ 4077 ecc->layout->oobavail = 0; 4078 for (i = 0; ecc->layout->oobfree[i].length 4079 && i < ARRAY_SIZE(ecc->layout->oobfree); i++) 4080 ecc->layout->oobavail += ecc->layout->oobfree[i].length; 4081 mtd->oobavail = ecc->layout->oobavail; 4082 4083 /* ECC sanity check: warn if it's too weak */ 4084 if (!nand_ecc_strength_good(mtd)) 4085 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", 4086 mtd->name); 4087 4088 /* 4089 * Set the number of read / write steps for one page depending on ECC 4090 * mode. 4091 */ 4092 ecc->steps = mtd->writesize / ecc->size; 4093 if (ecc->steps * ecc->size != mtd->writesize) { 4094 pr_warn("Invalid ECC parameters\n"); 4095 BUG(); 4096 } 4097 ecc->total = ecc->steps * ecc->bytes; 4098 4099 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 4100 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 4101 switch (ecc->steps) { 4102 case 2: 4103 mtd->subpage_sft = 1; 4104 break; 4105 case 4: 4106 case 8: 4107 case 16: 4108 mtd->subpage_sft = 2; 4109 break; 4110 } 4111 } 4112 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 4113 4114 /* Initialize state */ 4115 chip->state = FL_READY; 4116 4117 /* Invalidate the pagebuffer reference */ 4118 chip->pagebuf = -1; 4119 4120 /* Large page NAND with SOFT_ECC should support subpage reads */ 4121 switch (ecc->mode) { 4122 case NAND_ECC_SOFT: 4123 case NAND_ECC_SOFT_BCH: 4124 if (chip->page_shift > 9) 4125 chip->options |= NAND_SUBPAGE_READ; 4126 break; 4127 4128 default: 4129 break; 4130 } 4131 4132 /* Fill in remaining MTD driver data */ 4133 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; 4134 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : 4135 MTD_CAP_NANDFLASH; 4136 mtd->_erase = nand_erase; 4137 mtd->_point = NULL; 4138 mtd->_unpoint = NULL; 4139 mtd->_read = nand_read; 4140 mtd->_write = nand_write; 4141 mtd->_panic_write = panic_nand_write; 4142 mtd->_read_oob = nand_read_oob; 4143 mtd->_write_oob = nand_write_oob; 4144 mtd->_sync = nand_sync; 4145 mtd->_lock = NULL; 4146 mtd->_unlock = NULL; 4147 mtd->_suspend = nand_suspend; 4148 mtd->_resume = nand_resume; 4149 mtd->_block_isreserved = nand_block_isreserved; 4150 mtd->_block_isbad = nand_block_isbad; 4151 mtd->_block_markbad = nand_block_markbad; 4152 mtd->writebufsize = mtd->writesize; 4153 4154 /* propagate ecc info to mtd_info */ 4155 mtd->ecclayout = ecc->layout; 4156 mtd->ecc_strength = ecc->strength; 4157 mtd->ecc_step_size = ecc->size; 4158 /* 4159 * Initialize bitflip_threshold to its default prior scan_bbt() call. 4160 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 4161 * properly set. 4162 */ 4163 if (!mtd->bitflip_threshold) 4164 mtd->bitflip_threshold = mtd->ecc_strength; 4165 4166 /* Check, if we should skip the bad block table scan */ 4167 if (chip->options & NAND_SKIP_BBTSCAN) 4168 return 0; 4169 4170 /* Build bad block table */ 4171 return chip->scan_bbt(mtd); 4172} 4173EXPORT_SYMBOL(nand_scan_tail); 4174 4175/* 4176 * is_module_text_address() isn't exported, and it's mostly a pointless 4177 * test if this is a module _anyway_ -- they'd have to try _really_ hard 4178 * to call us from in-kernel code if the core NAND support is modular. 4179 */ 4180#ifdef MODULE 4181#define caller_is_module() (1) 4182#else 4183#define caller_is_module() \ 4184 is_module_text_address((unsigned long)__builtin_return_address(0)) 4185#endif 4186 4187/** 4188 * nand_scan - [NAND Interface] Scan for the NAND device 4189 * @mtd: MTD device structure 4190 * @maxchips: number of chips to scan for 4191 * 4192 * This fills out all the uninitialized function pointers with the defaults. 4193 * The flash ID is read and the mtd/chip structures are filled with the 4194 * appropriate values. The mtd->owner field must be set to the module of the 4195 * caller. 4196 */ 4197int nand_scan(struct mtd_info *mtd, int maxchips) 4198{ 4199 int ret; 4200 4201 /* Many callers got this wrong, so check for it for a while... */ 4202 if (!mtd->owner && caller_is_module()) { 4203 pr_crit("%s called with NULL mtd->owner!\n", __func__); 4204 BUG(); 4205 } 4206 4207 ret = nand_scan_ident(mtd, maxchips, NULL); 4208 if (!ret) 4209 ret = nand_scan_tail(mtd); 4210 return ret; 4211} 4212EXPORT_SYMBOL(nand_scan); 4213 4214/** 4215 * nand_release - [NAND Interface] Free resources held by the NAND device 4216 * @mtd: MTD device structure 4217 */ 4218void nand_release(struct mtd_info *mtd) 4219{ 4220 struct nand_chip *chip = mtd->priv; 4221 4222 if (chip->ecc.mode == NAND_ECC_SOFT_BCH) 4223 nand_bch_free((struct nand_bch_control *)chip->ecc.priv); 4224 4225 mtd_device_unregister(mtd); 4226 4227 /* Free bad block table memory */ 4228 kfree(chip->bbt); 4229 if (!(chip->options & NAND_OWN_BUFFERS)) 4230 kfree(chip->buffers); 4231 4232 /* Free bad block descriptor memory */ 4233 if (chip->badblock_pattern && chip->badblock_pattern->options 4234 & NAND_BBT_DYNAMICSTRUCT) 4235 kfree(chip->badblock_pattern); 4236} 4237EXPORT_SYMBOL_GPL(nand_release); 4238 4239static int __init nand_base_init(void) 4240{ 4241 led_trigger_register_simple("nand-disk", &nand_led_trigger); 4242 return 0; 4243} 4244 4245static void __exit nand_base_exit(void) 4246{ 4247 led_trigger_unregister_simple(nand_led_trigger); 4248} 4249 4250module_init(nand_base_init); 4251module_exit(nand_base_exit); 4252 4253MODULE_LICENSE("GPL"); 4254MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 4255MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 4256MODULE_DESCRIPTION("Generic NAND flash driver code"); 4257