1/* 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34#include <linux/interrupt.h> 35#include <linux/slab.h> 36#include <linux/export.h> 37#include <linux/mm.h> 38#include <linux/dma-mapping.h> 39 40#include <linux/mlx4/cmd.h> 41#include <linux/cpu_rmap.h> 42 43#include "mlx4.h" 44#include "fw.h" 45 46enum { 47 MLX4_IRQNAME_SIZE = 32 48}; 49 50enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54}; 55 56#define MLX4_EQ_STATUS_OK ( 0 << 28) 57#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58#define MLX4_EQ_OWNER_SW ( 0 << 24) 59#define MLX4_EQ_OWNER_HW ( 1 << 24) 60#define MLX4_EQ_FLAG_EC ( 1 << 18) 61#define MLX4_EQ_FLAG_OI ( 1 << 17) 62#define MLX4_EQ_STATE_ARMED ( 9 << 8) 63#define MLX4_EQ_STATE_FIRED (10 << 8) 64#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86static u64 get_async_ev_mask(struct mlx4_dev *dev) 87{ 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 92 return async_ev_mask; 93} 94 95static void eq_set_ci(struct mlx4_eq *eq, int req_not) 96{ 97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 98 req_not << 31), 99 eq->doorbell); 100 /* We still want ordering, just not swabbing, so add a barrier */ 101 mb(); 102} 103 104static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, 105 u8 eqe_size) 106{ 107 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 108 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; 109 /* CX3 is capable of extending the EQE from 32 to 64 bytes with 110 * strides of 64B,128B and 256B. 111 * When 64B EQE is used, the first (in the lower addresses) 112 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 113 * contain the legacy EQE information. 114 * In all other cases, the first 32B contains the legacy EQE info. 115 */ 116 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 117} 118 119static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) 120{ 121 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); 122 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 123} 124 125static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 126{ 127 struct mlx4_eqe *eqe = 128 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 129 return (!!(eqe->owner & 0x80) ^ 130 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 131 eqe : NULL; 132} 133 134void mlx4_gen_slave_eqe(struct work_struct *work) 135{ 136 struct mlx4_mfunc_master_ctx *master = 137 container_of(work, struct mlx4_mfunc_master_ctx, 138 slave_event_work); 139 struct mlx4_mfunc *mfunc = 140 container_of(master, struct mlx4_mfunc, master); 141 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 142 struct mlx4_dev *dev = &priv->dev; 143 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 144 struct mlx4_eqe *eqe; 145 u8 slave; 146 int i; 147 148 for (eqe = next_slave_event_eqe(slave_eq); eqe; 149 eqe = next_slave_event_eqe(slave_eq)) { 150 slave = eqe->slave_id; 151 152 /* All active slaves need to receive the event */ 153 if (slave == ALL_SLAVES) { 154 for (i = 0; i < dev->num_slaves; i++) { 155 if (i != dev->caps.function && 156 master->slave_state[i].active) 157 if (mlx4_GEN_EQE(dev, i, eqe)) 158 mlx4_warn(dev, "Failed to generate event for slave %d\n", 159 i); 160 } 161 } else { 162 if (mlx4_GEN_EQE(dev, slave, eqe)) 163 mlx4_warn(dev, "Failed to generate event for slave %d\n", 164 slave); 165 } 166 ++slave_eq->cons; 167 } 168} 169 170 171static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 172{ 173 struct mlx4_priv *priv = mlx4_priv(dev); 174 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 175 struct mlx4_eqe *s_eqe; 176 unsigned long flags; 177 178 spin_lock_irqsave(&slave_eq->event_lock, flags); 179 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 180 if ((!!(s_eqe->owner & 0x80)) ^ 181 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 182 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 183 slave); 184 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 185 return; 186 } 187 188 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); 189 s_eqe->slave_id = slave; 190 /* ensure all information is written before setting the ownersip bit */ 191 wmb(); 192 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 193 ++slave_eq->prod; 194 195 queue_work(priv->mfunc.master.comm_wq, 196 &priv->mfunc.master.slave_event_work); 197 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 198} 199 200static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 201 struct mlx4_eqe *eqe) 202{ 203 struct mlx4_priv *priv = mlx4_priv(dev); 204 struct mlx4_slave_state *s_slave = 205 &priv->mfunc.master.slave_state[slave]; 206 207 if (!s_slave->active) { 208 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/ 209 return; 210 } 211 212 slave_event(dev, slave, eqe); 213} 214 215int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 216{ 217 struct mlx4_eqe eqe; 218 219 struct mlx4_priv *priv = mlx4_priv(dev); 220 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 221 222 if (!s_slave->active) 223 return 0; 224 225 memset(&eqe, 0, sizeof eqe); 226 227 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 228 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 229 eqe.event.port_mgmt_change.port = port; 230 231 return mlx4_GEN_EQE(dev, slave, &eqe); 232} 233EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 234 235int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 236{ 237 struct mlx4_eqe eqe; 238 239 /*don't send if we don't have the that slave */ 240 if (dev->num_vfs < slave) 241 return 0; 242 memset(&eqe, 0, sizeof eqe); 243 244 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 245 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 246 eqe.event.port_mgmt_change.port = port; 247 248 return mlx4_GEN_EQE(dev, slave, &eqe); 249} 250EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 251 252int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 253 u8 port_subtype_change) 254{ 255 struct mlx4_eqe eqe; 256 257 /*don't send if we don't have the that slave */ 258 if (dev->num_vfs < slave) 259 return 0; 260 memset(&eqe, 0, sizeof eqe); 261 262 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 263 eqe.subtype = port_subtype_change; 264 eqe.event.port_change.port = cpu_to_be32(port << 28); 265 266 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 267 port_subtype_change, slave, port); 268 return mlx4_GEN_EQE(dev, slave, &eqe); 269} 270EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 271 272enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 273{ 274 struct mlx4_priv *priv = mlx4_priv(dev); 275 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 276 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 277 278 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 279 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 280 pr_err("%s: Error: asking for slave:%d, port:%d\n", 281 __func__, slave, port); 282 return SLAVE_PORT_DOWN; 283 } 284 return s_state[slave].port_state[port]; 285} 286EXPORT_SYMBOL(mlx4_get_slave_port_state); 287 288static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 289 enum slave_port_state state) 290{ 291 struct mlx4_priv *priv = mlx4_priv(dev); 292 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 293 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 294 295 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 296 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 297 pr_err("%s: Error: asking for slave:%d, port:%d\n", 298 __func__, slave, port); 299 return -1; 300 } 301 s_state[slave].port_state[port] = state; 302 303 return 0; 304} 305 306static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 307{ 308 int i; 309 enum slave_port_gen_event gen_event; 310 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 311 port); 312 313 for (i = 0; i < dev->num_vfs + 1; i++) 314 if (test_bit(i, slaves_pport.slaves)) 315 set_and_calc_slave_port_state(dev, i, port, 316 event, &gen_event); 317} 318/************************************************************************** 319 The function get as input the new event to that port, 320 and according to the prev state change the slave's port state. 321 The events are: 322 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 323 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 324 MLX4_PORT_STATE_IB_EVENT_GID_VALID 325 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 326***************************************************************************/ 327int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 328 u8 port, int event, 329 enum slave_port_gen_event *gen_event) 330{ 331 struct mlx4_priv *priv = mlx4_priv(dev); 332 struct mlx4_slave_state *ctx = NULL; 333 unsigned long flags; 334 int ret = -1; 335 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 336 enum slave_port_state cur_state = 337 mlx4_get_slave_port_state(dev, slave, port); 338 339 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 340 341 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 342 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 343 pr_err("%s: Error: asking for slave:%d, port:%d\n", 344 __func__, slave, port); 345 return ret; 346 } 347 348 ctx = &priv->mfunc.master.slave_state[slave]; 349 spin_lock_irqsave(&ctx->lock, flags); 350 351 switch (cur_state) { 352 case SLAVE_PORT_DOWN: 353 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 354 mlx4_set_slave_port_state(dev, slave, port, 355 SLAVE_PENDING_UP); 356 break; 357 case SLAVE_PENDING_UP: 358 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 359 mlx4_set_slave_port_state(dev, slave, port, 360 SLAVE_PORT_DOWN); 361 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 362 mlx4_set_slave_port_state(dev, slave, port, 363 SLAVE_PORT_UP); 364 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 365 } 366 break; 367 case SLAVE_PORT_UP: 368 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 369 mlx4_set_slave_port_state(dev, slave, port, 370 SLAVE_PORT_DOWN); 371 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 372 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 373 event) { 374 mlx4_set_slave_port_state(dev, slave, port, 375 SLAVE_PENDING_UP); 376 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 377 } 378 break; 379 default: 380 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 381 __func__, slave, port); 382 goto out; 383 } 384 ret = mlx4_get_slave_port_state(dev, slave, port); 385 386out: 387 spin_unlock_irqrestore(&ctx->lock, flags); 388 return ret; 389} 390 391EXPORT_SYMBOL(set_and_calc_slave_port_state); 392 393int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 394{ 395 struct mlx4_eqe eqe; 396 397 memset(&eqe, 0, sizeof eqe); 398 399 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 400 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 401 eqe.event.port_mgmt_change.port = port; 402 eqe.event.port_mgmt_change.params.port_info.changed_attr = 403 cpu_to_be32((u32) attr); 404 405 slave_event(dev, ALL_SLAVES, &eqe); 406 return 0; 407} 408EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 409 410void mlx4_master_handle_slave_flr(struct work_struct *work) 411{ 412 struct mlx4_mfunc_master_ctx *master = 413 container_of(work, struct mlx4_mfunc_master_ctx, 414 slave_flr_event_work); 415 struct mlx4_mfunc *mfunc = 416 container_of(master, struct mlx4_mfunc, master); 417 struct mlx4_priv *priv = 418 container_of(mfunc, struct mlx4_priv, mfunc); 419 struct mlx4_dev *dev = &priv->dev; 420 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 421 int i; 422 int err; 423 unsigned long flags; 424 425 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 426 427 for (i = 0 ; i < dev->num_slaves; i++) { 428 429 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 430 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 431 i); 432 433 mlx4_delete_all_resources_for_slave(dev, i); 434 /*return the slave to running mode*/ 435 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 436 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 437 slave_state[i].is_slave_going_down = 0; 438 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 439 /*notify the FW:*/ 440 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 441 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 442 if (err) 443 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 444 i); 445 } 446 } 447} 448 449static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 450{ 451 struct mlx4_priv *priv = mlx4_priv(dev); 452 struct mlx4_eqe *eqe; 453 int cqn; 454 int eqes_found = 0; 455 int set_ci = 0; 456 int port; 457 int slave = 0; 458 int ret; 459 u32 flr_slave; 460 u8 update_slave_state; 461 int i; 462 enum slave_port_gen_event gen_event; 463 unsigned long flags; 464 struct mlx4_vport_state *s_info; 465 int eqe_size = dev->caps.eqe_size; 466 467 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { 468 /* 469 * Make sure we read EQ entry contents after we've 470 * checked the ownership bit. 471 */ 472 rmb(); 473 474 switch (eqe->type) { 475 case MLX4_EVENT_TYPE_COMP: 476 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 477 mlx4_cq_completion(dev, cqn); 478 break; 479 480 case MLX4_EVENT_TYPE_PATH_MIG: 481 case MLX4_EVENT_TYPE_COMM_EST: 482 case MLX4_EVENT_TYPE_SQ_DRAINED: 483 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 484 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 485 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 486 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 487 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 488 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 489 if (mlx4_is_master(dev)) { 490 /* forward only to slave owning the QP */ 491 ret = mlx4_get_slave_from_resource_id(dev, 492 RES_QP, 493 be32_to_cpu(eqe->event.qp.qpn) 494 & 0xffffff, &slave); 495 if (ret && ret != -ENOENT) { 496 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 497 eqe->type, eqe->subtype, 498 eq->eqn, eq->cons_index, ret); 499 break; 500 } 501 502 if (!ret && slave != dev->caps.function) { 503 mlx4_slave_event(dev, slave, eqe); 504 break; 505 } 506 507 } 508 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 509 0xffffff, eqe->type); 510 break; 511 512 case MLX4_EVENT_TYPE_SRQ_LIMIT: 513 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 514 __func__); 515 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 516 if (mlx4_is_master(dev)) { 517 /* forward only to slave owning the SRQ */ 518 ret = mlx4_get_slave_from_resource_id(dev, 519 RES_SRQ, 520 be32_to_cpu(eqe->event.srq.srqn) 521 & 0xffffff, 522 &slave); 523 if (ret && ret != -ENOENT) { 524 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 525 eqe->type, eqe->subtype, 526 eq->eqn, eq->cons_index, ret); 527 break; 528 } 529 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 530 __func__, slave, 531 be32_to_cpu(eqe->event.srq.srqn), 532 eqe->type, eqe->subtype); 533 534 if (!ret && slave != dev->caps.function) { 535 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 536 __func__, eqe->type, 537 eqe->subtype, slave); 538 mlx4_slave_event(dev, slave, eqe); 539 break; 540 } 541 } 542 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 543 0xffffff, eqe->type); 544 break; 545 546 case MLX4_EVENT_TYPE_CMD: 547 mlx4_cmd_event(dev, 548 be16_to_cpu(eqe->event.cmd.token), 549 eqe->event.cmd.status, 550 be64_to_cpu(eqe->event.cmd.out_param)); 551 break; 552 553 case MLX4_EVENT_TYPE_PORT_CHANGE: { 554 struct mlx4_slaves_pport slaves_port; 555 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 556 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 557 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 558 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 559 port); 560 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 561 if (!mlx4_is_master(dev)) 562 break; 563 for (i = 0; i < dev->num_vfs + 1; i++) { 564 if (!test_bit(i, slaves_port.slaves)) 565 continue; 566 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 567 if (i == mlx4_master_func_num(dev)) 568 continue; 569 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 570 __func__, i, port); 571 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 572 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 573 eqe->event.port_change.port = 574 cpu_to_be32( 575 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 576 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 577 mlx4_slave_event(dev, i, eqe); 578 } 579 } else { /* IB port */ 580 set_and_calc_slave_port_state(dev, i, port, 581 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 582 &gen_event); 583 /*we can be in pending state, then do not send port_down event*/ 584 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 585 if (i == mlx4_master_func_num(dev)) 586 continue; 587 mlx4_slave_event(dev, i, eqe); 588 } 589 } 590 } 591 } else { 592 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 593 594 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 595 596 if (!mlx4_is_master(dev)) 597 break; 598 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 599 for (i = 0; i < dev->num_vfs + 1; i++) { 600 if (!test_bit(i, slaves_port.slaves)) 601 continue; 602 if (i == mlx4_master_func_num(dev)) 603 continue; 604 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; 605 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { 606 eqe->event.port_change.port = 607 cpu_to_be32( 608 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 609 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 610 mlx4_slave_event(dev, i, eqe); 611 } 612 } 613 else /* IB port */ 614 /* port-up event will be sent to a slave when the 615 * slave's alias-guid is set. This is done in alias_GUID.c 616 */ 617 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 618 } 619 break; 620 } 621 622 case MLX4_EVENT_TYPE_CQ_ERROR: 623 mlx4_warn(dev, "CQ %s on CQN %06x\n", 624 eqe->event.cq_err.syndrome == 1 ? 625 "overrun" : "access violation", 626 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 627 if (mlx4_is_master(dev)) { 628 ret = mlx4_get_slave_from_resource_id(dev, 629 RES_CQ, 630 be32_to_cpu(eqe->event.cq_err.cqn) 631 & 0xffffff, &slave); 632 if (ret && ret != -ENOENT) { 633 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 634 eqe->type, eqe->subtype, 635 eq->eqn, eq->cons_index, ret); 636 break; 637 } 638 639 if (!ret && slave != dev->caps.function) { 640 mlx4_slave_event(dev, slave, eqe); 641 break; 642 } 643 } 644 mlx4_cq_event(dev, 645 be32_to_cpu(eqe->event.cq_err.cqn) 646 & 0xffffff, 647 eqe->type); 648 break; 649 650 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 651 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 652 break; 653 654 case MLX4_EVENT_TYPE_OP_REQUIRED: 655 atomic_inc(&priv->opreq_count); 656 /* FW commands can't be executed from interrupt context 657 * working in deferred task 658 */ 659 queue_work(mlx4_wq, &priv->opreq_task); 660 break; 661 662 case MLX4_EVENT_TYPE_COMM_CHANNEL: 663 if (!mlx4_is_master(dev)) { 664 mlx4_warn(dev, "Received comm channel event for non master device\n"); 665 break; 666 } 667 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 668 eqe->event.comm_channel_arm.bit_vec, 669 sizeof eqe->event.comm_channel_arm.bit_vec); 670 queue_work(priv->mfunc.master.comm_wq, 671 &priv->mfunc.master.comm_work); 672 break; 673 674 case MLX4_EVENT_TYPE_FLR_EVENT: 675 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 676 if (!mlx4_is_master(dev)) { 677 mlx4_warn(dev, "Non-master function received FLR event\n"); 678 break; 679 } 680 681 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 682 683 if (flr_slave >= dev->num_slaves) { 684 mlx4_warn(dev, 685 "Got FLR for unknown function: %d\n", 686 flr_slave); 687 update_slave_state = 0; 688 } else 689 update_slave_state = 1; 690 691 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 692 if (update_slave_state) { 693 priv->mfunc.master.slave_state[flr_slave].active = false; 694 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 695 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 696 } 697 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 698 queue_work(priv->mfunc.master.comm_wq, 699 &priv->mfunc.master.slave_flr_event_work); 700 break; 701 702 case MLX4_EVENT_TYPE_FATAL_WARNING: 703 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 704 if (mlx4_is_master(dev)) 705 for (i = 0; i < dev->num_slaves; i++) { 706 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 707 __func__, i); 708 if (i == dev->caps.function) 709 continue; 710 mlx4_slave_event(dev, i, eqe); 711 } 712 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 713 be16_to_cpu(eqe->event.warming.warning_threshold), 714 be16_to_cpu(eqe->event.warming.current_temperature)); 715 } else 716 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 717 eqe->type, eqe->subtype, eq->eqn, 718 eq->cons_index, eqe->owner, eq->nent, 719 eqe->slave_id, 720 !!(eqe->owner & 0x80) ^ 721 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 722 723 break; 724 725 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 726 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 727 (unsigned long) eqe); 728 break; 729 730 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 731 case MLX4_EVENT_TYPE_ECC_DETECT: 732 default: 733 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 734 eqe->type, eqe->subtype, eq->eqn, 735 eq->cons_index, eqe->owner, eq->nent, 736 eqe->slave_id, 737 !!(eqe->owner & 0x80) ^ 738 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 739 break; 740 }; 741 742 ++eq->cons_index; 743 eqes_found = 1; 744 ++set_ci; 745 746 /* 747 * The HCA will think the queue has overflowed if we 748 * don't tell it we've been processing events. We 749 * create our EQs with MLX4_NUM_SPARE_EQE extra 750 * entries, so we must update our consumer index at 751 * least that often. 752 */ 753 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 754 eq_set_ci(eq, 0); 755 set_ci = 0; 756 } 757 } 758 759 eq_set_ci(eq, 1); 760 761 return eqes_found; 762} 763 764static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 765{ 766 struct mlx4_dev *dev = dev_ptr; 767 struct mlx4_priv *priv = mlx4_priv(dev); 768 int work = 0; 769 int i; 770 771 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 772 773 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 774 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 775 776 return IRQ_RETVAL(work); 777} 778 779static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 780{ 781 struct mlx4_eq *eq = eq_ptr; 782 struct mlx4_dev *dev = eq->dev; 783 784 mlx4_eq_int(dev, eq); 785 786 /* MSI-X vectors always belong to us */ 787 return IRQ_HANDLED; 788} 789 790int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 791 struct mlx4_vhcr *vhcr, 792 struct mlx4_cmd_mailbox *inbox, 793 struct mlx4_cmd_mailbox *outbox, 794 struct mlx4_cmd_info *cmd) 795{ 796 struct mlx4_priv *priv = mlx4_priv(dev); 797 struct mlx4_slave_event_eq_info *event_eq = 798 priv->mfunc.master.slave_state[slave].event_eq; 799 u32 in_modifier = vhcr->in_modifier; 800 u32 eqn = in_modifier & 0x3FF; 801 u64 in_param = vhcr->in_param; 802 int err = 0; 803 int i; 804 805 if (slave == dev->caps.function) 806 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 807 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 808 MLX4_CMD_NATIVE); 809 if (!err) 810 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 811 if (in_param & (1LL << i)) 812 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 813 814 return err; 815} 816 817static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 818 int eq_num) 819{ 820 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 821 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 822 MLX4_CMD_WRAPPED); 823} 824 825static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 826 int eq_num) 827{ 828 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 829 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 830 MLX4_CMD_WRAPPED); 831} 832 833static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 834 int eq_num) 835{ 836 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 837 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A, 838 MLX4_CMD_WRAPPED); 839} 840 841static int mlx4_num_eq_uar(struct mlx4_dev *dev) 842{ 843 /* 844 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 845 * we need to map, take the difference of highest index and 846 * the lowest index we'll use and add 1. 847 */ 848 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs + 849 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1; 850} 851 852static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 853{ 854 struct mlx4_priv *priv = mlx4_priv(dev); 855 int index; 856 857 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 858 859 if (!priv->eq_table.uar_map[index]) { 860 priv->eq_table.uar_map[index] = 861 ioremap(pci_resource_start(dev->pdev, 2) + 862 ((eq->eqn / 4) << PAGE_SHIFT), 863 PAGE_SIZE); 864 if (!priv->eq_table.uar_map[index]) { 865 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 866 eq->eqn); 867 return NULL; 868 } 869 } 870 871 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 872} 873 874static void mlx4_unmap_uar(struct mlx4_dev *dev) 875{ 876 struct mlx4_priv *priv = mlx4_priv(dev); 877 int i; 878 879 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 880 if (priv->eq_table.uar_map[i]) { 881 iounmap(priv->eq_table.uar_map[i]); 882 priv->eq_table.uar_map[i] = NULL; 883 } 884} 885 886static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 887 u8 intr, struct mlx4_eq *eq) 888{ 889 struct mlx4_priv *priv = mlx4_priv(dev); 890 struct mlx4_cmd_mailbox *mailbox; 891 struct mlx4_eq_context *eq_context; 892 int npages; 893 u64 *dma_list = NULL; 894 dma_addr_t t; 895 u64 mtt_addr; 896 int err = -ENOMEM; 897 int i; 898 899 eq->dev = dev; 900 eq->nent = roundup_pow_of_two(max(nent, 2)); 901 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 902 * strides of 64B,128B and 256B. 903 */ 904 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; 905 906 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 907 GFP_KERNEL); 908 if (!eq->page_list) 909 goto err_out; 910 911 for (i = 0; i < npages; ++i) 912 eq->page_list[i].buf = NULL; 913 914 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 915 if (!dma_list) 916 goto err_out_free; 917 918 mailbox = mlx4_alloc_cmd_mailbox(dev); 919 if (IS_ERR(mailbox)) 920 goto err_out_free; 921 eq_context = mailbox->buf; 922 923 for (i = 0; i < npages; ++i) { 924 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 925 PAGE_SIZE, &t, GFP_KERNEL); 926 if (!eq->page_list[i].buf) 927 goto err_out_free_pages; 928 929 dma_list[i] = t; 930 eq->page_list[i].map = t; 931 932 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 933 } 934 935 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 936 if (eq->eqn == -1) 937 goto err_out_free_pages; 938 939 eq->doorbell = mlx4_get_eq_uar(dev, eq); 940 if (!eq->doorbell) { 941 err = -ENOMEM; 942 goto err_out_free_eq; 943 } 944 945 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 946 if (err) 947 goto err_out_free_eq; 948 949 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 950 if (err) 951 goto err_out_free_mtt; 952 953 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 954 MLX4_EQ_STATE_ARMED); 955 eq_context->log_eq_size = ilog2(eq->nent); 956 eq_context->intr = intr; 957 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 958 959 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 960 eq_context->mtt_base_addr_h = mtt_addr >> 32; 961 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 962 963 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 964 if (err) { 965 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 966 goto err_out_free_mtt; 967 } 968 969 kfree(dma_list); 970 mlx4_free_cmd_mailbox(dev, mailbox); 971 972 eq->cons_index = 0; 973 974 return err; 975 976err_out_free_mtt: 977 mlx4_mtt_cleanup(dev, &eq->mtt); 978 979err_out_free_eq: 980 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 981 982err_out_free_pages: 983 for (i = 0; i < npages; ++i) 984 if (eq->page_list[i].buf) 985 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 986 eq->page_list[i].buf, 987 eq->page_list[i].map); 988 989 mlx4_free_cmd_mailbox(dev, mailbox); 990 991err_out_free: 992 kfree(eq->page_list); 993 kfree(dma_list); 994 995err_out: 996 return err; 997} 998 999static void mlx4_free_eq(struct mlx4_dev *dev, 1000 struct mlx4_eq *eq) 1001{ 1002 struct mlx4_priv *priv = mlx4_priv(dev); 1003 struct mlx4_cmd_mailbox *mailbox; 1004 int err; 1005 int i; 1006 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 1007 * strides of 64B,128B and 256B 1008 */ 1009 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; 1010 1011 mailbox = mlx4_alloc_cmd_mailbox(dev); 1012 if (IS_ERR(mailbox)) 1013 return; 1014 1015 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn); 1016 if (err) 1017 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1018 1019 if (0) { 1020 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 1021 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) { 1022 if (i % 4 == 0) 1023 pr_cont("[%02x] ", i * 4); 1024 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 1025 if ((i + 1) % 4 == 0) 1026 pr_cont("\n"); 1027 } 1028 } 1029 synchronize_irq(eq->irq); 1030 1031 mlx4_mtt_cleanup(dev, &eq->mtt); 1032 for (i = 0; i < npages; ++i) 1033 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 1034 eq->page_list[i].buf, 1035 eq->page_list[i].map); 1036 1037 kfree(eq->page_list); 1038 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1039 mlx4_free_cmd_mailbox(dev, mailbox); 1040} 1041 1042static void mlx4_free_irqs(struct mlx4_dev *dev) 1043{ 1044 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1045 struct mlx4_priv *priv = mlx4_priv(dev); 1046 int i, vec; 1047 1048 if (eq_table->have_irq) 1049 free_irq(dev->pdev->irq, dev); 1050 1051 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1052 if (eq_table->eq[i].have_irq) { 1053 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1054 eq_table->eq[i].have_irq = 0; 1055 } 1056 1057 for (i = 0; i < dev->caps.comp_pool; i++) { 1058 /* 1059 * Freeing the assigned irq's 1060 * all bits should be 0, but we need to validate 1061 */ 1062 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1063 /* NO need protecting*/ 1064 vec = dev->caps.num_comp_vectors + 1 + i; 1065 free_irq(priv->eq_table.eq[vec].irq, 1066 &priv->eq_table.eq[vec]); 1067 } 1068 } 1069 1070 1071 kfree(eq_table->irq_names); 1072} 1073 1074static int mlx4_map_clr_int(struct mlx4_dev *dev) 1075{ 1076 struct mlx4_priv *priv = mlx4_priv(dev); 1077 1078 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) + 1079 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1080 if (!priv->clr_base) { 1081 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1082 return -ENOMEM; 1083 } 1084 1085 return 0; 1086} 1087 1088static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1089{ 1090 struct mlx4_priv *priv = mlx4_priv(dev); 1091 1092 iounmap(priv->clr_base); 1093} 1094 1095int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1096{ 1097 struct mlx4_priv *priv = mlx4_priv(dev); 1098 1099 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1100 sizeof *priv->eq_table.eq, GFP_KERNEL); 1101 if (!priv->eq_table.eq) 1102 return -ENOMEM; 1103 1104 return 0; 1105} 1106 1107void mlx4_free_eq_table(struct mlx4_dev *dev) 1108{ 1109 kfree(mlx4_priv(dev)->eq_table.eq); 1110} 1111 1112int mlx4_init_eq_table(struct mlx4_dev *dev) 1113{ 1114 struct mlx4_priv *priv = mlx4_priv(dev); 1115 int err; 1116 int i; 1117 1118 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1119 sizeof *priv->eq_table.uar_map, 1120 GFP_KERNEL); 1121 if (!priv->eq_table.uar_map) { 1122 err = -ENOMEM; 1123 goto err_out_free; 1124 } 1125 1126 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs, 1127 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0); 1128 if (err) 1129 goto err_out_free; 1130 1131 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1132 priv->eq_table.uar_map[i] = NULL; 1133 1134 if (!mlx4_is_slave(dev)) { 1135 err = mlx4_map_clr_int(dev); 1136 if (err) 1137 goto err_out_bitmap; 1138 1139 priv->eq_table.clr_mask = 1140 swab32(1 << (priv->eq_table.inta_pin & 31)); 1141 priv->eq_table.clr_int = priv->clr_base + 1142 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1143 } 1144 1145 priv->eq_table.irq_names = 1146 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 + 1147 dev->caps.comp_pool), 1148 GFP_KERNEL); 1149 if (!priv->eq_table.irq_names) { 1150 err = -ENOMEM; 1151 goto err_out_bitmap; 1152 } 1153 1154 for (i = 0; i < dev->caps.num_comp_vectors; ++i) { 1155 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1156 dev->caps.reserved_cqs + 1157 MLX4_NUM_SPARE_EQE, 1158 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1159 &priv->eq_table.eq[i]); 1160 if (err) { 1161 --i; 1162 goto err_out_unmap; 1163 } 1164 } 1165 1166 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1167 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0, 1168 &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1169 if (err) 1170 goto err_out_comp; 1171 1172 /*if additional completion vectors poolsize is 0 this loop will not run*/ 1173 for (i = dev->caps.num_comp_vectors + 1; 1174 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) { 1175 1176 err = mlx4_create_eq(dev, dev->caps.num_cqs - 1177 dev->caps.reserved_cqs + 1178 MLX4_NUM_SPARE_EQE, 1179 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0, 1180 &priv->eq_table.eq[i]); 1181 if (err) { 1182 --i; 1183 goto err_out_unmap; 1184 } 1185 } 1186 1187 1188 if (dev->flags & MLX4_FLAG_MSI_X) { 1189 const char *eq_name; 1190 1191 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1192 if (i < dev->caps.num_comp_vectors) { 1193 snprintf(priv->eq_table.irq_names + 1194 i * MLX4_IRQNAME_SIZE, 1195 MLX4_IRQNAME_SIZE, 1196 "mlx4-comp-%d@pci:%s", i, 1197 pci_name(dev->pdev)); 1198 } else { 1199 snprintf(priv->eq_table.irq_names + 1200 i * MLX4_IRQNAME_SIZE, 1201 MLX4_IRQNAME_SIZE, 1202 "mlx4-async@pci:%s", 1203 pci_name(dev->pdev)); 1204 } 1205 1206 eq_name = priv->eq_table.irq_names + 1207 i * MLX4_IRQNAME_SIZE; 1208 err = request_irq(priv->eq_table.eq[i].irq, 1209 mlx4_msi_x_interrupt, 0, eq_name, 1210 priv->eq_table.eq + i); 1211 if (err) 1212 goto err_out_async; 1213 1214 priv->eq_table.eq[i].have_irq = 1; 1215 } 1216 } else { 1217 snprintf(priv->eq_table.irq_names, 1218 MLX4_IRQNAME_SIZE, 1219 DRV_NAME "@pci:%s", 1220 pci_name(dev->pdev)); 1221 err = request_irq(dev->pdev->irq, mlx4_interrupt, 1222 IRQF_SHARED, priv->eq_table.irq_names, dev); 1223 if (err) 1224 goto err_out_async; 1225 1226 priv->eq_table.have_irq = 1; 1227 } 1228 1229 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1230 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1231 if (err) 1232 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1233 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err); 1234 1235 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1236 eq_set_ci(&priv->eq_table.eq[i], 1); 1237 1238 return 0; 1239 1240err_out_async: 1241 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]); 1242 1243err_out_comp: 1244 i = dev->caps.num_comp_vectors - 1; 1245 1246err_out_unmap: 1247 while (i >= 0) { 1248 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1249 --i; 1250 } 1251 if (!mlx4_is_slave(dev)) 1252 mlx4_unmap_clr_int(dev); 1253 mlx4_free_irqs(dev); 1254 1255err_out_bitmap: 1256 mlx4_unmap_uar(dev); 1257 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1258 1259err_out_free: 1260 kfree(priv->eq_table.uar_map); 1261 1262 return err; 1263} 1264 1265void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1266{ 1267 struct mlx4_priv *priv = mlx4_priv(dev); 1268 int i; 1269 1270 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1271 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1272 1273 mlx4_free_irqs(dev); 1274 1275 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) 1276 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1277 1278 if (!mlx4_is_slave(dev)) 1279 mlx4_unmap_clr_int(dev); 1280 1281 mlx4_unmap_uar(dev); 1282 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1283 1284 kfree(priv->eq_table.uar_map); 1285} 1286 1287/* A test that verifies that we can accept interrupts on all 1288 * the irq vectors of the device. 1289 * Interrupts are checked using the NOP command. 1290 */ 1291int mlx4_test_interrupts(struct mlx4_dev *dev) 1292{ 1293 struct mlx4_priv *priv = mlx4_priv(dev); 1294 int i; 1295 int err; 1296 1297 err = mlx4_NOP(dev); 1298 /* When not in MSI_X, there is only one irq to check */ 1299 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) 1300 return err; 1301 1302 /* A loop over all completion vectors, for each vector we will check 1303 * whether it works by mapping command completions to that vector 1304 * and performing a NOP command 1305 */ 1306 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { 1307 /* Temporary use polling for command completions */ 1308 mlx4_cmd_use_polling(dev); 1309 1310 /* Map the new eq to handle all asynchronous events */ 1311 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1312 priv->eq_table.eq[i].eqn); 1313 if (err) { 1314 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1315 mlx4_cmd_use_events(dev); 1316 break; 1317 } 1318 1319 /* Go back to using events */ 1320 mlx4_cmd_use_events(dev); 1321 err = mlx4_NOP(dev); 1322 } 1323 1324 /* Return to default */ 1325 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1326 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn); 1327 return err; 1328} 1329EXPORT_SYMBOL(mlx4_test_interrupts); 1330 1331int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, 1332 int *vector) 1333{ 1334 1335 struct mlx4_priv *priv = mlx4_priv(dev); 1336 int vec = 0, err = 0, i; 1337 1338 mutex_lock(&priv->msix_ctl.pool_lock); 1339 for (i = 0; !vec && i < dev->caps.comp_pool; i++) { 1340 if (~priv->msix_ctl.pool_bm & 1ULL << i) { 1341 priv->msix_ctl.pool_bm |= 1ULL << i; 1342 vec = dev->caps.num_comp_vectors + 1 + i; 1343 snprintf(priv->eq_table.irq_names + 1344 vec * MLX4_IRQNAME_SIZE, 1345 MLX4_IRQNAME_SIZE, "%s", name); 1346#ifdef CONFIG_RFS_ACCEL 1347 if (rmap) { 1348 err = irq_cpu_rmap_add(rmap, 1349 priv->eq_table.eq[vec].irq); 1350 if (err) 1351 mlx4_warn(dev, "Failed adding irq rmap\n"); 1352 } 1353#endif 1354 err = request_irq(priv->eq_table.eq[vec].irq, 1355 mlx4_msi_x_interrupt, 0, 1356 &priv->eq_table.irq_names[vec<<5], 1357 priv->eq_table.eq + vec); 1358 if (err) { 1359 /*zero out bit by fliping it*/ 1360 priv->msix_ctl.pool_bm ^= 1 << i; 1361 vec = 0; 1362 continue; 1363 /*we dont want to break here*/ 1364 } 1365 1366 eq_set_ci(&priv->eq_table.eq[vec], 1); 1367 } 1368 } 1369 mutex_unlock(&priv->msix_ctl.pool_lock); 1370 1371 if (vec) { 1372 *vector = vec; 1373 } else { 1374 *vector = 0; 1375 err = (i == dev->caps.comp_pool) ? -ENOSPC : err; 1376 } 1377 return err; 1378} 1379EXPORT_SYMBOL(mlx4_assign_eq); 1380 1381int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec) 1382{ 1383 struct mlx4_priv *priv = mlx4_priv(dev); 1384 1385 return priv->eq_table.eq[vec].irq; 1386} 1387EXPORT_SYMBOL(mlx4_eq_get_irq); 1388 1389void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1390{ 1391 struct mlx4_priv *priv = mlx4_priv(dev); 1392 /*bm index*/ 1393 int i = vec - dev->caps.num_comp_vectors - 1; 1394 1395 if (likely(i >= 0)) { 1396 /*sanity check , making sure were not trying to free irq's 1397 Belonging to a legacy EQ*/ 1398 mutex_lock(&priv->msix_ctl.pool_lock); 1399 if (priv->msix_ctl.pool_bm & 1ULL << i) { 1400 free_irq(priv->eq_table.eq[vec].irq, 1401 &priv->eq_table.eq[vec]); 1402 priv->msix_ctl.pool_bm &= ~(1ULL << i); 1403 } 1404 mutex_unlock(&priv->msix_ctl.pool_lock); 1405 } 1406 1407} 1408EXPORT_SYMBOL(mlx4_release_eq); 1409 1410