1/* 2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved. 3 * 4 * Derived from Intel e1000 driver 5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the Free 9 * Software Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program; if not, write to the Free Software Foundation, Inc., 59 19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#ifndef _ATL1C_H_ 23#define _ATL1C_H_ 24 25#include <linux/interrupt.h> 26#include <linux/types.h> 27#include <linux/errno.h> 28#include <linux/module.h> 29#include <linux/pci.h> 30#include <linux/netdevice.h> 31#include <linux/etherdevice.h> 32#include <linux/skbuff.h> 33#include <linux/ioport.h> 34#include <linux/slab.h> 35#include <linux/list.h> 36#include <linux/delay.h> 37#include <linux/sched.h> 38#include <linux/in.h> 39#include <linux/ip.h> 40#include <linux/ipv6.h> 41#include <linux/udp.h> 42#include <linux/mii.h> 43#include <linux/io.h> 44#include <linux/vmalloc.h> 45#include <linux/pagemap.h> 46#include <linux/tcp.h> 47#include <linux/ethtool.h> 48#include <linux/if_vlan.h> 49#include <linux/workqueue.h> 50#include <net/checksum.h> 51#include <net/ip6_checksum.h> 52 53#include "atl1c_hw.h" 54 55/* Wake Up Filter Control */ 56#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 57#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 58#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 59#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ 60#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 61 62#define AT_VLAN_TO_TAG(_vlan, _tag) \ 63 _tag = ((((_vlan) >> 8) & 0xFF) |\ 64 (((_vlan) & 0xFF) << 8)) 65 66#define AT_TAG_TO_VLAN(_tag, _vlan) \ 67 _vlan = ((((_tag) >> 8) & 0xFF) |\ 68 (((_tag) & 0xFF) << 8)) 69 70#define SPEED_0 0xffff 71#define HALF_DUPLEX 1 72#define FULL_DUPLEX 2 73 74#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN) 75#define MAX_JUMBO_FRAME_SIZE (6*1024) 76 77#define AT_MAX_RECEIVE_QUEUE 4 78#define AT_DEF_RECEIVE_QUEUE 1 79#define AT_MAX_TRANSMIT_QUEUE 2 80 81#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL 82#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL 83 84#define AT_TX_WATCHDOG (5 * HZ) 85#define AT_MAX_INT_WORK 5 86#define AT_TWSI_EEPROM_TIMEOUT 100 87#define AT_HW_MAX_IDLE_DELAY 10 88#define AT_SUSPEND_LINK_TIMEOUT 100 89 90#define AT_ASPM_L0S_TIMER 6 91#define AT_ASPM_L1_TIMER 12 92#define AT_LCKDET_TIMER 12 93 94#define ATL1C_PCIE_L0S_L1_DISABLE 0x01 95#define ATL1C_PCIE_PHY_RESET 0x02 96 97#define ATL1C_ASPM_L0s_ENABLE 0x0001 98#define ATL1C_ASPM_L1_ENABLE 0x0002 99 100#define AT_REGS_LEN (74 * sizeof(u32)) 101#define AT_EEPROM_LEN 512 102 103#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) 104#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) 105#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) 106#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) 107 108/* tpd word 1 bit 0:7 General Checksum task offload */ 109#define TPD_L4HDR_OFFSET_MASK 0x00FF 110#define TPD_L4HDR_OFFSET_SHIFT 0 111 112/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */ 113#define TPD_TCPHDR_OFFSET_MASK 0x00FF 114#define TPD_TCPHDR_OFFSET_SHIFT 0 115 116/* tpd word 1 bit 0:7 Custom Checksum task offload */ 117#define TPD_PLOADOFFSET_MASK 0x00FF 118#define TPD_PLOADOFFSET_SHIFT 0 119 120/* tpd word 1 bit 8:17 */ 121#define TPD_CCSUM_EN_MASK 0x0001 122#define TPD_CCSUM_EN_SHIFT 8 123#define TPD_IP_CSUM_MASK 0x0001 124#define TPD_IP_CSUM_SHIFT 9 125#define TPD_TCP_CSUM_MASK 0x0001 126#define TPD_TCP_CSUM_SHIFT 10 127#define TPD_UDP_CSUM_MASK 0x0001 128#define TPD_UDP_CSUM_SHIFT 11 129#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */ 130#define TPD_LSO_EN_SHIFT 12 131#define TPD_LSO_VER_MASK 0x0001 132#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */ 133#define TPD_CON_VTAG_MASK 0x0001 134#define TPD_CON_VTAG_SHIFT 14 135#define TPD_INS_VTAG_MASK 0x0001 136#define TPD_INS_VTAG_SHIFT 15 137#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */ 138#define TPD_IPV4_PACKET_SHIFT 16 139#define TPD_ETH_TYPE_MASK 0x0001 140#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */ 141 142/* tpd word 18:25 Custom Checksum task offload */ 143#define TPD_CCSUM_OFFSET_MASK 0x00FF 144#define TPD_CCSUM_OFFSET_SHIFT 18 145#define TPD_CCSUM_EPAD_MASK 0x0001 146#define TPD_CCSUM_EPAD_SHIFT 30 147 148/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */ 149#define TPD_MSS_MASK 0x1FFF 150#define TPD_MSS_SHIFT 18 151 152#define TPD_EOP_MASK 0x0001 153#define TPD_EOP_SHIFT 31 154 155struct atl1c_tpd_desc { 156 __le16 buffer_len; /* include 4-byte CRC */ 157 __le16 vlan_tag; 158 __le32 word1; 159 __le64 buffer_addr; 160}; 161 162struct atl1c_tpd_ext_desc { 163 u32 reservd_0; 164 __le32 word1; 165 __le32 pkt_len; 166 u32 reservd_1; 167}; 168/* rrs word 0 bit 0:31 */ 169#define RRS_RX_CSUM_MASK 0xFFFF 170#define RRS_RX_CSUM_SHIFT 0 171#define RRS_RX_RFD_CNT_MASK 0x000F 172#define RRS_RX_RFD_CNT_SHIFT 16 173#define RRS_RX_RFD_INDEX_MASK 0x0FFF 174#define RRS_RX_RFD_INDEX_SHIFT 20 175 176/* rrs flag bit 0:16 */ 177#define RRS_HEAD_LEN_MASK 0x00FF 178#define RRS_HEAD_LEN_SHIFT 0 179#define RRS_HDS_TYPE_MASK 0x0003 180#define RRS_HDS_TYPE_SHIFT 8 181#define RRS_CPU_NUM_MASK 0x0003 182#define RRS_CPU_NUM_SHIFT 10 183#define RRS_HASH_FLG_MASK 0x000F 184#define RRS_HASH_FLG_SHIFT 12 185 186#define RRS_HDS_TYPE_HEAD 1 187#define RRS_HDS_TYPE_DATA 2 188 189#define RRS_IS_NO_HDS_TYPE(flag) \ 190 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0) 191 192#define RRS_IS_HDS_HEAD(flag) \ 193 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 194 RRS_HDS_TYPE_HEAD) 195 196#define RRS_IS_HDS_DATA(flag) \ 197 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \ 198 RRS_HDS_TYPE_DATA) 199 200/* rrs word 3 bit 0:31 */ 201#define RRS_PKT_SIZE_MASK 0x3FFF 202#define RRS_PKT_SIZE_SHIFT 0 203#define RRS_ERR_L4_CSUM_MASK 0x0001 204#define RRS_ERR_L4_CSUM_SHIFT 14 205#define RRS_ERR_IP_CSUM_MASK 0x0001 206#define RRS_ERR_IP_CSUM_SHIFT 15 207#define RRS_VLAN_INS_MASK 0x0001 208#define RRS_VLAN_INS_SHIFT 16 209#define RRS_PROT_ID_MASK 0x0007 210#define RRS_PROT_ID_SHIFT 17 211#define RRS_RX_ERR_SUM_MASK 0x0001 212#define RRS_RX_ERR_SUM_SHIFT 20 213#define RRS_RX_ERR_CRC_MASK 0x0001 214#define RRS_RX_ERR_CRC_SHIFT 21 215#define RRS_RX_ERR_FAE_MASK 0x0001 216#define RRS_RX_ERR_FAE_SHIFT 22 217#define RRS_RX_ERR_TRUNC_MASK 0x0001 218#define RRS_RX_ERR_TRUNC_SHIFT 23 219#define RRS_RX_ERR_RUNC_MASK 0x0001 220#define RRS_RX_ERR_RUNC_SHIFT 24 221#define RRS_RX_ERR_ICMP_MASK 0x0001 222#define RRS_RX_ERR_ICMP_SHIFT 25 223#define RRS_PACKET_BCAST_MASK 0x0001 224#define RRS_PACKET_BCAST_SHIFT 26 225#define RRS_PACKET_MCAST_MASK 0x0001 226#define RRS_PACKET_MCAST_SHIFT 27 227#define RRS_PACKET_TYPE_MASK 0x0001 228#define RRS_PACKET_TYPE_SHIFT 28 229#define RRS_FIFO_FULL_MASK 0x0001 230#define RRS_FIFO_FULL_SHIFT 29 231#define RRS_802_3_LEN_ERR_MASK 0x0001 232#define RRS_802_3_LEN_ERR_SHIFT 30 233#define RRS_RXD_UPDATED_MASK 0x0001 234#define RRS_RXD_UPDATED_SHIFT 31 235 236#define RRS_ERR_L4_CSUM 0x00004000 237#define RRS_ERR_IP_CSUM 0x00008000 238#define RRS_VLAN_INS 0x00010000 239#define RRS_RX_ERR_SUM 0x00100000 240#define RRS_RX_ERR_CRC 0x00200000 241#define RRS_802_3_LEN_ERR 0x40000000 242#define RRS_RXD_UPDATED 0x80000000 243 244#define RRS_PACKET_TYPE_802_3 1 245#define RRS_PACKET_TYPE_ETH 0 246#define RRS_PACKET_IS_ETH(word) \ 247 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \ 248 RRS_PACKET_TYPE_ETH) 249#define RRS_RXD_IS_VALID(word) \ 250 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1) 251 252#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \ 253 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1) 254#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \ 255 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6) 256 257struct atl1c_recv_ret_status { 258 __le32 word0; 259 __le32 rss_hash; 260 __le16 vlan_tag; 261 __le16 flag; 262 __le32 word3; 263}; 264 265/* RFD descriptor */ 266struct atl1c_rx_free_desc { 267 __le64 buffer_addr; 268}; 269 270/* DMA Order Settings */ 271enum atl1c_dma_order { 272 atl1c_dma_ord_in = 1, 273 atl1c_dma_ord_enh = 2, 274 atl1c_dma_ord_out = 4 275}; 276 277enum atl1c_dma_rcb { 278 atl1c_rcb_64 = 0, 279 atl1c_rcb_128 = 1 280}; 281 282enum atl1c_mac_speed { 283 atl1c_mac_speed_0 = 0, 284 atl1c_mac_speed_10_100 = 1, 285 atl1c_mac_speed_1000 = 2 286}; 287 288enum atl1c_dma_req_block { 289 atl1c_dma_req_128 = 0, 290 atl1c_dma_req_256 = 1, 291 atl1c_dma_req_512 = 2, 292 atl1c_dma_req_1024 = 3, 293 atl1c_dma_req_2048 = 4, 294 atl1c_dma_req_4096 = 5 295}; 296 297 298enum atl1c_nic_type { 299 athr_l1c = 0, 300 athr_l2c = 1, 301 athr_l2c_b, 302 athr_l2c_b2, 303 athr_l1d, 304 athr_l1d_2, 305}; 306 307enum atl1c_trans_queue { 308 atl1c_trans_normal = 0, 309 atl1c_trans_high = 1 310}; 311 312struct atl1c_hw_stats { 313 /* rx */ 314 unsigned long rx_ok; /* The number of good packet received. */ 315 unsigned long rx_bcast; /* The number of good broadcast packet received. */ 316 unsigned long rx_mcast; /* The number of good multicast packet received. */ 317 unsigned long rx_pause; /* The number of Pause packet received. */ 318 unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */ 319 unsigned long rx_fcs_err; /* The number of packets with bad FCS. */ 320 unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */ 321 unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */ 322 unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */ 323 unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */ 324 unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */ 325 unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */ 326 unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */ 327 unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */ 328 unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */ 329 unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */ 330 unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */ 331 unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */ 332 unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */ 333 unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */ 334 unsigned long rx_align_err; /* Alignment Error */ 335 unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */ 336 unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */ 337 unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */ 338 339 /* tx */ 340 unsigned long tx_ok; /* The number of good packet transmitted. */ 341 unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */ 342 unsigned long tx_mcast; /* The number of good multicast packet transmitted. */ 343 unsigned long tx_pause; /* The number of Pause packet transmitted. */ 344 unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */ 345 unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */ 346 unsigned long tx_defer; /* The number of packets transmitted that is deferred. */ 347 unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */ 348 unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */ 349 unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */ 350 unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */ 351 unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */ 352 unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */ 353 unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */ 354 unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */ 355 unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */ 356 unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */ 357 unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */ 358 unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */ 359 unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */ 360 unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */ 361 unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */ 362 unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */ 363 unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */ 364 unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */ 365}; 366 367struct atl1c_hw { 368 u8 __iomem *hw_addr; /* inner register address */ 369 struct atl1c_adapter *adapter; 370 enum atl1c_nic_type nic_type; 371 enum atl1c_dma_order dma_order; 372 enum atl1c_dma_rcb rcb_value; 373 enum atl1c_dma_req_block dmar_block; 374 375 u16 device_id; 376 u16 vendor_id; 377 u16 subsystem_id; 378 u16 subsystem_vendor_id; 379 u8 revision_id; 380 u16 phy_id1; 381 u16 phy_id2; 382 383 u32 intr_mask; 384 385 u8 preamble_len; 386 u16 max_frame_size; 387 u16 min_frame_size; 388 389 enum atl1c_mac_speed mac_speed; 390 bool mac_duplex; 391 bool hibernate; 392 u16 media_type; 393#define MEDIA_TYPE_AUTO_SENSOR 0 394#define MEDIA_TYPE_100M_FULL 1 395#define MEDIA_TYPE_100M_HALF 2 396#define MEDIA_TYPE_10M_FULL 3 397#define MEDIA_TYPE_10M_HALF 4 398 399 u16 autoneg_advertised; 400 u16 mii_autoneg_adv_reg; 401 u16 mii_1000t_ctrl_reg; 402 403 u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */ 404 u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */ 405 u16 ict; /* Interrupt Clear timer (2us resolution) */ 406 u16 ctrl_flags; 407#define ATL1C_INTR_CLEAR_ON_READ 0x0001 408#define ATL1C_INTR_MODRT_ENABLE 0x0002 409#define ATL1C_CMB_ENABLE 0x0004 410#define ATL1C_SMB_ENABLE 0x0010 411#define ATL1C_TXQ_MODE_ENHANCE 0x0020 412#define ATL1C_RX_IPV6_CHKSUM 0x0040 413#define ATL1C_ASPM_L0S_SUPPORT 0x0080 414#define ATL1C_ASPM_L1_SUPPORT 0x0100 415#define ATL1C_ASPM_CTRL_MON 0x0200 416#define ATL1C_HIB_DISABLE 0x0400 417#define ATL1C_APS_MODE_ENABLE 0x0800 418#define ATL1C_LINK_EXT_SYNC 0x1000 419#define ATL1C_CLK_GATING_EN 0x2000 420#define ATL1C_FPGA_VERSION 0x8000 421 u16 link_cap_flags; 422#define ATL1C_LINK_CAP_1000M 0x0001 423 u32 smb_timer; 424 425 u16 rrd_thresh; /* Threshold of number of RRD produced to trigger 426 interrupt request */ 427 u16 tpd_thresh; 428 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */ 429 u8 rfd_burst; 430 u32 base_cpu; 431 u32 indirect_tab; 432 u8 mac_addr[ETH_ALEN]; 433 u8 perm_mac_addr[ETH_ALEN]; 434 435 bool phy_configured; 436 bool re_autoneg; 437 bool emi_ca; 438 bool msi_lnkpatch; /* link patch for specific platforms */ 439}; 440 441/* 442 * atl1c_ring_header represents a single, contiguous block of DMA space 443 * mapped for the three descriptor rings (tpd, rfd, rrd) described below 444 */ 445struct atl1c_ring_header { 446 void *desc; /* virtual address */ 447 dma_addr_t dma; /* physical address*/ 448 unsigned int size; /* length in bytes */ 449}; 450 451/* 452 * atl1c_buffer is wrapper around a pointer to a socket buffer 453 * so a DMA handle can be stored along with the skb 454 */ 455struct atl1c_buffer { 456 struct sk_buff *skb; /* socket buffer */ 457 u16 length; /* rx buffer length */ 458 u16 flags; /* information of buffer */ 459#define ATL1C_BUFFER_FREE 0x0001 460#define ATL1C_BUFFER_BUSY 0x0002 461#define ATL1C_BUFFER_STATE_MASK 0x0003 462 463#define ATL1C_PCIMAP_SINGLE 0x0004 464#define ATL1C_PCIMAP_PAGE 0x0008 465#define ATL1C_PCIMAP_TYPE_MASK 0x000C 466 467#define ATL1C_PCIMAP_TODEVICE 0x0010 468#define ATL1C_PCIMAP_FROMDEVICE 0x0020 469#define ATL1C_PCIMAP_DIRECTION_MASK 0x0030 470 dma_addr_t dma; 471}; 472 473#define ATL1C_SET_BUFFER_STATE(buff, state) do { \ 474 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \ 475 ((buff)->flags) |= (state); \ 476 } while (0) 477 478#define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \ 479 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \ 480 ((buff)->flags) |= (type); \ 481 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \ 482 ((buff)->flags) |= (direction); \ 483 } while (0) 484 485/* transimit packet descriptor (tpd) ring */ 486struct atl1c_tpd_ring { 487 void *desc; /* descriptor ring virtual address */ 488 dma_addr_t dma; /* descriptor ring physical address */ 489 u16 size; /* descriptor ring length in bytes */ 490 u16 count; /* number of descriptors in the ring */ 491 u16 next_to_use; /* this is protectd by adapter->tx_lock */ 492 atomic_t next_to_clean; 493 struct atl1c_buffer *buffer_info; 494}; 495 496/* receive free descriptor (rfd) ring */ 497struct atl1c_rfd_ring { 498 void *desc; /* descriptor ring virtual address */ 499 dma_addr_t dma; /* descriptor ring physical address */ 500 u16 size; /* descriptor ring length in bytes */ 501 u16 count; /* number of descriptors in the ring */ 502 u16 next_to_use; 503 u16 next_to_clean; 504 struct atl1c_buffer *buffer_info; 505}; 506 507/* receive return descriptor (rrd) ring */ 508struct atl1c_rrd_ring { 509 void *desc; /* descriptor ring virtual address */ 510 dma_addr_t dma; /* descriptor ring physical address */ 511 u16 size; /* descriptor ring length in bytes */ 512 u16 count; /* number of descriptors in the ring */ 513 u16 next_to_use; 514 u16 next_to_clean; 515}; 516 517/* board specific private data structure */ 518struct atl1c_adapter { 519 struct net_device *netdev; 520 struct pci_dev *pdev; 521 struct napi_struct napi; 522 struct page *rx_page; 523 unsigned int rx_page_offset; 524 unsigned int rx_frag_size; 525 struct atl1c_hw hw; 526 struct atl1c_hw_stats hw_stats; 527 struct mii_if_info mii; /* MII interface info */ 528 u16 rx_buffer_len; 529 530 unsigned long flags; 531#define __AT_TESTING 0x0001 532#define __AT_RESETTING 0x0002 533#define __AT_DOWN 0x0003 534 unsigned long work_event; 535#define ATL1C_WORK_EVENT_RESET 0 536#define ATL1C_WORK_EVENT_LINK_CHANGE 1 537 u32 msg_enable; 538 539 bool have_msi; 540 u32 wol; 541 u16 link_speed; 542 u16 link_duplex; 543 544 spinlock_t mdio_lock; 545 spinlock_t tx_lock; 546 atomic_t irq_sem; 547 548 struct work_struct common_task; 549 struct timer_list watchdog_timer; 550 struct timer_list phy_config_timer; 551 552 /* All Descriptor memory */ 553 struct atl1c_ring_header ring_header; 554 struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE]; 555 struct atl1c_rfd_ring rfd_ring; 556 struct atl1c_rrd_ring rrd_ring; 557 u32 bd_number; /* board number;*/ 558}; 559 560#define AT_WRITE_REG(a, reg, value) ( \ 561 writel((value), ((a)->hw_addr + reg))) 562 563#define AT_WRITE_FLUSH(a) (\ 564 readl((a)->hw_addr)) 565 566#define AT_READ_REG(a, reg, pdata) do { \ 567 if (unlikely((a)->hibernate)) { \ 568 readl((a)->hw_addr + reg); \ 569 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 570 } else { \ 571 *(u32 *)pdata = readl((a)->hw_addr + reg); \ 572 } \ 573 } while (0) 574 575#define AT_WRITE_REGB(a, reg, value) (\ 576 writeb((value), ((a)->hw_addr + reg))) 577 578#define AT_READ_REGB(a, reg) (\ 579 readb((a)->hw_addr + reg)) 580 581#define AT_WRITE_REGW(a, reg, value) (\ 582 writew((value), ((a)->hw_addr + reg))) 583 584#define AT_READ_REGW(a, reg, pdata) do { \ 585 if (unlikely((a)->hibernate)) { \ 586 readw((a)->hw_addr + reg); \ 587 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 588 } else { \ 589 *(u16 *)pdata = readw((a)->hw_addr + reg); \ 590 } \ 591 } while (0) 592 593#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 594 writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) 595 596#define AT_READ_REG_ARRAY(a, reg, offset) ( \ 597 readl(((a)->hw_addr + reg) + ((offset) << 2))) 598 599extern char atl1c_driver_name[]; 600extern char atl1c_driver_version[]; 601 602void atl1c_reinit_locked(struct atl1c_adapter *adapter); 603s32 atl1c_reset_hw(struct atl1c_hw *hw); 604void atl1c_set_ethtool_ops(struct net_device *netdev); 605#endif /* _ATL1C_H_ */ 606