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1/*
2 * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2003 Advanced Micro Devices
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17
18Module Name:
19
20    amd8111e.h
21
22Abstract:
23
24 	 AMD8111 based 10/100 Ethernet Controller driver definitions.
25
26Environment:
27
28	Kernel Mode
29
30Revision History:
31 	3.0.0
32	   Initial Revision.
33	3.0.1
34*/
35
36#ifndef _AMD811E_H
37#define _AMD811E_H
38
39/* Command style register access
40
41Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register.
42
43eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
44
45*/
46
47/*  Offset for Memory Mapped Registers. */
48/* 32 bit registers */
49
50#define  ASF_STAT		0x00	/* ASF status register */
51#define CHIPID			0x04	/* Chip ID regsiter */
52#define	MIB_DATA		0x10	/* MIB data register */
53#define MIB_ADDR		0x14	/* MIB address register */
54#define STAT0			0x30	/* Status0 register */
55#define INT0			0x38	/* Interrupt0 register */
56#define INTEN0			0x40	/* Interrupt0  enable register*/
57#define CMD0			0x48	/* Command0 register */
58#define CMD2			0x50	/* Command2 register */
59#define CMD3			0x54	/* Command3 resiter */
60#define CMD7			0x64	/* Command7 register */
61
62#define CTRL1 			0x6C	/* Control1 register */
63#define CTRL2 			0x70	/* Control2 register */
64
65#define XMT_RING_LIMIT		0x7C	/* Transmit ring limit register */
66
67#define AUTOPOLL0		0x88	/* Auto-poll0 register */
68#define AUTOPOLL1		0x8A	/* Auto-poll1 register */
69#define AUTOPOLL2		0x8C	/* Auto-poll2 register */
70#define AUTOPOLL3		0x8E	/* Auto-poll3 register */
71#define AUTOPOLL4		0x90	/* Auto-poll4 register */
72#define	AUTOPOLL5		0x92	/* Auto-poll5 register */
73
74#define AP_VALUE		0x98	/* Auto-poll value register */
75#define DLY_INT_A		0xA8	/* Group A delayed interrupt register */
76#define DLY_INT_B		0xAC	/* Group B delayed interrupt register */
77
78#define FLOW_CONTROL		0xC8	/* Flow control register */
79#define PHY_ACCESS		0xD0	/* PHY access register */
80
81#define STVAL			0xD8	/* Software timer value register */
82
83#define XMT_RING_BASE_ADDR0	0x100	/* Transmit ring0 base addr register */
84#define XMT_RING_BASE_ADDR1	0x108	/* Transmit ring1 base addr register */
85#define XMT_RING_BASE_ADDR2	0x110	/* Transmit ring2 base addr register */
86#define XMT_RING_BASE_ADDR3	0x118	/* Transmit ring2 base addr register */
87
88#define RCV_RING_BASE_ADDR0	0x120	/* Transmit ring0 base addr register */
89
90#define PMAT0			0x190	/* OnNow pattern register0 */
91#define PMAT1			0x194	/* OnNow pattern register1 */
92
93/* 16bit registers */
94
95#define XMT_RING_LEN0		0x140	/* Transmit Ring0 length register */
96#define XMT_RING_LEN1		0x144	/* Transmit Ring1 length register */
97#define XMT_RING_LEN2		0x148 	/* Transmit Ring2 length register */
98#define XMT_RING_LEN3		0x14C	/* Transmit Ring3 length register */
99
100#define RCV_RING_LEN0		0x150	/* Receive Ring0 length register */
101
102#define SRAM_SIZE		0x178	/* SRAM size register */
103#define SRAM_BOUNDARY		0x17A	/* SRAM boundary register */
104
105/* 48bit register */
106
107#define PADR			0x160	/* Physical address register */
108
109#define IFS1			0x18C	/* Inter-frame spacing Part1 register */
110#define IFS			0x18D	/* Inter-frame spacing register */
111#define IPG			0x18E	/* Inter-frame gap register */
112/* 64bit register */
113
114#define LADRF			0x168	/* Logical address filter register */
115
116
117/* Register Bit Definitions */
118typedef enum {
119
120	ASF_INIT_DONE		= (1 << 1),
121	ASF_INIT_PRESENT	= (1 << 0),
122
123}STAT_ASF_BITS;
124
125typedef enum {
126
127	MIB_CMD_ACTIVE		= (1 << 15 ),
128	MIB_RD_CMD		= (1 << 13 ),
129	MIB_CLEAR		= (1 << 12 ),
130	MIB_ADDRESS		= (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
131					(1 << 4) | (1 << 5),
132}MIB_ADDR_BITS;
133
134
135typedef enum {
136
137	PMAT_DET		= (1 << 12),
138	MP_DET		        = (1 << 11),
139	LC_DET			= (1 << 10),
140	SPEED_MASK		= (1 << 9)|(1 << 8)|(1 << 7),
141	FULL_DPLX		= (1 << 6),
142	LINK_STATS		= (1 << 5),
143	AUTONEG_COMPLETE	= (1 << 4),
144	MIIPD			= (1 << 3),
145	RX_SUSPENDED		= (1 << 2),
146	TX_SUSPENDED		= (1 << 1),
147	RUNNING			= (1 << 0),
148
149}STAT0_BITS;
150
151#define PHY_SPEED_10		0x2
152#define PHY_SPEED_100		0x3
153
154/* INT0				0x38, 32bit register */
155typedef enum {
156
157	INTR			= (1 << 31),
158	PCSINT			= (1 << 28),
159	LCINT			= (1 << 27),
160	APINT5			= (1 << 26),
161	APINT4			= (1 << 25),
162	APINT3			= (1 << 24),
163	TINT_SUM		= (1 << 23),
164	APINT2			= (1 << 22),
165	APINT1			= (1 << 21),
166	APINT0			= (1 << 20),
167	MIIPDTINT		= (1 << 19),
168	MCCINT			= (1 << 17),
169	MREINT			= (1 << 16),
170	RINT_SUM		= (1 << 15),
171	SPNDINT			= (1 << 14),
172	MPINT			= (1 << 13),
173	SINT			= (1 << 12),
174	TINT3			= (1 << 11),
175	TINT2			= (1 << 10),
176	TINT1			= (1 << 9),
177	TINT0			= (1 << 8),
178	UINT			= (1 << 7),
179	STINT			= (1 << 4),
180	RINT0			= (1 << 0),
181
182}INT0_BITS;
183
184typedef enum {
185
186	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
187	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
188	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
189	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
190
191}VAL_BITS;
192
193typedef enum {
194
195	/* VAL3 */
196	LCINTEN			= (1 << 27),
197	APINT5EN		= (1 << 26),
198	APINT4EN		= (1 << 25),
199	APINT3EN		= (1 << 24),
200	/* VAL2 */
201	APINT2EN		= (1 << 22),
202	APINT1EN		= (1 << 21),
203	APINT0EN		= (1 << 20),
204	MIIPDTINTEN		= (1 << 19),
205	MCCIINTEN		= (1 << 18),
206	MCCINTEN		= (1 << 17),
207	MREINTEN		= (1 << 16),
208	/* VAL1 */
209	SPNDINTEN		= (1 << 14),
210	MPINTEN			= (1 << 13),
211	TINTEN3			= (1 << 11),
212	SINTEN			= (1 << 12),
213	TINTEN2			= (1 << 10),
214	TINTEN1			= (1 << 9),
215	TINTEN0			= (1 << 8),
216	/* VAL0 */
217	STINTEN			= (1 << 4),
218	RINTEN0			= (1 << 0),
219
220	INTEN0_CLEAR 		= 0x1F7F7F1F, /* Command style register */
221
222}INTEN0_BITS;
223
224typedef enum {
225	/* VAL2 */
226	RDMD0			= (1 << 16),
227	/* VAL1 */
228	TDMD3			= (1 << 11),
229	TDMD2			= (1 << 10),
230	TDMD1			= (1 << 9),
231	TDMD0			= (1 << 8),
232	/* VAL0 */
233	UINTCMD			= (1 << 6),
234	RX_FAST_SPND		= (1 << 5),
235	TX_FAST_SPND		= (1 << 4),
236	RX_SPND			= (1 << 3),
237	TX_SPND			= (1 << 2),
238	INTREN			= (1 << 1),
239	RUN			= (1 << 0),
240
241	CMD0_CLEAR 		= 0x000F0F7F,   /* Command style register */
242
243}CMD0_BITS;
244
245typedef enum {
246
247	/* VAL3 */
248	CONDUIT_MODE		= (1 << 29),
249	/* VAL2 */
250	RPA			= (1 << 19),
251	DRCVPA			= (1 << 18),
252	DRCVBC			= (1 << 17),
253	PROM			= (1 << 16),
254	/* VAL1 */
255	ASTRP_RCV		= (1 << 13),
256	RCV_DROP0	  	= (1 << 12),
257	EMBA			= (1 << 11),
258	DXMT2PD			= (1 << 10),
259	LTINTEN			= (1 << 9),
260	DXMTFCS			= (1 << 8),
261	/* VAL0 */
262	APAD_XMT		= (1 << 6),
263	DRTY			= (1 << 5),
264	INLOOP			= (1 << 4),
265	EXLOOP			= (1 << 3),
266	REX_RTRY		= (1 << 2),
267	REX_UFLO		= (1 << 1),
268	REX_LCOL		= (1 << 0),
269
270	CMD2_CLEAR 		= 0x3F7F3F7F,   /* Command style register */
271
272}CMD2_BITS;
273
274typedef enum {
275
276	/* VAL3 */
277	ASF_INIT_DONE_ALIAS	= (1 << 29),
278	/* VAL2 */
279	JUMBO			= (1 << 21),
280	VSIZE			= (1 << 20),
281	VLONLY			= (1 << 19),
282	VL_TAG_DEL		= (1 << 18),
283	/* VAL1 */
284	EN_PMGR			= (1 << 14),
285	INTLEVEL		= (1 << 13),
286	FORCE_FULL_DUPLEX	= (1 << 12),
287	FORCE_LINK_STATUS	= (1 << 11),
288	APEP			= (1 << 10),
289	MPPLBA			= (1 << 9),
290	/* VAL0 */
291	RESET_PHY_PULSE		= (1 << 2),
292	RESET_PHY		= (1 << 1),
293	PHY_RST_POL		= (1 << 0),
294
295}CMD3_BITS;
296
297
298typedef enum {
299
300	/* VAL0 */
301	PMAT_SAVE_MATCH		= (1 << 4),
302	PMAT_MODE		= (1 << 3),
303	MPEN_SW			= (1 << 1),
304	LCMODE_SW		= (1 << 0),
305
306	CMD7_CLEAR  		= 0x0000001B	/* Command style register */
307
308}CMD7_BITS;
309
310
311typedef enum {
312
313	RESET_PHY_WIDTH		= (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
314	XMTSP_MASK		= (1 << 9) | (1 << 8),	/* 9:8 */
315	XMTSP_128		= (1 << 9),	/* 9 */
316	XMTSP_64		= (1 << 8),
317	CACHE_ALIGN		= (1 << 4),
318	BURST_LIMIT_MASK	= (0xF << 0 ),
319	CTRL1_DEFAULT		= 0x00010111,
320
321}CTRL1_BITS;
322
323typedef enum {
324
325	FMDC_MASK		= (1 << 9)|(1 << 8),	/* 9:8 */
326	XPHYRST			= (1 << 7),
327	XPHYANE			= (1 << 6),
328	XPHYFD			= (1 << 5),
329	XPHYSP			= (1 << 4) | (1 << 3),	/* 4:3 */
330	APDW_MASK		= (1 <<	2) | (1 << 1) | (1 << 0), /* 2:0 */
331
332}CTRL2_BITS;
333
334/* XMT_RING_LIMIT		0x7C, 32bit register */
335typedef enum {
336
337	XMT_RING2_LIMIT		= (0xFF << 16),	/* 23:16 */
338	XMT_RING1_LIMIT		= (0xFF << 8),	/* 15:8 */
339	XMT_RING0_LIMIT		= (0xFF << 0), 	/* 7:0 */
340
341}XMT_RING_LIMIT_BITS;
342
343typedef enum {
344
345	AP_REG0_EN		= (1 << 15),
346	AP_REG0_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
347	AP_PHY0_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
348
349}AUTOPOLL0_BITS;
350
351/* AUTOPOLL1			0x8A, 16bit register */
352typedef enum {
353
354	AP_REG1_EN		= (1 << 15),
355	AP_REG1_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
356	AP_PRE_SUP1		= (1 << 6),
357	AP_PHY1_DFLT		= (1 << 5),
358	AP_PHY1_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
359
360}AUTOPOLL1_BITS;
361
362
363typedef enum {
364
365	AP_REG2_EN		= (1 << 15),
366	AP_REG2_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
367	AP_PRE_SUP2		= (1 << 6),
368	AP_PHY2_DFLT		= (1 << 5),
369	AP_PHY2_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
370
371}AUTOPOLL2_BITS;
372
373typedef enum {
374
375	AP_REG3_EN		= (1 << 15),
376	AP_REG3_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
377	AP_PRE_SUP3		= (1 << 6),
378	AP_PHY3_DFLT		= (1 << 5),
379	AP_PHY3_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
380
381}AUTOPOLL3_BITS;
382
383
384typedef enum {
385
386	AP_REG4_EN		= (1 << 15),
387	AP_REG4_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
388	AP_PRE_SUP4		= (1 << 6),
389	AP_PHY4_DFLT		= (1 << 5),
390	AP_PHY4_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
391
392}AUTOPOLL4_BITS;
393
394
395typedef enum {
396
397	AP_REG5_EN		= (1 << 15),
398	AP_REG5_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
399	AP_PRE_SUP5		= (1 << 6),
400	AP_PHY5_DFLT		= (1 << 5),
401	AP_PHY5_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
402
403}AUTOPOLL5_BITS;
404
405
406
407
408/* AP_VALUE 			0x98, 32bit ragister */
409typedef enum {
410
411	AP_VAL_ACTIVE		= (1 << 31),
412	AP_VAL_RD_CMD		= ( 1 << 29),
413	AP_ADDR			= (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
414	AP_VAL			= (0xF << 0) | (0xF << 4) |( 0xF << 8) |
415				  (0xF << 12),	/* 15:0 */
416
417}AP_VALUE_BITS;
418
419typedef enum {
420
421	DLY_INT_A_R3		= (1 << 31),
422	DLY_INT_A_R2		= (1 << 30),
423	DLY_INT_A_R1		= (1 << 29),
424	DLY_INT_A_R0		= (1 << 28),
425	DLY_INT_A_T3		= (1 << 27),
426	DLY_INT_A_T2		= (1 << 26),
427	DLY_INT_A_T1		= (1 << 25),
428	DLY_INT_A_T0		= ( 1 << 24),
429	EVENT_COUNT_A		= (0xF << 16) | (0x1 << 20),/* 20:16 */
430	MAX_DELAY_TIME_A	= (0xF << 0) | (0xF << 4) | (1 << 8)|
431				  (1 << 9) | (1 << 10),	/* 10:0 */
432
433}DLY_INT_A_BITS;
434
435typedef enum {
436
437	DLY_INT_B_R3		= (1 << 31),
438	DLY_INT_B_R2		= (1 << 30),
439	DLY_INT_B_R1		= (1 << 29),
440	DLY_INT_B_R0		= (1 << 28),
441	DLY_INT_B_T3		= (1 << 27),
442	DLY_INT_B_T2		= (1 << 26),
443	DLY_INT_B_T1		= (1 << 25),
444	DLY_INT_B_T0		= ( 1 << 24),
445	EVENT_COUNT_B		= (0xF << 16) | (0x1 << 20),/* 20:16 */
446	MAX_DELAY_TIME_B	= (0xF << 0) | (0xF << 4) | (1 << 8)|
447				  (1 << 9) | (1 << 10),	/* 10:0 */
448}DLY_INT_B_BITS;
449
450
451/* FLOW_CONTROL 		0xC8, 32bit register */
452typedef enum {
453
454	PAUSE_LEN_CHG		= (1 << 30),
455	FTPE			= (1 << 22),
456	FRPE			= (1 << 21),
457	NAPA			= (1 << 20),
458	NPA			= (1 << 19),
459	FIXP			= ( 1 << 18),
460	FCCMD			= ( 1 << 16),
461	PAUSE_LEN		= (0xF << 0) | (0xF << 4) |( 0xF << 8) |	 				  (0xF << 12),	/* 15:0 */
462
463}FLOW_CONTROL_BITS;
464
465/* PHY_ ACCESS			0xD0, 32bit register */
466typedef enum {
467
468	PHY_CMD_ACTIVE		= (1 << 31),
469	PHY_WR_CMD		= (1 << 30),
470	PHY_RD_CMD		= (1 << 29),
471	PHY_RD_ERR		= (1 << 28),
472	PHY_PRE_SUP		= (1 << 27),
473	PHY_ADDR		= (1 << 21) | (1 << 22) | (1 << 23)|
474				  	(1 << 24) |(1 << 25),/* 25:21 */
475	PHY_REG_ADDR		= (1 << 16) | (1 << 17) | (1 << 18)|	 			  	   	  	(1 << 19) | (1 << 20),/* 20:16 */
476	PHY_DATA		= (0xF << 0)|(0xF << 4) |(0xF << 8)|
477					(0xF << 12),/* 15:0 */
478
479}PHY_ACCESS_BITS;
480
481
482/* PMAT0			0x190,	 32bit register */
483typedef enum {
484	PMR_ACTIVE		= (1 << 31),
485	PMR_WR_CMD		= (1 << 30),
486	PMR_RD_CMD		= (1 << 29),
487	PMR_BANK		= (1 <<28),
488	PMR_ADDR		= (0xF << 16)|(1 << 20)|(1 << 21)|
489				  	(1 << 22),/* 22:16 */
490	PMR_B4			= (0xF << 0) | (0xF << 4),/* 15:0 */
491}PMAT0_BITS;
492
493
494/* PMAT1			0x194,	 32bit register */
495typedef enum {
496	PMR_B3			= (0xF << 24) | (0xF <<28),/* 31:24 */
497	PMR_B2			= (0xF << 16) |(0xF << 20),/* 23:16 */
498	PMR_B1			= (0xF << 8) | (0xF <<12), /* 15:8 */
499	PMR_B0			= (0xF << 0)|(0xF << 4),/* 7:0 */
500}PMAT1_BITS;
501
502/************************************************************************/
503/*                                                                      */
504/*                      MIB counter definitions                         */
505/*                                                                      */
506/************************************************************************/
507
508#define rcv_miss_pkts				0x00
509#define rcv_octets				0x01
510#define rcv_broadcast_pkts			0x02
511#define rcv_multicast_pkts			0x03
512#define rcv_undersize_pkts			0x04
513#define rcv_oversize_pkts			0x05
514#define rcv_fragments				0x06
515#define rcv_jabbers				0x07
516#define rcv_unicast_pkts			0x08
517#define rcv_alignment_errors			0x09
518#define rcv_fcs_errors				0x0A
519#define rcv_good_octets				0x0B
520#define rcv_mac_ctrl				0x0C
521#define rcv_flow_ctrl				0x0D
522#define rcv_pkts_64_octets			0x0E
523#define rcv_pkts_65to127_octets			0x0F
524#define rcv_pkts_128to255_octets		0x10
525#define rcv_pkts_256to511_octets		0x11
526#define rcv_pkts_512to1023_octets		0x12
527#define rcv_pkts_1024to1518_octets		0x13
528#define rcv_unsupported_opcode			0x14
529#define rcv_symbol_errors			0x15
530#define rcv_drop_pkts_ring1			0x16
531#define rcv_drop_pkts_ring2			0x17
532#define rcv_drop_pkts_ring3			0x18
533#define rcv_drop_pkts_ring4			0x19
534#define rcv_jumbo_pkts				0x1A
535
536#define xmt_underrun_pkts			0x20
537#define xmt_octets				0x21
538#define xmt_packets				0x22
539#define xmt_broadcast_pkts			0x23
540#define xmt_multicast_pkts			0x24
541#define xmt_collisions				0x25
542#define xmt_unicast_pkts			0x26
543#define xmt_one_collision			0x27
544#define xmt_multiple_collision			0x28
545#define xmt_deferred_transmit			0x29
546#define xmt_late_collision			0x2A
547#define xmt_excessive_defer			0x2B
548#define xmt_loss_carrier			0x2C
549#define xmt_excessive_collision			0x2D
550#define xmt_back_pressure			0x2E
551#define xmt_flow_ctrl				0x2F
552#define xmt_pkts_64_octets			0x30
553#define xmt_pkts_65to127_octets			0x31
554#define xmt_pkts_128to255_octets		0x32
555#define xmt_pkts_256to511_octets		0x33
556#define xmt_pkts_512to1023_octets		0x34
557#define xmt_pkts_1024to1518_octet		0x35
558#define xmt_oversize_pkts			0x36
559#define xmt_jumbo_pkts				0x37
560
561
562/* Driver definitions */
563
564#define	 PCI_VENDOR_ID_AMD		0x1022
565#define  PCI_DEVICE_ID_AMD8111E_7462	0x7462
566
567#define MAX_UNITS			8 /* Maximum number of devices possible */
568
569#define NUM_TX_BUFFERS			32 /* Number of transmit buffers */
570#define NUM_RX_BUFFERS			32 /* Number of receive buffers */
571
572#define TX_BUFF_MOD_MASK         	31 /* (NUM_TX_BUFFERS -1) */
573#define RX_BUFF_MOD_MASK         	31 /* (NUM_RX_BUFFERS -1) */
574
575#define NUM_TX_RING_DR			32
576#define NUM_RX_RING_DR			32
577
578#define TX_RING_DR_MOD_MASK         	31 /* (NUM_TX_RING_DR -1) */
579#define RX_RING_DR_MOD_MASK         	31 /* (NUM_RX_RING_DR -1) */
580
581#define MAX_FILTER_SIZE			64 /* Maximum multicast address */
582#define AMD8111E_MIN_MTU	 	60
583#define AMD8111E_MAX_MTU		9000
584
585#define PKT_BUFF_SZ			1536
586#define MIN_PKT_LEN			60
587
588#define  AMD8111E_TX_TIMEOUT		(3 * HZ)/* 3 sec */
589#define SOFT_TIMER_FREQ 		0xBEBC  /* 0.5 sec */
590#define DELAY_TIMER_CONV		50    /* msec to 10 usec conversion.
591						 Only 500 usec resolution */
592#define OPTION_VLAN_ENABLE		0x0001
593#define OPTION_JUMBO_ENABLE		0x0002
594#define OPTION_MULTICAST_ENABLE		0x0004
595#define OPTION_WOL_ENABLE		0x0008
596#define OPTION_WAKE_MAGIC_ENABLE	0x0010
597#define OPTION_WAKE_PHY_ENABLE		0x0020
598#define OPTION_INTR_COAL_ENABLE		0x0040
599#define OPTION_DYN_IPG_ENABLE	        0x0080
600
601#define PHY_REG_ADDR_MASK		0x1f
602
603/* ipg parameters */
604#define DEFAULT_IPG			0x60
605#define IFS1_DELTA			36
606#define	IPG_CONVERGE_JIFFIES (HZ/2)
607#define	IPG_STABLE_TIME	5
608#define	MIN_IPG	96
609#define	MAX_IPG	255
610#define IPG_STEP	16
611#define CSTATE  1
612#define SSTATE  2
613
614/* Assume contoller gets data 10 times the maximum processing time */
615#define  REPEAT_CNT			10
616
617/* amd8111e decriptor flag definitions */
618typedef enum {
619
620	OWN_BIT		=	(1 << 15),
621	ADD_FCS_BIT	=	(1 << 13),
622	LTINT_BIT	=	(1 << 12),
623	STP_BIT		=	(1 << 9),
624	ENP_BIT		=	(1 << 8),
625	KILL_BIT	= 	(1 << 6),
626	TCC_VLAN_INSERT	=	(1 << 1),
627	TCC_VLAN_REPLACE =	(1 << 1) |( 1<< 0),
628
629}TX_FLAG_BITS;
630
631typedef enum {
632	ERR_BIT 	=	(1 << 14),
633	FRAM_BIT	=  	(1 << 13),
634	OFLO_BIT	=       (1 << 12),
635	CRC_BIT		=	(1 << 11),
636	PAM_BIT		=	(1 << 6),
637	LAFM_BIT	= 	(1 << 5),
638	BAM_BIT		=	(1 << 4),
639	TT_VLAN_TAGGED	= 	(1 << 3) |(1 << 2),/* 0x000 */
640	TT_PRTY_TAGGED	=	(1 << 3),/* 0x0008 */
641
642}RX_FLAG_BITS;
643
644#define RESET_RX_FLAGS		0x0000
645#define TT_MASK			0x000c
646#define TCC_MASK		0x0003
647
648/* driver ioctl parameters */
649#define AMD8111E_REG_DUMP_LEN	 13*sizeof(u32)
650
651/* amd8111e desriptor format */
652
653struct amd8111e_tx_dr{
654
655	__le16 buff_count; /* Size of the buffer pointed by this descriptor */
656
657	__le16 tx_flags;
658
659	__le16 tag_ctrl_info;
660
661	__le16 tag_ctrl_cmd;
662
663	__le32 buff_phy_addr;
664
665	__le32 reserved;
666};
667
668struct amd8111e_rx_dr{
669
670	__le32 reserved;
671
672	__le16 msg_count; /* Received message len */
673
674	__le16 tag_ctrl_info;
675
676	__le16 buff_count;  /* Len of the buffer pointed by descriptor. */
677
678	__le16 rx_flags;
679
680	__le32 buff_phy_addr;
681
682};
683struct amd8111e_link_config{
684
685#define SPEED_INVALID		0xffff
686#define DUPLEX_INVALID		0xff
687#define AUTONEG_INVALID		0xff
688
689	unsigned long			orig_phy_option;
690	u16				speed;
691	u8				duplex;
692	u8				autoneg;
693	u8				reserved;  /* 32bit alignment */
694};
695
696enum coal_type{
697
698	NO_COALESCE,
699	LOW_COALESCE,
700	MEDIUM_COALESCE,
701	HIGH_COALESCE,
702
703};
704
705enum coal_mode{
706       	RX_INTR_COAL,
707	TX_INTR_COAL,
708	DISABLE_COAL,
709	ENABLE_COAL,
710
711};
712#define MAX_TIMEOUT	40
713#define MAX_EVENT_COUNT 31
714struct amd8111e_coalesce_conf{
715
716	unsigned int rx_timeout;
717	unsigned int rx_event_count;
718	unsigned long rx_packets;
719	unsigned long rx_prev_packets;
720	unsigned long rx_bytes;
721	unsigned long rx_prev_bytes;
722	unsigned int rx_coal_type;
723
724	unsigned int tx_timeout;
725	unsigned int tx_event_count;
726	unsigned long tx_packets;
727	unsigned long tx_prev_packets;
728	unsigned long tx_bytes;
729	unsigned long tx_prev_bytes;
730	unsigned int tx_coal_type;
731
732};
733struct ipg_info{
734
735	unsigned int ipg_state;
736	unsigned int ipg;
737	unsigned int current_ipg;
738	unsigned int col_cnt;
739	unsigned int diff_col_cnt;
740	unsigned int timer_tick;
741	unsigned int prev_ipg;
742	struct timer_list ipg_timer;
743};
744
745struct amd8111e_priv{
746
747	struct amd8111e_tx_dr*  tx_ring;
748	struct amd8111e_rx_dr* rx_ring;
749	dma_addr_t tx_ring_dma_addr;	/* tx descriptor ring base address */
750	dma_addr_t rx_ring_dma_addr;	/* rx descriptor ring base address */
751	const char *name;
752	struct pci_dev *pci_dev;	/* Ptr to the associated pci_dev */
753	struct net_device* amd8111e_net_dev; 	/* ptr to associated net_device */
754	/* Transmit and receive skbs */
755	struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
756	struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
757	/* Transmit and receive dma mapped addr */
758	dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
759	dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
760	/* Reg memory mapped address */
761	void __iomem *mmio;
762
763	struct napi_struct napi;
764
765	spinlock_t lock;	/* Guard lock */
766	unsigned long rx_idx, tx_idx;	/* The next free ring entry */
767	unsigned long tx_complete_idx;
768	unsigned long tx_ring_complete_idx;
769	unsigned long tx_ring_idx;
770	unsigned int rx_buff_len;	/* Buffer length of rx buffers */
771	int options;		/* Options enabled/disabled for the device */
772
773	unsigned long ext_phy_option;
774	int ext_phy_addr;
775	u32 ext_phy_id;
776
777	struct amd8111e_link_config link_config;
778	int pm_cap;
779
780	struct net_device *next;
781	int mii;
782	struct mii_if_info mii_if;
783	char opened;
784	unsigned int drv_rx_errors;
785	struct amd8111e_coalesce_conf coal_conf;
786
787	struct ipg_info  ipg_data;
788
789};
790
791/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
792BUG? */
793#define  amd8111e_writeq(_UlData,_memMap)   \
794		writel(*(u32*)(&_UlData), _memMap);	\
795		writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
796
797/* maps the external speed options to internal value */
798typedef enum {
799	SPEED_AUTONEG,
800	SPEED10_HALF,
801	SPEED10_FULL,
802	SPEED100_HALF,
803	SPEED100_FULL,
804}EXT_PHY_OPTION;
805
806static int card_idx;
807static int speed_duplex[MAX_UNITS] = { 0, };
808static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
809static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };
810static unsigned int chip_version;
811
812#endif /* _AMD8111E_H */
813
814