1/* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12#include <linux/types.h> 13#include <linux/delay.h> 14#include <linux/wait.h> 15#include <linux/mii.h> 16#include <linux/ethtool.h> 17#include <linux/bitops.h> 18#include <linux/netdevice.h> 19#include <linux/platform_device.h> 20#include <linux/phy.h> 21#include <linux/phy_fixed.h> 22#include <linux/brcmphy.h> 23#include <linux/of.h> 24#include <linux/of_net.h> 25#include <linux/of_mdio.h> 26 27#include "bcmgenet.h" 28 29/* read a value from the MII */ 30static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 31{ 32 int ret; 33 struct net_device *dev = bus->priv; 34 struct bcmgenet_priv *priv = netdev_priv(dev); 35 u32 reg; 36 37 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 38 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 39 /* Start MDIO transaction*/ 40 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 41 reg |= MDIO_START_BUSY; 42 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 43 wait_event_timeout(priv->wq, 44 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 45 & MDIO_START_BUSY), 46 HZ / 100); 47 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 48 49 if (ret & MDIO_READ_FAIL) 50 return -EIO; 51 52 return ret & 0xffff; 53} 54 55/* write a value to the MII */ 56static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 57 int location, u16 val) 58{ 59 struct net_device *dev = bus->priv; 60 struct bcmgenet_priv *priv = netdev_priv(dev); 61 u32 reg; 62 63 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 64 (location << MDIO_REG_SHIFT) | (0xffff & val)), 65 UMAC_MDIO_CMD); 66 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 67 reg |= MDIO_START_BUSY; 68 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 69 wait_event_timeout(priv->wq, 70 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 71 MDIO_START_BUSY), 72 HZ / 100); 73 74 return 0; 75} 76 77/* setup netdev link state when PHY link status change and 78 * update UMAC and RGMII block when link up 79 */ 80void bcmgenet_mii_setup(struct net_device *dev) 81{ 82 struct bcmgenet_priv *priv = netdev_priv(dev); 83 struct phy_device *phydev = priv->phydev; 84 u32 reg, cmd_bits = 0; 85 bool status_changed = false; 86 87 if (priv->old_link != phydev->link) { 88 status_changed = true; 89 priv->old_link = phydev->link; 90 } 91 92 if (phydev->link) { 93 /* check speed/duplex/pause changes */ 94 if (priv->old_speed != phydev->speed) { 95 status_changed = true; 96 priv->old_speed = phydev->speed; 97 } 98 99 if (priv->old_duplex != phydev->duplex) { 100 status_changed = true; 101 priv->old_duplex = phydev->duplex; 102 } 103 104 if (priv->old_pause != phydev->pause) { 105 status_changed = true; 106 priv->old_pause = phydev->pause; 107 } 108 109 /* done if nothing has changed */ 110 if (!status_changed) 111 return; 112 113 /* speed */ 114 if (phydev->speed == SPEED_1000) 115 cmd_bits = UMAC_SPEED_1000; 116 else if (phydev->speed == SPEED_100) 117 cmd_bits = UMAC_SPEED_100; 118 else 119 cmd_bits = UMAC_SPEED_10; 120 cmd_bits <<= CMD_SPEED_SHIFT; 121 122 /* duplex */ 123 if (phydev->duplex != DUPLEX_FULL) 124 cmd_bits |= CMD_HD_EN; 125 126 /* pause capability */ 127 if (!phydev->pause) 128 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 129 130 /* 131 * Program UMAC and RGMII block based on established 132 * link speed, duplex, and pause. The speed set in 133 * umac->cmd tell RGMII block which clock to use for 134 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 135 * Receive clock is provided by the PHY. 136 */ 137 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 138 reg &= ~OOB_DISABLE; 139 reg |= RGMII_LINK; 140 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 141 142 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 143 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 144 CMD_HD_EN | 145 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 146 reg |= cmd_bits; 147 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 148 } else { 149 /* done if nothing has changed */ 150 if (!status_changed) 151 return; 152 153 /* needed for MoCA fixed PHY to reflect correct link status */ 154 netif_carrier_off(dev); 155 } 156 157 phy_print_status(phydev); 158} 159 160void bcmgenet_mii_reset(struct net_device *dev) 161{ 162 struct bcmgenet_priv *priv = netdev_priv(dev); 163 164 if (priv->phydev) { 165 phy_init_hw(priv->phydev); 166 phy_start_aneg(priv->phydev); 167 } 168} 169 170static void bcmgenet_ephy_power_up(struct net_device *dev) 171{ 172 struct bcmgenet_priv *priv = netdev_priv(dev); 173 u32 reg = 0; 174 175 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 176 if (!GENET_IS_V4(priv)) 177 return; 178 179 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 180 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 181 reg |= EXT_GPHY_RESET; 182 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 183 mdelay(2); 184 185 reg &= ~EXT_GPHY_RESET; 186 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 187 udelay(20); 188} 189 190static void bcmgenet_internal_phy_setup(struct net_device *dev) 191{ 192 struct bcmgenet_priv *priv = netdev_priv(dev); 193 u32 reg; 194 195 /* Power up EPHY */ 196 bcmgenet_ephy_power_up(dev); 197 /* enable APD */ 198 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 199 reg |= EXT_PWR_DN_EN_LD; 200 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 201 bcmgenet_mii_reset(dev); 202} 203 204static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 205{ 206 u32 reg; 207 208 /* Speed settings are set in bcmgenet_mii_setup() */ 209 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 210 reg |= LED_ACT_SOURCE_MAC; 211 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 212} 213 214int bcmgenet_mii_config(struct net_device *dev, bool init) 215{ 216 struct bcmgenet_priv *priv = netdev_priv(dev); 217 struct phy_device *phydev = priv->phydev; 218 struct device *kdev = &priv->pdev->dev; 219 const char *phy_name = NULL; 220 u32 id_mode_dis = 0; 221 u32 port_ctrl; 222 u32 reg; 223 224 priv->ext_phy = !phy_is_internal(priv->phydev) && 225 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 226 227 if (phy_is_internal(priv->phydev)) 228 priv->phy_interface = PHY_INTERFACE_MODE_NA; 229 230 switch (priv->phy_interface) { 231 case PHY_INTERFACE_MODE_NA: 232 case PHY_INTERFACE_MODE_MOCA: 233 /* Irrespective of the actually configured PHY speed (100 or 234 * 1000) GENETv4 only has an internal GPHY so we will just end 235 * up masking the Gigabit features from what we support, not 236 * switching to the EPHY 237 */ 238 if (GENET_IS_V4(priv)) 239 port_ctrl = PORT_MODE_INT_GPHY; 240 else 241 port_ctrl = PORT_MODE_INT_EPHY; 242 243 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 244 245 if (phy_is_internal(priv->phydev)) { 246 phy_name = "internal PHY"; 247 bcmgenet_internal_phy_setup(dev); 248 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 249 phy_name = "MoCA"; 250 bcmgenet_moca_phy_setup(priv); 251 } 252 break; 253 254 case PHY_INTERFACE_MODE_MII: 255 phy_name = "external MII"; 256 phydev->supported &= PHY_BASIC_FEATURES; 257 bcmgenet_sys_writel(priv, 258 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 259 break; 260 261 case PHY_INTERFACE_MODE_REVMII: 262 phy_name = "external RvMII"; 263 /* of_mdiobus_register took care of reading the 'max-speed' 264 * PHY property for us, effectively limiting the PHY supported 265 * capabilities, use that knowledge to also configure the 266 * Reverse MII interface correctly. 267 */ 268 if ((priv->phydev->supported & PHY_BASIC_FEATURES) == 269 PHY_BASIC_FEATURES) 270 port_ctrl = PORT_MODE_EXT_RVMII_25; 271 else 272 port_ctrl = PORT_MODE_EXT_RVMII_50; 273 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 274 break; 275 276 case PHY_INTERFACE_MODE_RGMII: 277 /* RGMII_NO_ID: TXC transitions at the same time as TXD 278 * (requires PCB or receiver-side delay) 279 * RGMII: Add 2ns delay on TXC (90 degree shift) 280 * 281 * ID is implicitly disabled for 100Mbps (RG)MII operation. 282 */ 283 id_mode_dis = BIT(16); 284 /* fall through */ 285 case PHY_INTERFACE_MODE_RGMII_TXID: 286 if (id_mode_dis) 287 phy_name = "external RGMII (no delay)"; 288 else 289 phy_name = "external RGMII (TX delay)"; 290 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 291 reg |= RGMII_MODE_EN | id_mode_dis; 292 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 293 bcmgenet_sys_writel(priv, 294 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 295 break; 296 default: 297 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 298 return -EINVAL; 299 } 300 301 if (init) 302 dev_info(kdev, "configuring instance for %s\n", phy_name); 303 304 return 0; 305} 306 307static int bcmgenet_mii_probe(struct net_device *dev) 308{ 309 struct bcmgenet_priv *priv = netdev_priv(dev); 310 struct device_node *dn = priv->pdev->dev.of_node; 311 struct phy_device *phydev; 312 u32 phy_flags; 313 int ret; 314 315 if (priv->phydev) { 316 pr_info("PHY already attached\n"); 317 return 0; 318 } 319 320 /* In the case of a fixed PHY, the DT node associated 321 * to the PHY is the Ethernet MAC DT node. 322 */ 323 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 324 ret = of_phy_register_fixed_link(dn); 325 if (ret) 326 return ret; 327 328 priv->phy_dn = of_node_get(dn); 329 } 330 331 /* Communicate the integrated PHY revision */ 332 phy_flags = priv->gphy_rev; 333 334 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 335 priv->old_link = -1; 336 priv->old_speed = -1; 337 priv->old_duplex = -1; 338 priv->old_pause = -1; 339 340 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 341 phy_flags, priv->phy_interface); 342 if (!phydev) { 343 pr_err("could not attach to PHY\n"); 344 return -ENODEV; 345 } 346 347 priv->phydev = phydev; 348 349 /* Configure port multiplexer based on what the probed PHY device since 350 * reading the 'max-speed' property determines the maximum supported 351 * PHY speed which is needed for bcmgenet_mii_config() to configure 352 * things appropriately. 353 */ 354 ret = bcmgenet_mii_config(dev, true); 355 if (ret) { 356 phy_disconnect(priv->phydev); 357 return ret; 358 } 359 360 phydev->advertising = phydev->supported; 361 362 /* The internal PHY has its link interrupts routed to the 363 * Ethernet MAC ISRs 364 */ 365 if (phy_is_internal(priv->phydev)) 366 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT; 367 else 368 priv->mii_bus->irq[phydev->addr] = PHY_POLL; 369 370 pr_info("attached PHY at address %d [%s]\n", 371 phydev->addr, phydev->drv->name); 372 373 return 0; 374} 375 376static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 377{ 378 struct mii_bus *bus; 379 380 if (priv->mii_bus) 381 return 0; 382 383 priv->mii_bus = mdiobus_alloc(); 384 if (!priv->mii_bus) { 385 pr_err("failed to allocate\n"); 386 return -ENOMEM; 387 } 388 389 bus = priv->mii_bus; 390 bus->priv = priv->dev; 391 bus->name = "bcmgenet MII bus"; 392 bus->parent = &priv->pdev->dev; 393 bus->read = bcmgenet_mii_read; 394 bus->write = bcmgenet_mii_write; 395 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 396 priv->pdev->name, priv->pdev->id); 397 398 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 399 if (!bus->irq) { 400 mdiobus_free(priv->mii_bus); 401 return -ENOMEM; 402 } 403 404 return 0; 405} 406 407static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 408{ 409 struct device_node *dn = priv->pdev->dev.of_node; 410 struct device *kdev = &priv->pdev->dev; 411 struct device_node *mdio_dn; 412 char *compat; 413 int ret; 414 415 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 416 if (!compat) 417 return -ENOMEM; 418 419 mdio_dn = of_find_compatible_node(dn, NULL, compat); 420 kfree(compat); 421 if (!mdio_dn) { 422 dev_err(kdev, "unable to find MDIO bus node\n"); 423 return -ENODEV; 424 } 425 426 ret = of_mdiobus_register(priv->mii_bus, mdio_dn); 427 if (ret) { 428 dev_err(kdev, "failed to register MDIO bus\n"); 429 return ret; 430 } 431 432 /* Fetch the PHY phandle */ 433 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 434 435 /* Get the link mode */ 436 priv->phy_interface = of_get_phy_mode(dn); 437 438 return 0; 439} 440 441int bcmgenet_mii_init(struct net_device *dev) 442{ 443 struct bcmgenet_priv *priv = netdev_priv(dev); 444 int ret; 445 446 ret = bcmgenet_mii_alloc(priv); 447 if (ret) 448 return ret; 449 450 ret = bcmgenet_mii_of_init(priv); 451 if (ret) 452 goto out_free; 453 454 ret = bcmgenet_mii_probe(dev); 455 if (ret) 456 goto out; 457 458 return 0; 459 460out: 461 of_node_put(priv->phy_dn); 462 mdiobus_unregister(priv->mii_bus); 463out_free: 464 kfree(priv->mii_bus->irq); 465 mdiobus_free(priv->mii_bus); 466 return ret; 467} 468 469void bcmgenet_mii_exit(struct net_device *dev) 470{ 471 struct bcmgenet_priv *priv = netdev_priv(dev); 472 473 of_node_put(priv->phy_dn); 474 mdiobus_unregister(priv->mii_bus); 475 kfree(priv->mii_bus->irq); 476 mdiobus_free(priv->mii_bus); 477} 478