1/* 2 * Cadence MACB/GEM Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12#include <linux/clk.h> 13#include <linux/module.h> 14#include <linux/moduleparam.h> 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/circ_buf.h> 18#include <linux/slab.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <linux/gpio.h> 22#include <linux/interrupt.h> 23#include <linux/netdevice.h> 24#include <linux/etherdevice.h> 25#include <linux/dma-mapping.h> 26#include <linux/platform_data/macb.h> 27#include <linux/platform_device.h> 28#include <linux/phy.h> 29#include <linux/of.h> 30#include <linux/of_device.h> 31#include <linux/of_mdio.h> 32#include <linux/of_net.h> 33 34#include "macb.h" 35 36#define MACB_RX_BUFFER_SIZE 128 37#define RX_BUFFER_MULTIPLE 64 /* bytes */ 38#define RX_RING_SIZE 512 /* must be power of 2 */ 39#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) 40 41#define TX_RING_SIZE 128 /* must be power of 2 */ 42#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) 43 44/* level of occupied TX descriptors under which we wake up TX process */ 45#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4) 46 47#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ 48 | MACB_BIT(ISR_ROVR)) 49#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ 50 | MACB_BIT(ISR_RLE) \ 51 | MACB_BIT(TXERR)) 52#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) 53 54#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1)) 55#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1)) 56 57/* 58 * Graceful stop timeouts in us. We should allow up to 59 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) 60 */ 61#define MACB_HALT_TIMEOUT 1230 62 63/* Ring buffer accessors */ 64static unsigned int macb_tx_ring_wrap(unsigned int index) 65{ 66 return index & (TX_RING_SIZE - 1); 67} 68 69static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index) 70{ 71 return &bp->tx_ring[macb_tx_ring_wrap(index)]; 72} 73 74static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index) 75{ 76 return &bp->tx_skb[macb_tx_ring_wrap(index)]; 77} 78 79static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index) 80{ 81 dma_addr_t offset; 82 83 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); 84 85 return bp->tx_ring_dma + offset; 86} 87 88static unsigned int macb_rx_ring_wrap(unsigned int index) 89{ 90 return index & (RX_RING_SIZE - 1); 91} 92 93static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) 94{ 95 return &bp->rx_ring[macb_rx_ring_wrap(index)]; 96} 97 98static void *macb_rx_buffer(struct macb *bp, unsigned int index) 99{ 100 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index); 101} 102 103void macb_set_hwaddr(struct macb *bp) 104{ 105 u32 bottom; 106 u16 top; 107 108 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); 109 macb_or_gem_writel(bp, SA1B, bottom); 110 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); 111 macb_or_gem_writel(bp, SA1T, top); 112 113 /* Clear unused address register sets */ 114 macb_or_gem_writel(bp, SA2B, 0); 115 macb_or_gem_writel(bp, SA2T, 0); 116 macb_or_gem_writel(bp, SA3B, 0); 117 macb_or_gem_writel(bp, SA3T, 0); 118 macb_or_gem_writel(bp, SA4B, 0); 119 macb_or_gem_writel(bp, SA4T, 0); 120} 121EXPORT_SYMBOL_GPL(macb_set_hwaddr); 122 123void macb_get_hwaddr(struct macb *bp) 124{ 125 struct macb_platform_data *pdata; 126 u32 bottom; 127 u16 top; 128 u8 addr[6]; 129 int i; 130 131 pdata = dev_get_platdata(&bp->pdev->dev); 132 133 /* Check all 4 address register for vaild address */ 134 for (i = 0; i < 4; i++) { 135 bottom = macb_or_gem_readl(bp, SA1B + i * 8); 136 top = macb_or_gem_readl(bp, SA1T + i * 8); 137 138 if (pdata && pdata->rev_eth_addr) { 139 addr[5] = bottom & 0xff; 140 addr[4] = (bottom >> 8) & 0xff; 141 addr[3] = (bottom >> 16) & 0xff; 142 addr[2] = (bottom >> 24) & 0xff; 143 addr[1] = top & 0xff; 144 addr[0] = (top & 0xff00) >> 8; 145 } else { 146 addr[0] = bottom & 0xff; 147 addr[1] = (bottom >> 8) & 0xff; 148 addr[2] = (bottom >> 16) & 0xff; 149 addr[3] = (bottom >> 24) & 0xff; 150 addr[4] = top & 0xff; 151 addr[5] = (top >> 8) & 0xff; 152 } 153 154 if (is_valid_ether_addr(addr)) { 155 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 156 return; 157 } 158 } 159 160 netdev_info(bp->dev, "invalid hw address, using random\n"); 161 eth_hw_addr_random(bp->dev); 162} 163EXPORT_SYMBOL_GPL(macb_get_hwaddr); 164 165static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 166{ 167 struct macb *bp = bus->priv; 168 int value; 169 170 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 171 | MACB_BF(RW, MACB_MAN_READ) 172 | MACB_BF(PHYA, mii_id) 173 | MACB_BF(REGA, regnum) 174 | MACB_BF(CODE, MACB_MAN_CODE))); 175 176 /* wait for end of transfer */ 177 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 178 cpu_relax(); 179 180 value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); 181 182 return value; 183} 184 185static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 186 u16 value) 187{ 188 struct macb *bp = bus->priv; 189 190 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) 191 | MACB_BF(RW, MACB_MAN_WRITE) 192 | MACB_BF(PHYA, mii_id) 193 | MACB_BF(REGA, regnum) 194 | MACB_BF(CODE, MACB_MAN_CODE) 195 | MACB_BF(DATA, value))); 196 197 /* wait for end of transfer */ 198 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) 199 cpu_relax(); 200 201 return 0; 202} 203 204/** 205 * macb_set_tx_clk() - Set a clock to a new frequency 206 * @clk Pointer to the clock to change 207 * @rate New frequency in Hz 208 * @dev Pointer to the struct net_device 209 */ 210static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) 211{ 212 long ferr, rate, rate_rounded; 213 214 switch (speed) { 215 case SPEED_10: 216 rate = 2500000; 217 break; 218 case SPEED_100: 219 rate = 25000000; 220 break; 221 case SPEED_1000: 222 rate = 125000000; 223 break; 224 default: 225 return; 226 } 227 228 rate_rounded = clk_round_rate(clk, rate); 229 if (rate_rounded < 0) 230 return; 231 232 /* RGMII allows 50 ppm frequency error. Test and warn if this limit 233 * is not satisfied. 234 */ 235 ferr = abs(rate_rounded - rate); 236 ferr = DIV_ROUND_UP(ferr, rate / 100000); 237 if (ferr > 5) 238 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", 239 rate); 240 241 if (clk_set_rate(clk, rate_rounded)) 242 netdev_err(dev, "adjusting tx_clk failed.\n"); 243} 244 245static void macb_handle_link_change(struct net_device *dev) 246{ 247 struct macb *bp = netdev_priv(dev); 248 struct phy_device *phydev = bp->phy_dev; 249 unsigned long flags; 250 251 int status_change = 0; 252 253 spin_lock_irqsave(&bp->lock, flags); 254 255 if (phydev->link) { 256 if ((bp->speed != phydev->speed) || 257 (bp->duplex != phydev->duplex)) { 258 u32 reg; 259 260 reg = macb_readl(bp, NCFGR); 261 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 262 if (macb_is_gem(bp)) 263 reg &= ~GEM_BIT(GBE); 264 265 if (phydev->duplex) 266 reg |= MACB_BIT(FD); 267 if (phydev->speed == SPEED_100) 268 reg |= MACB_BIT(SPD); 269 if (phydev->speed == SPEED_1000 && 270 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) 271 reg |= GEM_BIT(GBE); 272 273 macb_or_gem_writel(bp, NCFGR, reg); 274 275 bp->speed = phydev->speed; 276 bp->duplex = phydev->duplex; 277 status_change = 1; 278 } 279 } 280 281 if (phydev->link != bp->link) { 282 if (!phydev->link) { 283 bp->speed = 0; 284 bp->duplex = -1; 285 } 286 bp->link = phydev->link; 287 288 status_change = 1; 289 } 290 291 spin_unlock_irqrestore(&bp->lock, flags); 292 293 if (!IS_ERR(bp->tx_clk)) 294 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev); 295 296 if (status_change) { 297 if (phydev->link) { 298 netif_carrier_on(dev); 299 netdev_info(dev, "link up (%d/%s)\n", 300 phydev->speed, 301 phydev->duplex == DUPLEX_FULL ? 302 "Full" : "Half"); 303 } else { 304 netif_carrier_off(dev); 305 netdev_info(dev, "link down\n"); 306 } 307 } 308} 309 310/* based on au1000_eth. c*/ 311static int macb_mii_probe(struct net_device *dev) 312{ 313 struct macb *bp = netdev_priv(dev); 314 struct macb_platform_data *pdata; 315 struct phy_device *phydev; 316 int phy_irq; 317 int ret; 318 319 phydev = phy_find_first(bp->mii_bus); 320 if (!phydev) { 321 netdev_err(dev, "no PHY found\n"); 322 return -ENXIO; 323 } 324 325 pdata = dev_get_platdata(&bp->pdev->dev); 326 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) { 327 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int"); 328 if (!ret) { 329 phy_irq = gpio_to_irq(pdata->phy_irq_pin); 330 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq; 331 } 332 } 333 334 /* attach the mac to the phy */ 335 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 336 bp->phy_interface); 337 if (ret) { 338 netdev_err(dev, "Could not attach to PHY\n"); 339 return ret; 340 } 341 342 /* mask with MAC supported features */ 343 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) 344 phydev->supported &= PHY_GBIT_FEATURES; 345 else 346 phydev->supported &= PHY_BASIC_FEATURES; 347 348 phydev->advertising = phydev->supported; 349 350 bp->link = 0; 351 bp->speed = 0; 352 bp->duplex = -1; 353 bp->phy_dev = phydev; 354 355 return 0; 356} 357 358int macb_mii_init(struct macb *bp) 359{ 360 struct macb_platform_data *pdata; 361 struct device_node *np; 362 int err = -ENXIO, i; 363 364 /* Enable management port */ 365 macb_writel(bp, NCR, MACB_BIT(MPE)); 366 367 bp->mii_bus = mdiobus_alloc(); 368 if (bp->mii_bus == NULL) { 369 err = -ENOMEM; 370 goto err_out; 371 } 372 373 bp->mii_bus->name = "MACB_mii_bus"; 374 bp->mii_bus->read = &macb_mdio_read; 375 bp->mii_bus->write = &macb_mdio_write; 376 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 377 bp->pdev->name, bp->pdev->id); 378 bp->mii_bus->priv = bp; 379 bp->mii_bus->parent = &bp->dev->dev; 380 pdata = dev_get_platdata(&bp->pdev->dev); 381 382 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 383 if (!bp->mii_bus->irq) { 384 err = -ENOMEM; 385 goto err_out_free_mdiobus; 386 } 387 388 dev_set_drvdata(&bp->dev->dev, bp->mii_bus); 389 390 np = bp->pdev->dev.of_node; 391 if (np) { 392 /* try dt phy registration */ 393 err = of_mdiobus_register(bp->mii_bus, np); 394 395 /* fallback to standard phy registration if no phy were 396 found during dt phy registration */ 397 if (!err && !phy_find_first(bp->mii_bus)) { 398 for (i = 0; i < PHY_MAX_ADDR; i++) { 399 struct phy_device *phydev; 400 401 phydev = mdiobus_scan(bp->mii_bus, i); 402 if (IS_ERR(phydev)) { 403 err = PTR_ERR(phydev); 404 break; 405 } 406 } 407 408 if (err) 409 goto err_out_unregister_bus; 410 } 411 } else { 412 for (i = 0; i < PHY_MAX_ADDR; i++) 413 bp->mii_bus->irq[i] = PHY_POLL; 414 415 if (pdata) 416 bp->mii_bus->phy_mask = pdata->phy_mask; 417 418 err = mdiobus_register(bp->mii_bus); 419 } 420 421 if (err) 422 goto err_out_free_mdio_irq; 423 424 err = macb_mii_probe(bp->dev); 425 if (err) 426 goto err_out_unregister_bus; 427 428 return 0; 429 430err_out_unregister_bus: 431 mdiobus_unregister(bp->mii_bus); 432err_out_free_mdio_irq: 433 kfree(bp->mii_bus->irq); 434err_out_free_mdiobus: 435 mdiobus_free(bp->mii_bus); 436err_out: 437 return err; 438} 439EXPORT_SYMBOL_GPL(macb_mii_init); 440 441static void macb_update_stats(struct macb *bp) 442{ 443 u32 __iomem *reg = bp->regs + MACB_PFR; 444 u32 *p = &bp->hw_stats.macb.rx_pause_frames; 445 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; 446 447 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); 448 449 for(; p < end; p++, reg++) 450 *p += __raw_readl(reg); 451} 452 453static int macb_halt_tx(struct macb *bp) 454{ 455 unsigned long halt_time, timeout; 456 u32 status; 457 458 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); 459 460 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); 461 do { 462 halt_time = jiffies; 463 status = macb_readl(bp, TSR); 464 if (!(status & MACB_BIT(TGO))) 465 return 0; 466 467 usleep_range(10, 250); 468 } while (time_before(halt_time, timeout)); 469 470 return -ETIMEDOUT; 471} 472 473static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb) 474{ 475 if (tx_skb->mapping) { 476 if (tx_skb->mapped_as_page) 477 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, 478 tx_skb->size, DMA_TO_DEVICE); 479 else 480 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, 481 tx_skb->size, DMA_TO_DEVICE); 482 tx_skb->mapping = 0; 483 } 484 485 if (tx_skb->skb) { 486 dev_kfree_skb_any(tx_skb->skb); 487 tx_skb->skb = NULL; 488 } 489} 490 491static void macb_tx_error_task(struct work_struct *work) 492{ 493 struct macb *bp = container_of(work, struct macb, tx_error_task); 494 struct macb_tx_skb *tx_skb; 495 struct sk_buff *skb; 496 unsigned int tail; 497 498 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n", 499 bp->tx_tail, bp->tx_head); 500 501 /* Make sure nobody is trying to queue up new packets */ 502 netif_stop_queue(bp->dev); 503 504 /* 505 * Stop transmission now 506 * (in case we have just queued new packets) 507 */ 508 if (macb_halt_tx(bp)) 509 /* Just complain for now, reinitializing TX path can be good */ 510 netdev_err(bp->dev, "BUG: halt tx timed out\n"); 511 512 /* No need for the lock here as nobody will interrupt us anymore */ 513 514 /* 515 * Treat frames in TX queue including the ones that caused the error. 516 * Free transmit buffers in upper layer. 517 */ 518 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) { 519 struct macb_dma_desc *desc; 520 u32 ctrl; 521 522 desc = macb_tx_desc(bp, tail); 523 ctrl = desc->ctrl; 524 tx_skb = macb_tx_skb(bp, tail); 525 skb = tx_skb->skb; 526 527 if (ctrl & MACB_BIT(TX_USED)) { 528 /* skb is set for the last buffer of the frame */ 529 while (!skb) { 530 macb_tx_unmap(bp, tx_skb); 531 tail++; 532 tx_skb = macb_tx_skb(bp, tail); 533 skb = tx_skb->skb; 534 } 535 536 /* ctrl still refers to the first buffer descriptor 537 * since it's the only one written back by the hardware 538 */ 539 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) { 540 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", 541 macb_tx_ring_wrap(tail), skb->data); 542 bp->stats.tx_packets++; 543 bp->stats.tx_bytes += skb->len; 544 } 545 } else { 546 /* 547 * "Buffers exhausted mid-frame" errors may only happen 548 * if the driver is buggy, so complain loudly about those. 549 * Statistics are updated by hardware. 550 */ 551 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) 552 netdev_err(bp->dev, 553 "BUG: TX buffers exhausted mid-frame\n"); 554 555 desc->ctrl = ctrl | MACB_BIT(TX_USED); 556 } 557 558 macb_tx_unmap(bp, tx_skb); 559 } 560 561 /* Make descriptor updates visible to hardware */ 562 wmb(); 563 564 /* Reinitialize the TX desc queue */ 565 macb_writel(bp, TBQP, bp->tx_ring_dma); 566 /* Make TX ring reflect state of hardware */ 567 bp->tx_head = bp->tx_tail = 0; 568 569 /* Now we are ready to start transmission again */ 570 netif_wake_queue(bp->dev); 571 572 /* Housework before enabling TX IRQ */ 573 macb_writel(bp, TSR, macb_readl(bp, TSR)); 574 macb_writel(bp, IER, MACB_TX_INT_FLAGS); 575} 576 577static void macb_tx_interrupt(struct macb *bp) 578{ 579 unsigned int tail; 580 unsigned int head; 581 u32 status; 582 583 status = macb_readl(bp, TSR); 584 macb_writel(bp, TSR, status); 585 586 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 587 macb_writel(bp, ISR, MACB_BIT(TCOMP)); 588 589 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", 590 (unsigned long)status); 591 592 head = bp->tx_head; 593 for (tail = bp->tx_tail; tail != head; tail++) { 594 struct macb_tx_skb *tx_skb; 595 struct sk_buff *skb; 596 struct macb_dma_desc *desc; 597 u32 ctrl; 598 599 desc = macb_tx_desc(bp, tail); 600 601 /* Make hw descriptor updates visible to CPU */ 602 rmb(); 603 604 ctrl = desc->ctrl; 605 606 /* TX_USED bit is only set by hardware on the very first buffer 607 * descriptor of the transmitted frame. 608 */ 609 if (!(ctrl & MACB_BIT(TX_USED))) 610 break; 611 612 /* Process all buffers of the current transmitted frame */ 613 for (;; tail++) { 614 tx_skb = macb_tx_skb(bp, tail); 615 skb = tx_skb->skb; 616 617 /* First, update TX stats if needed */ 618 if (skb) { 619 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", 620 macb_tx_ring_wrap(tail), skb->data); 621 bp->stats.tx_packets++; 622 bp->stats.tx_bytes += skb->len; 623 } 624 625 /* Now we can safely release resources */ 626 macb_tx_unmap(bp, tx_skb); 627 628 /* skb is set only for the last buffer of the frame. 629 * WARNING: at this point skb has been freed by 630 * macb_tx_unmap(). 631 */ 632 if (skb) 633 break; 634 } 635 } 636 637 bp->tx_tail = tail; 638 if (netif_queue_stopped(bp->dev) 639 && CIRC_CNT(bp->tx_head, bp->tx_tail, 640 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH) 641 netif_wake_queue(bp->dev); 642} 643 644static void gem_rx_refill(struct macb *bp) 645{ 646 unsigned int entry; 647 struct sk_buff *skb; 648 dma_addr_t paddr; 649 650 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) { 651 entry = macb_rx_ring_wrap(bp->rx_prepared_head); 652 653 /* Make hw descriptor updates visible to CPU */ 654 rmb(); 655 656 bp->rx_prepared_head++; 657 658 if (bp->rx_skbuff[entry] == NULL) { 659 /* allocate sk_buff for this free entry in ring */ 660 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); 661 if (unlikely(skb == NULL)) { 662 netdev_err(bp->dev, 663 "Unable to allocate sk_buff\n"); 664 break; 665 } 666 667 /* now fill corresponding descriptor entry */ 668 paddr = dma_map_single(&bp->pdev->dev, skb->data, 669 bp->rx_buffer_size, DMA_FROM_DEVICE); 670 if (dma_mapping_error(&bp->pdev->dev, paddr)) { 671 dev_kfree_skb(skb); 672 break; 673 } 674 675 bp->rx_skbuff[entry] = skb; 676 677 if (entry == RX_RING_SIZE - 1) 678 paddr |= MACB_BIT(RX_WRAP); 679 bp->rx_ring[entry].addr = paddr; 680 bp->rx_ring[entry].ctrl = 0; 681 682 /* properly align Ethernet header */ 683 skb_reserve(skb, NET_IP_ALIGN); 684 } 685 } 686 687 /* Make descriptor updates visible to hardware */ 688 wmb(); 689 690 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n", 691 bp->rx_prepared_head, bp->rx_tail); 692} 693 694/* Mark DMA descriptors from begin up to and not including end as unused */ 695static void discard_partial_frame(struct macb *bp, unsigned int begin, 696 unsigned int end) 697{ 698 unsigned int frag; 699 700 for (frag = begin; frag != end; frag++) { 701 struct macb_dma_desc *desc = macb_rx_desc(bp, frag); 702 desc->addr &= ~MACB_BIT(RX_USED); 703 } 704 705 /* Make descriptor updates visible to hardware */ 706 wmb(); 707 708 /* 709 * When this happens, the hardware stats registers for 710 * whatever caused this is updated, so we don't have to record 711 * anything. 712 */ 713} 714 715static int gem_rx(struct macb *bp, int budget) 716{ 717 unsigned int len; 718 unsigned int entry; 719 struct sk_buff *skb; 720 struct macb_dma_desc *desc; 721 int count = 0; 722 723 while (count < budget) { 724 u32 addr, ctrl; 725 726 entry = macb_rx_ring_wrap(bp->rx_tail); 727 desc = &bp->rx_ring[entry]; 728 729 /* Make hw descriptor updates visible to CPU */ 730 rmb(); 731 732 addr = desc->addr; 733 ctrl = desc->ctrl; 734 735 if (!(addr & MACB_BIT(RX_USED))) 736 break; 737 738 bp->rx_tail++; 739 count++; 740 741 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) { 742 netdev_err(bp->dev, 743 "not whole frame pointed by descriptor\n"); 744 bp->stats.rx_dropped++; 745 break; 746 } 747 skb = bp->rx_skbuff[entry]; 748 if (unlikely(!skb)) { 749 netdev_err(bp->dev, 750 "inconsistent Rx descriptor chain\n"); 751 bp->stats.rx_dropped++; 752 break; 753 } 754 /* now everything is ready for receiving packet */ 755 bp->rx_skbuff[entry] = NULL; 756 len = MACB_BFEXT(RX_FRMLEN, ctrl); 757 758 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); 759 760 skb_put(skb, len); 761 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr)); 762 dma_unmap_single(&bp->pdev->dev, addr, 763 bp->rx_buffer_size, DMA_FROM_DEVICE); 764 765 skb->protocol = eth_type_trans(skb, bp->dev); 766 skb_checksum_none_assert(skb); 767 if (bp->dev->features & NETIF_F_RXCSUM && 768 !(bp->dev->flags & IFF_PROMISC) && 769 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK) 770 skb->ip_summed = CHECKSUM_UNNECESSARY; 771 772 bp->stats.rx_packets++; 773 bp->stats.rx_bytes += skb->len; 774 775#if defined(DEBUG) && defined(VERBOSE_DEBUG) 776 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", 777 skb->len, skb->csum); 778 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, 779 skb->mac_header, 16, true); 780 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, 781 skb->data, 32, true); 782#endif 783 784 netif_receive_skb(skb); 785 } 786 787 gem_rx_refill(bp); 788 789 return count; 790} 791 792static int macb_rx_frame(struct macb *bp, unsigned int first_frag, 793 unsigned int last_frag) 794{ 795 unsigned int len; 796 unsigned int frag; 797 unsigned int offset; 798 struct sk_buff *skb; 799 struct macb_dma_desc *desc; 800 801 desc = macb_rx_desc(bp, last_frag); 802 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); 803 804 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", 805 macb_rx_ring_wrap(first_frag), 806 macb_rx_ring_wrap(last_frag), len); 807 808 /* 809 * The ethernet header starts NET_IP_ALIGN bytes into the 810 * first buffer. Since the header is 14 bytes, this makes the 811 * payload word-aligned. 812 * 813 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy 814 * the two padding bytes into the skb so that we avoid hitting 815 * the slowpath in memcpy(), and pull them off afterwards. 816 */ 817 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); 818 if (!skb) { 819 bp->stats.rx_dropped++; 820 for (frag = first_frag; ; frag++) { 821 desc = macb_rx_desc(bp, frag); 822 desc->addr &= ~MACB_BIT(RX_USED); 823 if (frag == last_frag) 824 break; 825 } 826 827 /* Make descriptor updates visible to hardware */ 828 wmb(); 829 830 return 1; 831 } 832 833 offset = 0; 834 len += NET_IP_ALIGN; 835 skb_checksum_none_assert(skb); 836 skb_put(skb, len); 837 838 for (frag = first_frag; ; frag++) { 839 unsigned int frag_len = bp->rx_buffer_size; 840 841 if (offset + frag_len > len) { 842 BUG_ON(frag != last_frag); 843 frag_len = len - offset; 844 } 845 skb_copy_to_linear_data_offset(skb, offset, 846 macb_rx_buffer(bp, frag), frag_len); 847 offset += bp->rx_buffer_size; 848 desc = macb_rx_desc(bp, frag); 849 desc->addr &= ~MACB_BIT(RX_USED); 850 851 if (frag == last_frag) 852 break; 853 } 854 855 /* Make descriptor updates visible to hardware */ 856 wmb(); 857 858 __skb_pull(skb, NET_IP_ALIGN); 859 skb->protocol = eth_type_trans(skb, bp->dev); 860 861 bp->stats.rx_packets++; 862 bp->stats.rx_bytes += skb->len; 863 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", 864 skb->len, skb->csum); 865 netif_receive_skb(skb); 866 867 return 0; 868} 869 870static int macb_rx(struct macb *bp, int budget) 871{ 872 int received = 0; 873 unsigned int tail; 874 int first_frag = -1; 875 876 for (tail = bp->rx_tail; budget > 0; tail++) { 877 struct macb_dma_desc *desc = macb_rx_desc(bp, tail); 878 u32 addr, ctrl; 879 880 /* Make hw descriptor updates visible to CPU */ 881 rmb(); 882 883 addr = desc->addr; 884 ctrl = desc->ctrl; 885 886 if (!(addr & MACB_BIT(RX_USED))) 887 break; 888 889 if (ctrl & MACB_BIT(RX_SOF)) { 890 if (first_frag != -1) 891 discard_partial_frame(bp, first_frag, tail); 892 first_frag = tail; 893 } 894 895 if (ctrl & MACB_BIT(RX_EOF)) { 896 int dropped; 897 BUG_ON(first_frag == -1); 898 899 dropped = macb_rx_frame(bp, first_frag, tail); 900 first_frag = -1; 901 if (!dropped) { 902 received++; 903 budget--; 904 } 905 } 906 } 907 908 if (first_frag != -1) 909 bp->rx_tail = first_frag; 910 else 911 bp->rx_tail = tail; 912 913 return received; 914} 915 916static int macb_poll(struct napi_struct *napi, int budget) 917{ 918 struct macb *bp = container_of(napi, struct macb, napi); 919 int work_done; 920 u32 status; 921 922 status = macb_readl(bp, RSR); 923 macb_writel(bp, RSR, status); 924 925 work_done = 0; 926 927 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", 928 (unsigned long)status, budget); 929 930 work_done = bp->macbgem_ops.mog_rx(bp, budget); 931 if (work_done < budget) { 932 napi_complete(napi); 933 934 /* Packets received while interrupts were disabled */ 935 status = macb_readl(bp, RSR); 936 if (status) { 937 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 938 macb_writel(bp, ISR, MACB_BIT(RCOMP)); 939 napi_reschedule(napi); 940 } else { 941 macb_writel(bp, IER, MACB_RX_INT_FLAGS); 942 } 943 } 944 945 /* TODO: Handle errors */ 946 947 return work_done; 948} 949 950static irqreturn_t macb_interrupt(int irq, void *dev_id) 951{ 952 struct net_device *dev = dev_id; 953 struct macb *bp = netdev_priv(dev); 954 u32 status; 955 956 status = macb_readl(bp, ISR); 957 958 if (unlikely(!status)) 959 return IRQ_NONE; 960 961 spin_lock(&bp->lock); 962 963 while (status) { 964 /* close possible race with dev_close */ 965 if (unlikely(!netif_running(dev))) { 966 macb_writel(bp, IDR, -1); 967 break; 968 } 969 970 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status); 971 972 if (status & MACB_RX_INT_FLAGS) { 973 /* 974 * There's no point taking any more interrupts 975 * until we have processed the buffers. The 976 * scheduling call may fail if the poll routine 977 * is already scheduled, so disable interrupts 978 * now. 979 */ 980 macb_writel(bp, IDR, MACB_RX_INT_FLAGS); 981 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 982 macb_writel(bp, ISR, MACB_BIT(RCOMP)); 983 984 if (napi_schedule_prep(&bp->napi)) { 985 netdev_vdbg(bp->dev, "scheduling RX softirq\n"); 986 __napi_schedule(&bp->napi); 987 } 988 } 989 990 if (unlikely(status & (MACB_TX_ERR_FLAGS))) { 991 macb_writel(bp, IDR, MACB_TX_INT_FLAGS); 992 schedule_work(&bp->tx_error_task); 993 994 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 995 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS); 996 997 break; 998 } 999 1000 if (status & MACB_BIT(TCOMP)) 1001 macb_tx_interrupt(bp); 1002 1003 /* 1004 * Link change detection isn't possible with RMII, so we'll 1005 * add that if/when we get our hands on a full-blown MII PHY. 1006 */ 1007 1008 if (status & MACB_BIT(ISR_ROVR)) { 1009 /* We missed at least one packet */ 1010 if (macb_is_gem(bp)) 1011 bp->hw_stats.gem.rx_overruns++; 1012 else 1013 bp->hw_stats.macb.rx_overruns++; 1014 1015 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1016 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR)); 1017 } 1018 1019 if (status & MACB_BIT(HRESP)) { 1020 /* 1021 * TODO: Reset the hardware, and maybe move the 1022 * netdev_err to a lower-priority context as well 1023 * (work queue?) 1024 */ 1025 netdev_err(dev, "DMA bus error: HRESP not OK\n"); 1026 1027 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) 1028 macb_writel(bp, ISR, MACB_BIT(HRESP)); 1029 } 1030 1031 status = macb_readl(bp, ISR); 1032 } 1033 1034 spin_unlock(&bp->lock); 1035 1036 return IRQ_HANDLED; 1037} 1038 1039#ifdef CONFIG_NET_POLL_CONTROLLER 1040/* 1041 * Polling receive - used by netconsole and other diagnostic tools 1042 * to allow network i/o with interrupts disabled. 1043 */ 1044static void macb_poll_controller(struct net_device *dev) 1045{ 1046 unsigned long flags; 1047 1048 local_irq_save(flags); 1049 macb_interrupt(dev->irq, dev); 1050 local_irq_restore(flags); 1051} 1052#endif 1053 1054static inline unsigned int macb_count_tx_descriptors(struct macb *bp, 1055 unsigned int len) 1056{ 1057 return (len + bp->max_tx_length - 1) / bp->max_tx_length; 1058} 1059 1060static unsigned int macb_tx_map(struct macb *bp, 1061 struct sk_buff *skb) 1062{ 1063 dma_addr_t mapping; 1064 unsigned int len, entry, i, tx_head = bp->tx_head; 1065 struct macb_tx_skb *tx_skb = NULL; 1066 struct macb_dma_desc *desc; 1067 unsigned int offset, size, count = 0; 1068 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; 1069 unsigned int eof = 1; 1070 u32 ctrl; 1071 1072 /* First, map non-paged data */ 1073 len = skb_headlen(skb); 1074 offset = 0; 1075 while (len) { 1076 size = min(len, bp->max_tx_length); 1077 entry = macb_tx_ring_wrap(tx_head); 1078 tx_skb = &bp->tx_skb[entry]; 1079 1080 mapping = dma_map_single(&bp->pdev->dev, 1081 skb->data + offset, 1082 size, DMA_TO_DEVICE); 1083 if (dma_mapping_error(&bp->pdev->dev, mapping)) 1084 goto dma_error; 1085 1086 /* Save info to properly release resources */ 1087 tx_skb->skb = NULL; 1088 tx_skb->mapping = mapping; 1089 tx_skb->size = size; 1090 tx_skb->mapped_as_page = false; 1091 1092 len -= size; 1093 offset += size; 1094 count++; 1095 tx_head++; 1096 } 1097 1098 /* Then, map paged data from fragments */ 1099 for (f = 0; f < nr_frags; f++) { 1100 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1101 1102 len = skb_frag_size(frag); 1103 offset = 0; 1104 while (len) { 1105 size = min(len, bp->max_tx_length); 1106 entry = macb_tx_ring_wrap(tx_head); 1107 tx_skb = &bp->tx_skb[entry]; 1108 1109 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 1110 offset, size, DMA_TO_DEVICE); 1111 if (dma_mapping_error(&bp->pdev->dev, mapping)) 1112 goto dma_error; 1113 1114 /* Save info to properly release resources */ 1115 tx_skb->skb = NULL; 1116 tx_skb->mapping = mapping; 1117 tx_skb->size = size; 1118 tx_skb->mapped_as_page = true; 1119 1120 len -= size; 1121 offset += size; 1122 count++; 1123 tx_head++; 1124 } 1125 } 1126 1127 /* Should never happen */ 1128 if (unlikely(tx_skb == NULL)) { 1129 netdev_err(bp->dev, "BUG! empty skb!\n"); 1130 return 0; 1131 } 1132 1133 /* This is the last buffer of the frame: save socket buffer */ 1134 tx_skb->skb = skb; 1135 1136 /* Update TX ring: update buffer descriptors in reverse order 1137 * to avoid race condition 1138 */ 1139 1140 /* Set 'TX_USED' bit in buffer descriptor at tx_head position 1141 * to set the end of TX queue 1142 */ 1143 i = tx_head; 1144 entry = macb_tx_ring_wrap(i); 1145 ctrl = MACB_BIT(TX_USED); 1146 desc = &bp->tx_ring[entry]; 1147 desc->ctrl = ctrl; 1148 1149 do { 1150 i--; 1151 entry = macb_tx_ring_wrap(i); 1152 tx_skb = &bp->tx_skb[entry]; 1153 desc = &bp->tx_ring[entry]; 1154 1155 ctrl = (u32)tx_skb->size; 1156 if (eof) { 1157 ctrl |= MACB_BIT(TX_LAST); 1158 eof = 0; 1159 } 1160 if (unlikely(entry == (TX_RING_SIZE - 1))) 1161 ctrl |= MACB_BIT(TX_WRAP); 1162 1163 /* Set TX buffer descriptor */ 1164 desc->addr = tx_skb->mapping; 1165 /* desc->addr must be visible to hardware before clearing 1166 * 'TX_USED' bit in desc->ctrl. 1167 */ 1168 wmb(); 1169 desc->ctrl = ctrl; 1170 } while (i != bp->tx_head); 1171 1172 bp->tx_head = tx_head; 1173 1174 return count; 1175 1176dma_error: 1177 netdev_err(bp->dev, "TX DMA map failed\n"); 1178 1179 for (i = bp->tx_head; i != tx_head; i++) { 1180 tx_skb = macb_tx_skb(bp, i); 1181 1182 macb_tx_unmap(bp, tx_skb); 1183 } 1184 1185 return 0; 1186} 1187 1188static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) 1189{ 1190 struct macb *bp = netdev_priv(dev); 1191 unsigned long flags; 1192 unsigned int count, nr_frags, frag_size, f; 1193 1194#if defined(DEBUG) && defined(VERBOSE_DEBUG) 1195 netdev_vdbg(bp->dev, 1196 "start_xmit: len %u head %p data %p tail %p end %p\n", 1197 skb->len, skb->head, skb->data, 1198 skb_tail_pointer(skb), skb_end_pointer(skb)); 1199 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, 1200 skb->data, 16, true); 1201#endif 1202 1203 /* Count how many TX buffer descriptors are needed to send this 1204 * socket buffer: skb fragments of jumbo frames may need to be 1205 * splitted into many buffer descriptors. 1206 */ 1207 count = macb_count_tx_descriptors(bp, skb_headlen(skb)); 1208 nr_frags = skb_shinfo(skb)->nr_frags; 1209 for (f = 0; f < nr_frags; f++) { 1210 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); 1211 count += macb_count_tx_descriptors(bp, frag_size); 1212 } 1213 1214 spin_lock_irqsave(&bp->lock, flags); 1215 1216 /* This is a hard error, log it. */ 1217 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < count) { 1218 netif_stop_queue(dev); 1219 spin_unlock_irqrestore(&bp->lock, flags); 1220 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", 1221 bp->tx_head, bp->tx_tail); 1222 return NETDEV_TX_BUSY; 1223 } 1224 1225 /* Map socket buffer for DMA transfer */ 1226 if (!macb_tx_map(bp, skb)) { 1227 dev_kfree_skb_any(skb); 1228 goto unlock; 1229 } 1230 1231 /* Make newly initialized descriptor visible to hardware */ 1232 wmb(); 1233 1234 skb_tx_timestamp(skb); 1235 1236 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); 1237 1238 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) 1239 netif_stop_queue(dev); 1240 1241unlock: 1242 spin_unlock_irqrestore(&bp->lock, flags); 1243 1244 return NETDEV_TX_OK; 1245} 1246 1247static void macb_init_rx_buffer_size(struct macb *bp, size_t size) 1248{ 1249 if (!macb_is_gem(bp)) { 1250 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; 1251 } else { 1252 bp->rx_buffer_size = size; 1253 1254 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { 1255 netdev_dbg(bp->dev, 1256 "RX buffer must be multiple of %d bytes, expanding\n", 1257 RX_BUFFER_MULTIPLE); 1258 bp->rx_buffer_size = 1259 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); 1260 } 1261 } 1262 1263 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n", 1264 bp->dev->mtu, bp->rx_buffer_size); 1265} 1266 1267static void gem_free_rx_buffers(struct macb *bp) 1268{ 1269 struct sk_buff *skb; 1270 struct macb_dma_desc *desc; 1271 dma_addr_t addr; 1272 int i; 1273 1274 if (!bp->rx_skbuff) 1275 return; 1276 1277 for (i = 0; i < RX_RING_SIZE; i++) { 1278 skb = bp->rx_skbuff[i]; 1279 1280 if (skb == NULL) 1281 continue; 1282 1283 desc = &bp->rx_ring[i]; 1284 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); 1285 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, 1286 DMA_FROM_DEVICE); 1287 dev_kfree_skb_any(skb); 1288 skb = NULL; 1289 } 1290 1291 kfree(bp->rx_skbuff); 1292 bp->rx_skbuff = NULL; 1293} 1294 1295static void macb_free_rx_buffers(struct macb *bp) 1296{ 1297 if (bp->rx_buffers) { 1298 dma_free_coherent(&bp->pdev->dev, 1299 RX_RING_SIZE * bp->rx_buffer_size, 1300 bp->rx_buffers, bp->rx_buffers_dma); 1301 bp->rx_buffers = NULL; 1302 } 1303} 1304 1305static void macb_free_consistent(struct macb *bp) 1306{ 1307 if (bp->tx_skb) { 1308 kfree(bp->tx_skb); 1309 bp->tx_skb = NULL; 1310 } 1311 bp->macbgem_ops.mog_free_rx_buffers(bp); 1312 if (bp->rx_ring) { 1313 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, 1314 bp->rx_ring, bp->rx_ring_dma); 1315 bp->rx_ring = NULL; 1316 } 1317 if (bp->tx_ring) { 1318 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, 1319 bp->tx_ring, bp->tx_ring_dma); 1320 bp->tx_ring = NULL; 1321 } 1322} 1323 1324static int gem_alloc_rx_buffers(struct macb *bp) 1325{ 1326 int size; 1327 1328 size = RX_RING_SIZE * sizeof(struct sk_buff *); 1329 bp->rx_skbuff = kzalloc(size, GFP_KERNEL); 1330 if (!bp->rx_skbuff) 1331 return -ENOMEM; 1332 else 1333 netdev_dbg(bp->dev, 1334 "Allocated %d RX struct sk_buff entries at %p\n", 1335 RX_RING_SIZE, bp->rx_skbuff); 1336 return 0; 1337} 1338 1339static int macb_alloc_rx_buffers(struct macb *bp) 1340{ 1341 int size; 1342 1343 size = RX_RING_SIZE * bp->rx_buffer_size; 1344 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, 1345 &bp->rx_buffers_dma, GFP_KERNEL); 1346 if (!bp->rx_buffers) 1347 return -ENOMEM; 1348 else 1349 netdev_dbg(bp->dev, 1350 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", 1351 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); 1352 return 0; 1353} 1354 1355static int macb_alloc_consistent(struct macb *bp) 1356{ 1357 int size; 1358 1359 size = TX_RING_SIZE * sizeof(struct macb_tx_skb); 1360 bp->tx_skb = kmalloc(size, GFP_KERNEL); 1361 if (!bp->tx_skb) 1362 goto out_err; 1363 1364 size = RX_RING_BYTES; 1365 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 1366 &bp->rx_ring_dma, GFP_KERNEL); 1367 if (!bp->rx_ring) 1368 goto out_err; 1369 netdev_dbg(bp->dev, 1370 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", 1371 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); 1372 1373 size = TX_RING_BYTES; 1374 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, 1375 &bp->tx_ring_dma, GFP_KERNEL); 1376 if (!bp->tx_ring) 1377 goto out_err; 1378 netdev_dbg(bp->dev, 1379 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", 1380 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); 1381 1382 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) 1383 goto out_err; 1384 1385 return 0; 1386 1387out_err: 1388 macb_free_consistent(bp); 1389 return -ENOMEM; 1390} 1391 1392static void gem_init_rings(struct macb *bp) 1393{ 1394 int i; 1395 1396 for (i = 0; i < TX_RING_SIZE; i++) { 1397 bp->tx_ring[i].addr = 0; 1398 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); 1399 } 1400 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); 1401 1402 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0; 1403 1404 gem_rx_refill(bp); 1405} 1406 1407static void macb_init_rings(struct macb *bp) 1408{ 1409 int i; 1410 dma_addr_t addr; 1411 1412 addr = bp->rx_buffers_dma; 1413 for (i = 0; i < RX_RING_SIZE; i++) { 1414 bp->rx_ring[i].addr = addr; 1415 bp->rx_ring[i].ctrl = 0; 1416 addr += bp->rx_buffer_size; 1417 } 1418 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); 1419 1420 for (i = 0; i < TX_RING_SIZE; i++) { 1421 bp->tx_ring[i].addr = 0; 1422 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); 1423 } 1424 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); 1425 1426 bp->rx_tail = bp->tx_head = bp->tx_tail = 0; 1427} 1428 1429static void macb_reset_hw(struct macb *bp) 1430{ 1431 /* 1432 * Disable RX and TX (XXX: Should we halt the transmission 1433 * more gracefully?) 1434 */ 1435 macb_writel(bp, NCR, 0); 1436 1437 /* Clear the stats registers (XXX: Update stats first?) */ 1438 macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); 1439 1440 /* Clear all status flags */ 1441 macb_writel(bp, TSR, -1); 1442 macb_writel(bp, RSR, -1); 1443 1444 /* Disable all interrupts */ 1445 macb_writel(bp, IDR, -1); 1446 macb_readl(bp, ISR); 1447} 1448 1449static u32 gem_mdc_clk_div(struct macb *bp) 1450{ 1451 u32 config; 1452 unsigned long pclk_hz = clk_get_rate(bp->pclk); 1453 1454 if (pclk_hz <= 20000000) 1455 config = GEM_BF(CLK, GEM_CLK_DIV8); 1456 else if (pclk_hz <= 40000000) 1457 config = GEM_BF(CLK, GEM_CLK_DIV16); 1458 else if (pclk_hz <= 80000000) 1459 config = GEM_BF(CLK, GEM_CLK_DIV32); 1460 else if (pclk_hz <= 120000000) 1461 config = GEM_BF(CLK, GEM_CLK_DIV48); 1462 else if (pclk_hz <= 160000000) 1463 config = GEM_BF(CLK, GEM_CLK_DIV64); 1464 else 1465 config = GEM_BF(CLK, GEM_CLK_DIV96); 1466 1467 return config; 1468} 1469 1470static u32 macb_mdc_clk_div(struct macb *bp) 1471{ 1472 u32 config; 1473 unsigned long pclk_hz; 1474 1475 if (macb_is_gem(bp)) 1476 return gem_mdc_clk_div(bp); 1477 1478 pclk_hz = clk_get_rate(bp->pclk); 1479 if (pclk_hz <= 20000000) 1480 config = MACB_BF(CLK, MACB_CLK_DIV8); 1481 else if (pclk_hz <= 40000000) 1482 config = MACB_BF(CLK, MACB_CLK_DIV16); 1483 else if (pclk_hz <= 80000000) 1484 config = MACB_BF(CLK, MACB_CLK_DIV32); 1485 else 1486 config = MACB_BF(CLK, MACB_CLK_DIV64); 1487 1488 return config; 1489} 1490 1491/* 1492 * Get the DMA bus width field of the network configuration register that we 1493 * should program. We find the width from decoding the design configuration 1494 * register to find the maximum supported data bus width. 1495 */ 1496static u32 macb_dbw(struct macb *bp) 1497{ 1498 if (!macb_is_gem(bp)) 1499 return 0; 1500 1501 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { 1502 case 4: 1503 return GEM_BF(DBW, GEM_DBW128); 1504 case 2: 1505 return GEM_BF(DBW, GEM_DBW64); 1506 case 1: 1507 default: 1508 return GEM_BF(DBW, GEM_DBW32); 1509 } 1510} 1511 1512/* 1513 * Configure the receive DMA engine 1514 * - use the correct receive buffer size 1515 * - set best burst length for DMA operations 1516 * (if not supported by FIFO, it will fallback to default) 1517 * - set both rx/tx packet buffers to full memory size 1518 * These are configurable parameters for GEM. 1519 */ 1520static void macb_configure_dma(struct macb *bp) 1521{ 1522 u32 dmacfg; 1523 1524 if (macb_is_gem(bp)) { 1525 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); 1526 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE); 1527 if (bp->dma_burst_length) 1528 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); 1529 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); 1530 dmacfg &= ~GEM_BIT(ENDIA); 1531 if (bp->dev->features & NETIF_F_HW_CSUM) 1532 dmacfg |= GEM_BIT(TXCOEN); 1533 else 1534 dmacfg &= ~GEM_BIT(TXCOEN); 1535 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", 1536 dmacfg); 1537 gem_writel(bp, DMACFG, dmacfg); 1538 } 1539} 1540 1541static void macb_init_hw(struct macb *bp) 1542{ 1543 u32 config; 1544 1545 macb_reset_hw(bp); 1546 macb_set_hwaddr(bp); 1547 1548 config = macb_mdc_clk_div(bp); 1549 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ 1550 config |= MACB_BIT(PAE); /* PAuse Enable */ 1551 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ 1552 config |= MACB_BIT(BIG); /* Receive oversized frames */ 1553 if (bp->dev->flags & IFF_PROMISC) 1554 config |= MACB_BIT(CAF); /* Copy All Frames */ 1555 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) 1556 config |= GEM_BIT(RXCOEN); 1557 if (!(bp->dev->flags & IFF_BROADCAST)) 1558 config |= MACB_BIT(NBC); /* No BroadCast */ 1559 config |= macb_dbw(bp); 1560 macb_writel(bp, NCFGR, config); 1561 bp->speed = SPEED_10; 1562 bp->duplex = DUPLEX_HALF; 1563 1564 macb_configure_dma(bp); 1565 1566 /* Initialize TX and RX buffers */ 1567 macb_writel(bp, RBQP, bp->rx_ring_dma); 1568 macb_writel(bp, TBQP, bp->tx_ring_dma); 1569 1570 /* Enable TX and RX */ 1571 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); 1572 1573 /* Enable interrupts */ 1574 macb_writel(bp, IER, (MACB_RX_INT_FLAGS 1575 | MACB_TX_INT_FLAGS 1576 | MACB_BIT(HRESP))); 1577 1578} 1579 1580/* 1581 * The hash address register is 64 bits long and takes up two 1582 * locations in the memory map. The least significant bits are stored 1583 * in EMAC_HSL and the most significant bits in EMAC_HSH. 1584 * 1585 * The unicast hash enable and the multicast hash enable bits in the 1586 * network configuration register enable the reception of hash matched 1587 * frames. The destination address is reduced to a 6 bit index into 1588 * the 64 bit hash register using the following hash function. The 1589 * hash function is an exclusive or of every sixth bit of the 1590 * destination address. 1591 * 1592 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] 1593 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] 1594 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] 1595 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] 1596 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] 1597 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] 1598 * 1599 * da[0] represents the least significant bit of the first byte 1600 * received, that is, the multicast/unicast indicator, and da[47] 1601 * represents the most significant bit of the last byte received. If 1602 * the hash index, hi[n], points to a bit that is set in the hash 1603 * register then the frame will be matched according to whether the 1604 * frame is multicast or unicast. A multicast match will be signalled 1605 * if the multicast hash enable bit is set, da[0] is 1 and the hash 1606 * index points to a bit set in the hash register. A unicast match 1607 * will be signalled if the unicast hash enable bit is set, da[0] is 0 1608 * and the hash index points to a bit set in the hash register. To 1609 * receive all multicast frames, the hash register should be set with 1610 * all ones and the multicast hash enable bit should be set in the 1611 * network configuration register. 1612 */ 1613 1614static inline int hash_bit_value(int bitnr, __u8 *addr) 1615{ 1616 if (addr[bitnr / 8] & (1 << (bitnr % 8))) 1617 return 1; 1618 return 0; 1619} 1620 1621/* 1622 * Return the hash index value for the specified address. 1623 */ 1624static int hash_get_index(__u8 *addr) 1625{ 1626 int i, j, bitval; 1627 int hash_index = 0; 1628 1629 for (j = 0; j < 6; j++) { 1630 for (i = 0, bitval = 0; i < 8; i++) 1631 bitval ^= hash_bit_value(i*6 + j, addr); 1632 1633 hash_index |= (bitval << j); 1634 } 1635 1636 return hash_index; 1637} 1638 1639/* 1640 * Add multicast addresses to the internal multicast-hash table. 1641 */ 1642static void macb_sethashtable(struct net_device *dev) 1643{ 1644 struct netdev_hw_addr *ha; 1645 unsigned long mc_filter[2]; 1646 unsigned int bitnr; 1647 struct macb *bp = netdev_priv(dev); 1648 1649 mc_filter[0] = mc_filter[1] = 0; 1650 1651 netdev_for_each_mc_addr(ha, dev) { 1652 bitnr = hash_get_index(ha->addr); 1653 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); 1654 } 1655 1656 macb_or_gem_writel(bp, HRB, mc_filter[0]); 1657 macb_or_gem_writel(bp, HRT, mc_filter[1]); 1658} 1659 1660/* 1661 * Enable/Disable promiscuous and multicast modes. 1662 */ 1663void macb_set_rx_mode(struct net_device *dev) 1664{ 1665 unsigned long cfg; 1666 struct macb *bp = netdev_priv(dev); 1667 1668 cfg = macb_readl(bp, NCFGR); 1669 1670 if (dev->flags & IFF_PROMISC) { 1671 /* Enable promiscuous mode */ 1672 cfg |= MACB_BIT(CAF); 1673 1674 /* Disable RX checksum offload */ 1675 if (macb_is_gem(bp)) 1676 cfg &= ~GEM_BIT(RXCOEN); 1677 } else { 1678 /* Disable promiscuous mode */ 1679 cfg &= ~MACB_BIT(CAF); 1680 1681 /* Enable RX checksum offload only if requested */ 1682 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) 1683 cfg |= GEM_BIT(RXCOEN); 1684 } 1685 1686 if (dev->flags & IFF_ALLMULTI) { 1687 /* Enable all multicast mode */ 1688 macb_or_gem_writel(bp, HRB, -1); 1689 macb_or_gem_writel(bp, HRT, -1); 1690 cfg |= MACB_BIT(NCFGR_MTI); 1691 } else if (!netdev_mc_empty(dev)) { 1692 /* Enable specific multicasts */ 1693 macb_sethashtable(dev); 1694 cfg |= MACB_BIT(NCFGR_MTI); 1695 } else if (dev->flags & (~IFF_ALLMULTI)) { 1696 /* Disable all multicast mode */ 1697 macb_or_gem_writel(bp, HRB, 0); 1698 macb_or_gem_writel(bp, HRT, 0); 1699 cfg &= ~MACB_BIT(NCFGR_MTI); 1700 } 1701 1702 macb_writel(bp, NCFGR, cfg); 1703} 1704EXPORT_SYMBOL_GPL(macb_set_rx_mode); 1705 1706static int macb_open(struct net_device *dev) 1707{ 1708 struct macb *bp = netdev_priv(dev); 1709 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; 1710 int err; 1711 1712 netdev_dbg(bp->dev, "open\n"); 1713 1714 /* carrier starts down */ 1715 netif_carrier_off(dev); 1716 1717 /* if the phy is not yet register, retry later*/ 1718 if (!bp->phy_dev) 1719 return -EAGAIN; 1720 1721 /* RX buffers initialization */ 1722 macb_init_rx_buffer_size(bp, bufsz); 1723 1724 err = macb_alloc_consistent(bp); 1725 if (err) { 1726 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", 1727 err); 1728 return err; 1729 } 1730 1731 napi_enable(&bp->napi); 1732 1733 bp->macbgem_ops.mog_init_rings(bp); 1734 macb_init_hw(bp); 1735 1736 /* schedule a link state check */ 1737 phy_start(bp->phy_dev); 1738 1739 netif_start_queue(dev); 1740 1741 return 0; 1742} 1743 1744static int macb_close(struct net_device *dev) 1745{ 1746 struct macb *bp = netdev_priv(dev); 1747 unsigned long flags; 1748 1749 netif_stop_queue(dev); 1750 napi_disable(&bp->napi); 1751 1752 if (bp->phy_dev) 1753 phy_stop(bp->phy_dev); 1754 1755 spin_lock_irqsave(&bp->lock, flags); 1756 macb_reset_hw(bp); 1757 netif_carrier_off(dev); 1758 spin_unlock_irqrestore(&bp->lock, flags); 1759 1760 macb_free_consistent(bp); 1761 1762 return 0; 1763} 1764 1765static void gem_update_stats(struct macb *bp) 1766{ 1767 u32 __iomem *reg = bp->regs + GEM_OTX; 1768 u32 *p = &bp->hw_stats.gem.tx_octets_31_0; 1769 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; 1770 1771 for (; p < end; p++, reg++) 1772 *p += __raw_readl(reg); 1773} 1774 1775static struct net_device_stats *gem_get_stats(struct macb *bp) 1776{ 1777 struct gem_stats *hwstat = &bp->hw_stats.gem; 1778 struct net_device_stats *nstat = &bp->stats; 1779 1780 gem_update_stats(bp); 1781 1782 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + 1783 hwstat->rx_alignment_errors + 1784 hwstat->rx_resource_errors + 1785 hwstat->rx_overruns + 1786 hwstat->rx_oversize_frames + 1787 hwstat->rx_jabbers + 1788 hwstat->rx_undersized_frames + 1789 hwstat->rx_length_field_frame_errors); 1790 nstat->tx_errors = (hwstat->tx_late_collisions + 1791 hwstat->tx_excessive_collisions + 1792 hwstat->tx_underrun + 1793 hwstat->tx_carrier_sense_errors); 1794 nstat->multicast = hwstat->rx_multicast_frames; 1795 nstat->collisions = (hwstat->tx_single_collision_frames + 1796 hwstat->tx_multiple_collision_frames + 1797 hwstat->tx_excessive_collisions); 1798 nstat->rx_length_errors = (hwstat->rx_oversize_frames + 1799 hwstat->rx_jabbers + 1800 hwstat->rx_undersized_frames + 1801 hwstat->rx_length_field_frame_errors); 1802 nstat->rx_over_errors = hwstat->rx_resource_errors; 1803 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; 1804 nstat->rx_frame_errors = hwstat->rx_alignment_errors; 1805 nstat->rx_fifo_errors = hwstat->rx_overruns; 1806 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; 1807 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; 1808 nstat->tx_fifo_errors = hwstat->tx_underrun; 1809 1810 return nstat; 1811} 1812 1813struct net_device_stats *macb_get_stats(struct net_device *dev) 1814{ 1815 struct macb *bp = netdev_priv(dev); 1816 struct net_device_stats *nstat = &bp->stats; 1817 struct macb_stats *hwstat = &bp->hw_stats.macb; 1818 1819 if (macb_is_gem(bp)) 1820 return gem_get_stats(bp); 1821 1822 /* read stats from hardware */ 1823 macb_update_stats(bp); 1824 1825 /* Convert HW stats into netdevice stats */ 1826 nstat->rx_errors = (hwstat->rx_fcs_errors + 1827 hwstat->rx_align_errors + 1828 hwstat->rx_resource_errors + 1829 hwstat->rx_overruns + 1830 hwstat->rx_oversize_pkts + 1831 hwstat->rx_jabbers + 1832 hwstat->rx_undersize_pkts + 1833 hwstat->sqe_test_errors + 1834 hwstat->rx_length_mismatch); 1835 nstat->tx_errors = (hwstat->tx_late_cols + 1836 hwstat->tx_excessive_cols + 1837 hwstat->tx_underruns + 1838 hwstat->tx_carrier_errors); 1839 nstat->collisions = (hwstat->tx_single_cols + 1840 hwstat->tx_multiple_cols + 1841 hwstat->tx_excessive_cols); 1842 nstat->rx_length_errors = (hwstat->rx_oversize_pkts + 1843 hwstat->rx_jabbers + 1844 hwstat->rx_undersize_pkts + 1845 hwstat->rx_length_mismatch); 1846 nstat->rx_over_errors = hwstat->rx_resource_errors + 1847 hwstat->rx_overruns; 1848 nstat->rx_crc_errors = hwstat->rx_fcs_errors; 1849 nstat->rx_frame_errors = hwstat->rx_align_errors; 1850 nstat->rx_fifo_errors = hwstat->rx_overruns; 1851 /* XXX: What does "missed" mean? */ 1852 nstat->tx_aborted_errors = hwstat->tx_excessive_cols; 1853 nstat->tx_carrier_errors = hwstat->tx_carrier_errors; 1854 nstat->tx_fifo_errors = hwstat->tx_underruns; 1855 /* Don't know about heartbeat or window errors... */ 1856 1857 return nstat; 1858} 1859EXPORT_SYMBOL_GPL(macb_get_stats); 1860 1861static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1862{ 1863 struct macb *bp = netdev_priv(dev); 1864 struct phy_device *phydev = bp->phy_dev; 1865 1866 if (!phydev) 1867 return -ENODEV; 1868 1869 return phy_ethtool_gset(phydev, cmd); 1870} 1871 1872static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1873{ 1874 struct macb *bp = netdev_priv(dev); 1875 struct phy_device *phydev = bp->phy_dev; 1876 1877 if (!phydev) 1878 return -ENODEV; 1879 1880 return phy_ethtool_sset(phydev, cmd); 1881} 1882 1883static int macb_get_regs_len(struct net_device *netdev) 1884{ 1885 return MACB_GREGS_NBR * sizeof(u32); 1886} 1887 1888static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1889 void *p) 1890{ 1891 struct macb *bp = netdev_priv(dev); 1892 unsigned int tail, head; 1893 u32 *regs_buff = p; 1894 1895 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) 1896 | MACB_GREGS_VERSION; 1897 1898 tail = macb_tx_ring_wrap(bp->tx_tail); 1899 head = macb_tx_ring_wrap(bp->tx_head); 1900 1901 regs_buff[0] = macb_readl(bp, NCR); 1902 regs_buff[1] = macb_or_gem_readl(bp, NCFGR); 1903 regs_buff[2] = macb_readl(bp, NSR); 1904 regs_buff[3] = macb_readl(bp, TSR); 1905 regs_buff[4] = macb_readl(bp, RBQP); 1906 regs_buff[5] = macb_readl(bp, TBQP); 1907 regs_buff[6] = macb_readl(bp, RSR); 1908 regs_buff[7] = macb_readl(bp, IMR); 1909 1910 regs_buff[8] = tail; 1911 regs_buff[9] = head; 1912 regs_buff[10] = macb_tx_dma(bp, tail); 1913 regs_buff[11] = macb_tx_dma(bp, head); 1914 1915 if (macb_is_gem(bp)) { 1916 regs_buff[12] = gem_readl(bp, USRIO); 1917 regs_buff[13] = gem_readl(bp, DMACFG); 1918 } 1919} 1920 1921const struct ethtool_ops macb_ethtool_ops = { 1922 .get_settings = macb_get_settings, 1923 .set_settings = macb_set_settings, 1924 .get_regs_len = macb_get_regs_len, 1925 .get_regs = macb_get_regs, 1926 .get_link = ethtool_op_get_link, 1927 .get_ts_info = ethtool_op_get_ts_info, 1928}; 1929EXPORT_SYMBOL_GPL(macb_ethtool_ops); 1930 1931int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1932{ 1933 struct macb *bp = netdev_priv(dev); 1934 struct phy_device *phydev = bp->phy_dev; 1935 1936 if (!netif_running(dev)) 1937 return -EINVAL; 1938 1939 if (!phydev) 1940 return -ENODEV; 1941 1942 return phy_mii_ioctl(phydev, rq, cmd); 1943} 1944EXPORT_SYMBOL_GPL(macb_ioctl); 1945 1946static int macb_set_features(struct net_device *netdev, 1947 netdev_features_t features) 1948{ 1949 struct macb *bp = netdev_priv(netdev); 1950 netdev_features_t changed = features ^ netdev->features; 1951 1952 /* TX checksum offload */ 1953 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) { 1954 u32 dmacfg; 1955 1956 dmacfg = gem_readl(bp, DMACFG); 1957 if (features & NETIF_F_HW_CSUM) 1958 dmacfg |= GEM_BIT(TXCOEN); 1959 else 1960 dmacfg &= ~GEM_BIT(TXCOEN); 1961 gem_writel(bp, DMACFG, dmacfg); 1962 } 1963 1964 /* RX checksum offload */ 1965 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) { 1966 u32 netcfg; 1967 1968 netcfg = gem_readl(bp, NCFGR); 1969 if (features & NETIF_F_RXCSUM && 1970 !(netdev->flags & IFF_PROMISC)) 1971 netcfg |= GEM_BIT(RXCOEN); 1972 else 1973 netcfg &= ~GEM_BIT(RXCOEN); 1974 gem_writel(bp, NCFGR, netcfg); 1975 } 1976 1977 return 0; 1978} 1979 1980static const struct net_device_ops macb_netdev_ops = { 1981 .ndo_open = macb_open, 1982 .ndo_stop = macb_close, 1983 .ndo_start_xmit = macb_start_xmit, 1984 .ndo_set_rx_mode = macb_set_rx_mode, 1985 .ndo_get_stats = macb_get_stats, 1986 .ndo_do_ioctl = macb_ioctl, 1987 .ndo_validate_addr = eth_validate_addr, 1988 .ndo_change_mtu = eth_change_mtu, 1989 .ndo_set_mac_address = eth_mac_addr, 1990#ifdef CONFIG_NET_POLL_CONTROLLER 1991 .ndo_poll_controller = macb_poll_controller, 1992#endif 1993 .ndo_set_features = macb_set_features, 1994}; 1995 1996#if defined(CONFIG_OF) 1997static struct macb_config pc302gem_config = { 1998 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, 1999 .dma_burst_length = 16, 2000}; 2001 2002static struct macb_config sama5d3_config = { 2003 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE, 2004 .dma_burst_length = 16, 2005}; 2006 2007static struct macb_config sama5d4_config = { 2008 .caps = 0, 2009 .dma_burst_length = 4, 2010}; 2011 2012static const struct of_device_id macb_dt_ids[] = { 2013 { .compatible = "cdns,at32ap7000-macb" }, 2014 { .compatible = "cdns,at91sam9260-macb" }, 2015 { .compatible = "cdns,macb" }, 2016 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config }, 2017 { .compatible = "cdns,gem", .data = &pc302gem_config }, 2018 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config }, 2019 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config }, 2020 { /* sentinel */ } 2021}; 2022MODULE_DEVICE_TABLE(of, macb_dt_ids); 2023#endif 2024 2025/* 2026 * Configure peripheral capacities according to device tree 2027 * and integration options used 2028 */ 2029static void macb_configure_caps(struct macb *bp) 2030{ 2031 u32 dcfg; 2032 const struct of_device_id *match; 2033 const struct macb_config *config; 2034 2035 if (bp->pdev->dev.of_node) { 2036 match = of_match_node(macb_dt_ids, bp->pdev->dev.of_node); 2037 if (match && match->data) { 2038 config = (const struct macb_config *)match->data; 2039 2040 bp->caps = config->caps; 2041 /* 2042 * As we have access to the matching node, configure 2043 * DMA burst length as well 2044 */ 2045 bp->dma_burst_length = config->dma_burst_length; 2046 } 2047 } 2048 2049 if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2) 2050 bp->caps |= MACB_CAPS_MACB_IS_GEM; 2051 2052 if (macb_is_gem(bp)) { 2053 dcfg = gem_readl(bp, DCFG1); 2054 if (GEM_BFEXT(IRQCOR, dcfg) == 0) 2055 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; 2056 dcfg = gem_readl(bp, DCFG2); 2057 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) 2058 bp->caps |= MACB_CAPS_FIFO_MODE; 2059 } 2060 2061 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps); 2062} 2063 2064static int __init macb_probe(struct platform_device *pdev) 2065{ 2066 struct macb_platform_data *pdata; 2067 struct resource *regs; 2068 struct net_device *dev; 2069 struct macb *bp; 2070 struct phy_device *phydev; 2071 u32 config; 2072 int err = -ENXIO; 2073 const char *mac; 2074 2075 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2076 if (!regs) { 2077 dev_err(&pdev->dev, "no mmio resource defined\n"); 2078 goto err_out; 2079 } 2080 2081 err = -ENOMEM; 2082 dev = alloc_etherdev(sizeof(*bp)); 2083 if (!dev) 2084 goto err_out; 2085 2086 SET_NETDEV_DEV(dev, &pdev->dev); 2087 2088 bp = netdev_priv(dev); 2089 bp->pdev = pdev; 2090 bp->dev = dev; 2091 2092 spin_lock_init(&bp->lock); 2093 INIT_WORK(&bp->tx_error_task, macb_tx_error_task); 2094 2095 bp->pclk = devm_clk_get(&pdev->dev, "pclk"); 2096 if (IS_ERR(bp->pclk)) { 2097 err = PTR_ERR(bp->pclk); 2098 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err); 2099 goto err_out_free_dev; 2100 } 2101 2102 bp->hclk = devm_clk_get(&pdev->dev, "hclk"); 2103 if (IS_ERR(bp->hclk)) { 2104 err = PTR_ERR(bp->hclk); 2105 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err); 2106 goto err_out_free_dev; 2107 } 2108 2109 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk"); 2110 2111 err = clk_prepare_enable(bp->pclk); 2112 if (err) { 2113 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err); 2114 goto err_out_free_dev; 2115 } 2116 2117 err = clk_prepare_enable(bp->hclk); 2118 if (err) { 2119 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err); 2120 goto err_out_disable_pclk; 2121 } 2122 2123 if (!IS_ERR(bp->tx_clk)) { 2124 err = clk_prepare_enable(bp->tx_clk); 2125 if (err) { 2126 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", 2127 err); 2128 goto err_out_disable_hclk; 2129 } 2130 } 2131 2132 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs)); 2133 if (!bp->regs) { 2134 dev_err(&pdev->dev, "failed to map registers, aborting.\n"); 2135 err = -ENOMEM; 2136 goto err_out_disable_clocks; 2137 } 2138 2139 dev->irq = platform_get_irq(pdev, 0); 2140 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0, 2141 dev->name, dev); 2142 if (err) { 2143 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", 2144 dev->irq, err); 2145 goto err_out_disable_clocks; 2146 } 2147 2148 dev->netdev_ops = &macb_netdev_ops; 2149 netif_napi_add(dev, &bp->napi, macb_poll, 64); 2150 dev->ethtool_ops = &macb_ethtool_ops; 2151 2152 dev->base_addr = regs->start; 2153 2154 /* setup capacities */ 2155 macb_configure_caps(bp); 2156 2157 /* setup appropriated routines according to adapter type */ 2158 if (macb_is_gem(bp)) { 2159 bp->max_tx_length = GEM_MAX_TX_LEN; 2160 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; 2161 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; 2162 bp->macbgem_ops.mog_init_rings = gem_init_rings; 2163 bp->macbgem_ops.mog_rx = gem_rx; 2164 } else { 2165 bp->max_tx_length = MACB_MAX_TX_LEN; 2166 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; 2167 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; 2168 bp->macbgem_ops.mog_init_rings = macb_init_rings; 2169 bp->macbgem_ops.mog_rx = macb_rx; 2170 } 2171 2172 /* Set features */ 2173 dev->hw_features = NETIF_F_SG; 2174 /* Checksum offload is only available on gem with packet buffer */ 2175 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) 2176 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; 2177 if (bp->caps & MACB_CAPS_SG_DISABLED) 2178 dev->hw_features &= ~NETIF_F_SG; 2179 dev->features = dev->hw_features; 2180 2181 /* Set MII management clock divider */ 2182 config = macb_mdc_clk_div(bp); 2183 config |= macb_dbw(bp); 2184 macb_writel(bp, NCFGR, config); 2185 2186 mac = of_get_mac_address(pdev->dev.of_node); 2187 if (mac) 2188 memcpy(bp->dev->dev_addr, mac, ETH_ALEN); 2189 else 2190 macb_get_hwaddr(bp); 2191 2192 err = of_get_phy_mode(pdev->dev.of_node); 2193 if (err < 0) { 2194 pdata = dev_get_platdata(&pdev->dev); 2195 if (pdata && pdata->is_rmii) 2196 bp->phy_interface = PHY_INTERFACE_MODE_RMII; 2197 else 2198 bp->phy_interface = PHY_INTERFACE_MODE_MII; 2199 } else { 2200 bp->phy_interface = err; 2201 } 2202 2203 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) 2204 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); 2205 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) 2206#if defined(CONFIG_ARCH_AT91) 2207 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | 2208 MACB_BIT(CLKEN))); 2209#else 2210 macb_or_gem_writel(bp, USRIO, 0); 2211#endif 2212 else 2213#if defined(CONFIG_ARCH_AT91) 2214 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); 2215#else 2216 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); 2217#endif 2218 2219 err = register_netdev(dev); 2220 if (err) { 2221 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 2222 goto err_out_disable_clocks; 2223 } 2224 2225 err = macb_mii_init(bp); 2226 if (err) 2227 goto err_out_unregister_netdev; 2228 2229 platform_set_drvdata(pdev, dev); 2230 2231 netif_carrier_off(dev); 2232 2233 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n", 2234 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID), 2235 dev->base_addr, dev->irq, dev->dev_addr); 2236 2237 phydev = bp->phy_dev; 2238 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 2239 phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 2240 2241 return 0; 2242 2243err_out_unregister_netdev: 2244 unregister_netdev(dev); 2245err_out_disable_clocks: 2246 if (!IS_ERR(bp->tx_clk)) 2247 clk_disable_unprepare(bp->tx_clk); 2248err_out_disable_hclk: 2249 clk_disable_unprepare(bp->hclk); 2250err_out_disable_pclk: 2251 clk_disable_unprepare(bp->pclk); 2252err_out_free_dev: 2253 free_netdev(dev); 2254err_out: 2255 return err; 2256} 2257 2258static int __exit macb_remove(struct platform_device *pdev) 2259{ 2260 struct net_device *dev; 2261 struct macb *bp; 2262 2263 dev = platform_get_drvdata(pdev); 2264 2265 if (dev) { 2266 bp = netdev_priv(dev); 2267 if (bp->phy_dev) 2268 phy_disconnect(bp->phy_dev); 2269 mdiobus_unregister(bp->mii_bus); 2270 kfree(bp->mii_bus->irq); 2271 mdiobus_free(bp->mii_bus); 2272 unregister_netdev(dev); 2273 if (!IS_ERR(bp->tx_clk)) 2274 clk_disable_unprepare(bp->tx_clk); 2275 clk_disable_unprepare(bp->hclk); 2276 clk_disable_unprepare(bp->pclk); 2277 free_netdev(dev); 2278 } 2279 2280 return 0; 2281} 2282 2283#ifdef CONFIG_PM 2284static int macb_suspend(struct device *dev) 2285{ 2286 struct platform_device *pdev = to_platform_device(dev); 2287 struct net_device *netdev = platform_get_drvdata(pdev); 2288 struct macb *bp = netdev_priv(netdev); 2289 2290 netif_carrier_off(netdev); 2291 netif_device_detach(netdev); 2292 2293 if (!IS_ERR(bp->tx_clk)) 2294 clk_disable_unprepare(bp->tx_clk); 2295 clk_disable_unprepare(bp->hclk); 2296 clk_disable_unprepare(bp->pclk); 2297 2298 return 0; 2299} 2300 2301static int macb_resume(struct device *dev) 2302{ 2303 struct platform_device *pdev = to_platform_device(dev); 2304 struct net_device *netdev = platform_get_drvdata(pdev); 2305 struct macb *bp = netdev_priv(netdev); 2306 2307 clk_prepare_enable(bp->pclk); 2308 clk_prepare_enable(bp->hclk); 2309 if (!IS_ERR(bp->tx_clk)) 2310 clk_prepare_enable(bp->tx_clk); 2311 2312 netif_device_attach(netdev); 2313 2314 return 0; 2315} 2316#endif 2317 2318static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume); 2319 2320static struct platform_driver macb_driver = { 2321 .remove = __exit_p(macb_remove), 2322 .driver = { 2323 .name = "macb", 2324 .owner = THIS_MODULE, 2325 .of_match_table = of_match_ptr(macb_dt_ids), 2326 .pm = &macb_pm_ops, 2327 }, 2328}; 2329 2330module_platform_driver_probe(macb_driver, macb_probe); 2331 2332MODULE_LICENSE("GPL"); 2333MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); 2334MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2335MODULE_ALIAS("platform:macb"); 2336