1f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */ 2f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#ifndef CHELSIO_MV8E1XXX_H 3f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define CHELSIO_MV8E1XXX_H 4f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 5f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#ifndef BMCR_SPEED1000 6f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger# define BMCR_SPEED1000 0x40 7f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#endif 8f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 9f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#ifndef ADVERTISE_PAUSE 10f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger# define ADVERTISE_PAUSE 0x400 11f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#endif 12f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#ifndef ADVERTISE_PAUSE_ASYM 13f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger# define ADVERTISE_PAUSE_ASYM 0x800 14f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#endif 15f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 16f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* Gigabit MII registers */ 17f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MII_GBCR 9 /* 1000Base-T control register */ 18f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MII_GBSR 10 /* 1000Base-T status register */ 19f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 20f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* 1000Base-T control register fields */ 21f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBCR_ADV_1000HALF 0x100 22f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBCR_ADV_1000FULL 0x200 23f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBCR_PREFER_MASTER 0x400 24f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBCR_MANUAL_AS_MASTER 0x800 25f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBCR_MANUAL_CONFIG_ENABLE 0x1000 26f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 27f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* 1000Base-T status register fields */ 28f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_LP_1000HALF 0x400 29f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_LP_1000FULL 0x800 30f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_REMOTE_OK 0x1000 31f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_LOCAL_OK 0x2000 32f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_LOCAL_MASTER 0x4000 33f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define GBSR_MASTER_FAULT 0x8000 34f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 35f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* Marvell PHY interrupt status bits. */ 36f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_JABBER 0x0001 37f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_POLARITY_CHNG 0x0002 38f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010 39f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_DOWNSHIFT 0x0020 40f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040 41f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080 42f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_FALSE_CARRIER 0x0100 43f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200 44f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_LINK_CHNG 0x0400 45f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_AUTONEG_DONE 0x0800 46f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_PAGE_RECV 0x1000 47f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000 48f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_SPEED_CHNG 0x4000 49f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTR_AUTONEG_ERR 0x8000 50f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 51f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* Marvell PHY specific registers. */ 52f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16 53f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17 54f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18 55f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19 56f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20 57f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21 58f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_RES_REGISTER 22 59f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_GLOBAL_STATUS_REGISTER 23 60f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_LED_CONTROL_REGISTER 24 61f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25 62f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26 63f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27 64f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28 65f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_EXTENDED_ADDR_REGISTER 29 66f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define MV88E1XXX_EXTENDED_REGISTER 30 67f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 68f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* PHY specific control register fields */ 69f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSCR_MDI_XOVER_MODE 5 70f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define M_PSCR_MDI_XOVER_MODE 0x3 71f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE) 72f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE) 73f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 74f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* Extended PHY specific control register fields */ 75f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_DOWNSHIFT_ENABLE 8 76f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE) 77f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 78f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_DOWNSHIFT_CNT 9 79f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define M_DOWNSHIFT_CNT 0x7 80f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT) 81f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT) 82f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 83f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger/* PHY specific status register fields */ 84f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_JABBER 0 85f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_JABBER (1 << S_PSSR_JABBER) 86f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 87f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_POLARITY 1 88f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY) 89f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 90f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_RX_PAUSE 2 91f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE) 92f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 93f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_TX_PAUSE 3 94f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE) 95f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 96f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_ENERGY_DETECT 4 97f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT) 98f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 99f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_DOWNSHIFT_STATUS 5 100f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS) 101f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 102f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_MDI 6 103f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_MDI (1 << S_PSSR_MDI) 104f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 105f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_CABLE_LEN 7 106f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define M_PSSR_CABLE_LEN 0x7 107f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN) 108f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN) 109f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 110f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_LINK 10 111f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_LINK (1 << S_PSSR_LINK) 112f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 113f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_STATUS_RESOLVED 11 114f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED) 115f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 116f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_PAGE_RECEIVED 12 117f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED) 118f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 119f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_DUPLEX 13 120f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX) 121f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 122f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define S_PSSR_SPEED 14 123f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define M_PSSR_SPEED 0x3 124f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED) 125f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED) 126f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger 127f1d3d38af75789f1b82969b83b69cab540609789Stephen Hemminger#endif 128