1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __T4_REGS_H 36#define __T4_REGS_H 37 38#define MYPF_BASE 0x1b000 39#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40 41#define PF0_BASE 0x1e000 42#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43 44#define PF_STRIDE 0x400 45#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46#define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47 48#define MYPORT_BASE 0x1c000 49#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50 51#define PORT0_BASE 0x20000 52#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53 54#define PORT_STRIDE 0x2000 55#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57 58#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60 61#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65 66#define SGE_PF_KDOORBELL 0x0 67#define QID_MASK 0xffff8000U 68#define QID_SHIFT 15 69#define QID(x) ((x) << QID_SHIFT) 70#define DBPRIO(x) ((x) << 14) 71#define DBTYPE(x) ((x) << 13) 72#define PIDX_MASK 0x00003fffU 73#define PIDX_SHIFT 0 74#define PIDX(x) ((x) << PIDX_SHIFT) 75#define PIDX_SHIFT_T5 0 76#define PIDX_T5(x) ((x) << PIDX_SHIFT_T5) 77 78 79#define SGE_TIMERREGS 6 80#define SGE_PF_GTS 0x4 81#define INGRESSQID_MASK 0xffff0000U 82#define INGRESSQID_SHIFT 16 83#define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 84#define TIMERREG_MASK 0x0000e000U 85#define TIMERREG_SHIFT 13 86#define TIMERREG(x) ((x) << TIMERREG_SHIFT) 87#define SEINTARM_MASK 0x00001000U 88#define SEINTARM_SHIFT 12 89#define SEINTARM(x) ((x) << SEINTARM_SHIFT) 90#define CIDXINC_MASK 0x00000fffU 91#define CIDXINC_SHIFT 0 92#define CIDXINC(x) ((x) << CIDXINC_SHIFT) 93 94#define X_RXPKTCPLMODE_SPLIT 1 95#define X_INGPADBOUNDARY_SHIFT 5 96 97#define SGE_CONTROL 0x1008 98#define SGE_CONTROL2_A 0x1124 99#define DCASYSTYPE 0x00080000U 100#define RXPKTCPLMODE_MASK 0x00040000U 101#define RXPKTCPLMODE_SHIFT 18 102#define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT) 103#define EGRSTATUSPAGESIZE_MASK 0x00020000U 104#define EGRSTATUSPAGESIZE_SHIFT 17 105#define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT) 106#define PKTSHIFT_MASK 0x00001c00U 107#define PKTSHIFT_SHIFT 10 108#define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 109#define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 110#define INGPCIEBOUNDARY_32B_X 0 111#define INGPCIEBOUNDARY_MASK 0x00000380U 112#define INGPCIEBOUNDARY_SHIFT 7 113#define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 114#define INGPADBOUNDARY_MASK 0x00000070U 115#define INGPADBOUNDARY_SHIFT 4 116#define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 117#define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 118 >> INGPADBOUNDARY_SHIFT) 119#define INGPACKBOUNDARY_16B_X 0 120#define INGPACKBOUNDARY_SHIFT_X 5 121 122#define INGPACKBOUNDARY_S 16 123#define INGPACKBOUNDARY_M 0x7U 124#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S) 125#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \ 126 & INGPACKBOUNDARY_M) 127#define EGRPCIEBOUNDARY_MASK 0x0000000eU 128#define EGRPCIEBOUNDARY_SHIFT 1 129#define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 130#define GLOBALENABLE 0x00000001U 131 132#define SGE_HOST_PAGE_SIZE 0x100c 133 134#define HOSTPAGESIZEPF7_MASK 0x0000000fU 135#define HOSTPAGESIZEPF7_SHIFT 28 136#define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT) 137 138#define HOSTPAGESIZEPF6_MASK 0x0000000fU 139#define HOSTPAGESIZEPF6_SHIFT 24 140#define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT) 141 142#define HOSTPAGESIZEPF5_MASK 0x0000000fU 143#define HOSTPAGESIZEPF5_SHIFT 20 144#define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT) 145 146#define HOSTPAGESIZEPF4_MASK 0x0000000fU 147#define HOSTPAGESIZEPF4_SHIFT 16 148#define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT) 149 150#define HOSTPAGESIZEPF3_MASK 0x0000000fU 151#define HOSTPAGESIZEPF3_SHIFT 12 152#define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT) 153 154#define HOSTPAGESIZEPF2_MASK 0x0000000fU 155#define HOSTPAGESIZEPF2_SHIFT 8 156#define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT) 157 158#define HOSTPAGESIZEPF1_MASK 0x0000000fU 159#define HOSTPAGESIZEPF1_SHIFT 4 160#define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT) 161 162#define HOSTPAGESIZEPF0_MASK 0x0000000fU 163#define HOSTPAGESIZEPF0_SHIFT 0 164#define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 165 166#define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 167#define QUEUESPERPAGEPF0_MASK 0x0000000fU 168#define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 169 170#define QUEUESPERPAGEPF0 0 171#define QUEUESPERPAGEPF1 4 172 173/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 174 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 175 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 176 * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues, 177 * we have a Going To Sleep register at offsets 8x+4. 178 * 179 * As noted above, we have many instances of the Simple Doorbell and Going To 180 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 181 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 182 * avoid buffering of the writes to the Simple Doorbell and we want to use a 183 * non-contiguous offset for the Going To Sleep writes in order to avoid 184 * possible combining between them. 185 */ 186#define SGE_UDB_SIZE 128 187#define SGE_UDB_KDOORBELL 8 188#define SGE_UDB_GTS 20 189#define SGE_UDB_WCDOORBELL 64 190 191#define SGE_INT_CAUSE1 0x1024 192#define SGE_INT_CAUSE2 0x1030 193#define SGE_INT_CAUSE3 0x103c 194#define ERR_FLM_DBP 0x80000000U 195#define ERR_FLM_IDMA1 0x40000000U 196#define ERR_FLM_IDMA0 0x20000000U 197#define ERR_FLM_HINT 0x10000000U 198#define ERR_PCIE_ERROR3 0x08000000U 199#define ERR_PCIE_ERROR2 0x04000000U 200#define ERR_PCIE_ERROR1 0x02000000U 201#define ERR_PCIE_ERROR0 0x01000000U 202#define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 203#define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 204#define ERR_INVALID_CIDX_INC 0x00200000U 205#define ERR_ITP_TIME_PAUSED 0x00100000U 206#define ERR_CPL_OPCODE_0 0x00080000U 207#define ERR_DROPPED_DB 0x00040000U 208#define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 209#define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 210#define ERR_BAD_DB_PIDX3 0x00008000U 211#define ERR_BAD_DB_PIDX2 0x00004000U 212#define ERR_BAD_DB_PIDX1 0x00002000U 213#define ERR_BAD_DB_PIDX0 0x00001000U 214#define ERR_ING_PCIE_CHAN 0x00000800U 215#define ERR_ING_CTXT_PRIO 0x00000400U 216#define ERR_EGR_CTXT_PRIO 0x00000200U 217#define DBFIFO_HP_INT 0x00000100U 218#define DBFIFO_LP_INT 0x00000080U 219#define REG_ADDRESS_ERR 0x00000040U 220#define INGRESS_SIZE_ERR 0x00000020U 221#define EGRESS_SIZE_ERR 0x00000010U 222#define ERR_INV_CTXT3 0x00000008U 223#define ERR_INV_CTXT2 0x00000004U 224#define ERR_INV_CTXT1 0x00000002U 225#define ERR_INV_CTXT0 0x00000001U 226 227#define SGE_INT_ENABLE3 0x1040 228#define SGE_FL_BUFFER_SIZE0 0x1044 229#define SGE_FL_BUFFER_SIZE1 0x1048 230#define SGE_FL_BUFFER_SIZE2 0x104c 231#define SGE_FL_BUFFER_SIZE3 0x1050 232#define SGE_FL_BUFFER_SIZE4 0x1054 233#define SGE_FL_BUFFER_SIZE5 0x1058 234#define SGE_FL_BUFFER_SIZE6 0x105c 235#define SGE_FL_BUFFER_SIZE7 0x1060 236#define SGE_FL_BUFFER_SIZE8 0x1064 237 238#define SGE_INGRESS_RX_THRESHOLD 0x10a0 239#define THRESHOLD_0_MASK 0x3f000000U 240#define THRESHOLD_0_SHIFT 24 241#define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 242#define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 243#define THRESHOLD_1_MASK 0x003f0000U 244#define THRESHOLD_1_SHIFT 16 245#define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 246#define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 247#define THRESHOLD_2_MASK 0x00003f00U 248#define THRESHOLD_2_SHIFT 8 249#define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 250#define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 251#define THRESHOLD_3_MASK 0x0000003fU 252#define THRESHOLD_3_SHIFT 0 253#define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 254#define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 255 256#define SGE_CONM_CTRL 0x1094 257#define EGRTHRESHOLD_MASK 0x00003f00U 258#define EGRTHRESHOLDshift 8 259#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift) 260#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift) 261 262#define EGRTHRESHOLDPACKING_MASK 0x3fU 263#define EGRTHRESHOLDPACKING_SHIFT 14 264#define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT) 265#define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \ 266 EGRTHRESHOLDPACKING_MASK) 267 268#define SGE_DBFIFO_STATUS 0x10a4 269#define HP_INT_THRESH_SHIFT 28 270#define HP_INT_THRESH_MASK 0xfU 271#define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT) 272#define LP_INT_THRESH_SHIFT 12 273#define LP_INT_THRESH_MASK 0xfU 274#define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT) 275 276#define SGE_DOORBELL_CONTROL 0x10a8 277#define ENABLE_DROP (1 << 13) 278 279#define S_NOCOALESCE 26 280#define V_NOCOALESCE(x) ((x) << S_NOCOALESCE) 281#define F_NOCOALESCE V_NOCOALESCE(1U) 282 283#define SGE_TIMESTAMP_LO 0x1098 284#define SGE_TIMESTAMP_HI 0x109c 285#define S_TSVAL 0 286#define M_TSVAL 0xfffffffU 287#define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL) 288 289#define SGE_TIMER_VALUE_0_AND_1 0x10b8 290#define TIMERVALUE0_MASK 0xffff0000U 291#define TIMERVALUE0_SHIFT 16 292#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 293#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 294#define TIMERVALUE1_MASK 0x0000ffffU 295#define TIMERVALUE1_SHIFT 0 296#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 297#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 298 299#define SGE_TIMER_VALUE_2_AND_3 0x10bc 300#define TIMERVALUE2_MASK 0xffff0000U 301#define TIMERVALUE2_SHIFT 16 302#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT) 303#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT) 304#define TIMERVALUE3_MASK 0x0000ffffU 305#define TIMERVALUE3_SHIFT 0 306#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT) 307#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT) 308 309#define SGE_TIMER_VALUE_4_AND_5 0x10c0 310#define TIMERVALUE4_MASK 0xffff0000U 311#define TIMERVALUE4_SHIFT 16 312#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT) 313#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT) 314#define TIMERVALUE5_MASK 0x0000ffffU 315#define TIMERVALUE5_SHIFT 0 316#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT) 317#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT) 318 319#define SGE_DEBUG_INDEX 0x10cc 320#define SGE_DEBUG_DATA_HIGH 0x10d0 321#define SGE_DEBUG_DATA_LOW 0x10d4 322#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 323#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc 324#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 325#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 326 327#define S_HP_INT_THRESH 28 328#define M_HP_INT_THRESH 0xfU 329#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH) 330#define S_LP_INT_THRESH_T5 18 331#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) 332#define M_LP_COUNT_T5 0x3ffffU 333#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5) 334#define M_HP_COUNT 0x7ffU 335#define S_HP_COUNT 16 336#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT) 337#define S_LP_INT_THRESH 12 338#define M_LP_INT_THRESH 0xfU 339#define M_LP_INT_THRESH_T5 0xfffU 340#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH) 341#define M_LP_COUNT 0x7ffU 342#define S_LP_COUNT 0 343#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) 344#define A_SGE_DBFIFO_STATUS 0x10a4 345 346#define SGE_STAT_TOTAL 0x10e4 347#define SGE_STAT_MATCH 0x10e8 348 349#define SGE_STAT_CFG 0x10ec 350#define S_STATSOURCE_T5 9 351#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) 352 353#define SGE_DBFIFO_STATUS2 0x1118 354#define M_HP_COUNT_T5 0x3ffU 355#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5) 356#define S_HP_INT_THRESH_T5 10 357#define M_HP_INT_THRESH_T5 0xfU 358#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) 359 360#define S_ENABLE_DROP 13 361#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP) 362#define F_ENABLE_DROP V_ENABLE_DROP(1U) 363#define S_DROPPED_DB 0 364#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB) 365#define F_DROPPED_DB V_DROPPED_DB(1U) 366#define A_SGE_DOORBELL_CONTROL 0x10a8 367 368#define A_SGE_CTXT_CMD 0x11fc 369#define A_SGE_DBQ_CTXT_BADDR 0x1084 370 371#define PCIE_PF_CFG 0x40 372#define AIVEC(x) ((x) << 4) 373#define AIVEC_MASK 0x3ffU 374 375#define PCIE_PF_CLI 0x44 376#define PCIE_INT_CAUSE 0x3004 377#define UNXSPLCPLERR 0x20000000U 378#define PCIEPINT 0x10000000U 379#define PCIESINT 0x08000000U 380#define RPLPERR 0x04000000U 381#define RXWRPERR 0x02000000U 382#define RXCPLPERR 0x01000000U 383#define PIOTAGPERR 0x00800000U 384#define MATAGPERR 0x00400000U 385#define INTXCLRPERR 0x00200000U 386#define FIDPERR 0x00100000U 387#define CFGSNPPERR 0x00080000U 388#define HRSPPERR 0x00040000U 389#define HREQPERR 0x00020000U 390#define HCNTPERR 0x00010000U 391#define DRSPPERR 0x00008000U 392#define DREQPERR 0x00004000U 393#define DCNTPERR 0x00002000U 394#define CRSPPERR 0x00001000U 395#define CREQPERR 0x00000800U 396#define CCNTPERR 0x00000400U 397#define TARTAGPERR 0x00000200U 398#define PIOREQPERR 0x00000100U 399#define PIOCPLPERR 0x00000080U 400#define MSIXDIPERR 0x00000040U 401#define MSIXDATAPERR 0x00000020U 402#define MSIXADDRHPERR 0x00000010U 403#define MSIXADDRLPERR 0x00000008U 404#define MSIDATAPERR 0x00000004U 405#define MSIADDRHPERR 0x00000002U 406#define MSIADDRLPERR 0x00000001U 407 408#define READRSPERR 0x20000000U 409#define TRGT1GRPPERR 0x10000000U 410#define IPSOTPERR 0x08000000U 411#define IPRXDATAGRPPERR 0x02000000U 412#define IPRXHDRGRPPERR 0x01000000U 413#define MAGRPPERR 0x00400000U 414#define VFIDPERR 0x00200000U 415#define HREQWRPERR 0x00010000U 416#define DREQWRPERR 0x00002000U 417#define MSTTAGQPERR 0x00000400U 418#define PIOREQGRPPERR 0x00000100U 419#define PIOCPLGRPPERR 0x00000080U 420#define MSIXSTIPERR 0x00000004U 421#define MSTTIMEOUTPERR 0x00000002U 422#define MSTGRPPERR 0x00000001U 423 424#define PCIE_NONFAT_ERR 0x3010 425#define PCIE_CFG_SPACE_REQ 0x3060 426#define PCIE_CFG_SPACE_DATA 0x3064 427#define PCIE_MEM_ACCESS_BASE_WIN 0x3068 428#define S_PCIEOFST 10 429#define M_PCIEOFST 0x3fffffU 430#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST) 431#define PCIEOFST_MASK 0xfffffc00U 432#define BIR_MASK 0x00000300U 433#define BIR_SHIFT 8 434#define BIR(x) ((x) << BIR_SHIFT) 435#define WINDOW_MASK 0x000000ffU 436#define WINDOW_SHIFT 0 437#define WINDOW(x) ((x) << WINDOW_SHIFT) 438#define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK) 439#define PCIE_MEM_ACCESS_OFFSET 0x306c 440#define ENABLE (1U << 30) 441#define FUNCTION(x) ((x) << 12) 442#define F_LOCALCFG (1U << 28) 443 444#define S_PFNUM 0 445#define V_PFNUM(x) ((x) << S_PFNUM) 446 447#define PCIE_FW 0x30b8 448#define PCIE_FW_ERR 0x80000000U 449#define PCIE_FW_INIT 0x40000000U 450#define PCIE_FW_HALT 0x20000000U 451#define PCIE_FW_MASTER_VLD 0x00008000U 452#define PCIE_FW_MASTER(x) ((x) << 12) 453#define PCIE_FW_MASTER_MASK 0x7 454#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK) 455 456#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 457#define RNPP 0x80000000U 458#define RPCP 0x20000000U 459#define RCIP 0x08000000U 460#define RCCP 0x04000000U 461#define RFTP 0x00800000U 462#define PTRP 0x00100000U 463 464#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 465#define TPCP 0x40000000U 466#define TNPP 0x20000000U 467#define TFTP 0x10000000U 468#define TCAP 0x08000000U 469#define TCIP 0x04000000U 470#define RCAP 0x02000000U 471#define PLUP 0x00800000U 472#define PLDN 0x00400000U 473#define OTDD 0x00200000U 474#define GTRP 0x00100000U 475#define RDPE 0x00040000U 476#define TDCE 0x00020000U 477#define TDUE 0x00010000U 478 479#define MC_INT_CAUSE 0x7518 480#define MC_P_INT_CAUSE 0x41318 481#define ECC_UE_INT_CAUSE 0x00000004U 482#define ECC_CE_INT_CAUSE 0x00000002U 483#define PERR_INT_CAUSE 0x00000001U 484 485#define MC_ECC_STATUS 0x751c 486#define MC_P_ECC_STATUS 0x4131c 487#define ECC_CECNT_MASK 0xffff0000U 488#define ECC_CECNT_SHIFT 16 489#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 490#define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 491#define ECC_UECNT_MASK 0x0000ffffU 492#define ECC_UECNT_SHIFT 0 493#define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 494#define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 495 496#define MC_BIST_CMD 0x7600 497#define START_BIST 0x80000000U 498#define BIST_CMD_GAP_MASK 0x0000ff00U 499#define BIST_CMD_GAP_SHIFT 8 500#define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 501#define BIST_OPCODE_MASK 0x00000003U 502#define BIST_OPCODE_SHIFT 0 503#define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 504 505#define MC_BIST_CMD_ADDR 0x7604 506#define MC_BIST_CMD_LEN 0x7608 507#define MC_BIST_DATA_PATTERN 0x760c 508#define BIST_DATA_TYPE_MASK 0x0000000fU 509#define BIST_DATA_TYPE_SHIFT 0 510#define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 511 512#define MC_BIST_STATUS_RDATA 0x7688 513 514#define MA_EDRAM0_BAR 0x77c0 515#define MA_EDRAM1_BAR 0x77c4 516#define EDRAM_SIZE_MASK 0xfffU 517#define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) 518 519#define MA_EXT_MEMORY_BAR 0x77c8 520#define EXT_MEM_SIZE_MASK 0x00000fffU 521#define EXT_MEM_SIZE_SHIFT 0 522#define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 523 524#define MA_TARGET_MEM_ENABLE 0x77d8 525#define EXT_MEM1_ENABLE 0x00000010U 526#define EXT_MEM_ENABLE 0x00000004U 527#define EDRAM1_ENABLE 0x00000002U 528#define EDRAM0_ENABLE 0x00000001U 529 530#define MA_INT_CAUSE 0x77e0 531#define MEM_PERR_INT_CAUSE 0x00000002U 532#define MEM_WRAP_INT_CAUSE 0x00000001U 533 534#define MA_INT_WRAP_STATUS 0x77e4 535#define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 536#define MEM_WRAP_ADDRESS_SHIFT 4 537#define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 538#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 539#define MEM_WRAP_CLIENT_NUM_SHIFT 0 540#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 541#define MA_PCIE_FW 0x30b8 542#define MA_PARITY_ERROR_STATUS 0x77f4 543#define MA_PARITY_ERROR_STATUS2 0x7804 544 545#define MA_EXT_MEMORY1_BAR 0x7808 546#define EDC_0_BASE_ADDR 0x7900 547 548#define EDC_BIST_CMD 0x7904 549#define EDC_BIST_CMD_ADDR 0x7908 550#define EDC_BIST_CMD_LEN 0x790c 551#define EDC_BIST_DATA_PATTERN 0x7910 552#define EDC_BIST_STATUS_RDATA 0x7928 553#define EDC_INT_CAUSE 0x7978 554#define ECC_UE_PAR 0x00000020U 555#define ECC_CE_PAR 0x00000010U 556#define PERR_PAR_CAUSE 0x00000008U 557 558#define EDC_ECC_STATUS 0x797c 559 560#define EDC_1_BASE_ADDR 0x7980 561 562#define CIM_BOOT_CFG 0x7b00 563#define BOOTADDR_MASK 0xffffff00U 564#define UPCRST 0x1U 565 566#define CIM_PF_MAILBOX_DATA 0x240 567#define CIM_PF_MAILBOX_CTRL 0x280 568#define MBMSGVALID 0x00000008U 569#define MBINTREQ 0x00000004U 570#define MBOWNER_MASK 0x00000003U 571#define MBOWNER_SHIFT 0 572#define MBOWNER(x) ((x) << MBOWNER_SHIFT) 573#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 574 575#define CIM_PF_HOST_INT_ENABLE 0x288 576#define MBMSGRDYINTEN(x) ((x) << 19) 577 578#define CIM_PF_HOST_INT_CAUSE 0x28c 579#define MBMSGRDYINT 0x00080000U 580 581#define CIM_HOST_INT_CAUSE 0x7b2c 582#define TIEQOUTPARERRINT 0x00100000U 583#define TIEQINPARERRINT 0x00080000U 584#define MBHOSTPARERR 0x00040000U 585#define MBUPPARERR 0x00020000U 586#define IBQPARERR 0x0001f800U 587#define IBQTP0PARERR 0x00010000U 588#define IBQTP1PARERR 0x00008000U 589#define IBQULPPARERR 0x00004000U 590#define IBQSGELOPARERR 0x00002000U 591#define IBQSGEHIPARERR 0x00001000U 592#define IBQNCSIPARERR 0x00000800U 593#define OBQPARERR 0x000007e0U 594#define OBQULP0PARERR 0x00000400U 595#define OBQULP1PARERR 0x00000200U 596#define OBQULP2PARERR 0x00000100U 597#define OBQULP3PARERR 0x00000080U 598#define OBQSGEPARERR 0x00000040U 599#define OBQNCSIPARERR 0x00000020U 600#define PREFDROPINT 0x00000002U 601#define UPACCNONZERO 0x00000001U 602 603#define CIM_HOST_UPACC_INT_CAUSE 0x7b34 604#define EEPROMWRINT 0x40000000U 605#define TIMEOUTMAINT 0x20000000U 606#define TIMEOUTINT 0x10000000U 607#define RSPOVRLOOKUPINT 0x08000000U 608#define REQOVRLOOKUPINT 0x04000000U 609#define BLKWRPLINT 0x02000000U 610#define BLKRDPLINT 0x01000000U 611#define SGLWRPLINT 0x00800000U 612#define SGLRDPLINT 0x00400000U 613#define BLKWRCTLINT 0x00200000U 614#define BLKRDCTLINT 0x00100000U 615#define SGLWRCTLINT 0x00080000U 616#define SGLRDCTLINT 0x00040000U 617#define BLKWREEPROMINT 0x00020000U 618#define BLKRDEEPROMINT 0x00010000U 619#define SGLWREEPROMINT 0x00008000U 620#define SGLRDEEPROMINT 0x00004000U 621#define BLKWRFLASHINT 0x00002000U 622#define BLKRDFLASHINT 0x00001000U 623#define SGLWRFLASHINT 0x00000800U 624#define SGLRDFLASHINT 0x00000400U 625#define BLKWRBOOTINT 0x00000200U 626#define BLKRDBOOTINT 0x00000100U 627#define SGLWRBOOTINT 0x00000080U 628#define SGLRDBOOTINT 0x00000040U 629#define ILLWRBEINT 0x00000020U 630#define ILLRDBEINT 0x00000010U 631#define ILLRDINT 0x00000008U 632#define ILLWRINT 0x00000004U 633#define ILLTRANSINT 0x00000002U 634#define RSVDSPACEINT 0x00000001U 635 636#define TP_OUT_CONFIG 0x7d04 637#define VLANEXTENABLE_MASK 0x0000f000U 638#define VLANEXTENABLE_SHIFT 12 639 640#define TP_GLOBAL_CONFIG 0x7d08 641#define FIVETUPLELOOKUP_SHIFT 17 642#define FIVETUPLELOOKUP_MASK 0x00060000U 643#define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) 644#define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ 645 FIVETUPLELOOKUP_SHIFT) 646 647#define TP_PARA_REG2 0x7d68 648#define MAXRXDATA_MASK 0xffff0000U 649#define MAXRXDATA_SHIFT 16 650#define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 651 652#define TP_TIMER_RESOLUTION 0x7d90 653#define TIMERRESOLUTION_MASK 0x00ff0000U 654#define TIMERRESOLUTION_SHIFT 16 655#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 656#define DELAYEDACKRESOLUTION_MASK 0x000000ffU 657#define DELAYEDACKRESOLUTION_SHIFT 0 658#define DELAYEDACKRESOLUTION_GET(x) \ 659 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) 660 661#define TP_SHIFT_CNT 0x7dc0 662#define SYNSHIFTMAX_SHIFT 24 663#define SYNSHIFTMAX_MASK 0xff000000U 664#define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) 665#define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ 666 SYNSHIFTMAX_SHIFT) 667#define RXTSHIFTMAXR1_SHIFT 20 668#define RXTSHIFTMAXR1_MASK 0x00f00000U 669#define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) 670#define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ 671 RXTSHIFTMAXR1_SHIFT) 672#define RXTSHIFTMAXR2_SHIFT 16 673#define RXTSHIFTMAXR2_MASK 0x000f0000U 674#define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) 675#define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ 676 RXTSHIFTMAXR2_SHIFT) 677#define PERSHIFTBACKOFFMAX_SHIFT 12 678#define PERSHIFTBACKOFFMAX_MASK 0x0000f000U 679#define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) 680#define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ 681 PERSHIFTBACKOFFMAX_SHIFT) 682#define PERSHIFTMAX_SHIFT 8 683#define PERSHIFTMAX_MASK 0x00000f00U 684#define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) 685#define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ 686 PERSHIFTMAX_SHIFT) 687#define KEEPALIVEMAXR1_SHIFT 4 688#define KEEPALIVEMAXR1_MASK 0x000000f0U 689#define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) 690#define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ 691 KEEPALIVEMAXR1_SHIFT) 692#define KEEPALIVEMAXR2_SHIFT 0 693#define KEEPALIVEMAXR2_MASK 0x0000000fU 694#define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) 695#define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ 696 KEEPALIVEMAXR2_SHIFT) 697 698#define TP_CCTRL_TABLE 0x7ddc 699#define TP_MTU_TABLE 0x7de4 700#define MTUINDEX_MASK 0xff000000U 701#define MTUINDEX_SHIFT 24 702#define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 703#define MTUWIDTH_MASK 0x000f0000U 704#define MTUWIDTH_SHIFT 16 705#define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 706#define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 707#define MTUVALUE_MASK 0x00003fffU 708#define MTUVALUE_SHIFT 0 709#define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 710#define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 711 712#define TP_RSS_LKP_TABLE 0x7dec 713#define LKPTBLROWVLD 0x80000000U 714#define LKPTBLQUEUE1_MASK 0x000ffc00U 715#define LKPTBLQUEUE1_SHIFT 10 716#define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 717#define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 718#define LKPTBLQUEUE0_MASK 0x000003ffU 719#define LKPTBLQUEUE0_SHIFT 0 720#define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 721#define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 722 723#define TP_PIO_ADDR 0x7e40 724#define TP_PIO_DATA 0x7e44 725#define TP_MIB_INDEX 0x7e50 726#define TP_MIB_DATA 0x7e54 727#define TP_INT_CAUSE 0x7e74 728#define FLMTXFLSTEMPTY 0x40000000U 729 730#define TP_VLAN_PRI_MAP 0x140 731#define FRAGMENTATION_SHIFT 9 732#define FRAGMENTATION_MASK 0x00000200U 733#define MPSHITTYPE_MASK 0x00000100U 734#define MACMATCH_MASK 0x00000080U 735#define ETHERTYPE_MASK 0x00000040U 736#define PROTOCOL_MASK 0x00000020U 737#define TOS_MASK 0x00000010U 738#define VLAN_MASK 0x00000008U 739#define VNIC_ID_MASK 0x00000004U 740#define PORT_MASK 0x00000002U 741#define FCOE_SHIFT 0 742#define FCOE_MASK 0x00000001U 743 744#define TP_INGRESS_CONFIG 0x141 745#define VNIC 0x00000800U 746#define CSUM_HAS_PSEUDO_HDR 0x00000400U 747#define RM_OVLAN 0x00000200U 748#define LOOKUPEVERYPKT 0x00000100U 749 750#define TP_MIB_MAC_IN_ERR_0 0x0 751#define TP_MIB_TCP_OUT_RST 0xc 752#define TP_MIB_TCP_IN_SEG_HI 0x10 753#define TP_MIB_TCP_IN_SEG_LO 0x11 754#define TP_MIB_TCP_OUT_SEG_HI 0x12 755#define TP_MIB_TCP_OUT_SEG_LO 0x13 756#define TP_MIB_TCP_RXT_SEG_HI 0x14 757#define TP_MIB_TCP_RXT_SEG_LO 0x15 758#define TP_MIB_TNL_CNG_DROP_0 0x18 759#define TP_MIB_TCP_V6IN_ERR_0 0x28 760#define TP_MIB_TCP_V6OUT_RST 0x2c 761#define TP_MIB_OFD_ARP_DROP 0x36 762#define TP_MIB_TNL_DROP_0 0x44 763#define TP_MIB_OFD_VLN_DROP_0 0x58 764 765#define ULP_TX_INT_CAUSE 0x8dcc 766#define PBL_BOUND_ERR_CH3 0x80000000U 767#define PBL_BOUND_ERR_CH2 0x40000000U 768#define PBL_BOUND_ERR_CH1 0x20000000U 769#define PBL_BOUND_ERR_CH0 0x10000000U 770 771#define PM_RX_INT_CAUSE 0x8fdc 772#define ZERO_E_CMD_ERROR 0x00400000U 773#define PMRX_FRAMING_ERROR 0x003ffff0U 774#define OCSPI_PAR_ERROR 0x00000008U 775#define DB_OPTIONS_PAR_ERROR 0x00000004U 776#define IESPI_PAR_ERROR 0x00000002U 777#define E_PCMD_PAR_ERROR 0x00000001U 778 779#define PM_TX_INT_CAUSE 0x8ffc 780#define PCMD_LEN_OVFL0 0x80000000U 781#define PCMD_LEN_OVFL1 0x40000000U 782#define PCMD_LEN_OVFL2 0x20000000U 783#define ZERO_C_CMD_ERROR 0x10000000U 784#define PMTX_FRAMING_ERROR 0x0ffffff0U 785#define OESPI_PAR_ERROR 0x00000008U 786#define ICSPI_PAR_ERROR 0x00000002U 787#define C_PCMD_PAR_ERROR 0x00000001U 788 789#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 790#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 791#define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 792#define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 793#define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 794#define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 795#define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 796#define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 797#define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 798#define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 799#define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 800#define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 801#define MPS_PORT_STAT_TX_PORT_64B_L 0x430 802#define MPS_PORT_STAT_TX_PORT_64B_H 0x434 803#define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 804#define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 805#define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 806#define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 807#define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 808#define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 809#define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 810#define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 811#define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 812#define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 813#define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 814#define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 815#define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 816#define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 817#define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 818#define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 819#define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 820#define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 821#define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 822#define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 823#define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 824#define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 825#define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 826#define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 827#define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 828#define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 829#define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 830#define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 831#define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 832#define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 833#define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 834#define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 835#define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 836#define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 837#define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 838#define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 839#define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 840#define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 841#define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 842#define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 843#define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 844#define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 845#define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 846#define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 847#define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 848#define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 849#define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 850#define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 851#define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 852#define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 853#define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 854#define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 855#define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 856#define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 857#define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 858#define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 859#define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 860#define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 861#define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 862#define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 863#define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 864#define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 865#define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 866#define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 867#define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 868#define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 869#define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 870#define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 871#define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 872#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 873#define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 874#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 875#define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 876#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 877#define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 878#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 879#define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 880#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 881#define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 882#define MPS_PORT_STAT_RX_PORT_64B_L 0x590 883#define MPS_PORT_STAT_RX_PORT_64B_H 0x594 884#define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 885#define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 886#define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 887#define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 888#define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 889#define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 890#define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 891#define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 892#define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 893#define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 894#define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 895#define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 896#define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 897#define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 898#define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 899#define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 900#define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 901#define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 902#define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 903#define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 904#define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 905#define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 906#define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 907#define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 908#define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 909#define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 910#define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 911#define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 912#define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 913#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 914#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 915#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 916#define MAC_PORT_CFG2 0x818 917#define MAC_PORT_MAGIC_MACID_LO 0x824 918#define MAC_PORT_MAGIC_MACID_HI 0x828 919#define MAC_PORT_EPIO_DATA0 0x8c0 920#define MAC_PORT_EPIO_DATA1 0x8c4 921#define MAC_PORT_EPIO_DATA2 0x8c8 922#define MAC_PORT_EPIO_DATA3 0x8cc 923#define MAC_PORT_EPIO_OP 0x8d0 924 925#define MPS_CMN_CTL 0x9000 926#define NUMPORTS_MASK 0x00000003U 927#define NUMPORTS_SHIFT 0 928#define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 929 930#define MPS_INT_CAUSE 0x9008 931#define STATINT 0x00000020U 932#define TXINT 0x00000010U 933#define RXINT 0x00000008U 934#define TRCINT 0x00000004U 935#define CLSINT 0x00000002U 936#define PLINT 0x00000001U 937 938#define MPS_TX_INT_CAUSE 0x9408 939#define PORTERR 0x00010000U 940#define FRMERR 0x00008000U 941#define SECNTERR 0x00004000U 942#define BUBBLE 0x00002000U 943#define TXDESCFIFO 0x00001e00U 944#define TXDATAFIFO 0x000001e0U 945#define NCSIFIFO 0x00000010U 946#define TPFIFO 0x0000000fU 947 948#define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 949#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 950#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 951 952#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 953#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 954#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 955#define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 956#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 957#define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 958#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 959#define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 960#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 961#define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 962#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 963#define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 964#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 965#define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 966#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 967#define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 968#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 969#define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 970#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 971#define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 972#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 973#define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 974#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 975#define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 976#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 977#define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 978#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 979#define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 980#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 981#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 982#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 983#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 984#define MPS_TRC_CFG 0x9800 985#define TRCFIFOEMPTY 0x00000010U 986#define TRCIGNOREDROPINPUT 0x00000008U 987#define TRCKEEPDUPLICATES 0x00000004U 988#define TRCEN 0x00000002U 989#define TRCMULTIFILTER 0x00000001U 990 991#define MPS_TRC_RSS_CONTROL 0x9808 992#define MPS_T5_TRC_RSS_CONTROL 0xa00c 993#define RSSCONTROL_MASK 0x00ff0000U 994#define RSSCONTROL_SHIFT 16 995#define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 996#define QUEUENUMBER_MASK 0x0000ffffU 997#define QUEUENUMBER_SHIFT 0 998#define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 999 1000#define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 1001#define TFINVERTMATCH 0x01000000U 1002#define TFPKTTOOLARGE 0x00800000U 1003#define TFEN 0x00400000U 1004#define TFPORT_MASK 0x003c0000U 1005#define TFPORT_SHIFT 18 1006#define TFPORT(x) ((x) << TFPORT_SHIFT) 1007#define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 1008#define TFDROP 0x00020000U 1009#define TFSOPEOPERR 0x00010000U 1010#define TFLENGTH_MASK 0x00001f00U 1011#define TFLENGTH_SHIFT 8 1012#define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 1013#define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 1014#define TFOFFSET_MASK 0x0000001fU 1015#define TFOFFSET_SHIFT 0 1016#define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 1017#define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 1018 1019#define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 1020#define TFMINPKTSIZE_MASK 0x01ff0000U 1021#define TFMINPKTSIZE_SHIFT 16 1022#define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 1023#define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 1024#define TFCAPTUREMAX_MASK 0x00003fffU 1025#define TFCAPTUREMAX_SHIFT 0 1026#define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 1027#define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 1028 1029#define MPS_TRC_INT_CAUSE 0x985c 1030#define MISCPERR 0x00000100U 1031#define PKTFIFO 0x000000f0U 1032#define FILTMEM 0x0000000fU 1033 1034#define MPS_TRC_FILTER0_MATCH 0x9c00 1035#define MPS_TRC_FILTER0_DONT_CARE 0x9c80 1036#define MPS_TRC_FILTER1_MATCH 0x9d00 1037#define MPS_CLS_INT_CAUSE 0xd028 1038#define PLERRENB 0x00000008U 1039#define HASHSRAM 0x00000004U 1040#define MATCHTCAM 0x00000002U 1041#define MATCHSRAM 0x00000001U 1042 1043#define MPS_RX_PERR_INT_CAUSE 0x11074 1044 1045#define CPL_INTR_CAUSE 0x19054 1046#define CIM_OP_MAP_PERR 0x00000020U 1047#define CIM_OVFL_ERROR 0x00000010U 1048#define TP_FRAMING_ERROR 0x00000008U 1049#define SGE_FRAMING_ERROR 0x00000004U 1050#define CIM_FRAMING_ERROR 0x00000002U 1051#define ZERO_SWITCH_ERROR 0x00000001U 1052 1053#define SMB_INT_CAUSE 0x19090 1054#define MSTTXFIFOPARINT 0x00200000U 1055#define MSTRXFIFOPARINT 0x00100000U 1056#define SLVFIFOPARINT 0x00080000U 1057 1058#define ULP_RX_INT_CAUSE 0x19158 1059#define ULP_RX_ISCSI_TAGMASK 0x19164 1060#define ULP_RX_ISCSI_PSZ 0x19168 1061#define HPZ3_MASK 0x0f000000U 1062#define HPZ3_SHIFT 24 1063#define HPZ3(x) ((x) << HPZ3_SHIFT) 1064#define HPZ2_MASK 0x000f0000U 1065#define HPZ2_SHIFT 16 1066#define HPZ2(x) ((x) << HPZ2_SHIFT) 1067#define HPZ1_MASK 0x00000f00U 1068#define HPZ1_SHIFT 8 1069#define HPZ1(x) ((x) << HPZ1_SHIFT) 1070#define HPZ0_MASK 0x0000000fU 1071#define HPZ0_SHIFT 0 1072#define HPZ0(x) ((x) << HPZ0_SHIFT) 1073 1074#define ULP_RX_TDDP_PSZ 0x19178 1075 1076#define SF_DATA 0x193f8 1077#define SF_OP 0x193fc 1078#define SF_BUSY 0x80000000U 1079#define SF_LOCK 0x00000010U 1080#define SF_CONT 0x00000008U 1081#define BYTECNT_MASK 0x00000006U 1082#define BYTECNT_SHIFT 1 1083#define BYTECNT(x) ((x) << BYTECNT_SHIFT) 1084#define OP_WR 0x00000001U 1085 1086#define PL_PF_INT_CAUSE 0x3c0 1087#define PFSW 0x00000008U 1088#define PFSGE 0x00000004U 1089#define PFCIM 0x00000002U 1090#define PFMPS 0x00000001U 1091 1092#define PL_PF_INT_ENABLE 0x3c4 1093#define PL_PF_CTL 0x3c8 1094#define SWINT 0x00000001U 1095 1096#define PL_WHOAMI 0x19400 1097#define SOURCEPF_MASK 0x00000700U 1098#define SOURCEPF_SHIFT 8 1099#define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 1100#define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 1101#define ISVF 0x00000080U 1102#define VFID_MASK 0x0000007fU 1103#define VFID_SHIFT 0 1104#define VFID(x) ((x) << VFID_SHIFT) 1105#define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 1106 1107#define PL_INT_CAUSE 0x1940c 1108#define ULP_TX 0x08000000U 1109#define SGE 0x04000000U 1110#define HMA 0x02000000U 1111#define CPL_SWITCH 0x01000000U 1112#define ULP_RX 0x00800000U 1113#define PM_RX 0x00400000U 1114#define PM_TX 0x00200000U 1115#define MA 0x00100000U 1116#define TP 0x00080000U 1117#define LE 0x00040000U 1118#define EDC1 0x00020000U 1119#define EDC0 0x00010000U 1120#define MC 0x00008000U 1121#define PCIE 0x00004000U 1122#define PMU 0x00002000U 1123#define XGMAC_KR1 0x00001000U 1124#define XGMAC_KR0 0x00000800U 1125#define XGMAC1 0x00000400U 1126#define XGMAC0 0x00000200U 1127#define SMB 0x00000100U 1128#define SF 0x00000080U 1129#define PL 0x00000040U 1130#define NCSI 0x00000020U 1131#define MPS 0x00000010U 1132#define MI 0x00000008U 1133#define DBG 0x00000004U 1134#define I2CM 0x00000002U 1135#define CIM 0x00000001U 1136 1137#define MC1 0x31 1138#define PL_INT_ENABLE 0x19410 1139#define PL_INT_MAP0 0x19414 1140#define PL_RST 0x19428 1141#define PIORST 0x00000002U 1142#define PIORSTMODE 0x00000001U 1143 1144#define PL_PL_INT_CAUSE 0x19430 1145#define FATALPERR 0x00000010U 1146#define PERRVFID 0x00000001U 1147 1148#define PL_REV 0x1943c 1149 1150#define S_REV 0 1151#define M_REV 0xfU 1152#define V_REV(x) ((x) << S_REV) 1153#define G_REV(x) (((x) >> S_REV) & M_REV) 1154 1155#define LE_DB_CONFIG 0x19c04 1156#define HASHEN 0x00100000U 1157 1158#define LE_DB_SERVER_INDEX 0x19c18 1159#define LE_DB_ACT_CNT_IPV4 0x19c20 1160#define LE_DB_ACT_CNT_IPV6 0x19c24 1161 1162#define LE_DB_INT_CAUSE 0x19c3c 1163#define REQQPARERR 0x00010000U 1164#define UNKNOWNCMD 0x00008000U 1165#define PARITYERR 0x00000040U 1166#define LIPMISS 0x00000020U 1167#define LIP0 0x00000010U 1168 1169#define LE_DB_TID_HASHBASE 0x19df8 1170 1171#define NCSI_INT_CAUSE 0x1a0d8 1172#define CIM_DM_PRTY_ERR 0x00000100U 1173#define MPS_DM_PRTY_ERR 0x00000080U 1174#define TXFIFO_PRTY_ERR 0x00000002U 1175#define RXFIFO_PRTY_ERR 0x00000001U 1176 1177#define XGMAC_PORT_CFG2 0x1018 1178#define PATEN 0x00040000U 1179#define MAGICEN 0x00020000U 1180 1181#define XGMAC_PORT_MAGIC_MACID_LO 0x1024 1182#define XGMAC_PORT_MAGIC_MACID_HI 0x1028 1183 1184#define XGMAC_PORT_EPIO_DATA0 0x10c0 1185#define XGMAC_PORT_EPIO_DATA1 0x10c4 1186#define XGMAC_PORT_EPIO_DATA2 0x10c8 1187#define XGMAC_PORT_EPIO_DATA3 0x10cc 1188#define XGMAC_PORT_EPIO_OP 0x10d0 1189#define EPIOWR 0x00000100U 1190#define ADDRESS_MASK 0x000000ffU 1191#define ADDRESS_SHIFT 0 1192#define ADDRESS(x) ((x) << ADDRESS_SHIFT) 1193 1194#define MAC_PORT_INT_CAUSE 0x8dc 1195#define XGMAC_PORT_INT_CAUSE 0x10dc 1196 1197#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 1198 1199#define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 1200 1201#define S_TX_MOD_QUEUE_REQ_MAP 0 1202#define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 1203#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1204 1205#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 1206 1207#define S_TX_MODQ_WEIGHT3 24 1208#define M_TX_MODQ_WEIGHT3 0xffU 1209#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 1210 1211#define S_TX_MODQ_WEIGHT2 16 1212#define M_TX_MODQ_WEIGHT2 0xffU 1213#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 1214 1215#define S_TX_MODQ_WEIGHT1 8 1216#define M_TX_MODQ_WEIGHT1 0xffU 1217#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 1218 1219#define S_TX_MODQ_WEIGHT0 0 1220#define M_TX_MODQ_WEIGHT0 0xffU 1221#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 1222 1223#define A_TP_TX_SCHED_HDR 0x23 1224 1225#define A_TP_TX_SCHED_FIFO 0x24 1226 1227#define A_TP_TX_SCHED_PCMD 0x25 1228 1229#define S_VNIC 11 1230#define V_VNIC(x) ((x) << S_VNIC) 1231#define F_VNIC V_VNIC(1U) 1232 1233#define S_FRAGMENTATION 9 1234#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) 1235#define F_FRAGMENTATION V_FRAGMENTATION(1U) 1236 1237#define S_MPSHITTYPE 8 1238#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) 1239#define F_MPSHITTYPE V_MPSHITTYPE(1U) 1240 1241#define S_MACMATCH 7 1242#define V_MACMATCH(x) ((x) << S_MACMATCH) 1243#define F_MACMATCH V_MACMATCH(1U) 1244 1245#define S_ETHERTYPE 6 1246#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) 1247#define F_ETHERTYPE V_ETHERTYPE(1U) 1248 1249#define S_PROTOCOL 5 1250#define V_PROTOCOL(x) ((x) << S_PROTOCOL) 1251#define F_PROTOCOL V_PROTOCOL(1U) 1252 1253#define S_TOS 4 1254#define V_TOS(x) ((x) << S_TOS) 1255#define F_TOS V_TOS(1U) 1256 1257#define S_VLAN 3 1258#define V_VLAN(x) ((x) << S_VLAN) 1259#define F_VLAN V_VLAN(1U) 1260 1261#define S_VNIC_ID 2 1262#define V_VNIC_ID(x) ((x) << S_VNIC_ID) 1263#define F_VNIC_ID V_VNIC_ID(1U) 1264 1265#define S_PORT 1 1266#define V_PORT(x) ((x) << S_PORT) 1267#define F_PORT V_PORT(1U) 1268 1269#define S_FCOE 0 1270#define V_FCOE(x) ((x) << S_FCOE) 1271#define F_FCOE V_FCOE(1U) 1272 1273#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 1274#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 1275 1276#define T5_PORT0_BASE 0x30000 1277#define T5_PORT_STRIDE 0x4000 1278#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) 1279#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) 1280 1281#define MC_0_BASE_ADDR 0x40000 1282#define MC_1_BASE_ADDR 0x48000 1283#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) 1284#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) 1285 1286#define MC_P_BIST_CMD 0x41400 1287#define MC_P_BIST_CMD_ADDR 0x41404 1288#define MC_P_BIST_CMD_LEN 0x41408 1289#define MC_P_BIST_DATA_PATTERN 0x4140c 1290#define MC_P_BIST_STATUS_RDATA 0x41488 1291#define EDC_T50_BASE_ADDR 0x50000 1292#define EDC_H_BIST_CMD 0x50004 1293#define EDC_H_BIST_CMD_ADDR 0x50008 1294#define EDC_H_BIST_CMD_LEN 0x5000c 1295#define EDC_H_BIST_DATA_PATTERN 0x50010 1296#define EDC_H_BIST_STATUS_RDATA 0x50028 1297 1298#define EDC_T51_BASE_ADDR 0x50800 1299#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 1300#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 1301 1302#define A_PL_VF_REV 0x4 1303#define A_PL_VF_WHOAMI 0x0 1304#define A_PL_VF_REVISION 0x8 1305 1306#define S_CHIPID 4 1307#define M_CHIPID 0xfU 1308#define V_CHIPID(x) ((x) << S_CHIPID) 1309#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) 1310 1311/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the 1312 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 1313 * selects for a particular field being present. These fields, when present 1314 * in the Compressed Filter Tuple, have the following widths in bits. 1315 */ 1316#define W_FT_FCOE 1 1317#define W_FT_PORT 3 1318#define W_FT_VNIC_ID 17 1319#define W_FT_VLAN 17 1320#define W_FT_TOS 8 1321#define W_FT_PROTOCOL 8 1322#define W_FT_ETHERTYPE 16 1323#define W_FT_MACMATCH 9 1324#define W_FT_MPSHITTYPE 3 1325#define W_FT_FRAGMENTATION 1 1326 1327/* Some of the Compressed Filter Tuple fields have internal structure. These 1328 * bit shifts/masks describe those structures. All shifts are relative to the 1329 * base position of the fields within the Compressed Filter Tuple 1330 */ 1331#define S_FT_VLAN_VLD 16 1332#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 1333#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 1334 1335#define S_FT_VNID_ID_VF 0 1336#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 1337 1338#define S_FT_VNID_ID_PF 7 1339#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 1340 1341#define S_FT_VNID_ID_VLD 16 1342#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 1343 1344#endif /* __T4_REGS_H */ 1345