1/* 2 * Copyright (C) 2005 - 2014 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18/* 19 * The driver sends configuration and managements command requests to the 20 * firmware in the BE. These requests are communicated to the processor 21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one 22 * WRB inside a MAILBOX. 23 * The commands are serviced by the ARM processor in the BladeEngine's MPU. 24 */ 25 26struct be_sge { 27 u32 pa_lo; 28 u32 pa_hi; 29 u32 len; 30}; 31 32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ 33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ 34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ 35struct be_mcc_wrb { 36 u32 embedded; /* dword 0 */ 37 u32 payload_length; /* dword 1 */ 38 u32 tag0; /* dword 2 */ 39 u32 tag1; /* dword 3 */ 40 u32 rsvd; /* dword 4 */ 41 union { 42 u8 embedded_payload[236]; /* used by embedded cmds */ 43 struct be_sge sgl[19]; /* used by non-embedded cmds */ 44 } payload; 45}; 46 47#define CQE_FLAGS_VALID_MASK (1 << 31) 48#define CQE_FLAGS_ASYNC_MASK (1 << 30) 49#define CQE_FLAGS_COMPLETED_MASK (1 << 28) 50#define CQE_FLAGS_CONSUMED_MASK (1 << 27) 51 52/* Completion Status */ 53enum mcc_base_status { 54 MCC_STATUS_SUCCESS = 0, 55 MCC_STATUS_FAILED = 1, 56 MCC_STATUS_ILLEGAL_REQUEST = 2, 57 MCC_STATUS_ILLEGAL_FIELD = 3, 58 MCC_STATUS_INSUFFICIENT_BUFFER = 4, 59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5, 60 MCC_STATUS_NOT_SUPPORTED = 66, 61 MCC_STATUS_FEATURE_NOT_SUPPORTED = 68 62}; 63 64/* Additional status */ 65enum mcc_addl_status { 66 MCC_ADDL_STATUS_INSUFFICIENT_RESOURCES = 0x16, 67 MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH = 0x4d, 68 MCC_ADDL_STATUS_TOO_MANY_INTERFACES = 0x4a 69}; 70 71#define CQE_BASE_STATUS_MASK 0xFFFF 72#define CQE_BASE_STATUS_SHIFT 0 /* bits 0 - 15 */ 73#define CQE_ADDL_STATUS_MASK 0xFF 74#define CQE_ADDL_STATUS_SHIFT 16 /* bits 16 - 31 */ 75 76#define base_status(status) \ 77 ((enum mcc_base_status) \ 78 (status > 0 ? (status & CQE_BASE_STATUS_MASK) : 0)) 79#define addl_status(status) \ 80 ((enum mcc_addl_status) \ 81 (status > 0 ? (status >> CQE_ADDL_STATUS_SHIFT) & \ 82 CQE_ADDL_STATUS_MASK : 0)) 83 84struct be_mcc_compl { 85 u32 status; /* dword 0 */ 86 u32 tag0; /* dword 1 */ 87 u32 tag1; /* dword 2 */ 88 u32 flags; /* dword 3 */ 89}; 90 91/* When the async bit of mcc_compl flags is set, flags 92 * is interpreted as follows: 93 */ 94#define ASYNC_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */ 95#define ASYNC_EVENT_CODE_MASK 0xFF 96#define ASYNC_EVENT_TYPE_SHIFT 16 97#define ASYNC_EVENT_TYPE_MASK 0xFF 98#define ASYNC_EVENT_CODE_LINK_STATE 0x1 99#define ASYNC_EVENT_CODE_GRP_5 0x5 100#define ASYNC_EVENT_QOS_SPEED 0x1 101#define ASYNC_EVENT_COS_PRIORITY 0x2 102#define ASYNC_EVENT_PVID_STATE 0x3 103#define ASYNC_EVENT_CODE_QNQ 0x6 104#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1 105 106enum { 107 LINK_DOWN = 0x0, 108 LINK_UP = 0x1 109}; 110#define LINK_STATUS_MASK 0x1 111#define LOGICAL_LINK_STATUS_MASK 0x2 112 113/* When the event code of compl->flags is link-state, the mcc_compl 114 * must be interpreted as follows 115 */ 116struct be_async_event_link_state { 117 u8 physical_port; 118 u8 port_link_status; 119 u8 port_duplex; 120 u8 port_speed; 121 u8 port_fault; 122 u8 rsvd0[7]; 123 u32 flags; 124} __packed; 125 126/* When the event code of compl->flags is GRP-5 and event_type is QOS_SPEED 127 * the mcc_compl must be interpreted as follows 128 */ 129struct be_async_event_grp5_qos_link_speed { 130 u8 physical_port; 131 u8 rsvd[5]; 132 u16 qos_link_speed; 133 u32 event_tag; 134 u32 flags; 135} __packed; 136 137/* When the event code of compl->flags is GRP5 and event type is 138 * CoS-Priority, the mcc_compl must be interpreted as follows 139 */ 140struct be_async_event_grp5_cos_priority { 141 u8 physical_port; 142 u8 available_priority_bmap; 143 u8 reco_default_priority; 144 u8 valid; 145 u8 rsvd0; 146 u8 event_tag; 147 u32 flags; 148} __packed; 149 150/* When the event code of compl->flags is GRP5 and event type is 151 * PVID state, the mcc_compl must be interpreted as follows 152 */ 153struct be_async_event_grp5_pvid_state { 154 u8 enabled; 155 u8 rsvd0; 156 u16 tag; 157 u32 event_tag; 158 u32 rsvd1; 159 u32 flags; 160} __packed; 161 162/* async event indicating outer VLAN tag in QnQ */ 163struct be_async_event_qnq { 164 u8 valid; /* Indicates if outer VLAN is valid */ 165 u8 rsvd0; 166 u16 vlan_tag; 167 u32 event_tag; 168 u8 rsvd1[4]; 169 u32 flags; 170} __packed; 171 172struct be_mcc_mailbox { 173 struct be_mcc_wrb wrb; 174 struct be_mcc_compl compl; 175}; 176 177#define CMD_SUBSYSTEM_COMMON 0x1 178#define CMD_SUBSYSTEM_ETH 0x3 179#define CMD_SUBSYSTEM_LOWLEVEL 0xb 180 181#define OPCODE_COMMON_NTWK_MAC_QUERY 1 182#define OPCODE_COMMON_NTWK_MAC_SET 2 183#define OPCODE_COMMON_NTWK_MULTICAST_SET 3 184#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 185#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 186#define OPCODE_COMMON_READ_FLASHROM 6 187#define OPCODE_COMMON_WRITE_FLASHROM 7 188#define OPCODE_COMMON_CQ_CREATE 12 189#define OPCODE_COMMON_EQ_CREATE 13 190#define OPCODE_COMMON_MCC_CREATE 21 191#define OPCODE_COMMON_SET_QOS 28 192#define OPCODE_COMMON_MCC_CREATE_EXT 90 193#define OPCODE_COMMON_SEEPROM_READ 30 194#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32 195#define OPCODE_COMMON_NTWK_RX_FILTER 34 196#define OPCODE_COMMON_GET_FW_VERSION 35 197#define OPCODE_COMMON_SET_FLOW_CONTROL 36 198#define OPCODE_COMMON_GET_FLOW_CONTROL 37 199#define OPCODE_COMMON_SET_FRAME_SIZE 39 200#define OPCODE_COMMON_MODIFY_EQ_DELAY 41 201#define OPCODE_COMMON_FIRMWARE_CONFIG 42 202#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 203#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 204#define OPCODE_COMMON_MCC_DESTROY 53 205#define OPCODE_COMMON_CQ_DESTROY 54 206#define OPCODE_COMMON_EQ_DESTROY 55 207#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 208#define OPCODE_COMMON_NTWK_PMAC_ADD 59 209#define OPCODE_COMMON_NTWK_PMAC_DEL 60 210#define OPCODE_COMMON_FUNCTION_RESET 61 211#define OPCODE_COMMON_MANAGE_FAT 68 212#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69 213#define OPCODE_COMMON_GET_BEACON_STATE 70 214#define OPCODE_COMMON_READ_TRANSRECV_DATA 73 215#define OPCODE_COMMON_GET_PORT_NAME 77 216#define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80 217#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89 218#define OPCODE_COMMON_SET_FN_PRIVILEGES 100 219#define OPCODE_COMMON_GET_PHY_DETAILS 102 220#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 221#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 222#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125 223#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126 224#define OPCODE_COMMON_GET_MAC_LIST 147 225#define OPCODE_COMMON_SET_MAC_LIST 148 226#define OPCODE_COMMON_GET_HSW_CONFIG 152 227#define OPCODE_COMMON_GET_FUNC_CONFIG 160 228#define OPCODE_COMMON_GET_PROFILE_CONFIG 164 229#define OPCODE_COMMON_SET_PROFILE_CONFIG 165 230#define OPCODE_COMMON_GET_ACTIVE_PROFILE 167 231#define OPCODE_COMMON_SET_HSW_CONFIG 153 232#define OPCODE_COMMON_GET_FN_PRIVILEGES 170 233#define OPCODE_COMMON_READ_OBJECT 171 234#define OPCODE_COMMON_WRITE_OBJECT 172 235#define OPCODE_COMMON_DELETE_OBJECT 174 236#define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193 237#define OPCODE_COMMON_GET_IFACE_LIST 194 238#define OPCODE_COMMON_ENABLE_DISABLE_VF 196 239 240#define OPCODE_ETH_RSS_CONFIG 1 241#define OPCODE_ETH_ACPI_CONFIG 2 242#define OPCODE_ETH_PROMISCUOUS 3 243#define OPCODE_ETH_GET_STATISTICS 4 244#define OPCODE_ETH_TX_CREATE 7 245#define OPCODE_ETH_RX_CREATE 8 246#define OPCODE_ETH_TX_DESTROY 9 247#define OPCODE_ETH_RX_DESTROY 10 248#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12 249#define OPCODE_ETH_GET_PPORT_STATS 18 250 251#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17 252#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18 253#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19 254 255struct be_cmd_req_hdr { 256 u8 opcode; /* dword 0 */ 257 u8 subsystem; /* dword 0 */ 258 u8 port_number; /* dword 0 */ 259 u8 domain; /* dword 0 */ 260 u32 timeout; /* dword 1 */ 261 u32 request_length; /* dword 2 */ 262 u8 version; /* dword 3 */ 263 u8 rsvd[3]; /* dword 3 */ 264}; 265 266#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ 267#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ 268struct be_cmd_resp_hdr { 269 u8 opcode; /* dword 0 */ 270 u8 subsystem; /* dword 0 */ 271 u8 rsvd[2]; /* dword 0 */ 272 u8 base_status; /* dword 1 */ 273 u8 addl_status; /* dword 1 */ 274 u8 rsvd1[2]; /* dword 1 */ 275 u32 response_length; /* dword 2 */ 276 u32 actual_resp_len; /* dword 3 */ 277}; 278 279struct phys_addr { 280 u32 lo; 281 u32 hi; 282}; 283 284/************************** 285 * BE Command definitions * 286 **************************/ 287 288/* Pseudo amap definition in which each bit of the actual structure is defined 289 * as a byte: used to calculate offset/shift/mask of each field */ 290struct amap_eq_context { 291 u8 cidx[13]; /* dword 0*/ 292 u8 rsvd0[3]; /* dword 0*/ 293 u8 epidx[13]; /* dword 0*/ 294 u8 valid; /* dword 0*/ 295 u8 rsvd1; /* dword 0*/ 296 u8 size; /* dword 0*/ 297 u8 pidx[13]; /* dword 1*/ 298 u8 rsvd2[3]; /* dword 1*/ 299 u8 pd[10]; /* dword 1*/ 300 u8 count[3]; /* dword 1*/ 301 u8 solevent; /* dword 1*/ 302 u8 stalled; /* dword 1*/ 303 u8 armed; /* dword 1*/ 304 u8 rsvd3[4]; /* dword 2*/ 305 u8 func[8]; /* dword 2*/ 306 u8 rsvd4; /* dword 2*/ 307 u8 delaymult[10]; /* dword 2*/ 308 u8 rsvd5[2]; /* dword 2*/ 309 u8 phase[2]; /* dword 2*/ 310 u8 nodelay; /* dword 2*/ 311 u8 rsvd6[4]; /* dword 2*/ 312 u8 rsvd7[32]; /* dword 3*/ 313} __packed; 314 315struct be_cmd_req_eq_create { 316 struct be_cmd_req_hdr hdr; 317 u16 num_pages; /* sword */ 318 u16 rsvd0; /* sword */ 319 u8 context[sizeof(struct amap_eq_context) / 8]; 320 struct phys_addr pages[8]; 321} __packed; 322 323struct be_cmd_resp_eq_create { 324 struct be_cmd_resp_hdr resp_hdr; 325 u16 eq_id; /* sword */ 326 u16 msix_idx; /* available only in v2 */ 327} __packed; 328 329/******************** Mac query ***************************/ 330enum { 331 MAC_ADDRESS_TYPE_STORAGE = 0x0, 332 MAC_ADDRESS_TYPE_NETWORK = 0x1, 333 MAC_ADDRESS_TYPE_PD = 0x2, 334 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 335}; 336 337struct mac_addr { 338 u16 size_of_struct; 339 u8 addr[ETH_ALEN]; 340} __packed; 341 342struct be_cmd_req_mac_query { 343 struct be_cmd_req_hdr hdr; 344 u8 type; 345 u8 permanent; 346 u16 if_id; 347 u32 pmac_id; 348} __packed; 349 350struct be_cmd_resp_mac_query { 351 struct be_cmd_resp_hdr hdr; 352 struct mac_addr mac; 353}; 354 355/******************** PMac Add ***************************/ 356struct be_cmd_req_pmac_add { 357 struct be_cmd_req_hdr hdr; 358 u32 if_id; 359 u8 mac_address[ETH_ALEN]; 360 u8 rsvd0[2]; 361} __packed; 362 363struct be_cmd_resp_pmac_add { 364 struct be_cmd_resp_hdr hdr; 365 u32 pmac_id; 366}; 367 368/******************** PMac Del ***************************/ 369struct be_cmd_req_pmac_del { 370 struct be_cmd_req_hdr hdr; 371 u32 if_id; 372 u32 pmac_id; 373}; 374 375/******************** Create CQ ***************************/ 376/* Pseudo amap definition in which each bit of the actual structure is defined 377 * as a byte: used to calculate offset/shift/mask of each field */ 378struct amap_cq_context_be { 379 u8 cidx[11]; /* dword 0*/ 380 u8 rsvd0; /* dword 0*/ 381 u8 coalescwm[2]; /* dword 0*/ 382 u8 nodelay; /* dword 0*/ 383 u8 epidx[11]; /* dword 0*/ 384 u8 rsvd1; /* dword 0*/ 385 u8 count[2]; /* dword 0*/ 386 u8 valid; /* dword 0*/ 387 u8 solevent; /* dword 0*/ 388 u8 eventable; /* dword 0*/ 389 u8 pidx[11]; /* dword 1*/ 390 u8 rsvd2; /* dword 1*/ 391 u8 pd[10]; /* dword 1*/ 392 u8 eqid[8]; /* dword 1*/ 393 u8 stalled; /* dword 1*/ 394 u8 armed; /* dword 1*/ 395 u8 rsvd3[4]; /* dword 2*/ 396 u8 func[8]; /* dword 2*/ 397 u8 rsvd4[20]; /* dword 2*/ 398 u8 rsvd5[32]; /* dword 3*/ 399} __packed; 400 401struct amap_cq_context_v2 { 402 u8 rsvd0[12]; /* dword 0*/ 403 u8 coalescwm[2]; /* dword 0*/ 404 u8 nodelay; /* dword 0*/ 405 u8 rsvd1[12]; /* dword 0*/ 406 u8 count[2]; /* dword 0*/ 407 u8 valid; /* dword 0*/ 408 u8 rsvd2; /* dword 0*/ 409 u8 eventable; /* dword 0*/ 410 u8 eqid[16]; /* dword 1*/ 411 u8 rsvd3[15]; /* dword 1*/ 412 u8 armed; /* dword 1*/ 413 u8 rsvd4[32]; /* dword 2*/ 414 u8 rsvd5[32]; /* dword 3*/ 415} __packed; 416 417struct be_cmd_req_cq_create { 418 struct be_cmd_req_hdr hdr; 419 u16 num_pages; 420 u8 page_size; 421 u8 rsvd0; 422 u8 context[sizeof(struct amap_cq_context_be) / 8]; 423 struct phys_addr pages[8]; 424} __packed; 425 426 427struct be_cmd_resp_cq_create { 428 struct be_cmd_resp_hdr hdr; 429 u16 cq_id; 430 u16 rsvd0; 431} __packed; 432 433struct be_cmd_req_get_fat { 434 struct be_cmd_req_hdr hdr; 435 u32 fat_operation; 436 u32 read_log_offset; 437 u32 read_log_length; 438 u32 data_buffer_size; 439 u32 data_buffer[1]; 440} __packed; 441 442struct be_cmd_resp_get_fat { 443 struct be_cmd_resp_hdr hdr; 444 u32 log_size; 445 u32 read_log_length; 446 u32 rsvd[2]; 447 u32 data_buffer[1]; 448} __packed; 449 450 451/******************** Create MCCQ ***************************/ 452/* Pseudo amap definition in which each bit of the actual structure is defined 453 * as a byte: used to calculate offset/shift/mask of each field */ 454struct amap_mcc_context_be { 455 u8 con_index[14]; 456 u8 rsvd0[2]; 457 u8 ring_size[4]; 458 u8 fetch_wrb; 459 u8 fetch_r2t; 460 u8 cq_id[10]; 461 u8 prod_index[14]; 462 u8 fid[8]; 463 u8 pdid[9]; 464 u8 valid; 465 u8 rsvd1[32]; 466 u8 rsvd2[32]; 467} __packed; 468 469struct amap_mcc_context_v1 { 470 u8 async_cq_id[16]; 471 u8 ring_size[4]; 472 u8 rsvd0[12]; 473 u8 rsvd1[31]; 474 u8 valid; 475 u8 async_cq_valid[1]; 476 u8 rsvd2[31]; 477 u8 rsvd3[32]; 478} __packed; 479 480struct be_cmd_req_mcc_create { 481 struct be_cmd_req_hdr hdr; 482 u16 num_pages; 483 u16 cq_id; 484 u8 context[sizeof(struct amap_mcc_context_be) / 8]; 485 struct phys_addr pages[8]; 486} __packed; 487 488struct be_cmd_req_mcc_ext_create { 489 struct be_cmd_req_hdr hdr; 490 u16 num_pages; 491 u16 cq_id; 492 u32 async_event_bitmap[1]; 493 u8 context[sizeof(struct amap_mcc_context_v1) / 8]; 494 struct phys_addr pages[8]; 495} __packed; 496 497struct be_cmd_resp_mcc_create { 498 struct be_cmd_resp_hdr hdr; 499 u16 id; 500 u16 rsvd0; 501} __packed; 502 503/******************** Create TxQ ***************************/ 504#define BE_ETH_TX_RING_TYPE_STANDARD 2 505#define BE_ULP1_NUM 1 506 507struct be_cmd_req_eth_tx_create { 508 struct be_cmd_req_hdr hdr; 509 u8 num_pages; 510 u8 ulp_num; 511 u16 type; 512 u16 if_id; 513 u8 queue_size; 514 u8 rsvd0; 515 u32 rsvd1; 516 u16 cq_id; 517 u16 rsvd2; 518 u32 rsvd3[13]; 519 struct phys_addr pages[8]; 520} __packed; 521 522struct be_cmd_resp_eth_tx_create { 523 struct be_cmd_resp_hdr hdr; 524 u16 cid; 525 u16 rid; 526 u32 db_offset; 527 u32 rsvd0[4]; 528} __packed; 529 530/******************** Create RxQ ***************************/ 531struct be_cmd_req_eth_rx_create { 532 struct be_cmd_req_hdr hdr; 533 u16 cq_id; 534 u8 frag_size; 535 u8 num_pages; 536 struct phys_addr pages[2]; 537 u32 interface_id; 538 u16 max_frame_size; 539 u16 rsvd0; 540 u32 rss_queue; 541} __packed; 542 543struct be_cmd_resp_eth_rx_create { 544 struct be_cmd_resp_hdr hdr; 545 u16 id; 546 u8 rss_id; 547 u8 rsvd0; 548} __packed; 549 550/******************** Q Destroy ***************************/ 551/* Type of Queue to be destroyed */ 552enum { 553 QTYPE_EQ = 1, 554 QTYPE_CQ, 555 QTYPE_TXQ, 556 QTYPE_RXQ, 557 QTYPE_MCCQ 558}; 559 560struct be_cmd_req_q_destroy { 561 struct be_cmd_req_hdr hdr; 562 u16 id; 563 u16 bypass_flush; /* valid only for rx q destroy */ 564} __packed; 565 566/************ I/f Create (it's actually I/f Config Create)**********/ 567 568/* Capability flags for the i/f */ 569enum be_if_flags { 570 BE_IF_FLAGS_RSS = 0x4, 571 BE_IF_FLAGS_PROMISCUOUS = 0x8, 572 BE_IF_FLAGS_BROADCAST = 0x10, 573 BE_IF_FLAGS_UNTAGGED = 0x20, 574 BE_IF_FLAGS_ULP = 0x40, 575 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, 576 BE_IF_FLAGS_VLAN = 0x100, 577 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, 578 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, 579 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800, 580 BE_IF_FLAGS_MULTICAST = 0x1000 581}; 582 583#define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\ 584 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\ 585 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\ 586 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\ 587 BE_IF_FLAGS_UNTAGGED) 588 589/* An RX interface is an object with one or more MAC addresses and 590 * filtering capabilities. */ 591struct be_cmd_req_if_create { 592 struct be_cmd_req_hdr hdr; 593 u32 version; /* ignore currently */ 594 u32 capability_flags; 595 u32 enable_flags; 596 u8 mac_addr[ETH_ALEN]; 597 u8 rsvd0; 598 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ 599 u32 vlan_tag; /* not used currently */ 600} __packed; 601 602struct be_cmd_resp_if_create { 603 struct be_cmd_resp_hdr hdr; 604 u32 interface_id; 605 u32 pmac_id; 606}; 607 608/****** I/f Destroy(it's actually I/f Config Destroy )**********/ 609struct be_cmd_req_if_destroy { 610 struct be_cmd_req_hdr hdr; 611 u32 interface_id; 612}; 613 614/*************** HW Stats Get **********************************/ 615struct be_port_rxf_stats_v0 { 616 u32 rx_bytes_lsd; /* dword 0*/ 617 u32 rx_bytes_msd; /* dword 1*/ 618 u32 rx_total_frames; /* dword 2*/ 619 u32 rx_unicast_frames; /* dword 3*/ 620 u32 rx_multicast_frames; /* dword 4*/ 621 u32 rx_broadcast_frames; /* dword 5*/ 622 u32 rx_crc_errors; /* dword 6*/ 623 u32 rx_alignment_symbol_errors; /* dword 7*/ 624 u32 rx_pause_frames; /* dword 8*/ 625 u32 rx_control_frames; /* dword 9*/ 626 u32 rx_in_range_errors; /* dword 10*/ 627 u32 rx_out_range_errors; /* dword 11*/ 628 u32 rx_frame_too_long; /* dword 12*/ 629 u32 rx_address_filtered; /* dword 13*/ 630 u32 rx_vlan_filtered; /* dword 14*/ 631 u32 rx_dropped_too_small; /* dword 15*/ 632 u32 rx_dropped_too_short; /* dword 16*/ 633 u32 rx_dropped_header_too_small; /* dword 17*/ 634 u32 rx_dropped_tcp_length; /* dword 18*/ 635 u32 rx_dropped_runt; /* dword 19*/ 636 u32 rx_64_byte_packets; /* dword 20*/ 637 u32 rx_65_127_byte_packets; /* dword 21*/ 638 u32 rx_128_256_byte_packets; /* dword 22*/ 639 u32 rx_256_511_byte_packets; /* dword 23*/ 640 u32 rx_512_1023_byte_packets; /* dword 24*/ 641 u32 rx_1024_1518_byte_packets; /* dword 25*/ 642 u32 rx_1519_2047_byte_packets; /* dword 26*/ 643 u32 rx_2048_4095_byte_packets; /* dword 27*/ 644 u32 rx_4096_8191_byte_packets; /* dword 28*/ 645 u32 rx_8192_9216_byte_packets; /* dword 29*/ 646 u32 rx_ip_checksum_errs; /* dword 30*/ 647 u32 rx_tcp_checksum_errs; /* dword 31*/ 648 u32 rx_udp_checksum_errs; /* dword 32*/ 649 u32 rx_non_rss_packets; /* dword 33*/ 650 u32 rx_ipv4_packets; /* dword 34*/ 651 u32 rx_ipv6_packets; /* dword 35*/ 652 u32 rx_ipv4_bytes_lsd; /* dword 36*/ 653 u32 rx_ipv4_bytes_msd; /* dword 37*/ 654 u32 rx_ipv6_bytes_lsd; /* dword 38*/ 655 u32 rx_ipv6_bytes_msd; /* dword 39*/ 656 u32 rx_chute1_packets; /* dword 40*/ 657 u32 rx_chute2_packets; /* dword 41*/ 658 u32 rx_chute3_packets; /* dword 42*/ 659 u32 rx_management_packets; /* dword 43*/ 660 u32 rx_switched_unicast_packets; /* dword 44*/ 661 u32 rx_switched_multicast_packets; /* dword 45*/ 662 u32 rx_switched_broadcast_packets; /* dword 46*/ 663 u32 tx_bytes_lsd; /* dword 47*/ 664 u32 tx_bytes_msd; /* dword 48*/ 665 u32 tx_unicastframes; /* dword 49*/ 666 u32 tx_multicastframes; /* dword 50*/ 667 u32 tx_broadcastframes; /* dword 51*/ 668 u32 tx_pauseframes; /* dword 52*/ 669 u32 tx_controlframes; /* dword 53*/ 670 u32 tx_64_byte_packets; /* dword 54*/ 671 u32 tx_65_127_byte_packets; /* dword 55*/ 672 u32 tx_128_256_byte_packets; /* dword 56*/ 673 u32 tx_256_511_byte_packets; /* dword 57*/ 674 u32 tx_512_1023_byte_packets; /* dword 58*/ 675 u32 tx_1024_1518_byte_packets; /* dword 59*/ 676 u32 tx_1519_2047_byte_packets; /* dword 60*/ 677 u32 tx_2048_4095_byte_packets; /* dword 61*/ 678 u32 tx_4096_8191_byte_packets; /* dword 62*/ 679 u32 tx_8192_9216_byte_packets; /* dword 63*/ 680 u32 rx_fifo_overflow; /* dword 64*/ 681 u32 rx_input_fifo_overflow; /* dword 65*/ 682}; 683 684struct be_rxf_stats_v0 { 685 struct be_port_rxf_stats_v0 port[2]; 686 u32 rx_drops_no_pbuf; /* dword 132*/ 687 u32 rx_drops_no_txpb; /* dword 133*/ 688 u32 rx_drops_no_erx_descr; /* dword 134*/ 689 u32 rx_drops_no_tpre_descr; /* dword 135*/ 690 u32 management_rx_port_packets; /* dword 136*/ 691 u32 management_rx_port_bytes; /* dword 137*/ 692 u32 management_rx_port_pause_frames; /* dword 138*/ 693 u32 management_rx_port_errors; /* dword 139*/ 694 u32 management_tx_port_packets; /* dword 140*/ 695 u32 management_tx_port_bytes; /* dword 141*/ 696 u32 management_tx_port_pause; /* dword 142*/ 697 u32 management_rx_port_rxfifo_overflow; /* dword 143*/ 698 u32 rx_drops_too_many_frags; /* dword 144*/ 699 u32 rx_drops_invalid_ring; /* dword 145*/ 700 u32 forwarded_packets; /* dword 146*/ 701 u32 rx_drops_mtu; /* dword 147*/ 702 u32 rsvd0[7]; 703 u32 port0_jabber_events; 704 u32 port1_jabber_events; 705 u32 rsvd1[6]; 706}; 707 708struct be_erx_stats_v0 { 709 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ 710 u32 rsvd[4]; 711}; 712 713struct be_pmem_stats { 714 u32 eth_red_drops; 715 u32 rsvd[5]; 716}; 717 718struct be_hw_stats_v0 { 719 struct be_rxf_stats_v0 rxf; 720 u32 rsvd[48]; 721 struct be_erx_stats_v0 erx; 722 struct be_pmem_stats pmem; 723}; 724 725struct be_cmd_req_get_stats_v0 { 726 struct be_cmd_req_hdr hdr; 727 u8 rsvd[sizeof(struct be_hw_stats_v0)]; 728}; 729 730struct be_cmd_resp_get_stats_v0 { 731 struct be_cmd_resp_hdr hdr; 732 struct be_hw_stats_v0 hw_stats; 733}; 734 735struct lancer_pport_stats { 736 u32 tx_packets_lo; 737 u32 tx_packets_hi; 738 u32 tx_unicast_packets_lo; 739 u32 tx_unicast_packets_hi; 740 u32 tx_multicast_packets_lo; 741 u32 tx_multicast_packets_hi; 742 u32 tx_broadcast_packets_lo; 743 u32 tx_broadcast_packets_hi; 744 u32 tx_bytes_lo; 745 u32 tx_bytes_hi; 746 u32 tx_unicast_bytes_lo; 747 u32 tx_unicast_bytes_hi; 748 u32 tx_multicast_bytes_lo; 749 u32 tx_multicast_bytes_hi; 750 u32 tx_broadcast_bytes_lo; 751 u32 tx_broadcast_bytes_hi; 752 u32 tx_discards_lo; 753 u32 tx_discards_hi; 754 u32 tx_errors_lo; 755 u32 tx_errors_hi; 756 u32 tx_pause_frames_lo; 757 u32 tx_pause_frames_hi; 758 u32 tx_pause_on_frames_lo; 759 u32 tx_pause_on_frames_hi; 760 u32 tx_pause_off_frames_lo; 761 u32 tx_pause_off_frames_hi; 762 u32 tx_internal_mac_errors_lo; 763 u32 tx_internal_mac_errors_hi; 764 u32 tx_control_frames_lo; 765 u32 tx_control_frames_hi; 766 u32 tx_packets_64_bytes_lo; 767 u32 tx_packets_64_bytes_hi; 768 u32 tx_packets_65_to_127_bytes_lo; 769 u32 tx_packets_65_to_127_bytes_hi; 770 u32 tx_packets_128_to_255_bytes_lo; 771 u32 tx_packets_128_to_255_bytes_hi; 772 u32 tx_packets_256_to_511_bytes_lo; 773 u32 tx_packets_256_to_511_bytes_hi; 774 u32 tx_packets_512_to_1023_bytes_lo; 775 u32 tx_packets_512_to_1023_bytes_hi; 776 u32 tx_packets_1024_to_1518_bytes_lo; 777 u32 tx_packets_1024_to_1518_bytes_hi; 778 u32 tx_packets_1519_to_2047_bytes_lo; 779 u32 tx_packets_1519_to_2047_bytes_hi; 780 u32 tx_packets_2048_to_4095_bytes_lo; 781 u32 tx_packets_2048_to_4095_bytes_hi; 782 u32 tx_packets_4096_to_8191_bytes_lo; 783 u32 tx_packets_4096_to_8191_bytes_hi; 784 u32 tx_packets_8192_to_9216_bytes_lo; 785 u32 tx_packets_8192_to_9216_bytes_hi; 786 u32 tx_lso_packets_lo; 787 u32 tx_lso_packets_hi; 788 u32 rx_packets_lo; 789 u32 rx_packets_hi; 790 u32 rx_unicast_packets_lo; 791 u32 rx_unicast_packets_hi; 792 u32 rx_multicast_packets_lo; 793 u32 rx_multicast_packets_hi; 794 u32 rx_broadcast_packets_lo; 795 u32 rx_broadcast_packets_hi; 796 u32 rx_bytes_lo; 797 u32 rx_bytes_hi; 798 u32 rx_unicast_bytes_lo; 799 u32 rx_unicast_bytes_hi; 800 u32 rx_multicast_bytes_lo; 801 u32 rx_multicast_bytes_hi; 802 u32 rx_broadcast_bytes_lo; 803 u32 rx_broadcast_bytes_hi; 804 u32 rx_unknown_protos; 805 u32 rsvd_69; /* Word 69 is reserved */ 806 u32 rx_discards_lo; 807 u32 rx_discards_hi; 808 u32 rx_errors_lo; 809 u32 rx_errors_hi; 810 u32 rx_crc_errors_lo; 811 u32 rx_crc_errors_hi; 812 u32 rx_alignment_errors_lo; 813 u32 rx_alignment_errors_hi; 814 u32 rx_symbol_errors_lo; 815 u32 rx_symbol_errors_hi; 816 u32 rx_pause_frames_lo; 817 u32 rx_pause_frames_hi; 818 u32 rx_pause_on_frames_lo; 819 u32 rx_pause_on_frames_hi; 820 u32 rx_pause_off_frames_lo; 821 u32 rx_pause_off_frames_hi; 822 u32 rx_frames_too_long_lo; 823 u32 rx_frames_too_long_hi; 824 u32 rx_internal_mac_errors_lo; 825 u32 rx_internal_mac_errors_hi; 826 u32 rx_undersize_packets; 827 u32 rx_oversize_packets; 828 u32 rx_fragment_packets; 829 u32 rx_jabbers; 830 u32 rx_control_frames_lo; 831 u32 rx_control_frames_hi; 832 u32 rx_control_frames_unknown_opcode_lo; 833 u32 rx_control_frames_unknown_opcode_hi; 834 u32 rx_in_range_errors; 835 u32 rx_out_of_range_errors; 836 u32 rx_address_filtered; 837 u32 rx_vlan_filtered; 838 u32 rx_dropped_too_small; 839 u32 rx_dropped_too_short; 840 u32 rx_dropped_header_too_small; 841 u32 rx_dropped_invalid_tcp_length; 842 u32 rx_dropped_runt; 843 u32 rx_ip_checksum_errors; 844 u32 rx_tcp_checksum_errors; 845 u32 rx_udp_checksum_errors; 846 u32 rx_non_rss_packets; 847 u32 rsvd_111; 848 u32 rx_ipv4_packets_lo; 849 u32 rx_ipv4_packets_hi; 850 u32 rx_ipv6_packets_lo; 851 u32 rx_ipv6_packets_hi; 852 u32 rx_ipv4_bytes_lo; 853 u32 rx_ipv4_bytes_hi; 854 u32 rx_ipv6_bytes_lo; 855 u32 rx_ipv6_bytes_hi; 856 u32 rx_nic_packets_lo; 857 u32 rx_nic_packets_hi; 858 u32 rx_tcp_packets_lo; 859 u32 rx_tcp_packets_hi; 860 u32 rx_iscsi_packets_lo; 861 u32 rx_iscsi_packets_hi; 862 u32 rx_management_packets_lo; 863 u32 rx_management_packets_hi; 864 u32 rx_switched_unicast_packets_lo; 865 u32 rx_switched_unicast_packets_hi; 866 u32 rx_switched_multicast_packets_lo; 867 u32 rx_switched_multicast_packets_hi; 868 u32 rx_switched_broadcast_packets_lo; 869 u32 rx_switched_broadcast_packets_hi; 870 u32 num_forwards_lo; 871 u32 num_forwards_hi; 872 u32 rx_fifo_overflow; 873 u32 rx_input_fifo_overflow; 874 u32 rx_drops_too_many_frags_lo; 875 u32 rx_drops_too_many_frags_hi; 876 u32 rx_drops_invalid_queue; 877 u32 rsvd_141; 878 u32 rx_drops_mtu_lo; 879 u32 rx_drops_mtu_hi; 880 u32 rx_packets_64_bytes_lo; 881 u32 rx_packets_64_bytes_hi; 882 u32 rx_packets_65_to_127_bytes_lo; 883 u32 rx_packets_65_to_127_bytes_hi; 884 u32 rx_packets_128_to_255_bytes_lo; 885 u32 rx_packets_128_to_255_bytes_hi; 886 u32 rx_packets_256_to_511_bytes_lo; 887 u32 rx_packets_256_to_511_bytes_hi; 888 u32 rx_packets_512_to_1023_bytes_lo; 889 u32 rx_packets_512_to_1023_bytes_hi; 890 u32 rx_packets_1024_to_1518_bytes_lo; 891 u32 rx_packets_1024_to_1518_bytes_hi; 892 u32 rx_packets_1519_to_2047_bytes_lo; 893 u32 rx_packets_1519_to_2047_bytes_hi; 894 u32 rx_packets_2048_to_4095_bytes_lo; 895 u32 rx_packets_2048_to_4095_bytes_hi; 896 u32 rx_packets_4096_to_8191_bytes_lo; 897 u32 rx_packets_4096_to_8191_bytes_hi; 898 u32 rx_packets_8192_to_9216_bytes_lo; 899 u32 rx_packets_8192_to_9216_bytes_hi; 900}; 901 902struct pport_stats_params { 903 u16 pport_num; 904 u8 rsvd; 905 u8 reset_stats; 906}; 907 908struct lancer_cmd_req_pport_stats { 909 struct be_cmd_req_hdr hdr; 910 union { 911 struct pport_stats_params params; 912 u8 rsvd[sizeof(struct lancer_pport_stats)]; 913 } cmd_params; 914}; 915 916struct lancer_cmd_resp_pport_stats { 917 struct be_cmd_resp_hdr hdr; 918 struct lancer_pport_stats pport_stats; 919}; 920 921static inline struct lancer_pport_stats* 922 pport_stats_from_cmd(struct be_adapter *adapter) 923{ 924 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va; 925 return &cmd->pport_stats; 926} 927 928struct be_cmd_req_get_cntl_addnl_attribs { 929 struct be_cmd_req_hdr hdr; 930 u8 rsvd[8]; 931}; 932 933struct be_cmd_resp_get_cntl_addnl_attribs { 934 struct be_cmd_resp_hdr hdr; 935 u16 ipl_file_number; 936 u8 ipl_file_version; 937 u8 rsvd0; 938 u8 on_die_temperature; /* in degrees centigrade*/ 939 u8 rsvd1[3]; 940}; 941 942struct be_cmd_req_vlan_config { 943 struct be_cmd_req_hdr hdr; 944 u8 interface_id; 945 u8 promiscuous; 946 u8 untagged; 947 u8 num_vlan; 948 u16 normal_vlan[64]; 949} __packed; 950 951/******************* RX FILTER ******************************/ 952#define BE_MAX_MC 64 /* set mcast promisc if > 64 */ 953struct macaddr { 954 u8 byte[ETH_ALEN]; 955}; 956 957struct be_cmd_req_rx_filter { 958 struct be_cmd_req_hdr hdr; 959 u32 global_flags_mask; 960 u32 global_flags; 961 u32 if_flags_mask; 962 u32 if_flags; 963 u32 if_id; 964 u32 mcast_num; 965 struct macaddr mcast_mac[BE_MAX_MC]; 966}; 967 968/******************** Link Status Query *******************/ 969struct be_cmd_req_link_status { 970 struct be_cmd_req_hdr hdr; 971 u32 rsvd; 972}; 973 974enum { 975 PHY_LINK_DUPLEX_NONE = 0x0, 976 PHY_LINK_DUPLEX_HALF = 0x1, 977 PHY_LINK_DUPLEX_FULL = 0x2 978}; 979 980enum { 981 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ 982 PHY_LINK_SPEED_10MBPS = 0x1, 983 PHY_LINK_SPEED_100MBPS = 0x2, 984 PHY_LINK_SPEED_1GBPS = 0x3, 985 PHY_LINK_SPEED_10GBPS = 0x4, 986 PHY_LINK_SPEED_20GBPS = 0x5, 987 PHY_LINK_SPEED_25GBPS = 0x6, 988 PHY_LINK_SPEED_40GBPS = 0x7 989}; 990 991struct be_cmd_resp_link_status { 992 struct be_cmd_resp_hdr hdr; 993 u8 physical_port; 994 u8 mac_duplex; 995 u8 mac_speed; 996 u8 mac_fault; 997 u8 mgmt_mac_duplex; 998 u8 mgmt_mac_speed; 999 u16 link_speed; 1000 u8 logical_link_status; 1001 u8 rsvd1[3]; 1002} __packed; 1003 1004/******************** Port Identification ***************************/ 1005/* Identifies the type of port attached to NIC */ 1006struct be_cmd_req_port_type { 1007 struct be_cmd_req_hdr hdr; 1008 __le32 page_num; 1009 __le32 port; 1010}; 1011 1012enum { 1013 TR_PAGE_A0 = 0xa0, 1014 TR_PAGE_A2 = 0xa2 1015}; 1016 1017/* From SFF-8436 QSFP+ spec */ 1018#define QSFP_PLUS_CABLE_TYPE_OFFSET 0x83 1019#define QSFP_PLUS_CR4_CABLE 0x8 1020#define QSFP_PLUS_SR4_CABLE 0x4 1021#define QSFP_PLUS_LR4_CABLE 0x2 1022 1023/* From SFF-8472 spec */ 1024#define SFP_PLUS_SFF_8472_COMP 0x5E 1025#define SFP_PLUS_CABLE_TYPE_OFFSET 0x8 1026#define SFP_PLUS_COPPER_CABLE 0x4 1027 1028#define PAGE_DATA_LEN 256 1029struct be_cmd_resp_port_type { 1030 struct be_cmd_resp_hdr hdr; 1031 u32 page_num; 1032 u32 port; 1033 u8 page_data[PAGE_DATA_LEN]; 1034}; 1035 1036/******************** Get FW Version *******************/ 1037struct be_cmd_req_get_fw_version { 1038 struct be_cmd_req_hdr hdr; 1039 u8 rsvd0[FW_VER_LEN]; 1040 u8 rsvd1[FW_VER_LEN]; 1041} __packed; 1042 1043struct be_cmd_resp_get_fw_version { 1044 struct be_cmd_resp_hdr hdr; 1045 u8 firmware_version_string[FW_VER_LEN]; 1046 u8 fw_on_flash_version_string[FW_VER_LEN]; 1047} __packed; 1048 1049/******************** Set Flow Contrl *******************/ 1050struct be_cmd_req_set_flow_control { 1051 struct be_cmd_req_hdr hdr; 1052 u16 tx_flow_control; 1053 u16 rx_flow_control; 1054} __packed; 1055 1056/******************** Get Flow Contrl *******************/ 1057struct be_cmd_req_get_flow_control { 1058 struct be_cmd_req_hdr hdr; 1059 u32 rsvd; 1060}; 1061 1062struct be_cmd_resp_get_flow_control { 1063 struct be_cmd_resp_hdr hdr; 1064 u16 tx_flow_control; 1065 u16 rx_flow_control; 1066} __packed; 1067 1068/******************** Modify EQ Delay *******************/ 1069struct be_set_eqd { 1070 u32 eq_id; 1071 u32 phase; 1072 u32 delay_multiplier; 1073}; 1074 1075struct be_cmd_req_modify_eq_delay { 1076 struct be_cmd_req_hdr hdr; 1077 u32 num_eq; 1078 struct be_set_eqd set_eqd[MAX_EVT_QS]; 1079} __packed; 1080 1081/******************** Get FW Config *******************/ 1082/* The HW can come up in either of the following multi-channel modes 1083 * based on the skew/IPL. 1084 */ 1085#define RDMA_ENABLED 0x4 1086#define QNQ_MODE 0x400 1087#define VNIC_MODE 0x20000 1088#define UMC_ENABLED 0x1000000 1089struct be_cmd_req_query_fw_cfg { 1090 struct be_cmd_req_hdr hdr; 1091 u32 rsvd[31]; 1092}; 1093 1094struct be_cmd_resp_query_fw_cfg { 1095 struct be_cmd_resp_hdr hdr; 1096 u32 be_config_number; 1097 u32 asic_revision; 1098 u32 phys_port; 1099 u32 function_mode; 1100 u32 rsvd[26]; 1101 u32 function_caps; 1102}; 1103 1104/******************** RSS Config ****************************************/ 1105/* RSS type Input parameters used to compute RX hash 1106 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4 1107 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT 1108 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6 1109 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT 1110 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT 1111 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT 1112 * 1113 * When multiple RSS types are enabled, HW picks the best hash policy 1114 * based on the type of the received packet. 1115 */ 1116#define RSS_ENABLE_NONE 0x0 1117#define RSS_ENABLE_IPV4 0x1 1118#define RSS_ENABLE_TCP_IPV4 0x2 1119#define RSS_ENABLE_IPV6 0x4 1120#define RSS_ENABLE_TCP_IPV6 0x8 1121#define RSS_ENABLE_UDP_IPV4 0x10 1122#define RSS_ENABLE_UDP_IPV6 0x20 1123 1124#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC) 1125#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3) 1126 1127struct be_cmd_req_rss_config { 1128 struct be_cmd_req_hdr hdr; 1129 u32 if_id; 1130 u16 enable_rss; 1131 u16 cpu_table_size_log2; 1132 u32 hash[10]; 1133 u8 cpu_table[128]; 1134 u8 flush; 1135 u8 rsvd0[3]; 1136}; 1137 1138/******************** Port Beacon ***************************/ 1139 1140#define BEACON_STATE_ENABLED 0x1 1141#define BEACON_STATE_DISABLED 0x0 1142 1143struct be_cmd_req_enable_disable_beacon { 1144 struct be_cmd_req_hdr hdr; 1145 u8 port_num; 1146 u8 beacon_state; 1147 u8 beacon_duration; 1148 u8 status_duration; 1149} __packed; 1150 1151struct be_cmd_req_get_beacon_state { 1152 struct be_cmd_req_hdr hdr; 1153 u8 port_num; 1154 u8 rsvd0; 1155 u16 rsvd1; 1156} __packed; 1157 1158struct be_cmd_resp_get_beacon_state { 1159 struct be_cmd_resp_hdr resp_hdr; 1160 u8 beacon_state; 1161 u8 rsvd0[3]; 1162} __packed; 1163 1164/****************** Firmware Flash ******************/ 1165struct flashrom_params { 1166 u32 op_code; 1167 u32 op_type; 1168 u32 data_buf_size; 1169 u32 offset; 1170}; 1171 1172struct be_cmd_write_flashrom { 1173 struct be_cmd_req_hdr hdr; 1174 struct flashrom_params params; 1175 u8 data_buf[32768]; 1176 u8 rsvd[4]; 1177} __packed; 1178 1179/* cmd to read flash crc */ 1180struct be_cmd_read_flash_crc { 1181 struct be_cmd_req_hdr hdr; 1182 struct flashrom_params params; 1183 u8 crc[4]; 1184 u8 rsvd[4]; 1185} __packed; 1186 1187/**************** Lancer Firmware Flash ************/ 1188struct amap_lancer_write_obj_context { 1189 u8 write_length[24]; 1190 u8 reserved1[7]; 1191 u8 eof; 1192} __packed; 1193 1194struct lancer_cmd_req_write_object { 1195 struct be_cmd_req_hdr hdr; 1196 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8]; 1197 u32 write_offset; 1198 u8 object_name[104]; 1199 u32 descriptor_count; 1200 u32 buf_len; 1201 u32 addr_low; 1202 u32 addr_high; 1203}; 1204 1205#define LANCER_NO_RESET_NEEDED 0x00 1206#define LANCER_FW_RESET_NEEDED 0x02 1207struct lancer_cmd_resp_write_object { 1208 u8 opcode; 1209 u8 subsystem; 1210 u8 rsvd1[2]; 1211 u8 status; 1212 u8 additional_status; 1213 u8 rsvd2[2]; 1214 u32 resp_len; 1215 u32 actual_resp_len; 1216 u32 actual_write_len; 1217 u8 change_status; 1218 u8 rsvd3[3]; 1219}; 1220 1221/************************ Lancer Read FW info **************/ 1222#define LANCER_READ_FILE_CHUNK (32*1024) 1223#define LANCER_READ_FILE_EOF_MASK 0x80000000 1224 1225#define LANCER_FW_DUMP_FILE "/dbg/dump.bin" 1226#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd" 1227#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd" 1228 1229struct lancer_cmd_req_read_object { 1230 struct be_cmd_req_hdr hdr; 1231 u32 desired_read_len; 1232 u32 read_offset; 1233 u8 object_name[104]; 1234 u32 descriptor_count; 1235 u32 buf_len; 1236 u32 addr_low; 1237 u32 addr_high; 1238}; 1239 1240struct lancer_cmd_resp_read_object { 1241 u8 opcode; 1242 u8 subsystem; 1243 u8 rsvd1[2]; 1244 u8 status; 1245 u8 additional_status; 1246 u8 rsvd2[2]; 1247 u32 resp_len; 1248 u32 actual_resp_len; 1249 u32 actual_read_len; 1250 u32 eof; 1251}; 1252 1253struct lancer_cmd_req_delete_object { 1254 struct be_cmd_req_hdr hdr; 1255 u32 rsvd1; 1256 u32 rsvd2; 1257 u8 object_name[104]; 1258}; 1259 1260/************************ WOL *******************************/ 1261struct be_cmd_req_acpi_wol_magic_config{ 1262 struct be_cmd_req_hdr hdr; 1263 u32 rsvd0[145]; 1264 u8 magic_mac[6]; 1265 u8 rsvd2[2]; 1266} __packed; 1267 1268struct be_cmd_req_acpi_wol_magic_config_v1 { 1269 struct be_cmd_req_hdr hdr; 1270 u8 rsvd0[2]; 1271 u8 query_options; 1272 u8 rsvd1[5]; 1273 u32 rsvd2[288]; 1274 u8 magic_mac[6]; 1275 u8 rsvd3[22]; 1276} __packed; 1277 1278struct be_cmd_resp_acpi_wol_magic_config_v1 { 1279 struct be_cmd_resp_hdr hdr; 1280 u8 rsvd0[2]; 1281 u8 wol_settings; 1282 u8 rsvd1[5]; 1283 u32 rsvd2[295]; 1284} __packed; 1285 1286#define BE_GET_WOL_CAP 2 1287 1288#define BE_WOL_CAP 0x1 1289#define BE_PME_D0_CAP 0x8 1290#define BE_PME_D1_CAP 0x10 1291#define BE_PME_D2_CAP 0x20 1292#define BE_PME_D3HOT_CAP 0x40 1293#define BE_PME_D3COLD_CAP 0x80 1294 1295/********************** LoopBack test *********************/ 1296struct be_cmd_req_loopback_test { 1297 struct be_cmd_req_hdr hdr; 1298 u32 loopback_type; 1299 u32 num_pkts; 1300 u64 pattern; 1301 u32 src_port; 1302 u32 dest_port; 1303 u32 pkt_size; 1304}; 1305 1306struct be_cmd_resp_loopback_test { 1307 struct be_cmd_resp_hdr resp_hdr; 1308 u32 status; 1309 u32 num_txfer; 1310 u32 num_rx; 1311 u32 miscomp_off; 1312 u32 ticks_compl; 1313}; 1314 1315struct be_cmd_req_set_lmode { 1316 struct be_cmd_req_hdr hdr; 1317 u8 src_port; 1318 u8 dest_port; 1319 u8 loopback_type; 1320 u8 loopback_state; 1321}; 1322 1323/********************** DDR DMA test *********************/ 1324struct be_cmd_req_ddrdma_test { 1325 struct be_cmd_req_hdr hdr; 1326 u64 pattern; 1327 u32 byte_count; 1328 u32 rsvd0; 1329 u8 snd_buff[4096]; 1330 u8 rsvd1[4096]; 1331}; 1332 1333struct be_cmd_resp_ddrdma_test { 1334 struct be_cmd_resp_hdr hdr; 1335 u64 pattern; 1336 u32 byte_cnt; 1337 u32 snd_err; 1338 u8 rsvd0[4096]; 1339 u8 rcv_buff[4096]; 1340}; 1341 1342/*********************** SEEPROM Read ***********************/ 1343 1344#define BE_READ_SEEPROM_LEN 1024 1345struct be_cmd_req_seeprom_read { 1346 struct be_cmd_req_hdr hdr; 1347 u8 rsvd0[BE_READ_SEEPROM_LEN]; 1348}; 1349 1350struct be_cmd_resp_seeprom_read { 1351 struct be_cmd_req_hdr hdr; 1352 u8 seeprom_data[BE_READ_SEEPROM_LEN]; 1353}; 1354 1355enum { 1356 PHY_TYPE_CX4_10GB = 0, 1357 PHY_TYPE_XFP_10GB, 1358 PHY_TYPE_SFP_1GB, 1359 PHY_TYPE_SFP_PLUS_10GB, 1360 PHY_TYPE_KR_10GB, 1361 PHY_TYPE_KX4_10GB, 1362 PHY_TYPE_BASET_10GB, 1363 PHY_TYPE_BASET_1GB, 1364 PHY_TYPE_BASEX_1GB, 1365 PHY_TYPE_SGMII, 1366 PHY_TYPE_QSFP, 1367 PHY_TYPE_KR4_40GB, 1368 PHY_TYPE_KR2_20GB, 1369 PHY_TYPE_DISABLED = 255 1370}; 1371 1372#define BE_SUPPORTED_SPEED_NONE 0 1373#define BE_SUPPORTED_SPEED_10MBPS 1 1374#define BE_SUPPORTED_SPEED_100MBPS 2 1375#define BE_SUPPORTED_SPEED_1GBPS 4 1376#define BE_SUPPORTED_SPEED_10GBPS 8 1377#define BE_SUPPORTED_SPEED_20GBPS 0x10 1378#define BE_SUPPORTED_SPEED_40GBPS 0x20 1379 1380#define BE_AN_EN 0x2 1381#define BE_PAUSE_SYM_EN 0x80 1382 1383/* MAC speed valid values */ 1384#define SPEED_DEFAULT 0x0 1385#define SPEED_FORCED_10GB 0x1 1386#define SPEED_FORCED_1GB 0x2 1387#define SPEED_AUTONEG_10GB 0x3 1388#define SPEED_AUTONEG_1GB 0x4 1389#define SPEED_AUTONEG_100MB 0x5 1390#define SPEED_AUTONEG_10GB_1GB 0x6 1391#define SPEED_AUTONEG_10GB_1GB_100MB 0x7 1392#define SPEED_AUTONEG_1GB_100MB 0x8 1393#define SPEED_AUTONEG_10MB 0x9 1394#define SPEED_AUTONEG_1GB_100MB_10MB 0xa 1395#define SPEED_AUTONEG_100MB_10MB 0xb 1396#define SPEED_FORCED_100MB 0xc 1397#define SPEED_FORCED_10MB 0xd 1398 1399struct be_cmd_req_get_phy_info { 1400 struct be_cmd_req_hdr hdr; 1401 u8 rsvd0[24]; 1402}; 1403 1404struct be_phy_info { 1405 u16 phy_type; 1406 u16 interface_type; 1407 u32 misc_params; 1408 u16 ext_phy_details; 1409 u16 rsvd; 1410 u16 auto_speeds_supported; 1411 u16 fixed_speeds_supported; 1412 u32 future_use[2]; 1413}; 1414 1415struct be_cmd_resp_get_phy_info { 1416 struct be_cmd_req_hdr hdr; 1417 struct be_phy_info phy_info; 1418}; 1419 1420/*********************** Set QOS ***********************/ 1421 1422#define BE_QOS_BITS_NIC 1 1423 1424struct be_cmd_req_set_qos { 1425 struct be_cmd_req_hdr hdr; 1426 u32 valid_bits; 1427 u32 max_bps_nic; 1428 u32 rsvd[7]; 1429}; 1430 1431/*********************** Controller Attributes ***********************/ 1432struct be_cmd_req_cntl_attribs { 1433 struct be_cmd_req_hdr hdr; 1434}; 1435 1436struct be_cmd_resp_cntl_attribs { 1437 struct be_cmd_resp_hdr hdr; 1438 struct mgmt_controller_attrib attribs; 1439}; 1440 1441/*********************** Set driver function ***********************/ 1442#define CAPABILITY_SW_TIMESTAMPS 2 1443#define CAPABILITY_BE3_NATIVE_ERX_API 4 1444 1445struct be_cmd_req_set_func_cap { 1446 struct be_cmd_req_hdr hdr; 1447 u32 valid_cap_flags; 1448 u32 cap_flags; 1449 u8 rsvd[212]; 1450}; 1451 1452struct be_cmd_resp_set_func_cap { 1453 struct be_cmd_resp_hdr hdr; 1454 u32 valid_cap_flags; 1455 u32 cap_flags; 1456 u8 rsvd[212]; 1457}; 1458 1459/*********************** Function Privileges ***********************/ 1460enum { 1461 BE_PRIV_DEFAULT = 0x1, 1462 BE_PRIV_LNKQUERY = 0x2, 1463 BE_PRIV_LNKSTATS = 0x4, 1464 BE_PRIV_LNKMGMT = 0x8, 1465 BE_PRIV_LNKDIAG = 0x10, 1466 BE_PRIV_UTILQUERY = 0x20, 1467 BE_PRIV_FILTMGMT = 0x40, 1468 BE_PRIV_IFACEMGMT = 0x80, 1469 BE_PRIV_VHADM = 0x100, 1470 BE_PRIV_DEVCFG = 0x200, 1471 BE_PRIV_DEVSEC = 0x400 1472}; 1473#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \ 1474 BE_PRIV_DEVSEC) 1475#define MIN_PRIVILEGES BE_PRIV_DEFAULT 1476 1477struct be_cmd_priv_map { 1478 u8 opcode; 1479 u8 subsystem; 1480 u32 priv_mask; 1481}; 1482 1483struct be_cmd_req_get_fn_privileges { 1484 struct be_cmd_req_hdr hdr; 1485 u32 rsvd; 1486}; 1487 1488struct be_cmd_resp_get_fn_privileges { 1489 struct be_cmd_resp_hdr hdr; 1490 u32 privilege_mask; 1491}; 1492 1493struct be_cmd_req_set_fn_privileges { 1494 struct be_cmd_req_hdr hdr; 1495 u32 privileges; /* Used by BE3, SH-R */ 1496 u32 privileges_lancer; /* Used by Lancer */ 1497}; 1498 1499/******************** GET/SET_MACLIST **************************/ 1500#define BE_MAX_MAC 64 1501struct be_cmd_req_get_mac_list { 1502 struct be_cmd_req_hdr hdr; 1503 u8 mac_type; 1504 u8 perm_override; 1505 u16 iface_id; 1506 u32 mac_id; 1507 u32 rsvd[3]; 1508} __packed; 1509 1510struct get_list_macaddr { 1511 u16 mac_addr_size; 1512 union { 1513 u8 macaddr[6]; 1514 struct { 1515 u8 rsvd[2]; 1516 u32 mac_id; 1517 } __packed s_mac_id; 1518 } __packed mac_addr_id; 1519} __packed; 1520 1521struct be_cmd_resp_get_mac_list { 1522 struct be_cmd_resp_hdr hdr; 1523 struct get_list_macaddr fd_macaddr; /* Factory default mac */ 1524 struct get_list_macaddr macid_macaddr; /* soft mac */ 1525 u8 true_mac_count; 1526 u8 pseudo_mac_count; 1527 u8 mac_list_size; 1528 u8 rsvd; 1529 /* perm override mac */ 1530 struct get_list_macaddr macaddr_list[BE_MAX_MAC]; 1531} __packed; 1532 1533struct be_cmd_req_set_mac_list { 1534 struct be_cmd_req_hdr hdr; 1535 u8 mac_count; 1536 u8 rsvd1; 1537 u16 rsvd2; 1538 struct macaddr mac[BE_MAX_MAC]; 1539} __packed; 1540 1541/*********************** HSW Config ***********************/ 1542#define PORT_FWD_TYPE_VEPA 0x3 1543#define PORT_FWD_TYPE_VEB 0x2 1544 1545struct amap_set_hsw_context { 1546 u8 interface_id[16]; 1547 u8 rsvd0[14]; 1548 u8 pvid_valid; 1549 u8 pport; 1550 u8 rsvd1[6]; 1551 u8 port_fwd_type[3]; 1552 u8 rsvd2[7]; 1553 u8 pvid[16]; 1554 u8 rsvd3[32]; 1555 u8 rsvd4[32]; 1556 u8 rsvd5[32]; 1557} __packed; 1558 1559struct be_cmd_req_set_hsw_config { 1560 struct be_cmd_req_hdr hdr; 1561 u8 context[sizeof(struct amap_set_hsw_context) / 8]; 1562} __packed; 1563 1564struct amap_get_hsw_req_context { 1565 u8 interface_id[16]; 1566 u8 rsvd0[14]; 1567 u8 pvid_valid; 1568 u8 pport; 1569} __packed; 1570 1571struct amap_get_hsw_resp_context { 1572 u8 rsvd0[6]; 1573 u8 port_fwd_type[3]; 1574 u8 rsvd1[7]; 1575 u8 pvid[16]; 1576 u8 rsvd2[32]; 1577 u8 rsvd3[32]; 1578 u8 rsvd4[32]; 1579} __packed; 1580 1581struct be_cmd_req_get_hsw_config { 1582 struct be_cmd_req_hdr hdr; 1583 u8 context[sizeof(struct amap_get_hsw_req_context) / 8]; 1584} __packed; 1585 1586struct be_cmd_resp_get_hsw_config { 1587 struct be_cmd_resp_hdr hdr; 1588 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8]; 1589 u32 rsvd; 1590}; 1591 1592/******************* get port names ***************/ 1593struct be_cmd_req_get_port_name { 1594 struct be_cmd_req_hdr hdr; 1595 u32 rsvd0; 1596}; 1597 1598struct be_cmd_resp_get_port_name { 1599 struct be_cmd_req_hdr hdr; 1600 u8 port_name[4]; 1601}; 1602 1603/*************** HW Stats Get v1 **********************************/ 1604#define BE_TXP_SW_SZ 48 1605struct be_port_rxf_stats_v1 { 1606 u32 rsvd0[12]; 1607 u32 rx_crc_errors; 1608 u32 rx_alignment_symbol_errors; 1609 u32 rx_pause_frames; 1610 u32 rx_priority_pause_frames; 1611 u32 rx_control_frames; 1612 u32 rx_in_range_errors; 1613 u32 rx_out_range_errors; 1614 u32 rx_frame_too_long; 1615 u32 rx_address_filtered; 1616 u32 rx_dropped_too_small; 1617 u32 rx_dropped_too_short; 1618 u32 rx_dropped_header_too_small; 1619 u32 rx_dropped_tcp_length; 1620 u32 rx_dropped_runt; 1621 u32 rsvd1[10]; 1622 u32 rx_ip_checksum_errs; 1623 u32 rx_tcp_checksum_errs; 1624 u32 rx_udp_checksum_errs; 1625 u32 rsvd2[7]; 1626 u32 rx_switched_unicast_packets; 1627 u32 rx_switched_multicast_packets; 1628 u32 rx_switched_broadcast_packets; 1629 u32 rsvd3[3]; 1630 u32 tx_pauseframes; 1631 u32 tx_priority_pauseframes; 1632 u32 tx_controlframes; 1633 u32 rsvd4[10]; 1634 u32 rxpp_fifo_overflow_drop; 1635 u32 rx_input_fifo_overflow_drop; 1636 u32 pmem_fifo_overflow_drop; 1637 u32 jabber_events; 1638 u32 rsvd5[3]; 1639}; 1640 1641 1642struct be_rxf_stats_v1 { 1643 struct be_port_rxf_stats_v1 port[4]; 1644 u32 rsvd0[2]; 1645 u32 rx_drops_no_pbuf; 1646 u32 rx_drops_no_txpb; 1647 u32 rx_drops_no_erx_descr; 1648 u32 rx_drops_no_tpre_descr; 1649 u32 rsvd1[6]; 1650 u32 rx_drops_too_many_frags; 1651 u32 rx_drops_invalid_ring; 1652 u32 forwarded_packets; 1653 u32 rx_drops_mtu; 1654 u32 rsvd2[14]; 1655}; 1656 1657struct be_erx_stats_v1 { 1658 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/ 1659 u32 rsvd[4]; 1660}; 1661 1662struct be_port_rxf_stats_v2 { 1663 u32 rsvd0[10]; 1664 u32 roce_bytes_received_lsd; 1665 u32 roce_bytes_received_msd; 1666 u32 rsvd1[5]; 1667 u32 roce_frames_received; 1668 u32 rx_crc_errors; 1669 u32 rx_alignment_symbol_errors; 1670 u32 rx_pause_frames; 1671 u32 rx_priority_pause_frames; 1672 u32 rx_control_frames; 1673 u32 rx_in_range_errors; 1674 u32 rx_out_range_errors; 1675 u32 rx_frame_too_long; 1676 u32 rx_address_filtered; 1677 u32 rx_dropped_too_small; 1678 u32 rx_dropped_too_short; 1679 u32 rx_dropped_header_too_small; 1680 u32 rx_dropped_tcp_length; 1681 u32 rx_dropped_runt; 1682 u32 rsvd2[10]; 1683 u32 rx_ip_checksum_errs; 1684 u32 rx_tcp_checksum_errs; 1685 u32 rx_udp_checksum_errs; 1686 u32 rsvd3[7]; 1687 u32 rx_switched_unicast_packets; 1688 u32 rx_switched_multicast_packets; 1689 u32 rx_switched_broadcast_packets; 1690 u32 rsvd4[3]; 1691 u32 tx_pauseframes; 1692 u32 tx_priority_pauseframes; 1693 u32 tx_controlframes; 1694 u32 rsvd5[10]; 1695 u32 rxpp_fifo_overflow_drop; 1696 u32 rx_input_fifo_overflow_drop; 1697 u32 pmem_fifo_overflow_drop; 1698 u32 jabber_events; 1699 u32 rsvd6[3]; 1700 u32 rx_drops_payload_size; 1701 u32 rx_drops_clipped_header; 1702 u32 rx_drops_crc; 1703 u32 roce_drops_payload_len; 1704 u32 roce_drops_crc; 1705 u32 rsvd7[19]; 1706}; 1707 1708struct be_rxf_stats_v2 { 1709 struct be_port_rxf_stats_v2 port[4]; 1710 u32 rsvd0[2]; 1711 u32 rx_drops_no_pbuf; 1712 u32 rx_drops_no_txpb; 1713 u32 rx_drops_no_erx_descr; 1714 u32 rx_drops_no_tpre_descr; 1715 u32 rsvd1[6]; 1716 u32 rx_drops_too_many_frags; 1717 u32 rx_drops_invalid_ring; 1718 u32 forwarded_packets; 1719 u32 rx_drops_mtu; 1720 u32 rsvd2[35]; 1721}; 1722 1723struct be_hw_stats_v1 { 1724 struct be_rxf_stats_v1 rxf; 1725 u32 rsvd0[BE_TXP_SW_SZ]; 1726 struct be_erx_stats_v1 erx; 1727 struct be_pmem_stats pmem; 1728 u32 rsvd1[18]; 1729}; 1730 1731struct be_cmd_req_get_stats_v1 { 1732 struct be_cmd_req_hdr hdr; 1733 u8 rsvd[sizeof(struct be_hw_stats_v1)]; 1734}; 1735 1736struct be_cmd_resp_get_stats_v1 { 1737 struct be_cmd_resp_hdr hdr; 1738 struct be_hw_stats_v1 hw_stats; 1739}; 1740 1741struct be_erx_stats_v2 { 1742 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/ 1743 u32 rsvd[3]; 1744}; 1745 1746struct be_hw_stats_v2 { 1747 struct be_rxf_stats_v2 rxf; 1748 u32 rsvd0[BE_TXP_SW_SZ]; 1749 struct be_erx_stats_v2 erx; 1750 struct be_pmem_stats pmem; 1751 u32 rsvd1[18]; 1752}; 1753 1754struct be_cmd_req_get_stats_v2 { 1755 struct be_cmd_req_hdr hdr; 1756 u8 rsvd[sizeof(struct be_hw_stats_v2)]; 1757}; 1758 1759struct be_cmd_resp_get_stats_v2 { 1760 struct be_cmd_resp_hdr hdr; 1761 struct be_hw_stats_v2 hw_stats; 1762}; 1763 1764/************** get fat capabilites *******************/ 1765#define MAX_MODULES 27 1766#define MAX_MODES 4 1767#define MODE_UART 0 1768#define FW_LOG_LEVEL_DEFAULT 48 1769#define FW_LOG_LEVEL_FATAL 64 1770 1771struct ext_fat_mode { 1772 u8 mode; 1773 u8 rsvd0; 1774 u16 port_mask; 1775 u32 dbg_lvl; 1776 u64 fun_mask; 1777} __packed; 1778 1779struct ext_fat_modules { 1780 u8 modules_str[32]; 1781 u32 modules_id; 1782 u32 num_modes; 1783 struct ext_fat_mode trace_lvl[MAX_MODES]; 1784} __packed; 1785 1786struct be_fat_conf_params { 1787 u32 max_log_entries; 1788 u32 log_entry_size; 1789 u8 log_type; 1790 u8 max_log_funs; 1791 u8 max_log_ports; 1792 u8 rsvd0; 1793 u32 supp_modes; 1794 u32 num_modules; 1795 struct ext_fat_modules module[MAX_MODULES]; 1796} __packed; 1797 1798struct be_cmd_req_get_ext_fat_caps { 1799 struct be_cmd_req_hdr hdr; 1800 u32 parameter_type; 1801}; 1802 1803struct be_cmd_resp_get_ext_fat_caps { 1804 struct be_cmd_resp_hdr hdr; 1805 struct be_fat_conf_params get_params; 1806}; 1807 1808struct be_cmd_req_set_ext_fat_caps { 1809 struct be_cmd_req_hdr hdr; 1810 struct be_fat_conf_params set_params; 1811}; 1812 1813#define RESOURCE_DESC_SIZE_V0 72 1814#define RESOURCE_DESC_SIZE_V1 88 1815#define PCIE_RESOURCE_DESC_TYPE_V0 0x40 1816#define NIC_RESOURCE_DESC_TYPE_V0 0x41 1817#define PCIE_RESOURCE_DESC_TYPE_V1 0x50 1818#define NIC_RESOURCE_DESC_TYPE_V1 0x51 1819#define PORT_RESOURCE_DESC_TYPE_V1 0x55 1820#define MAX_RESOURCE_DESC 264 1821 1822#define VFT_SHIFT 3 /* VF template */ 1823#define IMM_SHIFT 6 /* Immediate */ 1824#define NOSV_SHIFT 7 /* No save */ 1825 1826struct be_res_desc_hdr { 1827 u8 desc_type; 1828 u8 desc_len; 1829} __packed; 1830 1831struct be_port_res_desc { 1832 struct be_res_desc_hdr hdr; 1833 u8 rsvd0; 1834 u8 flags; 1835 u8 link_num; 1836 u8 mc_type; 1837 u16 rsvd1; 1838 1839#define NV_TYPE_MASK 0x3 /* bits 0-1 */ 1840#define NV_TYPE_DISABLED 1 1841#define NV_TYPE_VXLAN 3 1842#define SOCVID_SHIFT 2 /* Strip outer vlan */ 1843#define RCVID_SHIFT 4 /* Report vlan */ 1844 u8 nv_flags; 1845 u8 rsvd2; 1846 __le16 nv_port; /* vxlan/gre port */ 1847 u32 rsvd3[19]; 1848} __packed; 1849 1850struct be_pcie_res_desc { 1851 struct be_res_desc_hdr hdr; 1852 u8 rsvd0; 1853 u8 flags; 1854 u16 rsvd1; 1855 u8 pf_num; 1856 u8 rsvd2; 1857 u32 rsvd3; 1858 u8 sriov_state; 1859 u8 pf_state; 1860 u8 pf_type; 1861 u8 rsvd4; 1862 u16 num_vfs; 1863 u16 rsvd5; 1864 u32 rsvd6[17]; 1865} __packed; 1866 1867struct be_nic_res_desc { 1868 struct be_res_desc_hdr hdr; 1869 u8 rsvd1; 1870 1871#define QUN_SHIFT 4 /* QoS is in absolute units */ 1872 u8 flags; 1873 u8 vf_num; 1874 u8 rsvd2; 1875 u8 pf_num; 1876 u8 rsvd3; 1877 u16 unicast_mac_count; 1878 u8 rsvd4[6]; 1879 u16 mcc_count; 1880 u16 vlan_count; 1881 u16 mcast_mac_count; 1882 u16 txq_count; 1883 u16 rq_count; 1884 u16 rssq_count; 1885 u16 lro_count; 1886 u16 cq_count; 1887 u16 toe_conn_count; 1888 u16 eq_count; 1889 u16 vlan_id; 1890 u16 iface_count; 1891 u32 cap_flags; 1892 u8 link_param; 1893 u8 rsvd6; 1894 u16 channel_id_param; 1895 u32 bw_min; 1896 u32 bw_max; 1897 u8 acpi_params; 1898 u8 wol_param; 1899 u16 rsvd7; 1900 u16 tunnel_iface_count; 1901 u16 direct_tenant_iface_count; 1902 u32 rsvd8[6]; 1903} __packed; 1904 1905/************ Multi-Channel type ***********/ 1906enum mc_type { 1907 MC_NONE = 0x01, 1908 UMC = 0x02, 1909 FLEX10 = 0x03, 1910 vNIC1 = 0x04, 1911 nPAR = 0x05, 1912 UFP = 0x06, 1913 vNIC2 = 0x07 1914}; 1915 1916/* Is BE in a multi-channel mode */ 1917static inline bool be_is_mc(struct be_adapter *adapter) 1918{ 1919 return adapter->mc_type > MC_NONE; 1920} 1921 1922struct be_cmd_req_get_func_config { 1923 struct be_cmd_req_hdr hdr; 1924}; 1925 1926struct be_cmd_resp_get_func_config { 1927 struct be_cmd_resp_hdr hdr; 1928 u32 desc_count; 1929 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 1930}; 1931 1932#define ACTIVE_PROFILE_TYPE 0x2 1933struct be_cmd_req_get_profile_config { 1934 struct be_cmd_req_hdr hdr; 1935 u8 rsvd; 1936 u8 type; 1937 u16 rsvd1; 1938}; 1939 1940struct be_cmd_resp_get_profile_config { 1941 struct be_cmd_resp_hdr hdr; 1942 u32 desc_count; 1943 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1]; 1944}; 1945 1946struct be_cmd_req_set_profile_config { 1947 struct be_cmd_req_hdr hdr; 1948 u32 rsvd; 1949 u32 desc_count; 1950 u8 desc[2 * RESOURCE_DESC_SIZE_V1]; 1951} __packed; 1952 1953struct be_cmd_req_get_active_profile { 1954 struct be_cmd_req_hdr hdr; 1955 u32 rsvd; 1956} __packed; 1957 1958struct be_cmd_resp_get_active_profile { 1959 struct be_cmd_resp_hdr hdr; 1960 u16 active_profile_id; 1961 u16 next_profile_id; 1962} __packed; 1963 1964struct be_cmd_enable_disable_vf { 1965 struct be_cmd_req_hdr hdr; 1966 u8 enable; 1967 u8 rsvd[3]; 1968}; 1969 1970struct be_cmd_req_intr_set { 1971 struct be_cmd_req_hdr hdr; 1972 u8 intr_enabled; 1973 u8 rsvd[3]; 1974}; 1975 1976static inline bool check_privilege(struct be_adapter *adapter, u32 flags) 1977{ 1978 return flags & adapter->cmd_privileges ? true : false; 1979} 1980 1981/************** Get IFACE LIST *******************/ 1982struct be_if_desc { 1983 u32 if_id; 1984 u32 cap_flags; 1985 u32 en_flags; 1986}; 1987 1988struct be_cmd_req_get_iface_list { 1989 struct be_cmd_req_hdr hdr; 1990}; 1991 1992struct be_cmd_resp_get_iface_list { 1993 struct be_cmd_req_hdr hdr; 1994 u32 if_cnt; 1995 struct be_if_desc if_desc; 1996}; 1997 1998/*************** Set logical link ********************/ 1999#define PLINK_TRACK_SHIFT 8 2000struct be_cmd_req_set_ll_link { 2001 struct be_cmd_req_hdr hdr; 2002 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */ 2003}; 2004 2005/************** Manage IFACE Filters *******************/ 2006#define OP_CONVERT_NORMAL_TO_TUNNEL 0 2007#define OP_CONVERT_TUNNEL_TO_NORMAL 1 2008 2009struct be_cmd_req_manage_iface_filters { 2010 struct be_cmd_req_hdr hdr; 2011 u8 op; 2012 u8 rsvd0; 2013 u8 flags; 2014 u8 rsvd1; 2015 u32 tunnel_iface_id; 2016 u32 target_iface_id; 2017 u8 mac[6]; 2018 u16 vlan_tag; 2019 u32 tenant_id; 2020 u32 filter_id; 2021 u32 cap_flags; 2022 u32 cap_control_flags; 2023} __packed; 2024 2025int be_pci_fnum_get(struct be_adapter *adapter); 2026int be_fw_wait_ready(struct be_adapter *adapter); 2027int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, 2028 bool permanent, u32 if_handle, u32 pmac_id); 2029int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, 2030 u32 *pmac_id, u32 domain); 2031int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, 2032 u32 domain); 2033int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags, 2034 u32 *if_handle, u32 domain); 2035int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain); 2036int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo); 2037int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, 2038 struct be_queue_info *eq, bool no_delay, 2039 int num_cqe_dma_coalesce); 2040int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, 2041 struct be_queue_info *cq); 2042int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo); 2043int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, 2044 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id); 2045int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, 2046 int type); 2047int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); 2048int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed, 2049 u8 *link_status, u32 dom); 2050int be_cmd_reset(struct be_adapter *adapter); 2051int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); 2052int lancer_cmd_get_pport_stats(struct be_adapter *adapter, 2053 struct be_dma_mem *nonemb_cmd); 2054int be_cmd_get_fw_ver(struct be_adapter *adapter); 2055int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num); 2056int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array, 2057 u32 num); 2058int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status); 2059int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc); 2060int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc); 2061int be_cmd_query_fw_cfg(struct be_adapter *adapter); 2062int be_cmd_reset_function(struct be_adapter *adapter); 2063int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, 2064 u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey); 2065int be_process_mcc(struct be_adapter *adapter); 2066int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, 2067 u8 status, u8 state); 2068int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, 2069 u32 *state); 2070int be_cmd_read_port_transceiver_data(struct be_adapter *adapter, 2071 u8 page_num, u8 *data); 2072int be_cmd_query_cable_type(struct be_adapter *adapter); 2073int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, 2074 u32 flash_oper, u32 flash_opcode, u32 buf_size); 2075int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2076 u32 data_size, u32 data_offset, 2077 const char *obj_name, u32 *data_written, 2078 u8 *change_status, u8 *addn_status); 2079int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd, 2080 u32 data_size, u32 data_offset, const char *obj_name, 2081 u32 *data_read, u32 *eof, u8 *addn_status); 2082int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name); 2083int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, 2084 u16 optype, int offset); 2085int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, 2086 struct be_dma_mem *nonemb_cmd); 2087int be_cmd_fw_init(struct be_adapter *adapter); 2088int be_cmd_fw_clean(struct be_adapter *adapter); 2089void be_async_mcc_enable(struct be_adapter *adapter); 2090void be_async_mcc_disable(struct be_adapter *adapter); 2091int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num, 2092 u32 loopback_type, u32 pkt_size, u32 num_pkts, 2093 u64 pattern); 2094int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt, 2095 struct be_dma_mem *cmd); 2096int be_cmd_get_seeprom_data(struct be_adapter *adapter, 2097 struct be_dma_mem *nonemb_cmd); 2098int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, 2099 u8 loopback_type, u8 enable); 2100int be_cmd_get_phy_info(struct be_adapter *adapter); 2101int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, 2102 u16 link_speed, u8 domain); 2103void be_detect_error(struct be_adapter *adapter); 2104int be_cmd_get_die_temperature(struct be_adapter *adapter); 2105int be_cmd_get_cntl_attributes(struct be_adapter *adapter); 2106int be_cmd_req_native_mode(struct be_adapter *adapter); 2107int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); 2108int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); 2109int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege, 2110 u32 domain); 2111int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges, 2112 u32 vf_num); 2113int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac, 2114 bool *pmac_id_active, u32 *pmac_id, 2115 u32 if_handle, u8 domain); 2116int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac, 2117 u32 if_handle, bool active, u32 domain); 2118int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac); 2119int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, 2120 u32 domain); 2121int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom); 2122int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain, 2123 u16 intf_id, u16 hsw_mode); 2124int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain, 2125 u16 intf_id, u8 *mode); 2126int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); 2127int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level); 2128int be_cmd_get_fw_log_level(struct be_adapter *adapter); 2129int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter, 2130 struct be_dma_mem *cmd); 2131int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter, 2132 struct be_dma_mem *cmd, 2133 struct be_fat_conf_params *cfgs); 2134int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); 2135int lancer_initiate_dump(struct be_adapter *adapter); 2136int lancer_delete_dump(struct be_adapter *adapter); 2137bool dump_present(struct be_adapter *adapter); 2138int lancer_test_and_set_rdy_state(struct be_adapter *adapter); 2139int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name); 2140int be_cmd_get_func_config(struct be_adapter *adapter, 2141 struct be_resources *res); 2142int be_cmd_get_profile_config(struct be_adapter *adapter, 2143 struct be_resources *res, u8 domain); 2144int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile); 2145int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg, 2146 int vf_num); 2147int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain); 2148int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable); 2149int be_cmd_set_logical_link_config(struct be_adapter *adapter, 2150 int link_state, u8 domain); 2151int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port); 2152int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op); 2153int be_cmd_set_sriov_config(struct be_adapter *adapter, 2154 struct be_resources res, u16 num_vfs); 2155