1/* 2 * drivers/net/ethernet/freescale/gianfar.h 3 * 4 * Gianfar Ethernet Driver 5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 * Still left to do: 20 * -Add support for module parameters 21 * -Add patch for ethtool phys id 22 */ 23#ifndef __GIANFAR_H 24#define __GIANFAR_H 25 26#include <linux/kernel.h> 27#include <linux/sched.h> 28#include <linux/string.h> 29#include <linux/errno.h> 30#include <linux/slab.h> 31#include <linux/interrupt.h> 32#include <linux/delay.h> 33#include <linux/netdevice.h> 34#include <linux/etherdevice.h> 35#include <linux/skbuff.h> 36#include <linux/spinlock.h> 37#include <linux/mm.h> 38#include <linux/mii.h> 39#include <linux/phy.h> 40 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/uaccess.h> 44#include <linux/module.h> 45#include <linux/crc32.h> 46#include <linux/workqueue.h> 47#include <linux/ethtool.h> 48 49struct ethtool_flow_spec_container { 50 struct ethtool_rx_flow_spec fs; 51 struct list_head list; 52}; 53 54struct ethtool_rx_list { 55 struct list_head list; 56 unsigned int count; 57}; 58 59/* The maximum number of packets to be handled in one call of gfar_poll */ 60#define GFAR_DEV_WEIGHT 64 61 62/* Length for FCB */ 63#define GMAC_FCB_LEN 8 64 65/* Length for TxPAL */ 66#define GMAC_TXPAL_LEN 16 67 68/* Default padding amount */ 69#define DEFAULT_PADDING 2 70 71/* Number of bytes to align the rx bufs to */ 72#define RXBUF_ALIGNMENT 64 73 74/* The number of bytes which composes a unit for the purpose of 75 * allocating data buffers. ie-for any given MTU, the data buffer 76 * will be the next highest multiple of 512 bytes. */ 77#define INCREMENTAL_BUFFER_SIZE 512 78 79#define PHY_INIT_TIMEOUT 100000 80 81#define DRV_NAME "gfar-enet" 82extern const char gfar_driver_version[]; 83 84/* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 85#define MAX_TX_QS 0x8 86#define MAX_RX_QS 0x8 87 88/* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 89#define MAXGROUPS 0x2 90 91/* These need to be powers of 2 for this driver */ 92#define DEFAULT_TX_RING_SIZE 256 93#define DEFAULT_RX_RING_SIZE 256 94 95#define GFAR_RX_MAX_RING_SIZE 256 96#define GFAR_TX_MAX_RING_SIZE 256 97 98#define GFAR_MAX_FIFO_THRESHOLD 511 99#define GFAR_MAX_FIFO_STARVE 511 100#define GFAR_MAX_FIFO_STARVE_OFF 511 101 102#define DEFAULT_RX_BUFFER_SIZE 1536 103#define TX_RING_MOD_MASK(size) (size-1) 104#define RX_RING_MOD_MASK(size) (size-1) 105#define JUMBO_BUFFER_SIZE 9728 106#define JUMBO_FRAME_SIZE 9600 107 108#define DEFAULT_FIFO_TX_THR 0x100 109#define DEFAULT_FIFO_TX_STARVE 0x40 110#define DEFAULT_FIFO_TX_STARVE_OFF 0x80 111#define DEFAULT_BD_STASH 1 112#define DEFAULT_STASH_LENGTH 96 113#define DEFAULT_STASH_INDEX 0 114 115/* The number of Exact Match registers */ 116#define GFAR_EM_NUM 15 117 118/* Latency of interface clock in nanoseconds */ 119/* Interface clock latency , in this case, means the 120 * time described by a value of 1 in the interrupt 121 * coalescing registers' time fields. Since those fields 122 * refer to the time it takes for 64 clocks to pass, the 123 * latencies are as such: 124 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 125 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 126 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 127 */ 128#define GFAR_GBIT_TIME 512 129#define GFAR_100_TIME 2560 130#define GFAR_10_TIME 25600 131 132#define DEFAULT_TX_COALESCE 1 133#define DEFAULT_TXCOUNT 16 134#define DEFAULT_TXTIME 21 135 136#define DEFAULT_RXTIME 21 137 138#define DEFAULT_RX_COALESCE 0 139#define DEFAULT_RXCOUNT 0 140 141#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \ 142 | SUPPORTED_10baseT_Full \ 143 | SUPPORTED_100baseT_Half \ 144 | SUPPORTED_100baseT_Full \ 145 | SUPPORTED_Autoneg \ 146 | SUPPORTED_MII) 147 148#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \ 149 | SUPPORTED_Pause \ 150 | SUPPORTED_Asym_Pause) 151 152/* TBI register addresses */ 153#define MII_TBICON 0x11 154 155/* TBICON register bit fields */ 156#define TBICON_CLK_SELECT 0x0020 157 158/* MAC register bits */ 159#define MACCFG1_SOFT_RESET 0x80000000 160#define MACCFG1_RESET_RX_MC 0x00080000 161#define MACCFG1_RESET_TX_MC 0x00040000 162#define MACCFG1_RESET_RX_FUN 0x00020000 163#define MACCFG1_RESET_TX_FUN 0x00010000 164#define MACCFG1_LOOPBACK 0x00000100 165#define MACCFG1_RX_FLOW 0x00000020 166#define MACCFG1_TX_FLOW 0x00000010 167#define MACCFG1_SYNCD_RX_EN 0x00000008 168#define MACCFG1_RX_EN 0x00000004 169#define MACCFG1_SYNCD_TX_EN 0x00000002 170#define MACCFG1_TX_EN 0x00000001 171 172#define MACCFG2_INIT_SETTINGS 0x00007205 173#define MACCFG2_FULL_DUPLEX 0x00000001 174#define MACCFG2_IF 0x00000300 175#define MACCFG2_MII 0x00000100 176#define MACCFG2_GMII 0x00000200 177#define MACCFG2_HUGEFRAME 0x00000020 178#define MACCFG2_LENGTHCHECK 0x00000010 179#define MACCFG2_MPEN 0x00000008 180 181#define ECNTRL_FIFM 0x00008000 182#define ECNTRL_INIT_SETTINGS 0x00001000 183#define ECNTRL_TBI_MODE 0x00000020 184#define ECNTRL_REDUCED_MODE 0x00000010 185#define ECNTRL_R100 0x00000008 186#define ECNTRL_REDUCED_MII_MODE 0x00000004 187#define ECNTRL_SGMII_MODE 0x00000002 188 189#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 190 191#define MINFLR_INIT_SETTINGS 0x00000040 192 193/* Tqueue control */ 194#define TQUEUE_EN0 0x00008000 195#define TQUEUE_EN1 0x00004000 196#define TQUEUE_EN2 0x00002000 197#define TQUEUE_EN3 0x00001000 198#define TQUEUE_EN4 0x00000800 199#define TQUEUE_EN5 0x00000400 200#define TQUEUE_EN6 0x00000200 201#define TQUEUE_EN7 0x00000100 202#define TQUEUE_EN_ALL 0x0000FF00 203 204#define TR03WT_WT0_MASK 0xFF000000 205#define TR03WT_WT1_MASK 0x00FF0000 206#define TR03WT_WT2_MASK 0x0000FF00 207#define TR03WT_WT3_MASK 0x000000FF 208 209#define TR47WT_WT4_MASK 0xFF000000 210#define TR47WT_WT5_MASK 0x00FF0000 211#define TR47WT_WT6_MASK 0x0000FF00 212#define TR47WT_WT7_MASK 0x000000FF 213 214/* Rqueue control */ 215#define RQUEUE_EX0 0x00800000 216#define RQUEUE_EX1 0x00400000 217#define RQUEUE_EX2 0x00200000 218#define RQUEUE_EX3 0x00100000 219#define RQUEUE_EX4 0x00080000 220#define RQUEUE_EX5 0x00040000 221#define RQUEUE_EX6 0x00020000 222#define RQUEUE_EX7 0x00010000 223#define RQUEUE_EX_ALL 0x00FF0000 224 225#define RQUEUE_EN0 0x00000080 226#define RQUEUE_EN1 0x00000040 227#define RQUEUE_EN2 0x00000020 228#define RQUEUE_EN3 0x00000010 229#define RQUEUE_EN4 0x00000008 230#define RQUEUE_EN5 0x00000004 231#define RQUEUE_EN6 0x00000002 232#define RQUEUE_EN7 0x00000001 233#define RQUEUE_EN_ALL 0x000000FF 234 235/* Init to do tx snooping for buffers and descriptors */ 236#define DMACTRL_INIT_SETTINGS 0x000000c3 237#define DMACTRL_GRS 0x00000010 238#define DMACTRL_GTS 0x00000008 239 240#define TSTAT_CLEAR_THALT_ALL 0xFF000000 241#define TSTAT_CLEAR_THALT 0x80000000 242#define TSTAT_CLEAR_THALT0 0x80000000 243#define TSTAT_CLEAR_THALT1 0x40000000 244#define TSTAT_CLEAR_THALT2 0x20000000 245#define TSTAT_CLEAR_THALT3 0x10000000 246#define TSTAT_CLEAR_THALT4 0x08000000 247#define TSTAT_CLEAR_THALT5 0x04000000 248#define TSTAT_CLEAR_THALT6 0x02000000 249#define TSTAT_CLEAR_THALT7 0x01000000 250 251/* Interrupt coalescing macros */ 252#define IC_ICEN 0x80000000 253#define IC_ICFT_MASK 0x1fe00000 254#define IC_ICFT_SHIFT 21 255#define mk_ic_icft(x) \ 256 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 257#define IC_ICTT_MASK 0x0000ffff 258#define mk_ic_ictt(x) (x&IC_ICTT_MASK) 259 260#define mk_ic_value(count, time) (IC_ICEN | \ 261 mk_ic_icft(count) | \ 262 mk_ic_ictt(time)) 263#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 264 IC_ICFT_SHIFT) 265#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 266 267#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 268#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 269 270#define skip_bd(bdp, stride, base, ring_size) ({ \ 271 typeof(bdp) new_bd = (bdp) + (stride); \ 272 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; }) 273 274#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size) 275 276#define RCTRL_TS_ENABLE 0x01000000 277#define RCTRL_PAL_MASK 0x001f0000 278#define RCTRL_VLEX 0x00002000 279#define RCTRL_FILREN 0x00001000 280#define RCTRL_GHTX 0x00000400 281#define RCTRL_IPCSEN 0x00000200 282#define RCTRL_TUCSEN 0x00000100 283#define RCTRL_PRSDEP_MASK 0x000000c0 284#define RCTRL_PRSDEP_INIT 0x000000c0 285#define RCTRL_PRSFM 0x00000020 286#define RCTRL_PROM 0x00000008 287#define RCTRL_EMEN 0x00000002 288#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 289 RCTRL_TUCSEN | RCTRL_FILREN) 290#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 291 RCTRL_PRSDEP_INIT) 292#define RCTRL_EXTHASH (RCTRL_GHTX) 293#define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 294#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 295 296 297#define RSTAT_CLEAR_RHALT 0x00800000 298#define RSTAT_CLEAR_RXF0 0x00000080 299#define RSTAT_RXF_MASK 0x000000ff 300 301#define TCTRL_IPCSEN 0x00004000 302#define TCTRL_TUCSEN 0x00002000 303#define TCTRL_VLINS 0x00001000 304#define TCTRL_THDF 0x00000800 305#define TCTRL_RFCPAUSE 0x00000010 306#define TCTRL_TFCPAUSE 0x00000008 307#define TCTRL_TXSCHED_MASK 0x00000006 308#define TCTRL_TXSCHED_INIT 0x00000000 309/* priority scheduling */ 310#define TCTRL_TXSCHED_PRIO 0x00000002 311/* weighted round-robin scheduling (WRRS) */ 312#define TCTRL_TXSCHED_WRRS 0x00000004 313/* default WRRS weight and policy setting, 314 * tailored to the tr03wt and tr47wt registers: 315 * equal weight for all Tx Qs, measured in 64byte units 316 */ 317#define DEFAULT_WRRS_WEIGHT 0x18181818 318 319#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 320 321#define IEVENT_INIT_CLEAR 0xffffffff 322#define IEVENT_BABR 0x80000000 323#define IEVENT_RXC 0x40000000 324#define IEVENT_BSY 0x20000000 325#define IEVENT_EBERR 0x10000000 326#define IEVENT_MSRO 0x04000000 327#define IEVENT_GTSC 0x02000000 328#define IEVENT_BABT 0x01000000 329#define IEVENT_TXC 0x00800000 330#define IEVENT_TXE 0x00400000 331#define IEVENT_TXB 0x00200000 332#define IEVENT_TXF 0x00100000 333#define IEVENT_LC 0x00040000 334#define IEVENT_CRL 0x00020000 335#define IEVENT_XFUN 0x00010000 336#define IEVENT_RXB0 0x00008000 337#define IEVENT_MAG 0x00000800 338#define IEVENT_GRSC 0x00000100 339#define IEVENT_RXF0 0x00000080 340#define IEVENT_FIR 0x00000008 341#define IEVENT_FIQ 0x00000004 342#define IEVENT_DPE 0x00000002 343#define IEVENT_PERR 0x00000001 344#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 345#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 346#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 347#define IEVENT_ERR_MASK \ 348(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 349 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 350 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 351 | IEVENT_MAG | IEVENT_BABR) 352 353#define IMASK_INIT_CLEAR 0x00000000 354#define IMASK_BABR 0x80000000 355#define IMASK_RXC 0x40000000 356#define IMASK_BSY 0x20000000 357#define IMASK_EBERR 0x10000000 358#define IMASK_MSRO 0x04000000 359#define IMASK_GTSC 0x02000000 360#define IMASK_BABT 0x01000000 361#define IMASK_TXC 0x00800000 362#define IMASK_TXEEN 0x00400000 363#define IMASK_TXBEN 0x00200000 364#define IMASK_TXFEN 0x00100000 365#define IMASK_LC 0x00040000 366#define IMASK_CRL 0x00020000 367#define IMASK_XFUN 0x00010000 368#define IMASK_RXB0 0x00008000 369#define IMASK_MAG 0x00000800 370#define IMASK_GRSC 0x00000100 371#define IMASK_RXFEN0 0x00000080 372#define IMASK_FIR 0x00000008 373#define IMASK_FIQ 0x00000004 374#define IMASK_DPE 0x00000002 375#define IMASK_PERR 0x00000001 376#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 377 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 378 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 379 | IMASK_PERR) 380#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY) 381#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN) 382 383#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT) 384#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT) 385 386/* Fifo management */ 387#define FIFO_TX_THR_MASK 0x01ff 388#define FIFO_TX_STARVE_MASK 0x01ff 389#define FIFO_TX_STARVE_OFF_MASK 0x01ff 390 391/* Attribute fields */ 392 393/* This enables rx snooping for buffers and descriptors */ 394#define ATTR_BDSTASH 0x00000800 395 396#define ATTR_BUFSTASH 0x00004000 397 398#define ATTR_SNOOPING 0x000000c0 399#define ATTR_INIT_SETTINGS ATTR_SNOOPING 400 401#define ATTRELI_INIT_SETTINGS 0x0 402#define ATTRELI_EL_MASK 0x3fff0000 403#define ATTRELI_EL(x) (x << 16) 404#define ATTRELI_EI_MASK 0x00003fff 405#define ATTRELI_EI(x) (x) 406 407#define BD_LFLAG(flags) ((flags) << 16) 408#define BD_LENGTH_MASK 0x0000ffff 409 410#define FPR_FILER_MASK 0xFFFFFFFF 411#define MAX_FILER_IDX 0xFF 412 413/* This default RIR value directly corresponds 414 * to the 3-bit hash value generated */ 415#define DEFAULT_8RXQ_RIR0 0x05397700 416/* Map even hash values to Q0, and odd ones to Q1 */ 417#define DEFAULT_2RXQ_RIR0 0x04104100 418 419/* RQFCR register bits */ 420#define RQFCR_GPI 0x80000000 421#define RQFCR_HASHTBL_Q 0x00000000 422#define RQFCR_HASHTBL_0 0x00020000 423#define RQFCR_HASHTBL_1 0x00040000 424#define RQFCR_HASHTBL_2 0x00060000 425#define RQFCR_HASHTBL_3 0x00080000 426#define RQFCR_HASH 0x00010000 427#define RQFCR_QUEUE 0x0000FC00 428#define RQFCR_CLE 0x00000200 429#define RQFCR_RJE 0x00000100 430#define RQFCR_AND 0x00000080 431#define RQFCR_CMP_EXACT 0x00000000 432#define RQFCR_CMP_MATCH 0x00000020 433#define RQFCR_CMP_NOEXACT 0x00000040 434#define RQFCR_CMP_NOMATCH 0x00000060 435 436/* RQFCR PID values */ 437#define RQFCR_PID_MASK 0x00000000 438#define RQFCR_PID_PARSE 0x00000001 439#define RQFCR_PID_ARB 0x00000002 440#define RQFCR_PID_DAH 0x00000003 441#define RQFCR_PID_DAL 0x00000004 442#define RQFCR_PID_SAH 0x00000005 443#define RQFCR_PID_SAL 0x00000006 444#define RQFCR_PID_ETY 0x00000007 445#define RQFCR_PID_VID 0x00000008 446#define RQFCR_PID_PRI 0x00000009 447#define RQFCR_PID_TOS 0x0000000A 448#define RQFCR_PID_L4P 0x0000000B 449#define RQFCR_PID_DIA 0x0000000C 450#define RQFCR_PID_SIA 0x0000000D 451#define RQFCR_PID_DPT 0x0000000E 452#define RQFCR_PID_SPT 0x0000000F 453 454/* RQFPR when PID is 0x0001 */ 455#define RQFPR_HDR_GE_512 0x00200000 456#define RQFPR_LERR 0x00100000 457#define RQFPR_RAR 0x00080000 458#define RQFPR_RARQ 0x00040000 459#define RQFPR_AR 0x00020000 460#define RQFPR_ARQ 0x00010000 461#define RQFPR_EBC 0x00008000 462#define RQFPR_VLN 0x00004000 463#define RQFPR_CFI 0x00002000 464#define RQFPR_JUM 0x00001000 465#define RQFPR_IPF 0x00000800 466#define RQFPR_FIF 0x00000400 467#define RQFPR_IPV4 0x00000200 468#define RQFPR_IPV6 0x00000100 469#define RQFPR_ICC 0x00000080 470#define RQFPR_ICV 0x00000040 471#define RQFPR_TCP 0x00000020 472#define RQFPR_UDP 0x00000010 473#define RQFPR_TUC 0x00000008 474#define RQFPR_TUV 0x00000004 475#define RQFPR_PER 0x00000002 476#define RQFPR_EER 0x00000001 477 478/* TxBD status field bits */ 479#define TXBD_READY 0x8000 480#define TXBD_PADCRC 0x4000 481#define TXBD_WRAP 0x2000 482#define TXBD_INTERRUPT 0x1000 483#define TXBD_LAST 0x0800 484#define TXBD_CRC 0x0400 485#define TXBD_DEF 0x0200 486#define TXBD_HUGEFRAME 0x0080 487#define TXBD_LATECOLLISION 0x0080 488#define TXBD_RETRYLIMIT 0x0040 489#define TXBD_RETRYCOUNTMASK 0x003c 490#define TXBD_UNDERRUN 0x0002 491#define TXBD_TOE 0x0002 492 493/* Tx FCB param bits */ 494#define TXFCB_VLN 0x80 495#define TXFCB_IP 0x40 496#define TXFCB_IP6 0x20 497#define TXFCB_TUP 0x10 498#define TXFCB_UDP 0x08 499#define TXFCB_CIP 0x04 500#define TXFCB_CTU 0x02 501#define TXFCB_NPH 0x01 502#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 503 504/* RxBD status field bits */ 505#define RXBD_EMPTY 0x8000 506#define RXBD_RO1 0x4000 507#define RXBD_WRAP 0x2000 508#define RXBD_INTERRUPT 0x1000 509#define RXBD_LAST 0x0800 510#define RXBD_FIRST 0x0400 511#define RXBD_MISS 0x0100 512#define RXBD_BROADCAST 0x0080 513#define RXBD_MULTICAST 0x0040 514#define RXBD_LARGE 0x0020 515#define RXBD_NONOCTET 0x0010 516#define RXBD_SHORT 0x0008 517#define RXBD_CRCERR 0x0004 518#define RXBD_OVERRUN 0x0002 519#define RXBD_TRUNCATED 0x0001 520#define RXBD_STATS 0x01ff 521#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 522 | RXBD_CRCERR | RXBD_OVERRUN \ 523 | RXBD_TRUNCATED) 524 525/* Rx FCB status field bits */ 526#define RXFCB_VLN 0x8000 527#define RXFCB_IP 0x4000 528#define RXFCB_IP6 0x2000 529#define RXFCB_TUP 0x1000 530#define RXFCB_CIP 0x0800 531#define RXFCB_CTU 0x0400 532#define RXFCB_EIP 0x0200 533#define RXFCB_ETU 0x0100 534#define RXFCB_CSUM_MASK 0x0f00 535#define RXFCB_PERR_MASK 0x000c 536#define RXFCB_PERR_BADL3 0x0008 537 538#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 539 540struct txbd8 541{ 542 union { 543 struct { 544 u16 status; /* Status Fields */ 545 u16 length; /* Buffer length */ 546 }; 547 u32 lstatus; 548 }; 549 u32 bufPtr; /* Buffer Pointer */ 550}; 551 552struct txfcb { 553 u8 flags; 554 u8 ptp; /* Flag to enable tx timestamping */ 555 u8 l4os; /* Level 4 Header Offset */ 556 u8 l3os; /* Level 3 Header Offset */ 557 u16 phcs; /* Pseudo-header Checksum */ 558 u16 vlctl; /* VLAN control word */ 559}; 560 561struct rxbd8 562{ 563 union { 564 struct { 565 u16 status; /* Status Fields */ 566 u16 length; /* Buffer Length */ 567 }; 568 u32 lstatus; 569 }; 570 u32 bufPtr; /* Buffer Pointer */ 571}; 572 573struct rxfcb { 574 u16 flags; 575 u8 rq; /* Receive Queue index */ 576 u8 pro; /* Layer 4 Protocol */ 577 u16 reserved; 578 u16 vlctl; /* VLAN control word */ 579}; 580 581struct gianfar_skb_cb { 582 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ 583}; 584 585#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 586 587struct rmon_mib 588{ 589 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 590 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 591 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 592 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 593 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 594 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 595 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 596 u32 rbyt; /* 0x.69c - Receive Byte Counter */ 597 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 598 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 599 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 600 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 601 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 602 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 603 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 604 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 605 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 606 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 607 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 608 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 609 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 610 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 611 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 612 u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 613 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 614 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 615 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 616 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 617 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 618 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 619 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 620 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 621 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 622 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 623 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 624 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 625 u8 res1[4]; 626 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 627 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 628 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 629 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 630 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 631 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 632 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 633 u32 car1; /* 0x.730 - Carry Register One */ 634 u32 car2; /* 0x.734 - Carry Register Two */ 635 u32 cam1; /* 0x.738 - Carry Mask Register One */ 636 u32 cam2; /* 0x.73c - Carry Mask Register Two */ 637}; 638 639struct gfar_extra_stats { 640 atomic64_t rx_large; 641 atomic64_t rx_short; 642 atomic64_t rx_nonoctet; 643 atomic64_t rx_crcerr; 644 atomic64_t rx_overrun; 645 atomic64_t rx_bsy; 646 atomic64_t rx_babr; 647 atomic64_t rx_trunc; 648 atomic64_t eberr; 649 atomic64_t tx_babt; 650 atomic64_t tx_underrun; 651 atomic64_t rx_skbmissing; 652 atomic64_t tx_timeout; 653}; 654 655#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 656#define GFAR_EXTRA_STATS_LEN \ 657 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 658 659/* Number of stats exported via ethtool */ 660#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 661 662struct gfar { 663 u32 tsec_id; /* 0x.000 - Controller ID register */ 664 u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 665 u8 res1[8]; 666 u32 ievent; /* 0x.010 - Interrupt Event Register */ 667 u32 imask; /* 0x.014 - Interrupt Mask Register */ 668 u32 edis; /* 0x.018 - Error Disabled Register */ 669 u32 emapg; /* 0x.01c - Group Error mapping register */ 670 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 671 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 672 u32 ptv; /* 0x.028 - Pause Time Value Register */ 673 u32 dmactrl; /* 0x.02c - DMA Control Register */ 674 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 675 u8 res2[28]; 676 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 677 register */ 678 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 679 register */ 680 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 681 register */ 682 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 683 shutoff register */ 684 u8 res3[44]; 685 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 686 u8 res4[8]; 687 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 688 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 689 u8 res5[96]; 690 u32 tctrl; /* 0x.100 - Transmit Control Register */ 691 u32 tstat; /* 0x.104 - Transmit Status Register */ 692 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 693 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 694 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 695 u32 tqueue; /* 0x.114 - Transmit queue control register */ 696 u8 res7[40]; 697 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 698 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 699 u8 res8[52]; 700 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 701 u8 res9a[4]; 702 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 703 u8 res9b[4]; 704 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 705 u8 res9c[4]; 706 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 707 u8 res9d[4]; 708 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 709 u8 res9e[4]; 710 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 711 u8 res9f[4]; 712 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 713 u8 res9g[4]; 714 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 715 u8 res9h[4]; 716 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 717 u8 res9[64]; 718 u32 tbaseh; /* 0x.200 - TxBD base address high */ 719 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 720 u8 res10a[4]; 721 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 722 u8 res10b[4]; 723 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 724 u8 res10c[4]; 725 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 726 u8 res10d[4]; 727 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 728 u8 res10e[4]; 729 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 730 u8 res10f[4]; 731 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 732 u8 res10g[4]; 733 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 734 u8 res10[192]; 735 u32 rctrl; /* 0x.300 - Receive Control Register */ 736 u32 rstat; /* 0x.304 - Receive Status Register */ 737 u8 res12[8]; 738 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 739 u32 rqueue; /* 0x.314 - Receive queue control register */ 740 u32 rir0; /* 0x.318 - Ring mapping register 0 */ 741 u32 rir1; /* 0x.31c - Ring mapping register 1 */ 742 u32 rir2; /* 0x.320 - Ring mapping register 2 */ 743 u32 rir3; /* 0x.324 - Ring mapping register 3 */ 744 u8 res13[8]; 745 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 746 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 747 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 748 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 749 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 750 u8 res14[56]; 751 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 752 u8 res15a[4]; 753 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 754 u8 res15b[4]; 755 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 756 u8 res15c[4]; 757 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 758 u8 res15d[4]; 759 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 760 u8 res15e[4]; 761 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 762 u8 res15f[4]; 763 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 764 u8 res15g[4]; 765 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 766 u8 res15h[4]; 767 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 768 u8 res16[64]; 769 u32 rbaseh; /* 0x.400 - RxBD base address high */ 770 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 771 u8 res17a[4]; 772 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 773 u8 res17b[4]; 774 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 775 u8 res17c[4]; 776 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 777 u8 res17d[4]; 778 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 779 u8 res17e[4]; 780 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 781 u8 res17f[4]; 782 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 783 u8 res17g[4]; 784 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 785 u8 res17[192]; 786 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 787 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 788 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 789 u32 hafdup; /* 0x.50c - Half Duplex Register */ 790 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 791 u8 res18[12]; 792 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 793 u32 ifctrl; /* 0x.538 - Interface control register */ 794 u32 ifstat; /* 0x.53c - Interface Status Register */ 795 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 796 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 797 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 798 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 799 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 800 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 801 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 802 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 803 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 804 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 805 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 806 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 807 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 808 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 809 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 810 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 811 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 812 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 813 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 814 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 815 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 816 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 817 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 818 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 819 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 820 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 821 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 822 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 823 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 824 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 825 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 826 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 827 u8 res20[192]; 828 struct rmon_mib rmon; /* 0x.680-0x.73c */ 829 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 830 u8 res21[188]; 831 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 832 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 833 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 834 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 835 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 836 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 837 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 838 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 839 u8 res22[96]; 840 u32 gaddr0; /* 0x.880 - Group address register 0 */ 841 u32 gaddr1; /* 0x.884 - Group address register 1 */ 842 u32 gaddr2; /* 0x.888 - Group address register 2 */ 843 u32 gaddr3; /* 0x.88c - Group address register 3 */ 844 u32 gaddr4; /* 0x.890 - Group address register 4 */ 845 u32 gaddr5; /* 0x.894 - Group address register 5 */ 846 u32 gaddr6; /* 0x.898 - Group address register 6 */ 847 u32 gaddr7; /* 0x.89c - Group address register 7 */ 848 u8 res23a[352]; 849 u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 850 u8 res23b[252]; 851 u8 res23c[248]; 852 u32 attr; /* 0x.bf8 - Attributes Register */ 853 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 854 u8 res24[688]; 855 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 856 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 857 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 858 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 859 u8 res25[16]; 860 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 861 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 862 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 863 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 864 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 865 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 866 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 867 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 868 u8 res26[32]; 869 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 870 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 871 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 872 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 873 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 874 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 875 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 876 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 877 u8 res27[208]; 878}; 879 880/* Flags related to gianfar device features */ 881#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 882#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 883#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 884#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 885#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 886#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 887#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 888#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 889#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 890#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 891#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 892 893#if (MAXGROUPS == 2) 894#define DEFAULT_MAPPING 0xAA 895#else 896#define DEFAULT_MAPPING 0xFF 897#endif 898 899#define ISRG_RR0 0x80000000 900#define ISRG_TR0 0x00800000 901 902/* The same driver can operate in two modes */ 903/* SQ_SG_MODE: Single Queue Single Group Mode 904 * (Backward compatible mode) 905 * MQ_MG_MODE: Multi Queue Multi Group mode 906 */ 907enum { 908 SQ_SG_MODE = 0, 909 MQ_MG_MODE 910}; 911 912/* GFAR_SQ_POLLING: Single Queue NAPI polling mode 913 * The driver supports a single pair of RX/Tx queues 914 * per interrupt group (Rx/Tx int line). MQ_MG mode 915 * devices have 2 interrupt groups, so the device will 916 * have a total of 2 Tx and 2 Rx queues in this case. 917 * GFAR_MQ_POLLING: Multi Queue NAPI polling mode 918 * The driver supports all the 8 Rx and Tx HW queues 919 * each queue mapped by the Device Tree to one of 920 * the 2 interrupt groups. This mode implies significant 921 * processing overhead (CPU and controller level). 922 */ 923enum gfar_poll_mode { 924 GFAR_SQ_POLLING = 0, 925 GFAR_MQ_POLLING 926}; 927 928/* 929 * Per TX queue stats 930 */ 931struct tx_q_stats { 932 unsigned long tx_packets; 933 unsigned long tx_bytes; 934}; 935 936/** 937 * struct gfar_priv_tx_q - per tx queue structure 938 * @txlock: per queue tx spin lock 939 * @tx_skbuff:skb pointers 940 * @skb_curtx: to be used skb pointer 941 * @skb_dirtytx:the last used skb pointer 942 * @stats: bytes/packets stats 943 * @qindex: index of this queue 944 * @dev: back pointer to the dev structure 945 * @grp: back pointer to the group to which this queue belongs 946 * @tx_bd_base: First tx buffer descriptor 947 * @cur_tx: Next free ring entry 948 * @dirty_tx: First buffer in line to be transmitted 949 * @tx_ring_size: Tx ring size 950 * @num_txbdfree: number of free TxBds 951 * @txcoalescing: enable/disable tx coalescing 952 * @txic: transmit interrupt coalescing value 953 * @txcount: coalescing value if based on tx frame count 954 * @txtime: coalescing value if based on time 955 */ 956struct gfar_priv_tx_q { 957 /* cacheline 1 */ 958 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 959 struct txbd8 *tx_bd_base; 960 struct txbd8 *cur_tx; 961 unsigned int num_txbdfree; 962 unsigned short skb_curtx; 963 unsigned short tx_ring_size; 964 struct tx_q_stats stats; 965 struct gfar_priv_grp *grp; 966 /* cacheline 2 */ 967 struct net_device *dev; 968 struct sk_buff **tx_skbuff; 969 struct txbd8 *dirty_tx; 970 unsigned short skb_dirtytx; 971 unsigned short qindex; 972 /* Configuration info for the coalescing features */ 973 unsigned int txcoalescing; 974 unsigned long txic; 975 dma_addr_t tx_bd_dma_base; 976}; 977 978/* 979 * Per RX queue stats 980 */ 981struct rx_q_stats { 982 unsigned long rx_packets; 983 unsigned long rx_bytes; 984 unsigned long rx_dropped; 985}; 986 987/** 988 * struct gfar_priv_rx_q - per rx queue structure 989 * @rx_skbuff: skb pointers 990 * @skb_currx: currently use skb pointer 991 * @rx_bd_base: First rx buffer descriptor 992 * @cur_rx: Next free rx ring entry 993 * @qindex: index of this queue 994 * @dev: back pointer to the dev structure 995 * @rx_ring_size: Rx ring size 996 * @rxcoalescing: enable/disable rx-coalescing 997 * @rxic: receive interrupt coalescing vlaue 998 */ 999 1000struct gfar_priv_rx_q { 1001 struct sk_buff **rx_skbuff __aligned(SMP_CACHE_BYTES); 1002 dma_addr_t rx_bd_dma_base; 1003 struct rxbd8 *rx_bd_base; 1004 struct rxbd8 *cur_rx; 1005 struct net_device *dev; 1006 struct gfar_priv_grp *grp; 1007 struct rx_q_stats stats; 1008 u16 skb_currx; 1009 u16 qindex; 1010 unsigned int rx_ring_size; 1011 /* RX Coalescing values */ 1012 unsigned char rxcoalescing; 1013 unsigned long rxic; 1014}; 1015 1016enum gfar_irqinfo_id { 1017 GFAR_TX = 0, 1018 GFAR_RX = 1, 1019 GFAR_ER = 2, 1020 GFAR_NUM_IRQS = 3 1021}; 1022 1023struct gfar_irqinfo { 1024 unsigned int irq; 1025 char name[GFAR_INT_NAME_MAX]; 1026}; 1027 1028/** 1029 * struct gfar_priv_grp - per group structure 1030 * @napi: the napi poll function 1031 * @priv: back pointer to the priv structure 1032 * @regs: the ioremapped register space for this group 1033 * @irqinfo: TX/RX/ER irq data for this group 1034 */ 1035 1036struct gfar_priv_grp { 1037 spinlock_t grplock __aligned(SMP_CACHE_BYTES); 1038 struct napi_struct napi_rx; 1039 struct napi_struct napi_tx; 1040 struct gfar __iomem *regs; 1041 struct gfar_priv_tx_q *tx_queue; 1042 struct gfar_priv_rx_q *rx_queue; 1043 unsigned int tstat; 1044 unsigned int rstat; 1045 1046 struct gfar_private *priv; 1047 unsigned long num_tx_queues; 1048 unsigned long tx_bit_map; 1049 unsigned long num_rx_queues; 1050 unsigned long rx_bit_map; 1051 1052 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1053}; 1054 1055#define gfar_irq(grp, ID) \ 1056 ((grp)->irqinfo[GFAR_##ID]) 1057 1058enum gfar_errata { 1059 GFAR_ERRATA_74 = 0x01, 1060 GFAR_ERRATA_76 = 0x02, 1061 GFAR_ERRATA_A002 = 0x04, 1062 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1063}; 1064 1065enum gfar_dev_state { 1066 GFAR_DOWN = 1, 1067 GFAR_RESETTING 1068}; 1069 1070/* Struct stolen almost completely (and shamelessly) from the FCC enet source 1071 * (Ok, that's not so true anymore, but there is a family resemblance) 1072 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1073 * and tx_bd_base always point to the currently available buffer. 1074 * The dirty_tx tracks the current buffer that is being sent by the 1075 * controller. The cur_tx and dirty_tx are equal under both completely 1076 * empty and completely full conditions. The empty/ready indicator in 1077 * the buffer descriptor determines the actual condition. 1078 */ 1079struct gfar_private { 1080 struct device *dev; 1081 struct net_device *ndev; 1082 enum gfar_errata errata; 1083 unsigned int rx_buffer_size; 1084 1085 u16 uses_rxfcb; 1086 u16 padding; 1087 u32 device_flags; 1088 1089 /* HW time stamping enabled flag */ 1090 int hwts_rx_en; 1091 int hwts_tx_en; 1092 1093 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1094 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1095 struct gfar_priv_grp gfargrp[MAXGROUPS]; 1096 1097 unsigned long state; 1098 1099 unsigned short mode; 1100 unsigned short poll_mode; 1101 unsigned int num_tx_queues; 1102 unsigned int num_rx_queues; 1103 unsigned int num_grps; 1104 1105 /* Network Statistics */ 1106 struct gfar_extra_stats extra_stats; 1107 1108 /* PHY stuff */ 1109 phy_interface_t interface; 1110 struct device_node *phy_node; 1111 struct device_node *tbi_node; 1112 struct phy_device *phydev; 1113 struct mii_bus *mii_bus; 1114 int oldspeed; 1115 int oldduplex; 1116 int oldlink; 1117 1118 /* Bitfield update lock */ 1119 spinlock_t bflock; 1120 1121 uint32_t msg_enable; 1122 1123 struct work_struct reset_task; 1124 1125 struct platform_device *ofdev; 1126 unsigned char 1127 extended_hash:1, 1128 bd_stash_en:1, 1129 rx_filer_enable:1, 1130 /* Wake-on-LAN enabled */ 1131 wol_en:1, 1132 /* Enable priorty based Tx scheduling in Hw */ 1133 prio_sched_en:1, 1134 /* Flow control flags */ 1135 pause_aneg_en:1, 1136 tx_pause_en:1, 1137 rx_pause_en:1; 1138 1139 /* The total tx and rx ring size for the enabled queues */ 1140 unsigned int total_tx_ring_size; 1141 unsigned int total_rx_ring_size; 1142 1143 u32 rqueue; 1144 u32 tqueue; 1145 1146 /* RX per device parameters */ 1147 unsigned int rx_stash_size; 1148 unsigned int rx_stash_index; 1149 1150 u32 cur_filer_idx; 1151 1152 /* RX queue filer rule set*/ 1153 struct ethtool_rx_list rx_list; 1154 struct mutex rx_queue_access; 1155 1156 /* Hash registers and their width */ 1157 u32 __iomem *hash_regs[16]; 1158 int hash_width; 1159 1160 /*Filer table*/ 1161 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1162 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1163}; 1164 1165 1166static inline int gfar_has_errata(struct gfar_private *priv, 1167 enum gfar_errata err) 1168{ 1169 return priv->errata & err; 1170} 1171 1172static inline u32 gfar_read(unsigned __iomem *addr) 1173{ 1174 u32 val; 1175 val = ioread32be(addr); 1176 return val; 1177} 1178 1179static inline void gfar_write(unsigned __iomem *addr, u32 val) 1180{ 1181 iowrite32be(val, addr); 1182} 1183 1184static inline void gfar_write_filer(struct gfar_private *priv, 1185 unsigned int far, unsigned int fcr, unsigned int fpr) 1186{ 1187 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1188 1189 gfar_write(®s->rqfar, far); 1190 gfar_write(®s->rqfcr, fcr); 1191 gfar_write(®s->rqfpr, fpr); 1192} 1193 1194static inline void gfar_read_filer(struct gfar_private *priv, 1195 unsigned int far, unsigned int *fcr, unsigned int *fpr) 1196{ 1197 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1198 1199 gfar_write(®s->rqfar, far); 1200 *fcr = gfar_read(®s->rqfcr); 1201 *fpr = gfar_read(®s->rqfpr); 1202} 1203 1204static inline void gfar_write_isrg(struct gfar_private *priv) 1205{ 1206 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1207 u32 __iomem *baddr = ®s->isrg0; 1208 u32 isrg = 0; 1209 int grp_idx, i; 1210 1211 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1212 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; 1213 1214 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 1215 isrg |= (ISRG_RR0 >> i); 1216 } 1217 1218 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 1219 isrg |= (ISRG_TR0 >> i); 1220 } 1221 1222 gfar_write(baddr, isrg); 1223 1224 baddr++; 1225 isrg = 0; 1226 } 1227} 1228 1229static inline int gfar_is_dma_stopped(struct gfar_private *priv) 1230{ 1231 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1232 1233 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == 1234 (IEVENT_GRSC | IEVENT_GTSC)); 1235} 1236 1237static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) 1238{ 1239 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1240 1241 return gfar_read(®s->ievent) & IEVENT_GRSC; 1242} 1243 1244static inline void gfar_wmb(void) 1245{ 1246#if defined(CONFIG_PPC) 1247 /* The powerpc-specific eieio() is used, as wmb() has too strong 1248 * semantics (it requires synchronization between cacheable and 1249 * uncacheable mappings, which eieio() doesn't provide and which we 1250 * don't need), thus requiring a more expensive sync instruction. At 1251 * some point, the set of architecture-independent barrier functions 1252 * should be expanded to include weaker barriers. 1253 */ 1254 eieio(); 1255#else 1256 wmb(); /* order write acesses for BD (or FCB) fields */ 1257#endif 1258} 1259 1260irqreturn_t gfar_receive(int irq, void *dev_id); 1261int startup_gfar(struct net_device *dev); 1262void stop_gfar(struct net_device *dev); 1263void reset_gfar(struct net_device *dev); 1264void gfar_mac_reset(struct gfar_private *priv); 1265void gfar_halt(struct gfar_private *priv); 1266void gfar_start(struct gfar_private *priv); 1267void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, 1268 u32 regnum, u32 read); 1269void gfar_configure_coalescing_all(struct gfar_private *priv); 1270int gfar_set_features(struct net_device *dev, netdev_features_t features); 1271 1272extern const struct ethtool_ops gfar_ethtool_ops; 1273 1274#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1275 1276#define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1277#define RQFCR_PID_L4P_MASK 0xFFFFFF00 1278#define RQFCR_PID_VID_MASK 0xFFFFF000 1279#define RQFCR_PID_PORT_MASK 0xFFFF0000 1280#define RQFCR_PID_MAC_MASK 0xFF000000 1281 1282struct gfar_mask_entry { 1283 unsigned int mask; /* The mask value which is valid form start to end */ 1284 unsigned int start; 1285 unsigned int end; 1286 unsigned int block; /* Same block values indicate depended entries */ 1287}; 1288 1289/* Represents a receive filer table entry */ 1290struct gfar_filer_entry { 1291 u32 ctrl; 1292 u32 prop; 1293}; 1294 1295 1296/* The 20 additional entries are a shadow for one extra element */ 1297struct filer_table { 1298 u32 index; 1299 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1300}; 1301 1302/* The gianfar_ptp module will set this variable */ 1303extern int gfar_phc_index; 1304 1305#endif /* __GIANFAR_H */ 1306