1e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman/* Intel PRO/1000 Linux driver 2e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Copyright(c) 1999 - 2014 Intel Corporation. 3e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 4e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * This program is free software; you can redistribute it and/or modify it 5e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * under the terms and conditions of the GNU General Public License, 6e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * version 2, as published by the Free Software Foundation. 7e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 8e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * This program is distributed in the hope it will be useful, but WITHOUT 9e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * more details. 12e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 13e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * The full GNU General Public License is included in this distribution in 14e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * the file called "COPYING". 15e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 16e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Contact Information: 17e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Linux NICS <linux.nics@intel.com> 18e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman */ 21bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 22bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/* Linux PRO/1000 Ethernet Driver main header file */ 23bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 24bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#ifndef _E1000_H_ 25bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define _E1000_H_ 26bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 2786d70e532c352bd309dab5f1d18d113f441cb3aeJeff Kirsher#include <linux/bitops.h> 28bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include <linux/types.h> 29bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include <linux/timer.h> 30bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include <linux/workqueue.h> 31bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include <linux/io.h> 32bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include <linux/netdevice.h> 33d8014dbca7f5d2d6f0fdb47e5286bd2d887f7065Bruce Allan#include <linux/pci.h> 346f461f6c7c961f0b1b73c0f27becf472a0ac606bBruce Allan#include <linux/pci-aspm.h> 35fe46f58fa61f025564a3c1e80b789885cb4b0f30Bruce Allan#include <linux/crc32.h> 3686d70e532c352bd309dab5f1d18d113f441cb3aeJeff Kirsher#include <linux/if_vlan.h> 37b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#include <linux/clocksource.h> 38b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#include <linux/net_tstamp.h> 39d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allan#include <linux/ptp_clock_kernel.h> 40d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allan#include <linux/ptp_classify.h> 41c2ade1a41d69b8b734dd9947bf7ec25bb2fd2f33Bruce Allan#include <linux/mii.h> 42d495bcb84d2c3abb5ad5e43cfeea0e305ceffb30Bruce Allan#include <linux/mdio.h> 43bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#include "hw.h" 44bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 45bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_info; 46bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 4744defeb3f6f98ea9bb48a2fe6eb9004e9e1a49a1Jeff Kirsher#define e_dbg(format, arg...) \ 488544b9f7371ec6a7a5c0f8701ddde9e98f52a37eBruce Allan netdev_dbg(hw->adapter->netdev, format, ## arg) 4944defeb3f6f98ea9bb48a2fe6eb9004e9e1a49a1Jeff Kirsher#define e_err(format, arg...) \ 508544b9f7371ec6a7a5c0f8701ddde9e98f52a37eBruce Allan netdev_err(adapter->netdev, format, ## arg) 5144defeb3f6f98ea9bb48a2fe6eb9004e9e1a49a1Jeff Kirsher#define e_info(format, arg...) \ 528544b9f7371ec6a7a5c0f8701ddde9e98f52a37eBruce Allan netdev_info(adapter->netdev, format, ## arg) 5344defeb3f6f98ea9bb48a2fe6eb9004e9e1a49a1Jeff Kirsher#define e_warn(format, arg...) \ 548544b9f7371ec6a7a5c0f8701ddde9e98f52a37eBruce Allan netdev_warn(adapter->netdev, format, ## arg) 5544defeb3f6f98ea9bb48a2fe6eb9004e9e1a49a1Jeff Kirsher#define e_notice(format, arg...) \ 568544b9f7371ec6a7a5c0f8701ddde9e98f52a37eBruce Allan netdev_notice(adapter->netdev, format, ## arg) 57bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 5898a1708de1bfa5fe1c490febba850d6043d3c7faMartin Olsson/* Interrupt modes, as used by the IntMode parameter */ 594662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan#define E1000E_INT_MODE_LEGACY 0 604662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan#define E1000E_INT_MODE_MSI 1 614662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan#define E1000E_INT_MODE_MSIX 2 624662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan 63ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan/* Tx/Rx descriptor defines */ 64bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_DEFAULT_TXD 256 65bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_MAX_TXD 4096 667b1be1987c1e8163b3631dcd1ce4f03707d60c3bAuke Kok#define E1000_MIN_TXD 64 67bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 68bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_DEFAULT_RXD 256 69bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_MAX_RXD 4096 707b1be1987c1e8163b3631dcd1ce4f03707d60c3bAuke Kok#define E1000_MIN_RXD 64 71bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 72de5b3077da8275e87196a1e34c5535f5279c5e1aAuke Kok#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ 73de5b3077da8275e87196a1e34c5535f5279c5e1aAuke Kok#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ 74de5b3077da8275e87196a1e34c5535f5279c5e1aAuke Kok 75bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 76bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 77bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 78bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/* How many Rx Buffers do we bundle into one write to the hardware ? */ 79bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 80bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 81bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define AUTO_ALL_MODES 0 82bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_EEPROM_APME 0x0400 83bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 84bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_MNG_VLAN_NONE (-1) 85bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 862adc55c959940fc680074392eddbd5585a76f3d9Bruce Allan#define DEFAULT_JUMBO 9234 872adc55c959940fc680074392eddbd5585a76f3d9Bruce Allan 8823606cf5d1192c2b17912cb2ef6e62f9b11de133Rafael J. Wysocki/* Time to wait before putting the device into D3 if there's no link (in ms). */ 8923606cf5d1192c2b17912cb2ef6e62f9b11de133Rafael J. Wysocki#define LINK_TIMEOUT 100 9023606cf5d1192c2b17912cb2ef6e62f9b11de133Rafael J. Wysocki 91e921eb1ac411a32b98fa1a9ccbba1b24fae8de2dBruce Allan/* Count for polling __E1000_RESET condition every 10-20msec. 92bb9e44d0d0f45da356c39e485edacff6e14ba961Bruce Allan * Experimentation has shown the reset can take approximately 210msec. 93bb9e44d0d0f45da356c39e485edacff6e14ba961Bruce Allan */ 94bb9e44d0d0f45da356c39e485edacff6e14ba961Bruce Allan#define E1000_CHECK_RESET_COUNT 25 95bb9e44d0d0f45da356c39e485edacff6e14ba961Bruce Allan 963a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define DEFAULT_RDTR 0 973a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define DEFAULT_RADV 8 983a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define BURST_RDTR 0x20 993a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define BURST_RADV 0x20 1003a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 101e921eb1ac411a32b98fa1a9ccbba1b24fae8de2dBruce Allan/* in the case of WTHRESH, it appears at least the 82571/2 hardware 1023a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 1038edc0e624db3756783233e464879eb2e3b904c13Hiroaki SHIMODA * WTHRESH=4, so a setting of 5 gives the most efficient bus 1048edc0e624db3756783233e464879eb2e3b904c13Hiroaki SHIMODA * utilization but to avoid possible Tx stalls, set it to 1 1053a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg */ 1063a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define E1000_TXDCTL_DMA_BURST_ENABLE \ 1073a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 1083a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg E1000_TXDCTL_COUNT_DESC | \ 1098edc0e624db3756783233e464879eb2e3b904c13Hiroaki SHIMODA (1 << 16) | /* wthresh must be +1 more than desired */\ 1103a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg (1 << 8) | /* hthresh */ \ 1113a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 0x1f) /* pthresh */ 1123a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 1133a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define E1000_RXDCTL_DMA_BURST_ENABLE \ 1143a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg (0x01000000 | /* set descriptor granularity */ \ 1153a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg (4 << 16) | /* set writeback threshold */ \ 1163a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg (4 << 8) | /* set prefetch threshold */ \ 1173a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 0x20) /* set hthresh */ 1183a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 1193a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define E1000_TIDV_FPD (1 << 31) 1203a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define E1000_RDTR_FPD (1 << 31) 1213a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg 122bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokenum e1000_boards { 123bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_82571, 124bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_82572, 125bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_82573, 1264662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan board_82574, 1278c81c9c315b7e7e240906fab0e8dde1595101bd2Alexander Duyck board_82583, 128bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_80003es2lan, 129bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_ich8lan, 130bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok board_ich9lan, 131f4187b56e1f8a05dd110875d5094b21b51ebd79bBruce Allan board_ich10lan, 132a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan board_pchlan, 133d3738bb8203acf8552c3ec8b3447133fc0938dddBruce Allan board_pch2lan, 1342fbe4526e5aafc9ffa5d85fa4749a7c5b22af6b2Bruce Allan board_pch_lpt, 135bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 136bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 137bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_ps_page { 138bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct page *page; 139bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 dma; /* must be u64 - written to hw */ 140bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 141bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 142e921eb1ac411a32b98fa1a9ccbba1b24fae8de2dBruce Allan/* wrappers around a pointer to a socket buffer, 143bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok * so a DMA handle can be stored along with the buffer 144bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok */ 145bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_buffer { 146bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok dma_addr_t dma; 147bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct sk_buff *skb; 148bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok union { 149ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan /* Tx */ 150bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct { 151bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned long time_stamp; 152bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 length; 153bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 next_to_watch; 1549ed318d546a29d7a591dbe648fd1a2efe3be1180Tom Herbert unsigned int segs; 1559ed318d546a29d7a591dbe648fd1a2efe3be1180Tom Herbert unsigned int bytecount; 15603b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck u16 mapped_as_page; 157bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok }; 158ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan /* Rx */ 15903b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck struct { 16003b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck /* arrays of page information for packet split */ 16103b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck struct e1000_ps_page *ps_pages; 16203b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck struct page *page; 16303b1320dfceeb093890cdd7433e910dca6225ddbAlexander Duyck }; 164bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok }; 165bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 166bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 167bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_ring { 16855aa69854a93d7aaf123a882b0b1f93c86cf3c7eBruce Allan struct e1000_adapter *adapter; /* back pointer to adapter */ 169bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok void *desc; /* pointer to ring memory */ 170bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok dma_addr_t dma; /* phys address of ring */ 171bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int size; /* length of ring in bytes */ 172bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int count; /* number of desc. in ring */ 173bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 174bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 next_to_use; 175bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 next_to_clean; 176bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 177c5083cf6d286e4d3485eaf7904e5d60a2d9df6f5Bruce Allan void __iomem *head; 178c5083cf6d286e4d3485eaf7904e5d60a2d9df6f5Bruce Allan void __iomem *tail; 179bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 180bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok /* array of buffer information structs */ 181bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_buffer *buffer_info; 182bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 1834662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan char name[IFNAMSIZ + 5]; 1844662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan u32 ims_val; 1854662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan u32 itr_val; 186c5083cf6d286e4d3485eaf7904e5d60a2d9df6f5Bruce Allan void __iomem *itr_register; 1874662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan int set_itr; 1884662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan 189bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct sk_buff *rx_skb_top; 190bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 191bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 1927c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan/* PHY register snapshot values */ 1937c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allanstruct e1000_phy_regs { 1947c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 bmcr; /* basic mode control register */ 1957c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 bmsr; /* basic mode status register */ 1967c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 advertise; /* auto-negotiation advertisement */ 1977c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 lpa; /* link partner ability register */ 1987c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 expansion; /* auto-negotiation expansion reg */ 1997c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 ctrl1000; /* 1000BASE-T control register */ 2007c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 stat1000; /* 1000BASE-T status register */ 2017c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u16 estatus; /* extended status register */ 2027c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan}; 2037c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan 204bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/* board specific private data structure */ 205bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_adapter { 206bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct timer_list watchdog_timer; 207bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct timer_list phy_info_timer; 208bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct timer_list blink_timer; 209bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 210bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct work_struct reset_task; 211bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct work_struct watchdog_task; 212bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 213bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok const struct e1000_info *ei; 214bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 21586d70e532c352bd309dab5f1d18d113f441cb3aeJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 216bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 bd_number; 217bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 rx_buffer_len; 218bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 mng_vlan_id; 219bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 link_speed; 220bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 link_duplex; 2218452759060ad46fc071a7d5bbf1647df5ea2ceabBruce Allan u16 eeprom_vers; 222bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 223bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok /* track device up/down/testing state */ 224bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned long state; 225bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 226bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok /* Interrupt Throttle Rate */ 227bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 itr; 228bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 itr_setting; 229bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 tx_itr; 230bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 rx_itr; 231bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 23233550cecf5d22a216d497a9e1d7681537e8ffb68Bruce Allan /* Tx - one ring per active queue */ 23333550cecf5d22a216d497a9e1d7681537e8ffb68Bruce Allan struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; 234d821a4c4d11ad160925dab2bb009b8444beff484Bruce Allan u32 tx_fifo_limit; 235bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 236bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct napi_struct napi; 237bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 23894fb848bf43fae3410639fb2110a783200e9e1daBruce Allan unsigned int uncorr_errors; /* uncorrectable ECC errors */ 23994fb848bf43fae3410639fb2110a783200e9e1daBruce Allan unsigned int corr_errors; /* correctable ECC errors */ 240bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int restart_queue; 241bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 txd_cmd; 242bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 243bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok bool detect_tx_hung; 24409357b00255c233705b1cf6d76a8d147340545b8Jeff Kirsher bool tx_hang_recheck; 245bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u8 tx_timeout_factor; 246bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 247bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_int_delay; 248bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_abs_int_delay; 249bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 250bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int total_tx_bytes; 251bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int total_tx_packets; 252bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int total_rx_bytes; 253bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int total_rx_packets; 254bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 255ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan /* Tx stats */ 256bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 tpt_old; 257bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 colc_old; 2587c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u32 gotc; 2597c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u64 gotc_old; 260bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_timeout_count; 261bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_fifo_head; 262bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_head_addr; 263bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_fifo_size; 264bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 tx_dma_failed; 26559c871c5f0540c974db85eaa77f518de26940c1fJakub Kicinski u32 tx_hwtstamp_timeouts; 266bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 267e921eb1ac411a32b98fa1a9ccbba1b24fae8de2dBruce Allan /* Rx */ 268b56083ea6986a956ce6ecefc232b530640adfe0eDavid Ertman bool (*clean_rx)(struct e1000_ring *ring, int *work_done, 269b56083ea6986a956ce6ecefc232b530640adfe0eDavid Ertman int work_to_do) ____cacheline_aligned_in_smp; 270b56083ea6986a956ce6ecefc232b530640adfe0eDavid Ertman void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, 271b56083ea6986a956ce6ecefc232b530640adfe0eDavid Ertman gfp_t gfp); 272bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_ring *rx_ring; 273bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 274bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 rx_int_delay; 275bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 rx_abs_int_delay; 276bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 277ad68076e07fa01bd0c98278a959d0fd2bb26f1acBruce Allan /* Rx stats */ 278bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 hw_csum_err; 279bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 hw_csum_good; 280bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u64 rx_hdr_split; 2817c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u32 gorc; 2827c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan u64 gorc_old; 283bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 alloc_rx_buff_failed; 284bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 rx_dma_failed; 285b67e191307a3f330525265af3e2877a74d557cbfBruce Allan u32 rx_hwtstamp_cleared; 286bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 287bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int rx_ps_pages; 288bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u16 rx_ps_bsize0; 289318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher u32 max_frame_size; 290318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher u32 min_frame_size; 291bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 292bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok /* OS defined structs */ 293bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct net_device *netdev; 294bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct pci_dev *pdev; 295bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 296bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok /* structs defined in e1000_hw.h */ 297bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_hw hw; 298bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 2999d57088be9f1d166d6ca311218611a51cd3ecfc2Bruce Allan spinlock_t stats64_lock; /* protects statistics counters */ 300bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_hw_stats stats; 301bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_phy_info phy_info; 302bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_phy_stats phy_stats; 303bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 3047c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan /* Snapshot of PHY registers */ 3057c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan struct e1000_phy_regs phy_regs; 3067c25769f88ff0b186766d6a9f9390a2e9fd4670fBruce Allan 307bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_ring test_tx_ring; 308bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok struct e1000_ring test_rx_ring; 309bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 test_icr; 310bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 311bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 msg_enable; 3128e86acd7d5968e08b3e1604e685a8c45f6fd7f40Jeff Kirsher unsigned int num_vectors; 3134662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan struct msix_entry *msix_entries; 3144662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan int int_mode; 3154662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan u32 eiac_mask; 316bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 317bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 eeprom_wol; 318bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 wol; 319bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 pba; 3202adc55c959940fc680074392eddbd5585a76f3d9Bruce Allan u32 max_hw_frame_size; 321bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 322318a94d68979cbe9cc98a3050b4b7be2f08513c8Jeff Kirsher bool fc_autoneg; 323bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 324bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int flags; 325eb7c3adb1ca92450870dbb0d347fc986cd5e2af4Jeff Kirsher unsigned int flags2; 326a8f88ff5a5abc2ce9f7d7d2694178b2c617d713aJesse Brandeburg struct work_struct downshift_task; 327a8f88ff5a5abc2ce9f7d7d2694178b2c617d713aJesse Brandeburg struct work_struct update_phy_task; 32841cec6f1160c110bd69597c2a5611b46e8287801Bruce Allan struct work_struct print_hang_task; 32923606cf5d1192c2b17912cb2ef6e62f9b11de133Rafael J. Wysocki 330ff10e13cd06f3dbe90e9fffc3c2dd2057a116e4bCarolyn Wyborny int phy_hang_count; 33155aa69854a93d7aaf123a882b0b1f93c86cf3c7eBruce Allan 33255aa69854a93d7aaf123a882b0b1f93c86cf3c7eBruce Allan u16 tx_ring_count; 33355aa69854a93d7aaf123a882b0b1f93c86cf3c7eBruce Allan u16 rx_ring_count; 334b67e191307a3f330525265af3e2877a74d557cbfBruce Allan 335b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct hwtstamp_config hwtstamp_config; 336b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct delayed_work systim_overflow_work; 337b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct sk_buff *tx_hwtstamp_skb; 33859c871c5f0540c974db85eaa77f518de26940c1fJakub Kicinski unsigned long tx_hwtstamp_start; 339b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct work_struct tx_hwtstamp_work; 340b67e191307a3f330525265af3e2877a74d557cbfBruce Allan spinlock_t systim_lock; /* protects SYSTIML/H regsters */ 341b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct cyclecounter cc; 342b67e191307a3f330525265af3e2877a74d557cbfBruce Allan struct timecounter tc; 343d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allan struct ptp_clock *ptp_clock; 344d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allan struct ptp_clock_info ptp_clock_info; 345d495bcb84d2c3abb5ad5e43cfeea0e305ceffb30Bruce Allan 346d495bcb84d2c3abb5ad5e43cfeea0e305ceffb30Bruce Allan u16 eee_advert; 347bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 348bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 349bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstruct e1000_info { 350bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok enum e1000_mac_type mac; 351bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok unsigned int flags; 3526f461f6c7c961f0b1b73c0f27becf472a0ac606bBruce Allan unsigned int flags2; 353bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok u32 pba; 3542adc55c959940fc680074392eddbd5585a76f3d9Bruce Allan u32 max_hw_frame_size; 35569e3fd8ccc3d382b4ef72cade817ccd121d8911aJeff Kirsher s32 (*get_variants)(struct e1000_adapter *); 3568ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsher const struct e1000_mac_operations *mac_ops; 3578ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsher const struct e1000_phy_operations *phy_ops; 3588ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsher const struct e1000_nvm_operations *nvm_ops; 359bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 360bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 361d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allans32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); 362d89777bf0e42e7cb6ce8eae35190b9375c3b4211Bruce Allan 363b67e191307a3f330525265af3e2877a74d557cbfBruce Allan/* The system time is maintained by a 64-bit counter comprised of the 32-bit 364b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * SYSTIMH and SYSTIML registers. How the counter increments (and therefore 365b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * its resolution) is based on the contents of the TIMINCA register - it 366b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). 367b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * For the best accuracy, the incperiod should be as small as possible. The 368b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * incvalue is scaled by a factor as large as possible (while still fitting 369b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * in bits 23:0) so that relatively small clock corrections can be made. 370b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * 371b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of 372b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) 373b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * bits to count nanoseconds leaving the rest for fractional nonseconds. 374b67e191307a3f330525265af3e2877a74d557cbfBruce Allan */ 375b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCVALUE_96MHz 125 376b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCVALUE_SHIFT_96MHz 17 377b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCPERIOD_SHIFT_96MHz 2 378b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) 379b67e191307a3f330525265af3e2877a74d557cbfBruce Allan 380b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCVALUE_25MHz 40 381b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCVALUE_SHIFT_25MHz 18 382b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define INCPERIOD_25MHz 1 383b67e191307a3f330525265af3e2877a74d557cbfBruce Allan 384b67e191307a3f330525265af3e2877a74d557cbfBruce Allan/* Another drawback of scaling the incvalue by a large factor is the 385b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * 64-bit SYSTIM register overflows more quickly. This is dealt with 386b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * by simply reading the clock before it overflows. 387b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * 388b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * Clock ns bits Overflows after 389b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ 390b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs 391b67e191307a3f330525265af3e2877a74d557cbfBruce Allan * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours 392b67e191307a3f330525265af3e2877a74d557cbfBruce Allan */ 393b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) 3945e7ff970041321a26f2dc3aa41ba79e787fcf8f9Todd Fujinaka#define E1000_MAX_82574_SYSTIM_REREADS 50 3955e7ff970041321a26f2dc3aa41ba79e787fcf8f9Todd Fujinaka#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) 396b67e191307a3f330525265af3e2877a74d557cbfBruce Allan 397bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok/* hardware capability, feature, and workaround flags */ 398bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_AMT (1 << 0) 399bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_FLASH (1 << 1) 400bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_HW_VLAN_FILTER (1 << 2) 401bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_WOL (1 << 3) 40279d4e9087a6ecd6bf2103bf378bf8e0d79278b5aBruce Allan/* reserved bit4 */ 403bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) 404bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_SWSM_ON_LOAD (1 << 6) 405bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_JUMBO_FRAMES (1 << 7) 4064a7703582836f55a1cbad0e2c1c6ebbee3f9b3a7Bruce Allan#define FLAG_READ_ONLY_NVM (1 << 8) 40797ac8caee238d2a81c23661916f7acd3a22c85feBruce Allan#define FLAG_IS_ICH (1 << 9) 4084662e82b2cb41c60826e50474dd86dd5c6372b0cBruce Allan#define FLAG_HAS_MSIX (1 << 10) 409bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_HAS_SMART_POWER_DOWN (1 << 11) 410bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_IS_QUAD_PORT_A (1 << 12) 411bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_IS_QUAD_PORT (1 << 13) 412b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define FLAG_HAS_HW_TIMESTAMP (1 << 14) 413bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_APME_IN_WUC (1 << 15) 414bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_APME_IN_CTRL3 (1 << 16) 415bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_APME_CHECK_PORT_B (1 << 17) 416bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) 417bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_NO_WAKE_UCAST (1 << 19) 418bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_MNG_PT_ENABLED (1 << 20) 419bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_RESET_OVERWRITES_LAA (1 << 21) 420bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_TARC_SPEED_MODE_BIT (1 << 22) 421bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_TARC_SET_BIT_ZERO (1 << 23) 422bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_RX_NEEDS_RESTART (1 << 24) 423bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_LSC_GIG_SPEED_DROP (1 << 25) 424bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_SMART_POWER_DOWN (1 << 26) 425bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_MSI_ENABLED (1 << 27) 426dc221294719ae0f28cc260cc37edd439161088a9Bruce Allan/* reserved (1 << 28) */ 427bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define FLAG_TSO_FORCE (1 << 29) 42812d43f7d3cd36494a442dea6f2d2c7ccb76d0d80Bruce Allan#define FLAG_RESTART_NOW (1 << 30) 429f8d59f7826aa73c5e7682fbed6db38020635d466Bruce Allan#define FLAG_MSI_TEST_FAILED (1 << 31) 430bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 431eb7c3adb1ca92450870dbb0d347fc986cd5e2af4Jeff Kirsher#define FLAG2_CRC_STRIPPING (1 << 0) 432a4f58f5455ba0efda36fb33c37074922d1527a10Bruce Allan#define FLAG2_HAS_PHY_WAKEUP (1 << 1) 433b94b50289622e816adc9f94111cfc2679c80177cJesse Brandeburg#define FLAG2_IS_DISCARDING (1 << 2) 4346f461f6c7c961f0b1b73c0f27becf472a0ac606bBruce Allan#define FLAG2_DISABLE_ASPM_L1 (1 << 3) 4358c7bbb925337705dd1459070ac620aeec6a29666Bruce Allan#define FLAG2_HAS_PHY_STATS (1 << 4) 436e52997f96008fda655d7ec3aa4297d1272e8a385Bruce Allan#define FLAG2_HAS_EEE (1 << 5) 4373a3b75860527a11ba5035c6aa576079245d09e2aJesse Brandeburg#define FLAG2_DMA_BURST (1 << 6) 43878cd29d5a92ae5067377ad42089f2c8781312f4aBruce Allan#define FLAG2_DISABLE_ASPM_L0S (1 << 7) 439828bac87bb074f3366621724fdfbe314f98ccc7eBruce Allan#define FLAG2_DISABLE_AIM (1 << 8) 440ff10e13cd06f3dbe90e9fffc3c2dd2057a116e4bCarolyn Wyborny#define FLAG2_CHECK_PHY_HANG (1 << 9) 4417f99ae633884043c70f4cc4a03f43dad0f0ecba2Bruce Allan#define FLAG2_NO_DISABLE_RX (1 << 10) 442c6e7f51e73c1bc6044bce989ec503ef2e4758d55Bruce Allan#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) 4430184039a4b6727d6efd545919c773ef141090ae7Ben Greear#define FLAG2_DFLT_CRC_STRIPPING (1 << 12) 444b67e191307a3f330525265af3e2877a74d557cbfBruce Allan#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) 445eb7c3adb1ca92450870dbb0d347fc986cd5e2af4Jeff Kirsher 446bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_RX_DESC_PS(R, i) \ 447bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) 4485f450212f281272f4ef81d96b79bf68cebdbc210Bruce Allan#define E1000_RX_DESC_EXT(R, i) \ 4495f450212f281272f4ef81d96b79bf68cebdbc210Bruce Allan (&(((union e1000_rx_desc_extended *)((R).desc))[i])) 450bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 451bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 452bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) 453bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 454bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokenum e1000_state_t { 455bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok __E1000_TESTING, 456bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok __E1000_RESETTING, 457a90b412cb8c7ccc1689f9ea130883d00a1f0a5bbBruce Allan __E1000_ACCESS_SHARED_RESOURCE, 458bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok __E1000_DOWN 459bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 460bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 461bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokenum latency_range { 462bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok lowest_latency = 0, 463bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok low_latency = 1, 464bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok bulk_latency = 2, 465bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok latency_invalid = 255 466bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok}; 467bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 468bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokextern char e1000e_driver_name[]; 469bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokextern const char e1000e_driver_version[]; 470bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 4715ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_check_options(struct e1000_adapter *adapter); 4725ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_set_ethtool_ops(struct net_device *netdev); 4735ccc921af41a862fe969809228f029035f851502Joe Perches 4745ccc921af41a862fe969809228f029035f851502Joe Perchesint e1000e_up(struct e1000_adapter *adapter); 4752800209994f878b00724ceabb65d744855c8f99aDavid Ertmanvoid e1000e_down(struct e1000_adapter *adapter, bool reset); 4765ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_reinit_locked(struct e1000_adapter *adapter); 4775ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_reset(struct e1000_adapter *adapter); 4785ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_power_up_phy(struct e1000_adapter *adapter); 4795ccc921af41a862fe969809228f029035f851502Joe Perchesint e1000e_setup_rx_resources(struct e1000_ring *ring); 4805ccc921af41a862fe969809228f029035f851502Joe Perchesint e1000e_setup_tx_resources(struct e1000_ring *ring); 4815ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_free_rx_resources(struct e1000_ring *ring); 4825ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_free_tx_resources(struct e1000_ring *ring); 4835ccc921af41a862fe969809228f029035f851502Joe Perchesstruct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, 4845ccc921af41a862fe969809228f029035f851502Joe Perches struct rtnl_link_stats64 *stats); 4855ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_set_interrupt_capability(struct e1000_adapter *adapter); 4865ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); 4875ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_get_hw_control(struct e1000_adapter *adapter); 4885ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_release_hw_control(struct e1000_adapter *adapter); 4895ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); 490bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 491bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokextern unsigned int copybreak; 492bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 4938ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_82571_info; 4948ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_82572_info; 4958ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_82573_info; 4968ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_82574_info; 4978ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_82583_info; 4988ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_ich8_info; 4998ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_ich9_info; 5008ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_ich10_info; 5018ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_pch_info; 5028ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_pch2_info; 5032fbe4526e5aafc9ffa5d85fa4749a7c5b22af6b2Bruce Allanextern const struct e1000_info e1000_pch_lpt_info; 5048ce9d6c725b01989d2b18ee1df853837388ceaf6Jeff Kirsherextern const struct e1000_info e1000_es2_info; 505bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 5065ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_ptp_init(struct e1000_adapter *adapter); 5075ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_ptp_remove(struct e1000_adapter *adapter); 5080be8401051c716be4533272e983b7eed3d83946dBruce Allan 509bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) 510bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 51194d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->phy.ops.reset(hw); 512bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 513bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 514bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) 515bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 51694d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->phy.ops.read_reg(hw, offset, data); 517bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 518bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 519f1430d698d0caa743af61f72fd539726055718d3Bruce Allanstatic inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) 520f1430d698d0caa743af61f72fd539726055718d3Bruce Allan{ 521f1430d698d0caa743af61f72fd539726055718d3Bruce Allan return hw->phy.ops.read_reg_locked(hw, offset, data); 522f1430d698d0caa743af61f72fd539726055718d3Bruce Allan} 523f1430d698d0caa743af61f72fd539726055718d3Bruce Allan 524bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) 525bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 52694d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->phy.ops.write_reg(hw, offset, data); 527bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 528bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 529f1430d698d0caa743af61f72fd539726055718d3Bruce Allanstatic inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) 530f1430d698d0caa743af61f72fd539726055718d3Bruce Allan{ 531f1430d698d0caa743af61f72fd539726055718d3Bruce Allan return hw->phy.ops.write_reg_locked(hw, offset, data); 532f1430d698d0caa743af61f72fd539726055718d3Bruce Allan} 533f1430d698d0caa743af61f72fd539726055718d3Bruce Allan 5345ccc921af41a862fe969809228f029035f851502Joe Perchesvoid e1000e_reload_nvm_generic(struct e1000_hw *hw); 535608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan 536608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allanstatic inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) 537608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan{ 538608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan if (hw->mac.ops.read_mac_addr) 539608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan return hw->mac.ops.read_mac_addr(hw); 540608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan 541608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan return e1000_read_mac_addr_generic(hw); 542608f8a0d014db6cd18d4f535934d4b5d556e3013Bruce Allan} 543bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 544bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) 545bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 54694d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->nvm.ops.validate(hw); 547bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 548bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 549bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) 550bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 55194d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->nvm.ops.update(hw); 552bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 553bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 554c29c3ba55fbfb96e68c62f3ceff8a0ee7e66288fBruce Allanstatic inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, 555c29c3ba55fbfb96e68c62f3ceff8a0ee7e66288fBruce Allan u16 *data) 556bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 55794d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->nvm.ops.read(hw, offset, words, data); 558bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 559bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 560c29c3ba55fbfb96e68c62f3ceff8a0ee7e66288fBruce Allanstatic inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, 561c29c3ba55fbfb96e68c62f3ceff8a0ee7e66288fBruce Allan u16 *data) 562bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 56394d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->nvm.ops.write(hw, offset, words, data); 564bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 565bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 566bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline s32 e1000_get_phy_info(struct e1000_hw *hw) 567bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 56894d8186a693284344ee5cb9734086c7a2370241aBruce Allan return hw->phy.ops.get_info(hw); 569bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 570bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 571bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kokstatic inline u32 __er32(struct e1000_hw *hw, unsigned long reg) 572bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok{ 573bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok return readl(hw->hw_addr + reg); 574bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok} 575bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 576bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan#define er32(reg) __er32(hw, E1000_##reg) 577bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan 578c6f3148c5bcad2eb9ff1c700d6c79815173aed35Andi Kleens32 __ew32_prepare(struct e1000_hw *hw); 579c6f3148c5bcad2eb9ff1c700d6c79815173aed35Andi Kleenvoid __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); 580bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok 581bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan#define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) 582bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan 583bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan#define e1e_flush() er32(STATUS) 584bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan 585bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 586bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan (__ew32((a), (reg + ((offset) << 2)), (value))) 587bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan 588bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan#define E1000_READ_REG_ARRAY(a, reg, offset) \ 589bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan (readl((a)->hw_addr + reg + ((offset) << 2))) 590bdc125f73f3c810754e858b942d54faf4ba6bffeBruce Allan 591bc7f75fa97884d41efbfde1397b621fefb2550b4Auke Kok#endif /* _E1000_H_ */ 592