1/* Intel PRO/1000 Linux driver 2 * Copyright(c) 1999 - 2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Contact Information: 17 * Linux NICS <linux.nics@intel.com> 18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20 */ 21 22#ifndef _E1000_HW_H_ 23#define _E1000_HW_H_ 24 25#include "regs.h" 26#include "defines.h" 27 28struct e1000_hw; 29 30#define E1000_DEV_ID_82571EB_COPPER 0x105E 31#define E1000_DEV_ID_82571EB_FIBER 0x105F 32#define E1000_DEV_ID_82571EB_SERDES 0x1060 33#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 34#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 35#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 36#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 37#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 38#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 39#define E1000_DEV_ID_82572EI_COPPER 0x107D 40#define E1000_DEV_ID_82572EI_FIBER 0x107E 41#define E1000_DEV_ID_82572EI_SERDES 0x107F 42#define E1000_DEV_ID_82572EI 0x10B9 43#define E1000_DEV_ID_82573E 0x108B 44#define E1000_DEV_ID_82573E_IAMT 0x108C 45#define E1000_DEV_ID_82573L 0x109A 46#define E1000_DEV_ID_82574L 0x10D3 47#define E1000_DEV_ID_82574LA 0x10F6 48#define E1000_DEV_ID_82583V 0x150C 49#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 50#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 51#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 52#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 53#define E1000_DEV_ID_ICH8_82567V_3 0x1501 54#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 55#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 56#define E1000_DEV_ID_ICH8_IGP_C 0x104B 57#define E1000_DEV_ID_ICH8_IFE 0x104C 58#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 59#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 60#define E1000_DEV_ID_ICH8_IGP_M 0x104D 61#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 62#define E1000_DEV_ID_ICH9_BM 0x10E5 63#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 64#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 65#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 66#define E1000_DEV_ID_ICH9_IGP_C 0x294C 67#define E1000_DEV_ID_ICH9_IFE 0x10C0 68#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 69#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 70#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 71#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 72#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 73#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 74#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 75#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 76#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 77#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 78#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 79#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 80#define E1000_DEV_ID_PCH2_LV_LM 0x1502 81#define E1000_DEV_ID_PCH2_LV_V 0x1503 82#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 83#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 84#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 85#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 86#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 87#define E1000_DEV_ID_PCH_I218_V2 0x15A1 88#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 89#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 90 91#define E1000_REVISION_4 4 92 93#define E1000_FUNC_1 1 94 95#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 96#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 97 98enum e1000_mac_type { 99 e1000_82571, 100 e1000_82572, 101 e1000_82573, 102 e1000_82574, 103 e1000_82583, 104 e1000_80003es2lan, 105 e1000_ich8lan, 106 e1000_ich9lan, 107 e1000_ich10lan, 108 e1000_pchlan, 109 e1000_pch2lan, 110 e1000_pch_lpt, 111}; 112 113enum e1000_media_type { 114 e1000_media_type_unknown = 0, 115 e1000_media_type_copper = 1, 116 e1000_media_type_fiber = 2, 117 e1000_media_type_internal_serdes = 3, 118 e1000_num_media_types 119}; 120 121enum e1000_nvm_type { 122 e1000_nvm_unknown = 0, 123 e1000_nvm_none, 124 e1000_nvm_eeprom_spi, 125 e1000_nvm_flash_hw, 126 e1000_nvm_flash_sw 127}; 128 129enum e1000_nvm_override { 130 e1000_nvm_override_none = 0, 131 e1000_nvm_override_spi_small, 132 e1000_nvm_override_spi_large 133}; 134 135enum e1000_phy_type { 136 e1000_phy_unknown = 0, 137 e1000_phy_none, 138 e1000_phy_m88, 139 e1000_phy_igp, 140 e1000_phy_igp_2, 141 e1000_phy_gg82563, 142 e1000_phy_igp_3, 143 e1000_phy_ife, 144 e1000_phy_bm, 145 e1000_phy_82578, 146 e1000_phy_82577, 147 e1000_phy_82579, 148 e1000_phy_i217, 149}; 150 151enum e1000_bus_width { 152 e1000_bus_width_unknown = 0, 153 e1000_bus_width_pcie_x1, 154 e1000_bus_width_pcie_x2, 155 e1000_bus_width_pcie_x4 = 4, 156 e1000_bus_width_32, 157 e1000_bus_width_64, 158 e1000_bus_width_reserved 159}; 160 161enum e1000_1000t_rx_status { 162 e1000_1000t_rx_status_not_ok = 0, 163 e1000_1000t_rx_status_ok, 164 e1000_1000t_rx_status_undefined = 0xFF 165}; 166 167enum e1000_rev_polarity { 168 e1000_rev_polarity_normal = 0, 169 e1000_rev_polarity_reversed, 170 e1000_rev_polarity_undefined = 0xFF 171}; 172 173enum e1000_fc_mode { 174 e1000_fc_none = 0, 175 e1000_fc_rx_pause, 176 e1000_fc_tx_pause, 177 e1000_fc_full, 178 e1000_fc_default = 0xFF 179}; 180 181enum e1000_ms_type { 182 e1000_ms_hw_default = 0, 183 e1000_ms_force_master, 184 e1000_ms_force_slave, 185 e1000_ms_auto 186}; 187 188enum e1000_smart_speed { 189 e1000_smart_speed_default = 0, 190 e1000_smart_speed_on, 191 e1000_smart_speed_off 192}; 193 194enum e1000_serdes_link_state { 195 e1000_serdes_link_down = 0, 196 e1000_serdes_link_autoneg_progress, 197 e1000_serdes_link_autoneg_complete, 198 e1000_serdes_link_forced_up 199}; 200 201/* Receive Descriptor - Extended */ 202union e1000_rx_desc_extended { 203 struct { 204 __le64 buffer_addr; 205 __le64 reserved; 206 } read; 207 struct { 208 struct { 209 __le32 mrq; /* Multiple Rx Queues */ 210 union { 211 __le32 rss; /* RSS Hash */ 212 struct { 213 __le16 ip_id; /* IP id */ 214 __le16 csum; /* Packet Checksum */ 215 } csum_ip; 216 } hi_dword; 217 } lower; 218 struct { 219 __le32 status_error; /* ext status/error */ 220 __le16 length; 221 __le16 vlan; /* VLAN tag */ 222 } upper; 223 } wb; /* writeback */ 224}; 225 226#define MAX_PS_BUFFERS 4 227 228/* Number of packet split data buffers (not including the header buffer) */ 229#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 230 231/* Receive Descriptor - Packet Split */ 232union e1000_rx_desc_packet_split { 233 struct { 234 /* one buffer for protocol header(s), three data buffers */ 235 __le64 buffer_addr[MAX_PS_BUFFERS]; 236 } read; 237 struct { 238 struct { 239 __le32 mrq; /* Multiple Rx Queues */ 240 union { 241 __le32 rss; /* RSS Hash */ 242 struct { 243 __le16 ip_id; /* IP id */ 244 __le16 csum; /* Packet Checksum */ 245 } csum_ip; 246 } hi_dword; 247 } lower; 248 struct { 249 __le32 status_error; /* ext status/error */ 250 __le16 length0; /* length of buffer 0 */ 251 __le16 vlan; /* VLAN tag */ 252 } middle; 253 struct { 254 __le16 header_status; 255 /* length of buffers 1-3 */ 256 __le16 length[PS_PAGE_BUFFERS]; 257 } upper; 258 __le64 reserved; 259 } wb; /* writeback */ 260}; 261 262/* Transmit Descriptor */ 263struct e1000_tx_desc { 264 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 265 union { 266 __le32 data; 267 struct { 268 __le16 length; /* Data buffer length */ 269 u8 cso; /* Checksum offset */ 270 u8 cmd; /* Descriptor control */ 271 } flags; 272 } lower; 273 union { 274 __le32 data; 275 struct { 276 u8 status; /* Descriptor status */ 277 u8 css; /* Checksum start */ 278 __le16 special; 279 } fields; 280 } upper; 281}; 282 283/* Offload Context Descriptor */ 284struct e1000_context_desc { 285 union { 286 __le32 ip_config; 287 struct { 288 u8 ipcss; /* IP checksum start */ 289 u8 ipcso; /* IP checksum offset */ 290 __le16 ipcse; /* IP checksum end */ 291 } ip_fields; 292 } lower_setup; 293 union { 294 __le32 tcp_config; 295 struct { 296 u8 tucss; /* TCP checksum start */ 297 u8 tucso; /* TCP checksum offset */ 298 __le16 tucse; /* TCP checksum end */ 299 } tcp_fields; 300 } upper_setup; 301 __le32 cmd_and_length; 302 union { 303 __le32 data; 304 struct { 305 u8 status; /* Descriptor status */ 306 u8 hdr_len; /* Header length */ 307 __le16 mss; /* Maximum segment size */ 308 } fields; 309 } tcp_seg_setup; 310}; 311 312/* Offload data descriptor */ 313struct e1000_data_desc { 314 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 315 union { 316 __le32 data; 317 struct { 318 __le16 length; /* Data buffer length */ 319 u8 typ_len_ext; 320 u8 cmd; 321 } flags; 322 } lower; 323 union { 324 __le32 data; 325 struct { 326 u8 status; /* Descriptor status */ 327 u8 popts; /* Packet Options */ 328 __le16 special; 329 } fields; 330 } upper; 331}; 332 333/* Statistics counters collected by the MAC */ 334struct e1000_hw_stats { 335 u64 crcerrs; 336 u64 algnerrc; 337 u64 symerrs; 338 u64 rxerrc; 339 u64 mpc; 340 u64 scc; 341 u64 ecol; 342 u64 mcc; 343 u64 latecol; 344 u64 colc; 345 u64 dc; 346 u64 tncrs; 347 u64 sec; 348 u64 cexterr; 349 u64 rlec; 350 u64 xonrxc; 351 u64 xontxc; 352 u64 xoffrxc; 353 u64 xofftxc; 354 u64 fcruc; 355 u64 prc64; 356 u64 prc127; 357 u64 prc255; 358 u64 prc511; 359 u64 prc1023; 360 u64 prc1522; 361 u64 gprc; 362 u64 bprc; 363 u64 mprc; 364 u64 gptc; 365 u64 gorc; 366 u64 gotc; 367 u64 rnbc; 368 u64 ruc; 369 u64 rfc; 370 u64 roc; 371 u64 rjc; 372 u64 mgprc; 373 u64 mgpdc; 374 u64 mgptc; 375 u64 tor; 376 u64 tot; 377 u64 tpr; 378 u64 tpt; 379 u64 ptc64; 380 u64 ptc127; 381 u64 ptc255; 382 u64 ptc511; 383 u64 ptc1023; 384 u64 ptc1522; 385 u64 mptc; 386 u64 bptc; 387 u64 tsctc; 388 u64 tsctfc; 389 u64 iac; 390 u64 icrxptc; 391 u64 icrxatc; 392 u64 ictxptc; 393 u64 ictxatc; 394 u64 ictxqec; 395 u64 ictxqmtc; 396 u64 icrxdmtc; 397 u64 icrxoc; 398}; 399 400struct e1000_phy_stats { 401 u32 idle_errors; 402 u32 receive_errors; 403}; 404 405struct e1000_host_mng_dhcp_cookie { 406 u32 signature; 407 u8 status; 408 u8 reserved0; 409 u16 vlan_id; 410 u32 reserved1; 411 u16 reserved2; 412 u8 reserved3; 413 u8 checksum; 414}; 415 416/* Host Interface "Rev 1" */ 417struct e1000_host_command_header { 418 u8 command_id; 419 u8 command_length; 420 u8 command_options; 421 u8 checksum; 422}; 423 424#define E1000_HI_MAX_DATA_LENGTH 252 425struct e1000_host_command_info { 426 struct e1000_host_command_header command_header; 427 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 428}; 429 430/* Host Interface "Rev 2" */ 431struct e1000_host_mng_command_header { 432 u8 command_id; 433 u8 checksum; 434 u16 reserved1; 435 u16 reserved2; 436 u16 command_length; 437}; 438 439#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 440struct e1000_host_mng_command_info { 441 struct e1000_host_mng_command_header command_header; 442 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 443}; 444 445#include "mac.h" 446#include "phy.h" 447#include "nvm.h" 448#include "manage.h" 449 450/* Function pointers for the MAC. */ 451struct e1000_mac_operations { 452 s32 (*id_led_init)(struct e1000_hw *); 453 s32 (*blink_led)(struct e1000_hw *); 454 bool (*check_mng_mode)(struct e1000_hw *); 455 s32 (*check_for_link)(struct e1000_hw *); 456 s32 (*cleanup_led)(struct e1000_hw *); 457 void (*clear_hw_cntrs)(struct e1000_hw *); 458 void (*clear_vfta)(struct e1000_hw *); 459 s32 (*get_bus_info)(struct e1000_hw *); 460 void (*set_lan_id)(struct e1000_hw *); 461 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 462 s32 (*led_on)(struct e1000_hw *); 463 s32 (*led_off)(struct e1000_hw *); 464 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 465 s32 (*reset_hw)(struct e1000_hw *); 466 s32 (*init_hw)(struct e1000_hw *); 467 s32 (*setup_link)(struct e1000_hw *); 468 s32 (*setup_physical_interface)(struct e1000_hw *); 469 s32 (*setup_led)(struct e1000_hw *); 470 void (*write_vfta)(struct e1000_hw *, u32, u32); 471 void (*config_collision_dist)(struct e1000_hw *); 472 int (*rar_set)(struct e1000_hw *, u8 *, u32); 473 s32 (*read_mac_addr)(struct e1000_hw *); 474 u32 (*rar_get_count)(struct e1000_hw *); 475}; 476 477/* When to use various PHY register access functions: 478 * 479 * Func Caller 480 * Function Does Does When to use 481 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 482 * X_reg L,P,A n/a for simple PHY reg accesses 483 * X_reg_locked P,A L for multiple accesses of different regs 484 * on different pages 485 * X_reg_page A L,P for multiple accesses of different regs 486 * on the same page 487 * 488 * Where X=[read|write], L=locking, P=sets page, A=register access 489 * 490 */ 491struct e1000_phy_operations { 492 s32 (*acquire)(struct e1000_hw *); 493 s32 (*cfg_on_link_up)(struct e1000_hw *); 494 s32 (*check_polarity)(struct e1000_hw *); 495 s32 (*check_reset_block)(struct e1000_hw *); 496 s32 (*commit)(struct e1000_hw *); 497 s32 (*force_speed_duplex)(struct e1000_hw *); 498 s32 (*get_cfg_done)(struct e1000_hw *hw); 499 s32 (*get_cable_length)(struct e1000_hw *); 500 s32 (*get_info)(struct e1000_hw *); 501 s32 (*set_page)(struct e1000_hw *, u16); 502 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 503 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 504 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 505 void (*release)(struct e1000_hw *); 506 s32 (*reset)(struct e1000_hw *); 507 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 508 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 509 s32 (*write_reg)(struct e1000_hw *, u32, u16); 510 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 511 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 512 void (*power_up)(struct e1000_hw *); 513 void (*power_down)(struct e1000_hw *); 514}; 515 516/* Function pointers for the NVM. */ 517struct e1000_nvm_operations { 518 s32 (*acquire)(struct e1000_hw *); 519 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 520 void (*release)(struct e1000_hw *); 521 void (*reload)(struct e1000_hw *); 522 s32 (*update)(struct e1000_hw *); 523 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 524 s32 (*validate)(struct e1000_hw *); 525 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 526}; 527 528struct e1000_mac_info { 529 struct e1000_mac_operations ops; 530 u8 addr[ETH_ALEN]; 531 u8 perm_addr[ETH_ALEN]; 532 533 enum e1000_mac_type type; 534 535 u32 collision_delta; 536 u32 ledctl_default; 537 u32 ledctl_mode1; 538 u32 ledctl_mode2; 539 u32 mc_filter_type; 540 u32 tx_packet_delta; 541 u32 txcw; 542 543 u16 current_ifs_val; 544 u16 ifs_max_val; 545 u16 ifs_min_val; 546 u16 ifs_ratio; 547 u16 ifs_step_size; 548 u16 mta_reg_count; 549 550 /* Maximum size of the MTA register table in all supported adapters */ 551#define MAX_MTA_REG 128 552 u32 mta_shadow[MAX_MTA_REG]; 553 u16 rar_entry_count; 554 555 u8 forced_speed_duplex; 556 557 bool adaptive_ifs; 558 bool has_fwsm; 559 bool arc_subsystem_valid; 560 bool autoneg; 561 bool autoneg_failed; 562 bool get_link_status; 563 bool in_ifs_mode; 564 bool serdes_has_link; 565 bool tx_pkt_filtering; 566 enum e1000_serdes_link_state serdes_link_state; 567}; 568 569struct e1000_phy_info { 570 struct e1000_phy_operations ops; 571 572 enum e1000_phy_type type; 573 574 enum e1000_1000t_rx_status local_rx; 575 enum e1000_1000t_rx_status remote_rx; 576 enum e1000_ms_type ms_type; 577 enum e1000_ms_type original_ms_type; 578 enum e1000_rev_polarity cable_polarity; 579 enum e1000_smart_speed smart_speed; 580 581 u32 addr; 582 u32 id; 583 u32 reset_delay_us; /* in usec */ 584 u32 revision; 585 586 enum e1000_media_type media_type; 587 588 u16 autoneg_advertised; 589 u16 autoneg_mask; 590 u16 cable_length; 591 u16 max_cable_length; 592 u16 min_cable_length; 593 594 u8 mdix; 595 596 bool disable_polarity_correction; 597 bool is_mdix; 598 bool polarity_correction; 599 bool speed_downgraded; 600 bool autoneg_wait_to_complete; 601}; 602 603struct e1000_nvm_info { 604 struct e1000_nvm_operations ops; 605 606 enum e1000_nvm_type type; 607 enum e1000_nvm_override override; 608 609 u32 flash_bank_size; 610 u32 flash_base_addr; 611 612 u16 word_size; 613 u16 delay_usec; 614 u16 address_bits; 615 u16 opcode_bits; 616 u16 page_size; 617}; 618 619struct e1000_bus_info { 620 enum e1000_bus_width width; 621 622 u16 func; 623}; 624 625struct e1000_fc_info { 626 u32 high_water; /* Flow control high-water mark */ 627 u32 low_water; /* Flow control low-water mark */ 628 u16 pause_time; /* Flow control pause timer */ 629 u16 refresh_time; /* Flow control refresh timer */ 630 bool send_xon; /* Flow control send XON */ 631 bool strict_ieee; /* Strict IEEE mode */ 632 enum e1000_fc_mode current_mode; /* FC mode in effect */ 633 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 634}; 635 636struct e1000_dev_spec_82571 { 637 bool laa_is_present; 638 u32 smb_counter; 639}; 640 641struct e1000_dev_spec_80003es2lan { 642 bool mdic_wa_enable; 643}; 644 645struct e1000_shadow_ram { 646 u16 value; 647 bool modified; 648}; 649 650#define E1000_ICH8_SHADOW_RAM_WORDS 2048 651 652/* I218 PHY Ultra Low Power (ULP) states */ 653enum e1000_ulp_state { 654 e1000_ulp_state_unknown, 655 e1000_ulp_state_off, 656 e1000_ulp_state_on, 657}; 658 659struct e1000_dev_spec_ich8lan { 660 bool kmrn_lock_loss_workaround_enabled; 661 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS]; 662 bool nvm_k1_enabled; 663 bool eee_disable; 664 u16 eee_lp_ability; 665 enum e1000_ulp_state ulp_state; 666}; 667 668struct e1000_hw { 669 struct e1000_adapter *adapter; 670 671 void __iomem *hw_addr; 672 void __iomem *flash_address; 673 674 struct e1000_mac_info mac; 675 struct e1000_fc_info fc; 676 struct e1000_phy_info phy; 677 struct e1000_nvm_info nvm; 678 struct e1000_bus_info bus; 679 struct e1000_host_mng_dhcp_cookie mng_cookie; 680 681 union { 682 struct e1000_dev_spec_82571 e82571; 683 struct e1000_dev_spec_80003es2lan e80003es2lan; 684 struct e1000_dev_spec_ich8lan ich8lan; 685 } dev_spec; 686}; 687 688#include "82571.h" 689#include "80003es2lan.h" 690#include "ich8lan.h" 691 692#endif 693