1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_TXRX_H_ 28#define _I40E_TXRX_H_ 29 30/* Interrupt Throttling and Rate Limiting Goodies */ 31 32#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33#define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */ 34#define I40E_MAX_IRATE 0x03F 35#define I40E_MIN_IRATE 0x001 36#define I40E_IRATE_USEC_RESOLUTION 4 37#define I40E_ITR_100K 0x0005 38#define I40E_ITR_20K 0x0019 39#define I40E_ITR_8K 0x003E 40#define I40E_ITR_4K 0x007A 41#define I40E_ITR_RX_DEF I40E_ITR_8K 42#define I40E_ITR_TX_DEF I40E_ITR_4K 43#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46#define I40E_DEFAULT_IRQ_WORK 256 47#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 51#define I40E_QUEUE_END_OF_LIST 0x7FF 52 53/* this enum matches hardware bits and is meant to be used by DYN_CTLN 54 * registers and QINT registers or more generally anywhere in the manual 55 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 56 * register but instead is a special value meaning "don't update" ITR0/1/2. 57 */ 58enum i40e_dyn_idx_t { 59 I40E_IDX_ITR0 = 0, 60 I40E_IDX_ITR1 = 1, 61 I40E_IDX_ITR2 = 2, 62 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 63}; 64 65/* these are indexes into ITRN registers */ 66#define I40E_RX_ITR I40E_IDX_ITR0 67#define I40E_TX_ITR I40E_IDX_ITR1 68#define I40E_PE_ITR I40E_IDX_ITR2 69 70/* Supported RSS offloads */ 71#define I40E_DEFAULT_RSS_HENA ( \ 72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 73 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 76 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 78 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 79 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 80 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 81 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 82 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 83 84/* Supported Rx Buffer Sizes */ 85#define I40E_RXBUFFER_512 512 /* Used for packet split */ 86#define I40E_RXBUFFER_2048 2048 87#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ 88#define I40E_RXBUFFER_4096 4096 89#define I40E_RXBUFFER_8192 8192 90#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 91 92/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 93 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 94 * this adds up to 512 bytes of extra data meaning the smallest allocation 95 * we could have is 1K. 96 * i.e. RXBUFFER_512 --> size-1024 slab 97 */ 98#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 99 100/* How many Rx Buffers do we bundle into one write to the hardware ? */ 101#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 102#define I40E_RX_NEXT_DESC(r, i, n) \ 103 do { \ 104 (i)++; \ 105 if ((i) == (r)->count) \ 106 i = 0; \ 107 (n) = I40E_RX_DESC((r), (i)); \ 108 } while (0) 109 110#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 111 do { \ 112 I40E_RX_NEXT_DESC((r), (i), (n)); \ 113 prefetch((n)); \ 114 } while (0) 115 116#define i40e_rx_desc i40e_32byte_rx_desc 117 118#define I40E_MIN_TX_LEN 17 119#define I40E_MAX_DATA_PER_TXD 8192 120 121/* Tx Descriptors needed, worst case */ 122#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) 123#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 124#define I40E_MIN_DESC_PENDING 4 125 126#define I40E_TX_FLAGS_CSUM (u32)(1) 127#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) 128#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) 129#define I40E_TX_FLAGS_TSO (u32)(1 << 3) 130#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) 131#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) 132#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) 133#define I40E_TX_FLAGS_FSO (u32)(1 << 7) 134#define I40E_TX_FLAGS_TSYN (u32)(1 << 8) 135#define I40E_TX_FLAGS_FD_SB (u32)(1 << 9) 136#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 137#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 138#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 139#define I40E_TX_FLAGS_VLAN_SHIFT 16 140 141struct i40e_tx_buffer { 142 struct i40e_tx_desc *next_to_watch; 143 unsigned long time_stamp; 144 union { 145 struct sk_buff *skb; 146 void *raw_buf; 147 }; 148 unsigned int bytecount; 149 unsigned short gso_segs; 150 DEFINE_DMA_UNMAP_ADDR(dma); 151 DEFINE_DMA_UNMAP_LEN(len); 152 u32 tx_flags; 153}; 154 155struct i40e_rx_buffer { 156 struct sk_buff *skb; 157 dma_addr_t dma; 158 struct page *page; 159 dma_addr_t page_dma; 160 unsigned int page_offset; 161}; 162 163struct i40e_queue_stats { 164 u64 packets; 165 u64 bytes; 166}; 167 168struct i40e_tx_queue_stats { 169 u64 restart_queue; 170 u64 tx_busy; 171 u64 tx_done_old; 172}; 173 174struct i40e_rx_queue_stats { 175 u64 non_eop_descs; 176 u64 alloc_page_failed; 177 u64 alloc_buff_failed; 178}; 179 180enum i40e_ring_state_t { 181 __I40E_TX_FDIR_INIT_DONE, 182 __I40E_TX_XPS_INIT_DONE, 183 __I40E_TX_DETECT_HANG, 184 __I40E_HANG_CHECK_ARMED, 185 __I40E_RX_PS_ENABLED, 186 __I40E_RX_16BYTE_DESC_ENABLED, 187}; 188 189#define ring_is_ps_enabled(ring) \ 190 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 191#define set_ring_ps_enabled(ring) \ 192 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 193#define clear_ring_ps_enabled(ring) \ 194 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 195#define check_for_tx_hang(ring) \ 196 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 197#define set_check_for_tx_hang(ring) \ 198 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 199#define clear_check_for_tx_hang(ring) \ 200 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 201#define ring_is_16byte_desc_enabled(ring) \ 202 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 203#define set_ring_16byte_desc_enabled(ring) \ 204 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 205#define clear_ring_16byte_desc_enabled(ring) \ 206 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 207 208/* struct that defines a descriptor ring, associated with a VSI */ 209struct i40e_ring { 210 struct i40e_ring *next; /* pointer to next ring in q_vector */ 211 void *desc; /* Descriptor ring memory */ 212 struct device *dev; /* Used for DMA mapping */ 213 struct net_device *netdev; /* netdev ring maps to */ 214 union { 215 struct i40e_tx_buffer *tx_bi; 216 struct i40e_rx_buffer *rx_bi; 217 }; 218 unsigned long state; 219 u16 queue_index; /* Queue number of ring */ 220 u8 dcb_tc; /* Traffic class of ring */ 221 u8 __iomem *tail; 222 223 u16 count; /* Number of descriptors */ 224 u16 reg_idx; /* HW register index of the ring */ 225 u16 rx_hdr_len; 226 u16 rx_buf_len; 227 u8 dtype; 228#define I40E_RX_DTYPE_NO_SPLIT 0 229#define I40E_RX_DTYPE_SPLIT_ALWAYS 1 230#define I40E_RX_DTYPE_HEADER_SPLIT 2 231 u8 hsplit; 232#define I40E_RX_SPLIT_L2 0x1 233#define I40E_RX_SPLIT_IP 0x2 234#define I40E_RX_SPLIT_TCP_UDP 0x4 235#define I40E_RX_SPLIT_SCTP 0x8 236 237 /* used in interrupt processing */ 238 u16 next_to_use; 239 u16 next_to_clean; 240 241 u8 atr_sample_rate; 242 u8 atr_count; 243 244 unsigned long last_rx_timestamp; 245 246 bool ring_active; /* is ring online or not */ 247 248 /* stats structs */ 249 struct i40e_queue_stats stats; 250 struct u64_stats_sync syncp; 251 union { 252 struct i40e_tx_queue_stats tx_stats; 253 struct i40e_rx_queue_stats rx_stats; 254 }; 255 256 unsigned int size; /* length of descriptor ring in bytes */ 257 dma_addr_t dma; /* physical address of ring */ 258 259 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 260 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 261 262 struct rcu_head rcu; /* to avoid race on free */ 263} ____cacheline_internodealigned_in_smp; 264 265enum i40e_latency_range { 266 I40E_LOWEST_LATENCY = 0, 267 I40E_LOW_LATENCY = 1, 268 I40E_BULK_LATENCY = 2, 269}; 270 271struct i40e_ring_container { 272 /* array of pointers to rings */ 273 struct i40e_ring *ring; 274 unsigned int total_bytes; /* total bytes processed this int */ 275 unsigned int total_packets; /* total packets processed this int */ 276 u16 count; 277 enum i40e_latency_range latency_range; 278 u16 itr; 279}; 280 281/* iterator for handling rings in ring container */ 282#define i40e_for_each_ring(pos, head) \ 283 for (pos = (head).ring; pos != NULL; pos = pos->next) 284 285void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 286netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 287void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 288void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 289int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 290int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 291void i40e_free_tx_resources(struct i40e_ring *tx_ring); 292void i40e_free_rx_resources(struct i40e_ring *rx_ring); 293int i40e_napi_poll(struct napi_struct *napi, int budget); 294#ifdef I40E_FCOE 295void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 296 struct i40e_tx_buffer *first, u32 tx_flags, 297 const u8 hdr_len, u32 td_cmd, u32 td_offset); 298int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 299int i40e_xmit_descriptor_count(struct sk_buff *skb, struct i40e_ring *tx_ring); 300int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 301 struct i40e_ring *tx_ring, u32 *flags); 302#endif 303#endif /* _I40E_TXRX_H_ */ 304