i40e_adminq.c revision dc641b7319f19a17639ed7d36aaddbf090206644
1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#include "i40e_status.h" 28#include "i40e_type.h" 29#include "i40e_register.h" 30#include "i40e_adminq.h" 31#include "i40e_prototype.h" 32 33static void i40e_resume_aq(struct i40e_hw *hw); 34 35/** 36 * i40e_adminq_init_regs - Initialize AdminQ registers 37 * @hw: pointer to the hardware structure 38 * 39 * This assumes the alloc_asq and alloc_arq functions have already been called 40 **/ 41static void i40e_adminq_init_regs(struct i40e_hw *hw) 42{ 43 /* set head and tail registers in our local struct */ 44 if (hw->mac.type == I40E_MAC_VF) { 45 hw->aq.asq.tail = I40E_VF_ATQT1; 46 hw->aq.asq.head = I40E_VF_ATQH1; 47 hw->aq.asq.len = I40E_VF_ATQLEN1; 48 hw->aq.arq.tail = I40E_VF_ARQT1; 49 hw->aq.arq.head = I40E_VF_ARQH1; 50 hw->aq.arq.len = I40E_VF_ARQLEN1; 51 } else { 52 hw->aq.asq.tail = I40E_PF_ATQT; 53 hw->aq.asq.head = I40E_PF_ATQH; 54 hw->aq.asq.len = I40E_PF_ATQLEN; 55 hw->aq.arq.tail = I40E_PF_ARQT; 56 hw->aq.arq.head = I40E_PF_ARQH; 57 hw->aq.arq.len = I40E_PF_ARQLEN; 58 } 59} 60 61/** 62 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings 63 * @hw: pointer to the hardware structure 64 **/ 65static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 66{ 67 i40e_status ret_code; 68 69 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, 70 i40e_mem_atq_ring, 71 (hw->aq.num_asq_entries * 72 sizeof(struct i40e_aq_desc)), 73 I40E_ADMINQ_DESC_ALIGNMENT); 74 if (ret_code) 75 return ret_code; 76 77 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, 78 (hw->aq.num_asq_entries * 79 sizeof(struct i40e_asq_cmd_details))); 80 if (ret_code) { 81 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 82 return ret_code; 83 } 84 85 return ret_code; 86} 87 88/** 89 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings 90 * @hw: pointer to the hardware structure 91 **/ 92static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 93{ 94 i40e_status ret_code; 95 96 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, 97 i40e_mem_arq_ring, 98 (hw->aq.num_arq_entries * 99 sizeof(struct i40e_aq_desc)), 100 I40E_ADMINQ_DESC_ALIGNMENT); 101 102 return ret_code; 103} 104 105/** 106 * i40e_free_adminq_asq - Free Admin Queue send rings 107 * @hw: pointer to the hardware structure 108 * 109 * This assumes the posted send buffers have already been cleaned 110 * and de-allocated 111 **/ 112static void i40e_free_adminq_asq(struct i40e_hw *hw) 113{ 114 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 115} 116 117/** 118 * i40e_free_adminq_arq - Free Admin Queue receive rings 119 * @hw: pointer to the hardware structure 120 * 121 * This assumes the posted receive buffers have already been cleaned 122 * and de-allocated 123 **/ 124static void i40e_free_adminq_arq(struct i40e_hw *hw) 125{ 126 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 127} 128 129/** 130 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue 131 * @hw: pointer to the hardware structure 132 **/ 133static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw) 134{ 135 i40e_status ret_code; 136 struct i40e_aq_desc *desc; 137 struct i40e_dma_mem *bi; 138 int i; 139 140 /* We'll be allocating the buffer info memory first, then we can 141 * allocate the mapped buffers for the event processing 142 */ 143 144 /* buffer_info structures do not need alignment */ 145 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, 146 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); 147 if (ret_code) 148 goto alloc_arq_bufs; 149 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; 150 151 /* allocate the mapped buffers */ 152 for (i = 0; i < hw->aq.num_arq_entries; i++) { 153 bi = &hw->aq.arq.r.arq_bi[i]; 154 ret_code = i40e_allocate_dma_mem(hw, bi, 155 i40e_mem_arq_buf, 156 hw->aq.arq_buf_size, 157 I40E_ADMINQ_DESC_ALIGNMENT); 158 if (ret_code) 159 goto unwind_alloc_arq_bufs; 160 161 /* now configure the descriptors for use */ 162 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); 163 164 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 165 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 166 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 167 desc->opcode = 0; 168 /* This is in accordance with Admin queue design, there is no 169 * register for buffer size configuration 170 */ 171 desc->datalen = cpu_to_le16((u16)bi->size); 172 desc->retval = 0; 173 desc->cookie_high = 0; 174 desc->cookie_low = 0; 175 desc->params.external.addr_high = 176 cpu_to_le32(upper_32_bits(bi->pa)); 177 desc->params.external.addr_low = 178 cpu_to_le32(lower_32_bits(bi->pa)); 179 desc->params.external.param0 = 0; 180 desc->params.external.param1 = 0; 181 } 182 183alloc_arq_bufs: 184 return ret_code; 185 186unwind_alloc_arq_bufs: 187 /* don't try to free the one that failed... */ 188 i--; 189 for (; i >= 0; i--) 190 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 191 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 192 193 return ret_code; 194} 195 196/** 197 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue 198 * @hw: pointer to the hardware structure 199 **/ 200static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw) 201{ 202 i40e_status ret_code; 203 struct i40e_dma_mem *bi; 204 int i; 205 206 /* No mapped memory needed yet, just the buffer info structures */ 207 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, 208 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); 209 if (ret_code) 210 goto alloc_asq_bufs; 211 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; 212 213 /* allocate the mapped buffers */ 214 for (i = 0; i < hw->aq.num_asq_entries; i++) { 215 bi = &hw->aq.asq.r.asq_bi[i]; 216 ret_code = i40e_allocate_dma_mem(hw, bi, 217 i40e_mem_asq_buf, 218 hw->aq.asq_buf_size, 219 I40E_ADMINQ_DESC_ALIGNMENT); 220 if (ret_code) 221 goto unwind_alloc_asq_bufs; 222 } 223alloc_asq_bufs: 224 return ret_code; 225 226unwind_alloc_asq_bufs: 227 /* don't try to free the one that failed... */ 228 i--; 229 for (; i >= 0; i--) 230 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 231 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 232 233 return ret_code; 234} 235 236/** 237 * i40e_free_arq_bufs - Free receive queue buffer info elements 238 * @hw: pointer to the hardware structure 239 **/ 240static void i40e_free_arq_bufs(struct i40e_hw *hw) 241{ 242 int i; 243 244 /* free descriptors */ 245 for (i = 0; i < hw->aq.num_arq_entries; i++) 246 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); 247 248 /* free the descriptor memory */ 249 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); 250 251 /* free the dma header */ 252 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); 253} 254 255/** 256 * i40e_free_asq_bufs - Free send queue buffer info elements 257 * @hw: pointer to the hardware structure 258 **/ 259static void i40e_free_asq_bufs(struct i40e_hw *hw) 260{ 261 int i; 262 263 /* only unmap if the address is non-NULL */ 264 for (i = 0; i < hw->aq.num_asq_entries; i++) 265 if (hw->aq.asq.r.asq_bi[i].pa) 266 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); 267 268 /* free the buffer info list */ 269 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); 270 271 /* free the descriptor memory */ 272 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); 273 274 /* free the dma header */ 275 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); 276} 277 278/** 279 * i40e_config_asq_regs - configure ASQ registers 280 * @hw: pointer to the hardware structure 281 * 282 * Configure base address and length registers for the transmit queue 283 **/ 284static void i40e_config_asq_regs(struct i40e_hw *hw) 285{ 286 if (hw->mac.type == I40E_MAC_VF) { 287 /* configure the transmit queue */ 288 wr32(hw, I40E_VF_ATQBAH1, 289 upper_32_bits(hw->aq.asq.desc_buf.pa)); 290 wr32(hw, I40E_VF_ATQBAL1, 291 lower_32_bits(hw->aq.asq.desc_buf.pa)); 292 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries | 293 I40E_VF_ATQLEN1_ATQENABLE_MASK)); 294 } else { 295 /* configure the transmit queue */ 296 wr32(hw, I40E_PF_ATQBAH, 297 upper_32_bits(hw->aq.asq.desc_buf.pa)); 298 wr32(hw, I40E_PF_ATQBAL, 299 lower_32_bits(hw->aq.asq.desc_buf.pa)); 300 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries | 301 I40E_PF_ATQLEN_ATQENABLE_MASK)); 302 } 303} 304 305/** 306 * i40e_config_arq_regs - ARQ register configuration 307 * @hw: pointer to the hardware structure 308 * 309 * Configure base address and length registers for the receive (event queue) 310 **/ 311static void i40e_config_arq_regs(struct i40e_hw *hw) 312{ 313 if (hw->mac.type == I40E_MAC_VF) { 314 /* configure the receive queue */ 315 wr32(hw, I40E_VF_ARQBAH1, 316 upper_32_bits(hw->aq.arq.desc_buf.pa)); 317 wr32(hw, I40E_VF_ARQBAL1, 318 lower_32_bits(hw->aq.arq.desc_buf.pa)); 319 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries | 320 I40E_VF_ARQLEN1_ARQENABLE_MASK)); 321 } else { 322 /* configure the receive queue */ 323 wr32(hw, I40E_PF_ARQBAH, 324 upper_32_bits(hw->aq.arq.desc_buf.pa)); 325 wr32(hw, I40E_PF_ARQBAL, 326 lower_32_bits(hw->aq.arq.desc_buf.pa)); 327 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries | 328 I40E_PF_ARQLEN_ARQENABLE_MASK)); 329 } 330 331 /* Update tail in the HW to post pre-allocated buffers */ 332 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); 333} 334 335/** 336 * i40e_init_asq - main initialization routine for ASQ 337 * @hw: pointer to the hardware structure 338 * 339 * This is the main initialization routine for the Admin Send Queue 340 * Prior to calling this function, drivers *MUST* set the following fields 341 * in the hw->aq structure: 342 * - hw->aq.num_asq_entries 343 * - hw->aq.arq_buf_size 344 * 345 * Do *NOT* hold the lock when calling this as the memory allocation routines 346 * called are not going to be atomic context safe 347 **/ 348static i40e_status i40e_init_asq(struct i40e_hw *hw) 349{ 350 i40e_status ret_code = 0; 351 352 if (hw->aq.asq.count > 0) { 353 /* queue already initialized */ 354 ret_code = I40E_ERR_NOT_READY; 355 goto init_adminq_exit; 356 } 357 358 /* verify input for valid configuration */ 359 if ((hw->aq.num_asq_entries == 0) || 360 (hw->aq.asq_buf_size == 0)) { 361 ret_code = I40E_ERR_CONFIG; 362 goto init_adminq_exit; 363 } 364 365 hw->aq.asq.next_to_use = 0; 366 hw->aq.asq.next_to_clean = 0; 367 hw->aq.asq.count = hw->aq.num_asq_entries; 368 369 /* allocate the ring memory */ 370 ret_code = i40e_alloc_adminq_asq_ring(hw); 371 if (ret_code) 372 goto init_adminq_exit; 373 374 /* allocate buffers in the rings */ 375 ret_code = i40e_alloc_asq_bufs(hw); 376 if (ret_code) 377 goto init_adminq_free_rings; 378 379 /* initialize base registers */ 380 i40e_config_asq_regs(hw); 381 382 /* success! */ 383 goto init_adminq_exit; 384 385init_adminq_free_rings: 386 i40e_free_adminq_asq(hw); 387 388init_adminq_exit: 389 return ret_code; 390} 391 392/** 393 * i40e_init_arq - initialize ARQ 394 * @hw: pointer to the hardware structure 395 * 396 * The main initialization routine for the Admin Receive (Event) Queue. 397 * Prior to calling this function, drivers *MUST* set the following fields 398 * in the hw->aq structure: 399 * - hw->aq.num_asq_entries 400 * - hw->aq.arq_buf_size 401 * 402 * Do *NOT* hold the lock when calling this as the memory allocation routines 403 * called are not going to be atomic context safe 404 **/ 405static i40e_status i40e_init_arq(struct i40e_hw *hw) 406{ 407 i40e_status ret_code = 0; 408 409 if (hw->aq.arq.count > 0) { 410 /* queue already initialized */ 411 ret_code = I40E_ERR_NOT_READY; 412 goto init_adminq_exit; 413 } 414 415 /* verify input for valid configuration */ 416 if ((hw->aq.num_arq_entries == 0) || 417 (hw->aq.arq_buf_size == 0)) { 418 ret_code = I40E_ERR_CONFIG; 419 goto init_adminq_exit; 420 } 421 422 hw->aq.arq.next_to_use = 0; 423 hw->aq.arq.next_to_clean = 0; 424 hw->aq.arq.count = hw->aq.num_arq_entries; 425 426 /* allocate the ring memory */ 427 ret_code = i40e_alloc_adminq_arq_ring(hw); 428 if (ret_code) 429 goto init_adminq_exit; 430 431 /* allocate buffers in the rings */ 432 ret_code = i40e_alloc_arq_bufs(hw); 433 if (ret_code) 434 goto init_adminq_free_rings; 435 436 /* initialize base registers */ 437 i40e_config_arq_regs(hw); 438 439 /* success! */ 440 goto init_adminq_exit; 441 442init_adminq_free_rings: 443 i40e_free_adminq_arq(hw); 444 445init_adminq_exit: 446 return ret_code; 447} 448 449/** 450 * i40e_shutdown_asq - shutdown the ASQ 451 * @hw: pointer to the hardware structure 452 * 453 * The main shutdown routine for the Admin Send Queue 454 **/ 455static i40e_status i40e_shutdown_asq(struct i40e_hw *hw) 456{ 457 i40e_status ret_code = 0; 458 459 if (hw->aq.asq.count == 0) 460 return I40E_ERR_NOT_READY; 461 462 /* Stop firmware AdminQ processing */ 463 wr32(hw, hw->aq.asq.head, 0); 464 wr32(hw, hw->aq.asq.tail, 0); 465 wr32(hw, hw->aq.asq.len, 0); 466 467 /* make sure lock is available */ 468 mutex_lock(&hw->aq.asq_mutex); 469 470 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ 471 472 /* free ring buffers */ 473 i40e_free_asq_bufs(hw); 474 475 mutex_unlock(&hw->aq.asq_mutex); 476 477 return ret_code; 478} 479 480/** 481 * i40e_shutdown_arq - shutdown ARQ 482 * @hw: pointer to the hardware structure 483 * 484 * The main shutdown routine for the Admin Receive Queue 485 **/ 486static i40e_status i40e_shutdown_arq(struct i40e_hw *hw) 487{ 488 i40e_status ret_code = 0; 489 490 if (hw->aq.arq.count == 0) 491 return I40E_ERR_NOT_READY; 492 493 /* Stop firmware AdminQ processing */ 494 wr32(hw, hw->aq.arq.head, 0); 495 wr32(hw, hw->aq.arq.tail, 0); 496 wr32(hw, hw->aq.arq.len, 0); 497 498 /* make sure lock is available */ 499 mutex_lock(&hw->aq.arq_mutex); 500 501 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ 502 503 /* free ring buffers */ 504 i40e_free_arq_bufs(hw); 505 506 mutex_unlock(&hw->aq.arq_mutex); 507 508 return ret_code; 509} 510 511/** 512 * i40e_init_adminq - main initialization routine for Admin Queue 513 * @hw: pointer to the hardware structure 514 * 515 * Prior to calling this function, drivers *MUST* set the following fields 516 * in the hw->aq structure: 517 * - hw->aq.num_asq_entries 518 * - hw->aq.num_arq_entries 519 * - hw->aq.arq_buf_size 520 * - hw->aq.asq_buf_size 521 **/ 522i40e_status i40e_init_adminq(struct i40e_hw *hw) 523{ 524 i40e_status ret_code; 525 u16 eetrack_lo, eetrack_hi; 526 int retry = 0; 527 528 /* verify input for valid configuration */ 529 if ((hw->aq.num_arq_entries == 0) || 530 (hw->aq.num_asq_entries == 0) || 531 (hw->aq.arq_buf_size == 0) || 532 (hw->aq.asq_buf_size == 0)) { 533 ret_code = I40E_ERR_CONFIG; 534 goto init_adminq_exit; 535 } 536 537 /* initialize locks */ 538 mutex_init(&hw->aq.asq_mutex); 539 mutex_init(&hw->aq.arq_mutex); 540 541 /* Set up register offsets */ 542 i40e_adminq_init_regs(hw); 543 544 /* allocate the ASQ */ 545 ret_code = i40e_init_asq(hw); 546 if (ret_code) 547 goto init_adminq_destroy_locks; 548 549 /* allocate the ARQ */ 550 ret_code = i40e_init_arq(hw); 551 if (ret_code) 552 goto init_adminq_free_asq; 553 554 /* There are some cases where the firmware may not be quite ready 555 * for AdminQ operations, so we retry the AdminQ setup a few times 556 * if we see timeouts in this first AQ call. 557 */ 558 do { 559 ret_code = i40e_aq_get_firmware_version(hw, 560 &hw->aq.fw_maj_ver, 561 &hw->aq.fw_min_ver, 562 &hw->aq.api_maj_ver, 563 &hw->aq.api_min_ver, 564 NULL); 565 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) 566 break; 567 retry++; 568 msleep(100); 569 i40e_resume_aq(hw); 570 } while (retry < 10); 571 if (ret_code != I40E_SUCCESS) 572 goto init_adminq_free_arq; 573 574 /* get the NVM version info */ 575 i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version); 576 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); 577 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); 578 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 579 580 if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR || 581 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) { 582 ret_code = I40E_ERR_FIRMWARE_API_VERSION; 583 goto init_adminq_free_arq; 584 } 585 586 ret_code = i40e_aq_set_hmc_resource_profile(hw, 587 I40E_HMC_PROFILE_DEFAULT, 588 0, 589 NULL); 590 ret_code = 0; 591 592 /* success! */ 593 goto init_adminq_exit; 594 595init_adminq_free_arq: 596 i40e_shutdown_arq(hw); 597init_adminq_free_asq: 598 i40e_shutdown_asq(hw); 599init_adminq_destroy_locks: 600 601init_adminq_exit: 602 return ret_code; 603} 604 605/** 606 * i40e_shutdown_adminq - shutdown routine for the Admin Queue 607 * @hw: pointer to the hardware structure 608 **/ 609i40e_status i40e_shutdown_adminq(struct i40e_hw *hw) 610{ 611 i40e_status ret_code = 0; 612 613 if (i40e_check_asq_alive(hw)) 614 i40e_aq_queue_shutdown(hw, true); 615 616 i40e_shutdown_asq(hw); 617 i40e_shutdown_arq(hw); 618 619 /* destroy the locks */ 620 621 return ret_code; 622} 623 624/** 625 * i40e_clean_asq - cleans Admin send queue 626 * @asq: pointer to the adminq send ring 627 * 628 * returns the number of free desc 629 **/ 630static u16 i40e_clean_asq(struct i40e_hw *hw) 631{ 632 struct i40e_adminq_ring *asq = &(hw->aq.asq); 633 struct i40e_asq_cmd_details *details; 634 u16 ntc = asq->next_to_clean; 635 struct i40e_aq_desc desc_cb; 636 struct i40e_aq_desc *desc; 637 638 desc = I40E_ADMINQ_DESC(*asq, ntc); 639 details = I40E_ADMINQ_DETAILS(*asq, ntc); 640 while (rd32(hw, hw->aq.asq.head) != ntc) { 641 if (details->callback) { 642 I40E_ADMINQ_CALLBACK cb_func = 643 (I40E_ADMINQ_CALLBACK)details->callback; 644 desc_cb = *desc; 645 cb_func(hw, &desc_cb); 646 } 647 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 648 memset((void *)details, 0, 649 sizeof(struct i40e_asq_cmd_details)); 650 ntc++; 651 if (ntc == asq->count) 652 ntc = 0; 653 desc = I40E_ADMINQ_DESC(*asq, ntc); 654 details = I40E_ADMINQ_DETAILS(*asq, ntc); 655 } 656 657 asq->next_to_clean = ntc; 658 659 return I40E_DESC_UNUSED(asq); 660} 661 662/** 663 * i40e_asq_done - check if FW has processed the Admin Send Queue 664 * @hw: pointer to the hw struct 665 * 666 * Returns true if the firmware has processed all descriptors on the 667 * admin send queue. Returns false if there are still requests pending. 668 **/ 669static bool i40e_asq_done(struct i40e_hw *hw) 670{ 671 /* AQ designers suggest use of head for better 672 * timing reliability than DD bit 673 */ 674 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; 675 676} 677 678/** 679 * i40e_asq_send_command - send command to Admin Queue 680 * @hw: pointer to the hw struct 681 * @desc: prefilled descriptor describing the command (non DMA mem) 682 * @buff: buffer to use for indirect commands 683 * @buff_size: size of buffer for indirect commands 684 * @cmd_details: pointer to command details structure 685 * 686 * This is the main send command driver routine for the Admin Queue send 687 * queue. It runs the queue, cleans the queue, etc 688 **/ 689i40e_status i40e_asq_send_command(struct i40e_hw *hw, 690 struct i40e_aq_desc *desc, 691 void *buff, /* can be NULL */ 692 u16 buff_size, 693 struct i40e_asq_cmd_details *cmd_details) 694{ 695 i40e_status status = 0; 696 struct i40e_dma_mem *dma_buff = NULL; 697 struct i40e_asq_cmd_details *details; 698 struct i40e_aq_desc *desc_on_ring; 699 bool cmd_completed = false; 700 u16 retval = 0; 701 702 if (hw->aq.asq.count == 0) { 703 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, 704 "AQTX: Admin queue not initialized.\n"); 705 status = I40E_ERR_QUEUE_EMPTY; 706 goto asq_send_command_exit; 707 } 708 709 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); 710 if (cmd_details) { 711 *details = *cmd_details; 712 713 /* If the cmd_details are defined copy the cookie. The 714 * cpu_to_le32 is not needed here because the data is ignored 715 * by the FW, only used by the driver 716 */ 717 if (details->cookie) { 718 desc->cookie_high = 719 cpu_to_le32(upper_32_bits(details->cookie)); 720 desc->cookie_low = 721 cpu_to_le32(lower_32_bits(details->cookie)); 722 } 723 } else { 724 memset(details, 0, sizeof(struct i40e_asq_cmd_details)); 725 } 726 727 /* clear requested flags and then set additional flags if defined */ 728 desc->flags &= ~cpu_to_le16(details->flags_dis); 729 desc->flags |= cpu_to_le16(details->flags_ena); 730 731 mutex_lock(&hw->aq.asq_mutex); 732 733 if (buff_size > hw->aq.asq_buf_size) { 734 i40e_debug(hw, 735 I40E_DEBUG_AQ_MESSAGE, 736 "AQTX: Invalid buffer size: %d.\n", 737 buff_size); 738 status = I40E_ERR_INVALID_SIZE; 739 goto asq_send_command_error; 740 } 741 742 if (details->postpone && !details->async) { 743 i40e_debug(hw, 744 I40E_DEBUG_AQ_MESSAGE, 745 "AQTX: Async flag not set along with postpone flag"); 746 status = I40E_ERR_PARAM; 747 goto asq_send_command_error; 748 } 749 750 /* call clean and check queue available function to reclaim the 751 * descriptors that were processed by FW, the function returns the 752 * number of desc available 753 */ 754 /* the clean function called here could be called in a separate thread 755 * in case of asynchronous completions 756 */ 757 if (i40e_clean_asq(hw) == 0) { 758 i40e_debug(hw, 759 I40E_DEBUG_AQ_MESSAGE, 760 "AQTX: Error queue is full.\n"); 761 status = I40E_ERR_ADMIN_QUEUE_FULL; 762 goto asq_send_command_error; 763 } 764 765 /* initialize the temp desc pointer with the right desc */ 766 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); 767 768 /* if the desc is available copy the temp desc to the right place */ 769 *desc_on_ring = *desc; 770 771 /* if buff is not NULL assume indirect command */ 772 if (buff != NULL) { 773 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); 774 /* copy the user buff into the respective DMA buff */ 775 memcpy(dma_buff->va, buff, buff_size); 776 desc_on_ring->datalen = cpu_to_le16(buff_size); 777 778 /* Update the address values in the desc with the pa value 779 * for respective buffer 780 */ 781 desc_on_ring->params.external.addr_high = 782 cpu_to_le32(upper_32_bits(dma_buff->pa)); 783 desc_on_ring->params.external.addr_low = 784 cpu_to_le32(lower_32_bits(dma_buff->pa)); 785 } 786 787 /* bump the tail */ 788 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); 789 (hw->aq.asq.next_to_use)++; 790 if (hw->aq.asq.next_to_use == hw->aq.asq.count) 791 hw->aq.asq.next_to_use = 0; 792 if (!details->postpone) 793 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); 794 795 /* if cmd_details are not defined or async flag is not set, 796 * we need to wait for desc write back 797 */ 798 if (!details->async && !details->postpone) { 799 u32 total_delay = 0; 800 u32 delay_len = 10; 801 802 do { 803 /* AQ designers suggest use of head for better 804 * timing reliability than DD bit 805 */ 806 if (i40e_asq_done(hw)) 807 break; 808 /* ugh! delay while spin_lock */ 809 udelay(delay_len); 810 total_delay += delay_len; 811 } while (total_delay < I40E_ASQ_CMD_TIMEOUT); 812 } 813 814 /* if ready, copy the desc back to temp */ 815 if (i40e_asq_done(hw)) { 816 *desc = *desc_on_ring; 817 if (buff != NULL) 818 memcpy(buff, dma_buff->va, buff_size); 819 retval = le16_to_cpu(desc->retval); 820 if (retval != 0) { 821 i40e_debug(hw, 822 I40E_DEBUG_AQ_MESSAGE, 823 "AQTX: Command completed with error 0x%X.\n", 824 retval); 825 /* strip off FW internal code */ 826 retval &= 0xff; 827 } 828 cmd_completed = true; 829 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) 830 status = 0; 831 else 832 status = I40E_ERR_ADMIN_QUEUE_ERROR; 833 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; 834 } 835 836 /* update the error if time out occurred */ 837 if ((!cmd_completed) && 838 (!details->async && !details->postpone)) { 839 i40e_debug(hw, 840 I40E_DEBUG_AQ_MESSAGE, 841 "AQTX: Writeback timeout.\n"); 842 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT; 843 } 844 845asq_send_command_error: 846 mutex_unlock(&hw->aq.asq_mutex); 847asq_send_command_exit: 848 return status; 849} 850 851/** 852 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function 853 * @desc: pointer to the temp descriptor (non DMA mem) 854 * @opcode: the opcode can be used to decide which flags to turn off or on 855 * 856 * Fill the desc with default values 857 **/ 858void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 859 u16 opcode) 860{ 861 /* zero out the desc */ 862 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 863 desc->opcode = cpu_to_le16(opcode); 864 desc->flags = cpu_to_le16(I40E_AQ_FLAG_EI | I40E_AQ_FLAG_SI); 865} 866 867/** 868 * i40e_clean_arq_element 869 * @hw: pointer to the hw struct 870 * @e: event info from the receive descriptor, includes any buffers 871 * @pending: number of events that could be left to process 872 * 873 * This function cleans one Admin Receive Queue element and returns 874 * the contents through e. It can also return how many events are 875 * left to process through 'pending' 876 **/ 877i40e_status i40e_clean_arq_element(struct i40e_hw *hw, 878 struct i40e_arq_event_info *e, 879 u16 *pending) 880{ 881 i40e_status ret_code = 0; 882 u16 ntc = hw->aq.arq.next_to_clean; 883 struct i40e_aq_desc *desc; 884 struct i40e_dma_mem *bi; 885 u16 desc_idx; 886 u16 datalen; 887 u16 flags; 888 u16 ntu; 889 890 /* take the lock before we start messing with the ring */ 891 mutex_lock(&hw->aq.arq_mutex); 892 893 /* set next_to_use to head */ 894 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); 895 if (ntu == ntc) { 896 /* nothing to do - shouldn't need to update ring's values */ 897 i40e_debug(hw, 898 I40E_DEBUG_AQ_MESSAGE, 899 "AQRX: Queue is empty.\n"); 900 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK; 901 goto clean_arq_element_out; 902 } 903 904 /* now clean the next descriptor */ 905 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); 906 desc_idx = ntc; 907 i40e_debug_aq(hw, 908 I40E_DEBUG_AQ_COMMAND, 909 (void *)desc, 910 hw->aq.arq.r.arq_bi[desc_idx].va); 911 912 flags = le16_to_cpu(desc->flags); 913 if (flags & I40E_AQ_FLAG_ERR) { 914 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; 915 hw->aq.arq_last_status = 916 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval); 917 i40e_debug(hw, 918 I40E_DEBUG_AQ_MESSAGE, 919 "AQRX: Event received with error 0x%X.\n", 920 hw->aq.arq_last_status); 921 } else { 922 memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc)); 923 datalen = le16_to_cpu(desc->datalen); 924 e->msg_size = min(datalen, e->msg_size); 925 if (e->msg_buf != NULL && (e->msg_size != 0)) 926 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va, 927 e->msg_size); 928 } 929 930 /* Restore the original datalen and buffer address in the desc, 931 * FW updates datalen to indicate the event message 932 * size 933 */ 934 bi = &hw->aq.arq.r.arq_bi[ntc]; 935 memset((void *)desc, 0, sizeof(struct i40e_aq_desc)); 936 937 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF); 938 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) 939 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB); 940 desc->datalen = cpu_to_le16((u16)bi->size); 941 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa)); 942 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa)); 943 944 /* set tail = the last cleaned desc index. */ 945 wr32(hw, hw->aq.arq.tail, ntc); 946 /* ntc is updated to tail + 1 */ 947 ntc++; 948 if (ntc == hw->aq.num_arq_entries) 949 ntc = 0; 950 hw->aq.arq.next_to_clean = ntc; 951 hw->aq.arq.next_to_use = ntu; 952 953clean_arq_element_out: 954 /* Set pending if needed, unlock and return */ 955 if (pending != NULL) 956 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); 957 mutex_unlock(&hw->aq.arq_mutex); 958 959 return ret_code; 960} 961 962static void i40e_resume_aq(struct i40e_hw *hw) 963{ 964 /* Registers are reset after PF reset */ 965 hw->aq.asq.next_to_use = 0; 966 hw->aq.asq.next_to_clean = 0; 967 968 i40e_config_asq_regs(hw); 969 970 hw->aq.arq.next_to_use = 0; 971 hw->aq.arq.next_to_clean = 0; 972 973 i40e_config_arq_regs(hw); 974} 975