1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#include "i40e_type.h" 28#include "i40e_adminq.h" 29#include "i40e_prototype.h" 30#include "i40e_virtchnl.h" 31 32/** 33 * i40e_set_mac_type - Sets MAC type 34 * @hw: pointer to the HW structure 35 * 36 * This function sets the mac type of the adapter based on the 37 * vendor ID and device ID stored in the hw structure. 38 **/ 39static i40e_status i40e_set_mac_type(struct i40e_hw *hw) 40{ 41 i40e_status status = 0; 42 43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) { 44 switch (hw->device_id) { 45 case I40E_DEV_ID_SFP_XL710: 46 case I40E_DEV_ID_QEMU: 47 case I40E_DEV_ID_KX_A: 48 case I40E_DEV_ID_KX_B: 49 case I40E_DEV_ID_KX_C: 50 case I40E_DEV_ID_QSFP_A: 51 case I40E_DEV_ID_QSFP_B: 52 case I40E_DEV_ID_QSFP_C: 53 hw->mac.type = I40E_MAC_XL710; 54 break; 55 case I40E_DEV_ID_VF: 56 case I40E_DEV_ID_VF_HV: 57 hw->mac.type = I40E_MAC_VF; 58 break; 59 default: 60 hw->mac.type = I40E_MAC_GENERIC; 61 break; 62 } 63 } else { 64 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 65 } 66 67 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n", 68 hw->mac.type, status); 69 return status; 70} 71 72/** 73 * i40e_debug_aq 74 * @hw: debug mask related to admin queue 75 * @mask: debug mask 76 * @desc: pointer to admin queue descriptor 77 * @buffer: pointer to command buffer 78 * @buf_len: max length of buffer 79 * 80 * Dumps debug log about adminq command with descriptor contents. 81 **/ 82void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 83 void *buffer, u16 buf_len) 84{ 85 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 86 u16 len = le16_to_cpu(aq_desc->datalen); 87 u8 *aq_buffer = (u8 *)buffer; 88 u32 data[4]; 89 u32 i = 0; 90 91 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 92 return; 93 94 i40e_debug(hw, mask, 95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen, 97 aq_desc->retval); 98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 99 aq_desc->cookie_high, aq_desc->cookie_low); 100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 101 aq_desc->params.internal.param0, 102 aq_desc->params.internal.param1); 103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 104 aq_desc->params.external.addr_high, 105 aq_desc->params.external.addr_low); 106 107 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 108 memset(data, 0, sizeof(data)); 109 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 110 if (buf_len < len) 111 len = buf_len; 112 for (i = 0; i < len; i++) { 113 data[((i % 16) / 4)] |= 114 ((u32)aq_buffer[i]) << (8 * (i % 4)); 115 if ((i % 16) == 15) { 116 i40e_debug(hw, mask, 117 "\t0x%04X %08X %08X %08X %08X\n", 118 i - 15, data[0], data[1], data[2], 119 data[3]); 120 memset(data, 0, sizeof(data)); 121 } 122 } 123 if ((i % 16) != 0) 124 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n", 125 i - (i % 16), data[0], data[1], data[2], 126 data[3]); 127 } 128} 129 130/** 131 * i40e_check_asq_alive 132 * @hw: pointer to the hw struct 133 * 134 * Returns true if Queue is enabled else false. 135 **/ 136bool i40e_check_asq_alive(struct i40e_hw *hw) 137{ 138 if (hw->aq.asq.len) 139 return !!(rd32(hw, hw->aq.asq.len) & 140 I40E_PF_ATQLEN_ATQENABLE_MASK); 141 else 142 return false; 143} 144 145/** 146 * i40e_aq_queue_shutdown 147 * @hw: pointer to the hw struct 148 * @unloading: is the driver unloading itself 149 * 150 * Tell the Firmware that we're shutting down the AdminQ and whether 151 * or not the driver is unloading as well. 152 **/ 153i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, 154 bool unloading) 155{ 156 struct i40e_aq_desc desc; 157 struct i40e_aqc_queue_shutdown *cmd = 158 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 159 i40e_status status; 160 161 i40e_fill_default_direct_cmd_desc(&desc, 162 i40e_aqc_opc_queue_shutdown); 163 164 if (unloading) 165 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING); 166 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 167 168 return status; 169} 170 171/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 172 * hardware to a bit-field that can be used by SW to more easily determine the 173 * packet type. 174 * 175 * Macros are used to shorten the table lines and make this table human 176 * readable. 177 * 178 * We store the PTYPE in the top byte of the bit field - this is just so that 179 * we can check that the table doesn't have a row missing, as the index into 180 * the table should be the PTYPE. 181 * 182 * Typical work flow: 183 * 184 * IF NOT i40e_ptype_lookup[ptype].known 185 * THEN 186 * Packet is unknown 187 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 188 * Use the rest of the fields to look at the tunnels, inner protocols, etc 189 * ELSE 190 * Use the enum i40e_rx_l2_ptype to decode the packet type 191 * ENDIF 192 */ 193 194/* macro to make the table lines short */ 195#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 196 { PTYPE, \ 197 1, \ 198 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 199 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 200 I40E_RX_PTYPE_##OUTER_FRAG, \ 201 I40E_RX_PTYPE_TUNNEL_##T, \ 202 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 203 I40E_RX_PTYPE_##TEF, \ 204 I40E_RX_PTYPE_INNER_PROT_##I, \ 205 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 206 207#define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 208 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 209 210/* shorter macros makes the table fit but are terse */ 211#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 212#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 213#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 214 215/* Lookup table mapping the HW PTYPE to the bit field for decoding */ 216struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 217 /* L2 Packet types */ 218 I40E_PTT_UNUSED_ENTRY(0), 219 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 220 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 221 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 222 I40E_PTT_UNUSED_ENTRY(4), 223 I40E_PTT_UNUSED_ENTRY(5), 224 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 225 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 226 I40E_PTT_UNUSED_ENTRY(8), 227 I40E_PTT_UNUSED_ENTRY(9), 228 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 229 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 230 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 231 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 232 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 233 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 234 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 235 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 236 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 237 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 238 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 239 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 240 241 /* Non Tunneled IPv4 */ 242 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 243 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 244 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 245 I40E_PTT_UNUSED_ENTRY(25), 246 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 247 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 248 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 249 250 /* IPv4 --> IPv4 */ 251 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 252 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 253 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 254 I40E_PTT_UNUSED_ENTRY(32), 255 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 256 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 257 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 258 259 /* IPv4 --> IPv6 */ 260 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 261 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 262 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 263 I40E_PTT_UNUSED_ENTRY(39), 264 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 265 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 266 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 267 268 /* IPv4 --> GRE/NAT */ 269 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 270 271 /* IPv4 --> GRE/NAT --> IPv4 */ 272 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 273 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 274 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 275 I40E_PTT_UNUSED_ENTRY(47), 276 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 277 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 278 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 279 280 /* IPv4 --> GRE/NAT --> IPv6 */ 281 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 282 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 283 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 284 I40E_PTT_UNUSED_ENTRY(54), 285 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 286 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 287 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 288 289 /* IPv4 --> GRE/NAT --> MAC */ 290 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 291 292 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 293 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 294 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 295 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 296 I40E_PTT_UNUSED_ENTRY(62), 297 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 298 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 299 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 300 301 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 302 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 303 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 304 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 305 I40E_PTT_UNUSED_ENTRY(69), 306 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 307 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 308 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 309 310 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 311 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 312 313 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 314 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 315 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 316 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 317 I40E_PTT_UNUSED_ENTRY(77), 318 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 319 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 320 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 321 322 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 323 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 324 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 325 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 326 I40E_PTT_UNUSED_ENTRY(84), 327 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 328 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 329 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 330 331 /* Non Tunneled IPv6 */ 332 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 333 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 334 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 335 I40E_PTT_UNUSED_ENTRY(91), 336 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 337 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 338 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 339 340 /* IPv6 --> IPv4 */ 341 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 342 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 343 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 344 I40E_PTT_UNUSED_ENTRY(98), 345 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 346 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 347 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 348 349 /* IPv6 --> IPv6 */ 350 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 351 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 352 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 353 I40E_PTT_UNUSED_ENTRY(105), 354 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 355 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 356 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 357 358 /* IPv6 --> GRE/NAT */ 359 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 360 361 /* IPv6 --> GRE/NAT -> IPv4 */ 362 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 363 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 364 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 365 I40E_PTT_UNUSED_ENTRY(113), 366 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 367 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 368 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 369 370 /* IPv6 --> GRE/NAT -> IPv6 */ 371 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 372 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 373 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 374 I40E_PTT_UNUSED_ENTRY(120), 375 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 376 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 377 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 378 379 /* IPv6 --> GRE/NAT -> MAC */ 380 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 381 382 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 383 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 384 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 385 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 386 I40E_PTT_UNUSED_ENTRY(128), 387 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 388 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 389 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 390 391 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 392 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 393 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 394 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 395 I40E_PTT_UNUSED_ENTRY(135), 396 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 397 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 398 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 399 400 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 401 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 402 403 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 404 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 405 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 406 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 407 I40E_PTT_UNUSED_ENTRY(143), 408 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 409 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 410 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 411 412 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 413 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 414 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 415 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 416 I40E_PTT_UNUSED_ENTRY(150), 417 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 418 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 419 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 420 421 /* unused entries */ 422 I40E_PTT_UNUSED_ENTRY(154), 423 I40E_PTT_UNUSED_ENTRY(155), 424 I40E_PTT_UNUSED_ENTRY(156), 425 I40E_PTT_UNUSED_ENTRY(157), 426 I40E_PTT_UNUSED_ENTRY(158), 427 I40E_PTT_UNUSED_ENTRY(159), 428 429 I40E_PTT_UNUSED_ENTRY(160), 430 I40E_PTT_UNUSED_ENTRY(161), 431 I40E_PTT_UNUSED_ENTRY(162), 432 I40E_PTT_UNUSED_ENTRY(163), 433 I40E_PTT_UNUSED_ENTRY(164), 434 I40E_PTT_UNUSED_ENTRY(165), 435 I40E_PTT_UNUSED_ENTRY(166), 436 I40E_PTT_UNUSED_ENTRY(167), 437 I40E_PTT_UNUSED_ENTRY(168), 438 I40E_PTT_UNUSED_ENTRY(169), 439 440 I40E_PTT_UNUSED_ENTRY(170), 441 I40E_PTT_UNUSED_ENTRY(171), 442 I40E_PTT_UNUSED_ENTRY(172), 443 I40E_PTT_UNUSED_ENTRY(173), 444 I40E_PTT_UNUSED_ENTRY(174), 445 I40E_PTT_UNUSED_ENTRY(175), 446 I40E_PTT_UNUSED_ENTRY(176), 447 I40E_PTT_UNUSED_ENTRY(177), 448 I40E_PTT_UNUSED_ENTRY(178), 449 I40E_PTT_UNUSED_ENTRY(179), 450 451 I40E_PTT_UNUSED_ENTRY(180), 452 I40E_PTT_UNUSED_ENTRY(181), 453 I40E_PTT_UNUSED_ENTRY(182), 454 I40E_PTT_UNUSED_ENTRY(183), 455 I40E_PTT_UNUSED_ENTRY(184), 456 I40E_PTT_UNUSED_ENTRY(185), 457 I40E_PTT_UNUSED_ENTRY(186), 458 I40E_PTT_UNUSED_ENTRY(187), 459 I40E_PTT_UNUSED_ENTRY(188), 460 I40E_PTT_UNUSED_ENTRY(189), 461 462 I40E_PTT_UNUSED_ENTRY(190), 463 I40E_PTT_UNUSED_ENTRY(191), 464 I40E_PTT_UNUSED_ENTRY(192), 465 I40E_PTT_UNUSED_ENTRY(193), 466 I40E_PTT_UNUSED_ENTRY(194), 467 I40E_PTT_UNUSED_ENTRY(195), 468 I40E_PTT_UNUSED_ENTRY(196), 469 I40E_PTT_UNUSED_ENTRY(197), 470 I40E_PTT_UNUSED_ENTRY(198), 471 I40E_PTT_UNUSED_ENTRY(199), 472 473 I40E_PTT_UNUSED_ENTRY(200), 474 I40E_PTT_UNUSED_ENTRY(201), 475 I40E_PTT_UNUSED_ENTRY(202), 476 I40E_PTT_UNUSED_ENTRY(203), 477 I40E_PTT_UNUSED_ENTRY(204), 478 I40E_PTT_UNUSED_ENTRY(205), 479 I40E_PTT_UNUSED_ENTRY(206), 480 I40E_PTT_UNUSED_ENTRY(207), 481 I40E_PTT_UNUSED_ENTRY(208), 482 I40E_PTT_UNUSED_ENTRY(209), 483 484 I40E_PTT_UNUSED_ENTRY(210), 485 I40E_PTT_UNUSED_ENTRY(211), 486 I40E_PTT_UNUSED_ENTRY(212), 487 I40E_PTT_UNUSED_ENTRY(213), 488 I40E_PTT_UNUSED_ENTRY(214), 489 I40E_PTT_UNUSED_ENTRY(215), 490 I40E_PTT_UNUSED_ENTRY(216), 491 I40E_PTT_UNUSED_ENTRY(217), 492 I40E_PTT_UNUSED_ENTRY(218), 493 I40E_PTT_UNUSED_ENTRY(219), 494 495 I40E_PTT_UNUSED_ENTRY(220), 496 I40E_PTT_UNUSED_ENTRY(221), 497 I40E_PTT_UNUSED_ENTRY(222), 498 I40E_PTT_UNUSED_ENTRY(223), 499 I40E_PTT_UNUSED_ENTRY(224), 500 I40E_PTT_UNUSED_ENTRY(225), 501 I40E_PTT_UNUSED_ENTRY(226), 502 I40E_PTT_UNUSED_ENTRY(227), 503 I40E_PTT_UNUSED_ENTRY(228), 504 I40E_PTT_UNUSED_ENTRY(229), 505 506 I40E_PTT_UNUSED_ENTRY(230), 507 I40E_PTT_UNUSED_ENTRY(231), 508 I40E_PTT_UNUSED_ENTRY(232), 509 I40E_PTT_UNUSED_ENTRY(233), 510 I40E_PTT_UNUSED_ENTRY(234), 511 I40E_PTT_UNUSED_ENTRY(235), 512 I40E_PTT_UNUSED_ENTRY(236), 513 I40E_PTT_UNUSED_ENTRY(237), 514 I40E_PTT_UNUSED_ENTRY(238), 515 I40E_PTT_UNUSED_ENTRY(239), 516 517 I40E_PTT_UNUSED_ENTRY(240), 518 I40E_PTT_UNUSED_ENTRY(241), 519 I40E_PTT_UNUSED_ENTRY(242), 520 I40E_PTT_UNUSED_ENTRY(243), 521 I40E_PTT_UNUSED_ENTRY(244), 522 I40E_PTT_UNUSED_ENTRY(245), 523 I40E_PTT_UNUSED_ENTRY(246), 524 I40E_PTT_UNUSED_ENTRY(247), 525 I40E_PTT_UNUSED_ENTRY(248), 526 I40E_PTT_UNUSED_ENTRY(249), 527 528 I40E_PTT_UNUSED_ENTRY(250), 529 I40E_PTT_UNUSED_ENTRY(251), 530 I40E_PTT_UNUSED_ENTRY(252), 531 I40E_PTT_UNUSED_ENTRY(253), 532 I40E_PTT_UNUSED_ENTRY(254), 533 I40E_PTT_UNUSED_ENTRY(255) 534}; 535 536 537/** 538 * i40e_init_shared_code - Initialize the shared code 539 * @hw: pointer to hardware structure 540 * 541 * This assigns the MAC type and PHY code and inits the NVM. 542 * Does not touch the hardware. This function must be called prior to any 543 * other function in the shared code. The i40e_hw structure should be 544 * memset to 0 prior to calling this function. The following fields in 545 * hw structure should be filled in prior to calling this function: 546 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 547 * subsystem_vendor_id, and revision_id 548 **/ 549i40e_status i40e_init_shared_code(struct i40e_hw *hw) 550{ 551 i40e_status status = 0; 552 u32 reg; 553 554 i40e_set_mac_type(hw); 555 556 switch (hw->mac.type) { 557 case I40E_MAC_XL710: 558 break; 559 default: 560 return I40E_ERR_DEVICE_NOT_SUPPORTED; 561 } 562 563 hw->phy.get_link_info = true; 564 565 /* Determine port number */ 566 reg = rd32(hw, I40E_PFGEN_PORTNUM); 567 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >> 568 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT); 569 hw->port = (u8)reg; 570 571 /* Determine the PF number based on the PCI fn */ 572 reg = rd32(hw, I40E_GLPCI_CAPSUP); 573 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK) 574 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func); 575 else 576 hw->pf_id = (u8)hw->bus.func; 577 578 status = i40e_init_nvm(hw); 579 return status; 580} 581 582/** 583 * i40e_aq_mac_address_read - Retrieve the MAC addresses 584 * @hw: pointer to the hw struct 585 * @flags: a return indicator of what addresses were added to the addr store 586 * @addrs: the requestor's mac addr store 587 * @cmd_details: pointer to command details structure or NULL 588 **/ 589static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw, 590 u16 *flags, 591 struct i40e_aqc_mac_address_read_data *addrs, 592 struct i40e_asq_cmd_details *cmd_details) 593{ 594 struct i40e_aq_desc desc; 595 struct i40e_aqc_mac_address_read *cmd_data = 596 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 597 i40e_status status; 598 599 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 600 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF); 601 602 status = i40e_asq_send_command(hw, &desc, addrs, 603 sizeof(*addrs), cmd_details); 604 *flags = le16_to_cpu(cmd_data->command_flags); 605 606 return status; 607} 608 609/** 610 * i40e_aq_mac_address_write - Change the MAC addresses 611 * @hw: pointer to the hw struct 612 * @flags: indicates which MAC to be written 613 * @mac_addr: address to write 614 * @cmd_details: pointer to command details structure or NULL 615 **/ 616i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw, 617 u16 flags, u8 *mac_addr, 618 struct i40e_asq_cmd_details *cmd_details) 619{ 620 struct i40e_aq_desc desc; 621 struct i40e_aqc_mac_address_write *cmd_data = 622 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 623 i40e_status status; 624 625 i40e_fill_default_direct_cmd_desc(&desc, 626 i40e_aqc_opc_mac_address_write); 627 cmd_data->command_flags = cpu_to_le16(flags); 628 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]); 629 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) | 630 ((u32)mac_addr[3] << 16) | 631 ((u32)mac_addr[4] << 8) | 632 mac_addr[5]); 633 634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 635 636 return status; 637} 638 639/** 640 * i40e_get_mac_addr - get MAC address 641 * @hw: pointer to the HW structure 642 * @mac_addr: pointer to MAC address 643 * 644 * Reads the adapter's MAC address from register 645 **/ 646i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 647{ 648 struct i40e_aqc_mac_address_read_data addrs; 649 i40e_status status; 650 u16 flags = 0; 651 652 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 653 654 if (flags & I40E_AQC_LAN_ADDR_VALID) 655 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac)); 656 657 return status; 658} 659 660/** 661 * i40e_get_port_mac_addr - get Port MAC address 662 * @hw: pointer to the HW structure 663 * @mac_addr: pointer to Port MAC address 664 * 665 * Reads the adapter's Port MAC address 666 **/ 667i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 668{ 669 struct i40e_aqc_mac_address_read_data addrs; 670 i40e_status status; 671 u16 flags = 0; 672 673 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 674 if (status) 675 return status; 676 677 if (flags & I40E_AQC_PORT_ADDR_VALID) 678 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac)); 679 else 680 status = I40E_ERR_INVALID_MAC_ADDR; 681 682 return status; 683} 684 685/** 686 * i40e_pre_tx_queue_cfg - pre tx queue configure 687 * @hw: pointer to the HW structure 688 * @queue: target pf queue index 689 * @enable: state change request 690 * 691 * Handles hw requirement to indicate intention to enable 692 * or disable target queue. 693 **/ 694void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 695{ 696 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 697 u32 reg_block = 0; 698 u32 reg_val; 699 700 if (abs_queue_idx >= 128) { 701 reg_block = abs_queue_idx / 128; 702 abs_queue_idx %= 128; 703 } 704 705 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 706 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 707 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 708 709 if (enable) 710 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 711 else 712 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 713 714 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 715} 716#ifdef I40E_FCOE 717 718/** 719 * i40e_get_san_mac_addr - get SAN MAC address 720 * @hw: pointer to the HW structure 721 * @mac_addr: pointer to SAN MAC address 722 * 723 * Reads the adapter's SAN MAC address from NVM 724 **/ 725i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 726{ 727 struct i40e_aqc_mac_address_read_data addrs; 728 i40e_status status; 729 u16 flags = 0; 730 731 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 732 if (status) 733 return status; 734 735 if (flags & I40E_AQC_SAN_ADDR_VALID) 736 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac)); 737 else 738 status = I40E_ERR_INVALID_MAC_ADDR; 739 740 return status; 741} 742#endif 743 744/** 745 * i40e_get_media_type - Gets media type 746 * @hw: pointer to the hardware structure 747 **/ 748static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 749{ 750 enum i40e_media_type media; 751 752 switch (hw->phy.link_info.phy_type) { 753 case I40E_PHY_TYPE_10GBASE_SR: 754 case I40E_PHY_TYPE_10GBASE_LR: 755 case I40E_PHY_TYPE_1000BASE_SX: 756 case I40E_PHY_TYPE_1000BASE_LX: 757 case I40E_PHY_TYPE_40GBASE_SR4: 758 case I40E_PHY_TYPE_40GBASE_LR4: 759 media = I40E_MEDIA_TYPE_FIBER; 760 break; 761 case I40E_PHY_TYPE_100BASE_TX: 762 case I40E_PHY_TYPE_1000BASE_T: 763 case I40E_PHY_TYPE_10GBASE_T: 764 media = I40E_MEDIA_TYPE_BASET; 765 break; 766 case I40E_PHY_TYPE_10GBASE_CR1_CU: 767 case I40E_PHY_TYPE_40GBASE_CR4_CU: 768 case I40E_PHY_TYPE_10GBASE_CR1: 769 case I40E_PHY_TYPE_40GBASE_CR4: 770 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 771 media = I40E_MEDIA_TYPE_DA; 772 break; 773 case I40E_PHY_TYPE_1000BASE_KX: 774 case I40E_PHY_TYPE_10GBASE_KX4: 775 case I40E_PHY_TYPE_10GBASE_KR: 776 case I40E_PHY_TYPE_40GBASE_KR4: 777 media = I40E_MEDIA_TYPE_BACKPLANE; 778 break; 779 case I40E_PHY_TYPE_SGMII: 780 case I40E_PHY_TYPE_XAUI: 781 case I40E_PHY_TYPE_XFI: 782 case I40E_PHY_TYPE_XLAUI: 783 case I40E_PHY_TYPE_XLPPI: 784 default: 785 media = I40E_MEDIA_TYPE_UNKNOWN; 786 break; 787 } 788 789 return media; 790} 791 792#define I40E_PF_RESET_WAIT_COUNT_A0 200 793#define I40E_PF_RESET_WAIT_COUNT 100 794/** 795 * i40e_pf_reset - Reset the PF 796 * @hw: pointer to the hardware structure 797 * 798 * Assuming someone else has triggered a global reset, 799 * assure the global reset is complete and then reset the PF 800 **/ 801i40e_status i40e_pf_reset(struct i40e_hw *hw) 802{ 803 u32 cnt = 0; 804 u32 cnt1 = 0; 805 u32 reg = 0; 806 u32 grst_del; 807 808 /* Poll for Global Reset steady state in case of recent GRST. 809 * The grst delay value is in 100ms units, and we'll wait a 810 * couple counts longer to be sure we don't just miss the end. 811 */ 812 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK 813 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 814 for (cnt = 0; cnt < grst_del + 2; cnt++) { 815 reg = rd32(hw, I40E_GLGEN_RSTAT); 816 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 817 break; 818 msleep(100); 819 } 820 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 821 hw_dbg(hw, "Global reset polling failed to complete.\n"); 822 return I40E_ERR_RESET_FAILED; 823 } 824 825 /* Now Wait for the FW to be ready */ 826 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 827 reg = rd32(hw, I40E_GLNVM_ULD); 828 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 829 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 830 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 831 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 832 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1); 833 break; 834 } 835 usleep_range(10000, 20000); 836 } 837 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 838 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 839 hw_dbg(hw, "wait for FW Reset complete timedout\n"); 840 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); 841 return I40E_ERR_RESET_FAILED; 842 } 843 844 /* If there was a Global Reset in progress when we got here, 845 * we don't need to do the PF Reset 846 */ 847 if (!cnt) { 848 if (hw->revision_id == 0) 849 cnt = I40E_PF_RESET_WAIT_COUNT_A0; 850 else 851 cnt = I40E_PF_RESET_WAIT_COUNT; 852 reg = rd32(hw, I40E_PFGEN_CTRL); 853 wr32(hw, I40E_PFGEN_CTRL, 854 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 855 for (; cnt; cnt--) { 856 reg = rd32(hw, I40E_PFGEN_CTRL); 857 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 858 break; 859 usleep_range(1000, 2000); 860 } 861 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 862 hw_dbg(hw, "PF reset polling failed to complete.\n"); 863 return I40E_ERR_RESET_FAILED; 864 } 865 } 866 867 i40e_clear_pxe_mode(hw); 868 869 return 0; 870} 871 872/** 873 * i40e_clear_hw - clear out any left over hw state 874 * @hw: pointer to the hw struct 875 * 876 * Clear queues and interrupts, typically called at init time, 877 * but after the capabilities have been found so we know how many 878 * queues and msix vectors have been allocated. 879 **/ 880void i40e_clear_hw(struct i40e_hw *hw) 881{ 882 u32 num_queues, base_queue; 883 u32 num_pf_int; 884 u32 num_vf_int; 885 u32 num_vfs; 886 u32 i, j; 887 u32 val; 888 u32 eol = 0x7ff; 889 890 /* get number of interrupts, queues, and vfs */ 891 val = rd32(hw, I40E_GLPCI_CNF2); 892 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 893 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 894 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 895 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 896 897 val = rd32(hw, I40E_PFLAN_QALLOC); 898 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 899 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 900 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 901 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 902 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 903 num_queues = (j - base_queue) + 1; 904 else 905 num_queues = 0; 906 907 val = rd32(hw, I40E_PF_VT_PFALLOC); 908 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 909 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 910 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 911 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 912 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 913 num_vfs = (j - i) + 1; 914 else 915 num_vfs = 0; 916 917 /* stop all the interrupts */ 918 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 919 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 920 for (i = 0; i < num_pf_int - 2; i++) 921 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 922 923 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 924 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 925 wr32(hw, I40E_PFINT_LNKLST0, val); 926 for (i = 0; i < num_pf_int - 2; i++) 927 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 928 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 929 for (i = 0; i < num_vfs; i++) 930 wr32(hw, I40E_VPINT_LNKLST0(i), val); 931 for (i = 0; i < num_vf_int - 2; i++) 932 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 933 934 /* warn the HW of the coming Tx disables */ 935 for (i = 0; i < num_queues; i++) { 936 u32 abs_queue_idx = base_queue + i; 937 u32 reg_block = 0; 938 939 if (abs_queue_idx >= 128) { 940 reg_block = abs_queue_idx / 128; 941 abs_queue_idx %= 128; 942 } 943 944 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 945 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 946 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 947 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 948 949 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 950 } 951 udelay(400); 952 953 /* stop all the queues */ 954 for (i = 0; i < num_queues; i++) { 955 wr32(hw, I40E_QINT_TQCTL(i), 0); 956 wr32(hw, I40E_QTX_ENA(i), 0); 957 wr32(hw, I40E_QINT_RQCTL(i), 0); 958 wr32(hw, I40E_QRX_ENA(i), 0); 959 } 960 961 /* short wait for all queue disables to settle */ 962 udelay(50); 963} 964 965/** 966 * i40e_clear_pxe_mode - clear pxe operations mode 967 * @hw: pointer to the hw struct 968 * 969 * Make sure all PXE mode settings are cleared, including things 970 * like descriptor fetch/write-back mode. 971 **/ 972void i40e_clear_pxe_mode(struct i40e_hw *hw) 973{ 974 u32 reg; 975 976 if (i40e_check_asq_alive(hw)) 977 i40e_aq_clear_pxe_mode(hw, NULL); 978 979 /* Clear single descriptor fetch/write-back mode */ 980 reg = rd32(hw, I40E_GLLAN_RCTL_0); 981 982 if (hw->revision_id == 0) { 983 /* As a work around clear PXE_MODE instead of setting it */ 984 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); 985 } else { 986 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); 987 } 988} 989 990/** 991 * i40e_led_is_mine - helper to find matching led 992 * @hw: pointer to the hw struct 993 * @idx: index into GPIO registers 994 * 995 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 996 */ 997static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 998{ 999 u32 gpio_val = 0; 1000 u32 port; 1001 1002 if (!hw->func_caps.led[idx]) 1003 return 0; 1004 1005 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1006 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1007 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1008 1009 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1010 * if it is not our port then ignore 1011 */ 1012 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1013 (port != hw->port)) 1014 return 0; 1015 1016 return gpio_val; 1017} 1018 1019#define I40E_LED0 22 1020#define I40E_LINK_ACTIVITY 0xC 1021 1022/** 1023 * i40e_led_get - return current on/off mode 1024 * @hw: pointer to the hw struct 1025 * 1026 * The value returned is the 'mode' field as defined in the 1027 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1028 * values are variations of possible behaviors relating to 1029 * blink, link, and wire. 1030 **/ 1031u32 i40e_led_get(struct i40e_hw *hw) 1032{ 1033 u32 mode = 0; 1034 int i; 1035 1036 /* as per the documentation GPIO 22-29 are the LED 1037 * GPIO pins named LED0..LED7 1038 */ 1039 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1040 u32 gpio_val = i40e_led_is_mine(hw, i); 1041 1042 if (!gpio_val) 1043 continue; 1044 1045 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1046 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1047 break; 1048 } 1049 1050 return mode; 1051} 1052 1053/** 1054 * i40e_led_set - set new on/off mode 1055 * @hw: pointer to the hw struct 1056 * @mode: 0=off, 0xf=on (else see manual for mode details) 1057 * @blink: true if the LED should blink when on, false if steady 1058 * 1059 * if this function is used to turn on the blink it should 1060 * be used to disable the blink when restoring the original state. 1061 **/ 1062void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1063{ 1064 int i; 1065 1066 if (mode & 0xfffffff0) 1067 hw_dbg(hw, "invalid mode passed in %X\n", mode); 1068 1069 /* as per the documentation GPIO 22-29 are the LED 1070 * GPIO pins named LED0..LED7 1071 */ 1072 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1073 u32 gpio_val = i40e_led_is_mine(hw, i); 1074 1075 if (!gpio_val) 1076 continue; 1077 1078 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1079 /* this & is a bit of paranoia, but serves as a range check */ 1080 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1081 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1082 1083 if (mode == I40E_LINK_ACTIVITY) 1084 blink = false; 1085 1086 gpio_val |= (blink ? 1 : 0) << 1087 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT; 1088 1089 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1090 break; 1091 } 1092} 1093 1094/* Admin command wrappers */ 1095 1096/** 1097 * i40e_aq_get_phy_capabilities 1098 * @hw: pointer to the hw struct 1099 * @abilities: structure for PHY capabilities to be filled 1100 * @qualified_modules: report Qualified Modules 1101 * @report_init: report init capabilities (active are default) 1102 * @cmd_details: pointer to command details structure or NULL 1103 * 1104 * Returns the various PHY abilities supported on the Port. 1105 **/ 1106i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1107 bool qualified_modules, bool report_init, 1108 struct i40e_aq_get_phy_abilities_resp *abilities, 1109 struct i40e_asq_cmd_details *cmd_details) 1110{ 1111 struct i40e_aq_desc desc; 1112 i40e_status status; 1113 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1114 1115 if (!abilities) 1116 return I40E_ERR_PARAM; 1117 1118 i40e_fill_default_direct_cmd_desc(&desc, 1119 i40e_aqc_opc_get_phy_abilities); 1120 1121 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1122 if (abilities_size > I40E_AQ_LARGE_BUF) 1123 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1124 1125 if (qualified_modules) 1126 desc.params.external.param0 |= 1127 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1128 1129 if (report_init) 1130 desc.params.external.param0 |= 1131 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1132 1133 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1134 cmd_details); 1135 1136 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1137 status = I40E_ERR_UNKNOWN_PHY; 1138 1139 return status; 1140} 1141 1142/** 1143 * i40e_aq_set_phy_config 1144 * @hw: pointer to the hw struct 1145 * @config: structure with PHY configuration to be set 1146 * @cmd_details: pointer to command details structure or NULL 1147 * 1148 * Set the various PHY configuration parameters 1149 * supported on the Port.One or more of the Set PHY config parameters may be 1150 * ignored in an MFP mode as the PF may not have the privilege to set some 1151 * of the PHY Config parameters. This status will be indicated by the 1152 * command response. 1153 **/ 1154enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1155 struct i40e_aq_set_phy_config *config, 1156 struct i40e_asq_cmd_details *cmd_details) 1157{ 1158 struct i40e_aq_desc desc; 1159 struct i40e_aq_set_phy_config *cmd = 1160 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1161 enum i40e_status_code status; 1162 1163 if (!config) 1164 return I40E_ERR_PARAM; 1165 1166 i40e_fill_default_direct_cmd_desc(&desc, 1167 i40e_aqc_opc_set_phy_config); 1168 1169 *cmd = *config; 1170 1171 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1172 1173 return status; 1174} 1175 1176/** 1177 * i40e_set_fc 1178 * @hw: pointer to the hw struct 1179 * 1180 * Set the requested flow control mode using set_phy_config. 1181 **/ 1182enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1183 bool atomic_restart) 1184{ 1185 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1186 struct i40e_aq_get_phy_abilities_resp abilities; 1187 struct i40e_aq_set_phy_config config; 1188 enum i40e_status_code status; 1189 u8 pause_mask = 0x0; 1190 1191 *aq_failures = 0x0; 1192 1193 switch (fc_mode) { 1194 case I40E_FC_FULL: 1195 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1196 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1197 break; 1198 case I40E_FC_RX_PAUSE: 1199 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1200 break; 1201 case I40E_FC_TX_PAUSE: 1202 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 /* Get the current phy config */ 1209 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, 1210 NULL); 1211 if (status) { 1212 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1213 return status; 1214 } 1215 1216 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config)); 1217 /* clear the old pause settings */ 1218 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1219 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1220 /* set the new abilities */ 1221 config.abilities |= pause_mask; 1222 /* If the abilities have changed, then set the new config */ 1223 if (config.abilities != abilities.abilities) { 1224 /* Auto restart link so settings take effect */ 1225 if (atomic_restart) 1226 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1227 /* Copy over all the old settings */ 1228 config.phy_type = abilities.phy_type; 1229 config.link_speed = abilities.link_speed; 1230 config.eee_capability = abilities.eee_capability; 1231 config.eeer = abilities.eeer_val; 1232 config.low_power_ctrl = abilities.d3_lpan; 1233 status = i40e_aq_set_phy_config(hw, &config, NULL); 1234 1235 if (status) 1236 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1237 } 1238 /* Update the link info */ 1239 status = i40e_update_link_info(hw, true); 1240 if (status) { 1241 /* Wait a little bit (on 40G cards it sometimes takes a really 1242 * long time for link to come back from the atomic reset) 1243 * and try once more 1244 */ 1245 msleep(1000); 1246 status = i40e_update_link_info(hw, true); 1247 } 1248 if (status) 1249 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1250 1251 return status; 1252} 1253 1254/** 1255 * i40e_aq_clear_pxe_mode 1256 * @hw: pointer to the hw struct 1257 * @cmd_details: pointer to command details structure or NULL 1258 * 1259 * Tell the firmware that the driver is taking over from PXE 1260 **/ 1261i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1262 struct i40e_asq_cmd_details *cmd_details) 1263{ 1264 i40e_status status; 1265 struct i40e_aq_desc desc; 1266 struct i40e_aqc_clear_pxe *cmd = 1267 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1268 1269 i40e_fill_default_direct_cmd_desc(&desc, 1270 i40e_aqc_opc_clear_pxe_mode); 1271 1272 cmd->rx_cnt = 0x2; 1273 1274 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1275 1276 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1277 1278 return status; 1279} 1280 1281/** 1282 * i40e_aq_set_link_restart_an 1283 * @hw: pointer to the hw struct 1284 * @enable_link: if true: enable link, if false: disable link 1285 * @cmd_details: pointer to command details structure or NULL 1286 * 1287 * Sets up the link and restarts the Auto-Negotiation over the link. 1288 **/ 1289i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1290 bool enable_link, 1291 struct i40e_asq_cmd_details *cmd_details) 1292{ 1293 struct i40e_aq_desc desc; 1294 struct i40e_aqc_set_link_restart_an *cmd = 1295 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1296 i40e_status status; 1297 1298 i40e_fill_default_direct_cmd_desc(&desc, 1299 i40e_aqc_opc_set_link_restart_an); 1300 1301 cmd->command = I40E_AQ_PHY_RESTART_AN; 1302 if (enable_link) 1303 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1304 else 1305 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1306 1307 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1308 1309 return status; 1310} 1311 1312/** 1313 * i40e_aq_get_link_info 1314 * @hw: pointer to the hw struct 1315 * @enable_lse: enable/disable LinkStatusEvent reporting 1316 * @link: pointer to link status structure - optional 1317 * @cmd_details: pointer to command details structure or NULL 1318 * 1319 * Returns the link status of the adapter. 1320 **/ 1321i40e_status i40e_aq_get_link_info(struct i40e_hw *hw, 1322 bool enable_lse, struct i40e_link_status *link, 1323 struct i40e_asq_cmd_details *cmd_details) 1324{ 1325 struct i40e_aq_desc desc; 1326 struct i40e_aqc_get_link_status *resp = 1327 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1328 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1329 i40e_status status; 1330 bool tx_pause, rx_pause; 1331 u16 command_flags; 1332 1333 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1334 1335 if (enable_lse) 1336 command_flags = I40E_AQ_LSE_ENABLE; 1337 else 1338 command_flags = I40E_AQ_LSE_DISABLE; 1339 resp->command_flags = cpu_to_le16(command_flags); 1340 1341 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1342 1343 if (status) 1344 goto aq_get_link_info_exit; 1345 1346 /* save off old link status information */ 1347 hw->phy.link_info_old = *hw_link_info; 1348 1349 /* update link status */ 1350 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1351 hw->phy.media_type = i40e_get_media_type(hw); 1352 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1353 hw_link_info->link_info = resp->link_info; 1354 hw_link_info->an_info = resp->an_info; 1355 hw_link_info->ext_info = resp->ext_info; 1356 hw_link_info->loopback = resp->loopback; 1357 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size); 1358 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1359 1360 /* update fc info */ 1361 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1362 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1363 if (tx_pause & rx_pause) 1364 hw->fc.current_mode = I40E_FC_FULL; 1365 else if (tx_pause) 1366 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1367 else if (rx_pause) 1368 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1369 else 1370 hw->fc.current_mode = I40E_FC_NONE; 1371 1372 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1373 hw_link_info->crc_enable = true; 1374 else 1375 hw_link_info->crc_enable = false; 1376 1377 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE)) 1378 hw_link_info->lse_enable = true; 1379 else 1380 hw_link_info->lse_enable = false; 1381 1382 /* save link status information */ 1383 if (link) 1384 *link = *hw_link_info; 1385 1386 /* flag cleared so helper functions don't call AQ again */ 1387 hw->phy.get_link_info = false; 1388 1389aq_get_link_info_exit: 1390 return status; 1391} 1392 1393/** 1394 * i40e_update_link_info 1395 * @hw: pointer to the hw struct 1396 * @enable_lse: enable/disable LinkStatusEvent reporting 1397 * 1398 * Returns the link status of the adapter 1399 **/ 1400i40e_status i40e_update_link_info(struct i40e_hw *hw, bool enable_lse) 1401{ 1402 struct i40e_aq_get_phy_abilities_resp abilities; 1403 i40e_status status; 1404 1405 status = i40e_aq_get_link_info(hw, enable_lse, NULL, NULL); 1406 if (status) 1407 return status; 1408 1409 status = i40e_aq_get_phy_capabilities(hw, false, false, 1410 &abilities, NULL); 1411 if (status) 1412 return status; 1413 1414 if (abilities.abilities & I40E_AQ_PHY_AN_ENABLED) 1415 hw->phy.link_info.an_enabled = true; 1416 else 1417 hw->phy.link_info.an_enabled = false; 1418 1419 return status; 1420} 1421 1422/** 1423 * i40e_aq_add_vsi 1424 * @hw: pointer to the hw struct 1425 * @vsi_ctx: pointer to a vsi context struct 1426 * @cmd_details: pointer to command details structure or NULL 1427 * 1428 * Add a VSI context to the hardware. 1429**/ 1430i40e_status i40e_aq_add_vsi(struct i40e_hw *hw, 1431 struct i40e_vsi_context *vsi_ctx, 1432 struct i40e_asq_cmd_details *cmd_details) 1433{ 1434 struct i40e_aq_desc desc; 1435 struct i40e_aqc_add_get_update_vsi *cmd = 1436 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1437 struct i40e_aqc_add_get_update_vsi_completion *resp = 1438 (struct i40e_aqc_add_get_update_vsi_completion *) 1439 &desc.params.raw; 1440 i40e_status status; 1441 1442 i40e_fill_default_direct_cmd_desc(&desc, 1443 i40e_aqc_opc_add_vsi); 1444 1445 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid); 1446 cmd->connection_type = vsi_ctx->connection_type; 1447 cmd->vf_id = vsi_ctx->vf_num; 1448 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags); 1449 1450 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1451 1452 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1453 sizeof(vsi_ctx->info), cmd_details); 1454 1455 if (status) 1456 goto aq_add_vsi_exit; 1457 1458 vsi_ctx->seid = le16_to_cpu(resp->seid); 1459 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1460 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1461 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1462 1463aq_add_vsi_exit: 1464 return status; 1465} 1466 1467/** 1468 * i40e_aq_set_vsi_unicast_promiscuous 1469 * @hw: pointer to the hw struct 1470 * @seid: vsi number 1471 * @set: set unicast promiscuous enable/disable 1472 * @cmd_details: pointer to command details structure or NULL 1473 **/ 1474i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 1475 u16 seid, bool set, 1476 struct i40e_asq_cmd_details *cmd_details) 1477{ 1478 struct i40e_aq_desc desc; 1479 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1480 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1481 i40e_status status; 1482 u16 flags = 0; 1483 1484 i40e_fill_default_direct_cmd_desc(&desc, 1485 i40e_aqc_opc_set_vsi_promiscuous_modes); 1486 1487 if (set) 1488 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 1489 1490 cmd->promiscuous_flags = cpu_to_le16(flags); 1491 1492 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 1493 1494 cmd->seid = cpu_to_le16(seid); 1495 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1496 1497 return status; 1498} 1499 1500/** 1501 * i40e_aq_set_vsi_multicast_promiscuous 1502 * @hw: pointer to the hw struct 1503 * @seid: vsi number 1504 * @set: set multicast promiscuous enable/disable 1505 * @cmd_details: pointer to command details structure or NULL 1506 **/ 1507i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 1508 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 1509{ 1510 struct i40e_aq_desc desc; 1511 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1512 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1513 i40e_status status; 1514 u16 flags = 0; 1515 1516 i40e_fill_default_direct_cmd_desc(&desc, 1517 i40e_aqc_opc_set_vsi_promiscuous_modes); 1518 1519 if (set) 1520 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 1521 1522 cmd->promiscuous_flags = cpu_to_le16(flags); 1523 1524 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 1525 1526 cmd->seid = cpu_to_le16(seid); 1527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1528 1529 return status; 1530} 1531 1532/** 1533 * i40e_aq_set_vsi_broadcast 1534 * @hw: pointer to the hw struct 1535 * @seid: vsi number 1536 * @set_filter: true to set filter, false to clear filter 1537 * @cmd_details: pointer to command details structure or NULL 1538 * 1539 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 1540 **/ 1541i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 1542 u16 seid, bool set_filter, 1543 struct i40e_asq_cmd_details *cmd_details) 1544{ 1545 struct i40e_aq_desc desc; 1546 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 1547 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 1548 i40e_status status; 1549 1550 i40e_fill_default_direct_cmd_desc(&desc, 1551 i40e_aqc_opc_set_vsi_promiscuous_modes); 1552 1553 if (set_filter) 1554 cmd->promiscuous_flags 1555 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1556 else 1557 cmd->promiscuous_flags 1558 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1559 1560 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 1561 cmd->seid = cpu_to_le16(seid); 1562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1563 1564 return status; 1565} 1566 1567/** 1568 * i40e_get_vsi_params - get VSI configuration info 1569 * @hw: pointer to the hw struct 1570 * @vsi_ctx: pointer to a vsi context struct 1571 * @cmd_details: pointer to command details structure or NULL 1572 **/ 1573i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw, 1574 struct i40e_vsi_context *vsi_ctx, 1575 struct i40e_asq_cmd_details *cmd_details) 1576{ 1577 struct i40e_aq_desc desc; 1578 struct i40e_aqc_add_get_update_vsi *cmd = 1579 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1580 struct i40e_aqc_add_get_update_vsi_completion *resp = 1581 (struct i40e_aqc_add_get_update_vsi_completion *) 1582 &desc.params.raw; 1583 i40e_status status; 1584 1585 i40e_fill_default_direct_cmd_desc(&desc, 1586 i40e_aqc_opc_get_vsi_parameters); 1587 1588 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1589 1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1591 1592 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1593 sizeof(vsi_ctx->info), NULL); 1594 1595 if (status) 1596 goto aq_get_vsi_params_exit; 1597 1598 vsi_ctx->seid = le16_to_cpu(resp->seid); 1599 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number); 1600 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used); 1601 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free); 1602 1603aq_get_vsi_params_exit: 1604 return status; 1605} 1606 1607/** 1608 * i40e_aq_update_vsi_params 1609 * @hw: pointer to the hw struct 1610 * @vsi_ctx: pointer to a vsi context struct 1611 * @cmd_details: pointer to command details structure or NULL 1612 * 1613 * Update a VSI context. 1614 **/ 1615i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw, 1616 struct i40e_vsi_context *vsi_ctx, 1617 struct i40e_asq_cmd_details *cmd_details) 1618{ 1619 struct i40e_aq_desc desc; 1620 struct i40e_aqc_add_get_update_vsi *cmd = 1621 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 1622 i40e_status status; 1623 1624 i40e_fill_default_direct_cmd_desc(&desc, 1625 i40e_aqc_opc_update_vsi_parameters); 1626 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid); 1627 1628 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1629 1630 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 1631 sizeof(vsi_ctx->info), cmd_details); 1632 1633 return status; 1634} 1635 1636/** 1637 * i40e_aq_get_switch_config 1638 * @hw: pointer to the hardware structure 1639 * @buf: pointer to the result buffer 1640 * @buf_size: length of input buffer 1641 * @start_seid: seid to start for the report, 0 == beginning 1642 * @cmd_details: pointer to command details structure or NULL 1643 * 1644 * Fill the buf with switch configuration returned from AdminQ command 1645 **/ 1646i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 1647 struct i40e_aqc_get_switch_config_resp *buf, 1648 u16 buf_size, u16 *start_seid, 1649 struct i40e_asq_cmd_details *cmd_details) 1650{ 1651 struct i40e_aq_desc desc; 1652 struct i40e_aqc_switch_seid *scfg = 1653 (struct i40e_aqc_switch_seid *)&desc.params.raw; 1654 i40e_status status; 1655 1656 i40e_fill_default_direct_cmd_desc(&desc, 1657 i40e_aqc_opc_get_switch_config); 1658 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 1659 if (buf_size > I40E_AQ_LARGE_BUF) 1660 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1661 scfg->seid = cpu_to_le16(*start_seid); 1662 1663 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 1664 *start_seid = le16_to_cpu(scfg->seid); 1665 1666 return status; 1667} 1668 1669/** 1670 * i40e_aq_get_firmware_version 1671 * @hw: pointer to the hw struct 1672 * @fw_major_version: firmware major version 1673 * @fw_minor_version: firmware minor version 1674 * @api_major_version: major queue version 1675 * @api_minor_version: minor queue version 1676 * @cmd_details: pointer to command details structure or NULL 1677 * 1678 * Get the firmware version from the admin queue commands 1679 **/ 1680i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, 1681 u16 *fw_major_version, u16 *fw_minor_version, 1682 u16 *api_major_version, u16 *api_minor_version, 1683 struct i40e_asq_cmd_details *cmd_details) 1684{ 1685 struct i40e_aq_desc desc; 1686 struct i40e_aqc_get_version *resp = 1687 (struct i40e_aqc_get_version *)&desc.params.raw; 1688 i40e_status status; 1689 1690 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 1691 1692 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1693 1694 if (!status) { 1695 if (fw_major_version != NULL) 1696 *fw_major_version = le16_to_cpu(resp->fw_major); 1697 if (fw_minor_version != NULL) 1698 *fw_minor_version = le16_to_cpu(resp->fw_minor); 1699 if (api_major_version != NULL) 1700 *api_major_version = le16_to_cpu(resp->api_major); 1701 if (api_minor_version != NULL) 1702 *api_minor_version = le16_to_cpu(resp->api_minor); 1703 } 1704 1705 return status; 1706} 1707 1708/** 1709 * i40e_aq_send_driver_version 1710 * @hw: pointer to the hw struct 1711 * @dv: driver's major, minor version 1712 * @cmd_details: pointer to command details structure or NULL 1713 * 1714 * Send the driver version to the firmware 1715 **/ 1716i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw, 1717 struct i40e_driver_version *dv, 1718 struct i40e_asq_cmd_details *cmd_details) 1719{ 1720 struct i40e_aq_desc desc; 1721 struct i40e_aqc_driver_version *cmd = 1722 (struct i40e_aqc_driver_version *)&desc.params.raw; 1723 i40e_status status; 1724 u16 len; 1725 1726 if (dv == NULL) 1727 return I40E_ERR_PARAM; 1728 1729 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 1730 1731 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI); 1732 cmd->driver_major_ver = dv->major_version; 1733 cmd->driver_minor_ver = dv->minor_version; 1734 cmd->driver_build_ver = dv->build_version; 1735 cmd->driver_subbuild_ver = dv->subbuild_version; 1736 1737 len = 0; 1738 while (len < sizeof(dv->driver_string) && 1739 (dv->driver_string[len] < 0x80) && 1740 dv->driver_string[len]) 1741 len++; 1742 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 1743 len, cmd_details); 1744 1745 return status; 1746} 1747 1748/** 1749 * i40e_get_link_status - get status of the HW network link 1750 * @hw: pointer to the hw struct 1751 * 1752 * Returns true if link is up, false if link is down. 1753 * 1754 * Side effect: LinkStatusEvent reporting becomes enabled 1755 **/ 1756bool i40e_get_link_status(struct i40e_hw *hw) 1757{ 1758 i40e_status status = 0; 1759 bool link_status = false; 1760 1761 if (hw->phy.get_link_info) { 1762 status = i40e_aq_get_link_info(hw, true, NULL, NULL); 1763 1764 if (status) 1765 goto i40e_get_link_status_exit; 1766 } 1767 1768 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 1769 1770i40e_get_link_status_exit: 1771 return link_status; 1772} 1773 1774/** 1775 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 1776 * @hw: pointer to the hw struct 1777 * @uplink_seid: the MAC or other gizmo SEID 1778 * @downlink_seid: the VSI SEID 1779 * @enabled_tc: bitmap of TCs to be enabled 1780 * @default_port: true for default port VSI, false for control port 1781 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support 1782 * @veb_seid: pointer to where to put the resulting VEB SEID 1783 * @cmd_details: pointer to command details structure or NULL 1784 * 1785 * This asks the FW to add a VEB between the uplink and downlink 1786 * elements. If the uplink SEID is 0, this will be a floating VEB. 1787 **/ 1788i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 1789 u16 downlink_seid, u8 enabled_tc, 1790 bool default_port, bool enable_l2_filtering, 1791 u16 *veb_seid, 1792 struct i40e_asq_cmd_details *cmd_details) 1793{ 1794 struct i40e_aq_desc desc; 1795 struct i40e_aqc_add_veb *cmd = 1796 (struct i40e_aqc_add_veb *)&desc.params.raw; 1797 struct i40e_aqc_add_veb_completion *resp = 1798 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 1799 i40e_status status; 1800 u16 veb_flags = 0; 1801 1802 /* SEIDs need to either both be set or both be 0 for floating VEB */ 1803 if (!!uplink_seid != !!downlink_seid) 1804 return I40E_ERR_PARAM; 1805 1806 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 1807 1808 cmd->uplink_seid = cpu_to_le16(uplink_seid); 1809 cmd->downlink_seid = cpu_to_le16(downlink_seid); 1810 cmd->enable_tcs = enabled_tc; 1811 if (!uplink_seid) 1812 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 1813 if (default_port) 1814 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 1815 else 1816 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 1817 1818 if (enable_l2_filtering) 1819 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER; 1820 1821 cmd->veb_flags = cpu_to_le16(veb_flags); 1822 1823 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1824 1825 if (!status && veb_seid) 1826 *veb_seid = le16_to_cpu(resp->veb_seid); 1827 1828 return status; 1829} 1830 1831/** 1832 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 1833 * @hw: pointer to the hw struct 1834 * @veb_seid: the SEID of the VEB to query 1835 * @switch_id: the uplink switch id 1836 * @floating: set to true if the VEB is floating 1837 * @statistic_index: index of the stats counter block for this VEB 1838 * @vebs_used: number of VEB's used by function 1839 * @vebs_free: total VEB's not reserved by any function 1840 * @cmd_details: pointer to command details structure or NULL 1841 * 1842 * This retrieves the parameters for a particular VEB, specified by 1843 * uplink_seid, and returns them to the caller. 1844 **/ 1845i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw, 1846 u16 veb_seid, u16 *switch_id, 1847 bool *floating, u16 *statistic_index, 1848 u16 *vebs_used, u16 *vebs_free, 1849 struct i40e_asq_cmd_details *cmd_details) 1850{ 1851 struct i40e_aq_desc desc; 1852 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 1853 (struct i40e_aqc_get_veb_parameters_completion *) 1854 &desc.params.raw; 1855 i40e_status status; 1856 1857 if (veb_seid == 0) 1858 return I40E_ERR_PARAM; 1859 1860 i40e_fill_default_direct_cmd_desc(&desc, 1861 i40e_aqc_opc_get_veb_parameters); 1862 cmd_resp->seid = cpu_to_le16(veb_seid); 1863 1864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1865 if (status) 1866 goto get_veb_exit; 1867 1868 if (switch_id) 1869 *switch_id = le16_to_cpu(cmd_resp->switch_id); 1870 if (statistic_index) 1871 *statistic_index = le16_to_cpu(cmd_resp->statistic_index); 1872 if (vebs_used) 1873 *vebs_used = le16_to_cpu(cmd_resp->vebs_used); 1874 if (vebs_free) 1875 *vebs_free = le16_to_cpu(cmd_resp->vebs_free); 1876 if (floating) { 1877 u16 flags = le16_to_cpu(cmd_resp->veb_flags); 1878 if (flags & I40E_AQC_ADD_VEB_FLOATING) 1879 *floating = true; 1880 else 1881 *floating = false; 1882 } 1883 1884get_veb_exit: 1885 return status; 1886} 1887 1888/** 1889 * i40e_aq_add_macvlan 1890 * @hw: pointer to the hw struct 1891 * @seid: VSI for the mac address 1892 * @mv_list: list of macvlans to be added 1893 * @count: length of the list 1894 * @cmd_details: pointer to command details structure or NULL 1895 * 1896 * Add MAC/VLAN addresses to the HW filtering 1897 **/ 1898i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 1899 struct i40e_aqc_add_macvlan_element_data *mv_list, 1900 u16 count, struct i40e_asq_cmd_details *cmd_details) 1901{ 1902 struct i40e_aq_desc desc; 1903 struct i40e_aqc_macvlan *cmd = 1904 (struct i40e_aqc_macvlan *)&desc.params.raw; 1905 i40e_status status; 1906 u16 buf_size; 1907 1908 if (count == 0 || !mv_list || !hw) 1909 return I40E_ERR_PARAM; 1910 1911 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data); 1912 1913 /* prep the rest of the request */ 1914 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 1915 cmd->num_addresses = cpu_to_le16(count); 1916 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 1917 cmd->seid[1] = 0; 1918 cmd->seid[2] = 0; 1919 1920 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1921 if (buf_size > I40E_AQ_LARGE_BUF) 1922 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1923 1924 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 1925 cmd_details); 1926 1927 return status; 1928} 1929 1930/** 1931 * i40e_aq_remove_macvlan 1932 * @hw: pointer to the hw struct 1933 * @seid: VSI for the mac address 1934 * @mv_list: list of macvlans to be removed 1935 * @count: length of the list 1936 * @cmd_details: pointer to command details structure or NULL 1937 * 1938 * Remove MAC/VLAN addresses from the HW filtering 1939 **/ 1940i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 1941 struct i40e_aqc_remove_macvlan_element_data *mv_list, 1942 u16 count, struct i40e_asq_cmd_details *cmd_details) 1943{ 1944 struct i40e_aq_desc desc; 1945 struct i40e_aqc_macvlan *cmd = 1946 (struct i40e_aqc_macvlan *)&desc.params.raw; 1947 i40e_status status; 1948 u16 buf_size; 1949 1950 if (count == 0 || !mv_list || !hw) 1951 return I40E_ERR_PARAM; 1952 1953 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data); 1954 1955 /* prep the rest of the request */ 1956 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 1957 cmd->num_addresses = cpu_to_le16(count); 1958 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 1959 cmd->seid[1] = 0; 1960 cmd->seid[2] = 0; 1961 1962 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 1963 if (buf_size > I40E_AQ_LARGE_BUF) 1964 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 1965 1966 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 1967 cmd_details); 1968 1969 return status; 1970} 1971 1972/** 1973 * i40e_aq_send_msg_to_vf 1974 * @hw: pointer to the hardware structure 1975 * @vfid: vf id to send msg 1976 * @v_opcode: opcodes for VF-PF communication 1977 * @v_retval: return error code 1978 * @msg: pointer to the msg buffer 1979 * @msglen: msg length 1980 * @cmd_details: pointer to command details 1981 * 1982 * send msg to vf 1983 **/ 1984i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 1985 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 1986 struct i40e_asq_cmd_details *cmd_details) 1987{ 1988 struct i40e_aq_desc desc; 1989 struct i40e_aqc_pf_vf_message *cmd = 1990 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 1991 i40e_status status; 1992 1993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 1994 cmd->id = cpu_to_le32(vfid); 1995 desc.cookie_high = cpu_to_le32(v_opcode); 1996 desc.cookie_low = cpu_to_le32(v_retval); 1997 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI); 1998 if (msglen) { 1999 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | 2000 I40E_AQ_FLAG_RD)); 2001 if (msglen > I40E_AQ_LARGE_BUF) 2002 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2003 desc.datalen = cpu_to_le16(msglen); 2004 } 2005 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 2006 2007 return status; 2008} 2009 2010/** 2011 * i40e_aq_debug_write_register 2012 * @hw: pointer to the hw struct 2013 * @reg_addr: register address 2014 * @reg_val: register value 2015 * @cmd_details: pointer to command details structure or NULL 2016 * 2017 * Write to a register using the admin queue commands 2018 **/ 2019i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, 2020 u32 reg_addr, u64 reg_val, 2021 struct i40e_asq_cmd_details *cmd_details) 2022{ 2023 struct i40e_aq_desc desc; 2024 struct i40e_aqc_debug_reg_read_write *cmd = 2025 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 2026 i40e_status status; 2027 2028 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 2029 2030 cmd->address = cpu_to_le32(reg_addr); 2031 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); 2032 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); 2033 2034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2035 2036 return status; 2037} 2038 2039/** 2040 * i40e_aq_set_hmc_resource_profile 2041 * @hw: pointer to the hw struct 2042 * @profile: type of profile the HMC is to be set as 2043 * @pe_vf_enabled_count: the number of PE enabled VFs the system has 2044 * @cmd_details: pointer to command details structure or NULL 2045 * 2046 * set the HMC profile of the device. 2047 **/ 2048i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw, 2049 enum i40e_aq_hmc_profile profile, 2050 u8 pe_vf_enabled_count, 2051 struct i40e_asq_cmd_details *cmd_details) 2052{ 2053 struct i40e_aq_desc desc; 2054 struct i40e_aq_get_set_hmc_resource_profile *cmd = 2055 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw; 2056 i40e_status status; 2057 2058 i40e_fill_default_direct_cmd_desc(&desc, 2059 i40e_aqc_opc_set_hmc_resource_profile); 2060 2061 cmd->pm_profile = (u8)profile; 2062 cmd->pe_vf_enabled = pe_vf_enabled_count; 2063 2064 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2065 2066 return status; 2067} 2068 2069/** 2070 * i40e_aq_request_resource 2071 * @hw: pointer to the hw struct 2072 * @resource: resource id 2073 * @access: access type 2074 * @sdp_number: resource number 2075 * @timeout: the maximum time in ms that the driver may hold the resource 2076 * @cmd_details: pointer to command details structure or NULL 2077 * 2078 * requests common resource using the admin queue commands 2079 **/ 2080i40e_status i40e_aq_request_resource(struct i40e_hw *hw, 2081 enum i40e_aq_resources_ids resource, 2082 enum i40e_aq_resource_access_type access, 2083 u8 sdp_number, u64 *timeout, 2084 struct i40e_asq_cmd_details *cmd_details) 2085{ 2086 struct i40e_aq_desc desc; 2087 struct i40e_aqc_request_resource *cmd_resp = 2088 (struct i40e_aqc_request_resource *)&desc.params.raw; 2089 i40e_status status; 2090 2091 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 2092 2093 cmd_resp->resource_id = cpu_to_le16(resource); 2094 cmd_resp->access_type = cpu_to_le16(access); 2095 cmd_resp->resource_number = cpu_to_le32(sdp_number); 2096 2097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2098 /* The completion specifies the maximum time in ms that the driver 2099 * may hold the resource in the Timeout field. 2100 * If the resource is held by someone else, the command completes with 2101 * busy return value and the timeout field indicates the maximum time 2102 * the current owner of the resource has to free it. 2103 */ 2104 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 2105 *timeout = le32_to_cpu(cmd_resp->timeout); 2106 2107 return status; 2108} 2109 2110/** 2111 * i40e_aq_release_resource 2112 * @hw: pointer to the hw struct 2113 * @resource: resource id 2114 * @sdp_number: resource number 2115 * @cmd_details: pointer to command details structure or NULL 2116 * 2117 * release common resource using the admin queue commands 2118 **/ 2119i40e_status i40e_aq_release_resource(struct i40e_hw *hw, 2120 enum i40e_aq_resources_ids resource, 2121 u8 sdp_number, 2122 struct i40e_asq_cmd_details *cmd_details) 2123{ 2124 struct i40e_aq_desc desc; 2125 struct i40e_aqc_request_resource *cmd = 2126 (struct i40e_aqc_request_resource *)&desc.params.raw; 2127 i40e_status status; 2128 2129 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 2130 2131 cmd->resource_id = cpu_to_le16(resource); 2132 cmd->resource_number = cpu_to_le32(sdp_number); 2133 2134 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2135 2136 return status; 2137} 2138 2139/** 2140 * i40e_aq_read_nvm 2141 * @hw: pointer to the hw struct 2142 * @module_pointer: module pointer location in words from the NVM beginning 2143 * @offset: byte offset from the module beginning 2144 * @length: length of the section to be read (in bytes from the offset) 2145 * @data: command buffer (size [bytes] = length) 2146 * @last_command: tells if this is the last command in a series 2147 * @cmd_details: pointer to command details structure or NULL 2148 * 2149 * Read the NVM using the admin queue commands 2150 **/ 2151i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 2152 u32 offset, u16 length, void *data, 2153 bool last_command, 2154 struct i40e_asq_cmd_details *cmd_details) 2155{ 2156 struct i40e_aq_desc desc; 2157 struct i40e_aqc_nvm_update *cmd = 2158 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2159 i40e_status status; 2160 2161 /* In offset the highest byte must be zeroed. */ 2162 if (offset & 0xFF000000) { 2163 status = I40E_ERR_PARAM; 2164 goto i40e_aq_read_nvm_exit; 2165 } 2166 2167 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 2168 2169 /* If this is the last command in a series, set the proper flag. */ 2170 if (last_command) 2171 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2172 cmd->module_pointer = module_pointer; 2173 cmd->offset = cpu_to_le32(offset); 2174 cmd->length = cpu_to_le16(length); 2175 2176 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2177 if (length > I40E_AQ_LARGE_BUF) 2178 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2179 2180 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2181 2182i40e_aq_read_nvm_exit: 2183 return status; 2184} 2185 2186/** 2187 * i40e_aq_erase_nvm 2188 * @hw: pointer to the hw struct 2189 * @module_pointer: module pointer location in words from the NVM beginning 2190 * @offset: offset in the module (expressed in 4 KB from module's beginning) 2191 * @length: length of the section to be erased (expressed in 4 KB) 2192 * @last_command: tells if this is the last command in a series 2193 * @cmd_details: pointer to command details structure or NULL 2194 * 2195 * Erase the NVM sector using the admin queue commands 2196 **/ 2197i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 2198 u32 offset, u16 length, bool last_command, 2199 struct i40e_asq_cmd_details *cmd_details) 2200{ 2201 struct i40e_aq_desc desc; 2202 struct i40e_aqc_nvm_update *cmd = 2203 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2204 i40e_status status; 2205 2206 /* In offset the highest byte must be zeroed. */ 2207 if (offset & 0xFF000000) { 2208 status = I40E_ERR_PARAM; 2209 goto i40e_aq_erase_nvm_exit; 2210 } 2211 2212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 2213 2214 /* If this is the last command in a series, set the proper flag. */ 2215 if (last_command) 2216 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2217 cmd->module_pointer = module_pointer; 2218 cmd->offset = cpu_to_le32(offset); 2219 cmd->length = cpu_to_le16(length); 2220 2221 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2222 2223i40e_aq_erase_nvm_exit: 2224 return status; 2225} 2226 2227#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01 2228#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02 2229#define I40E_DEV_FUNC_CAP_NPAR 0x03 2230#define I40E_DEV_FUNC_CAP_OS2BMC 0x04 2231#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05 2232#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12 2233#define I40E_DEV_FUNC_CAP_VF 0x13 2234#define I40E_DEV_FUNC_CAP_VMDQ 0x14 2235#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15 2236#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16 2237#define I40E_DEV_FUNC_CAP_VSI 0x17 2238#define I40E_DEV_FUNC_CAP_DCB 0x18 2239#define I40E_DEV_FUNC_CAP_FCOE 0x21 2240#define I40E_DEV_FUNC_CAP_RSS 0x40 2241#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41 2242#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42 2243#define I40E_DEV_FUNC_CAP_MSIX 0x43 2244#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44 2245#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45 2246#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46 2247#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1 2248#define I40E_DEV_FUNC_CAP_CEM 0xF2 2249#define I40E_DEV_FUNC_CAP_IWARP 0x51 2250#define I40E_DEV_FUNC_CAP_LED 0x61 2251#define I40E_DEV_FUNC_CAP_SDP 0x62 2252#define I40E_DEV_FUNC_CAP_MDIO 0x63 2253 2254/** 2255 * i40e_parse_discover_capabilities 2256 * @hw: pointer to the hw struct 2257 * @buff: pointer to a buffer containing device/function capability records 2258 * @cap_count: number of capability records in the list 2259 * @list_type_opc: type of capabilities list to parse 2260 * 2261 * Parse the device/function capabilities list. 2262 **/ 2263static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 2264 u32 cap_count, 2265 enum i40e_admin_queue_opc list_type_opc) 2266{ 2267 struct i40e_aqc_list_capabilities_element_resp *cap; 2268 u32 number, logical_id, phys_id; 2269 struct i40e_hw_capabilities *p; 2270 u32 i = 0; 2271 u16 id; 2272 2273 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 2274 2275 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 2276 p = &hw->dev_caps; 2277 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 2278 p = &hw->func_caps; 2279 else 2280 return; 2281 2282 for (i = 0; i < cap_count; i++, cap++) { 2283 id = le16_to_cpu(cap->id); 2284 number = le32_to_cpu(cap->number); 2285 logical_id = le32_to_cpu(cap->logical_id); 2286 phys_id = le32_to_cpu(cap->phys_id); 2287 2288 switch (id) { 2289 case I40E_DEV_FUNC_CAP_SWITCH_MODE: 2290 p->switch_mode = number; 2291 break; 2292 case I40E_DEV_FUNC_CAP_MGMT_MODE: 2293 p->management_mode = number; 2294 break; 2295 case I40E_DEV_FUNC_CAP_NPAR: 2296 p->npar_enable = number; 2297 break; 2298 case I40E_DEV_FUNC_CAP_OS2BMC: 2299 p->os2bmc = number; 2300 break; 2301 case I40E_DEV_FUNC_CAP_VALID_FUNC: 2302 p->valid_functions = number; 2303 break; 2304 case I40E_DEV_FUNC_CAP_SRIOV_1_1: 2305 if (number == 1) 2306 p->sr_iov_1_1 = true; 2307 break; 2308 case I40E_DEV_FUNC_CAP_VF: 2309 p->num_vfs = number; 2310 p->vf_base_id = logical_id; 2311 break; 2312 case I40E_DEV_FUNC_CAP_VMDQ: 2313 if (number == 1) 2314 p->vmdq = true; 2315 break; 2316 case I40E_DEV_FUNC_CAP_802_1_QBG: 2317 if (number == 1) 2318 p->evb_802_1_qbg = true; 2319 break; 2320 case I40E_DEV_FUNC_CAP_802_1_QBH: 2321 if (number == 1) 2322 p->evb_802_1_qbh = true; 2323 break; 2324 case I40E_DEV_FUNC_CAP_VSI: 2325 p->num_vsis = number; 2326 break; 2327 case I40E_DEV_FUNC_CAP_DCB: 2328 if (number == 1) { 2329 p->dcb = true; 2330 p->enabled_tcmap = logical_id; 2331 p->maxtc = phys_id; 2332 } 2333 break; 2334 case I40E_DEV_FUNC_CAP_FCOE: 2335 if (number == 1) 2336 p->fcoe = true; 2337 break; 2338 case I40E_DEV_FUNC_CAP_RSS: 2339 p->rss = true; 2340 p->rss_table_size = number; 2341 p->rss_table_entry_width = logical_id; 2342 break; 2343 case I40E_DEV_FUNC_CAP_RX_QUEUES: 2344 p->num_rx_qp = number; 2345 p->base_queue = phys_id; 2346 break; 2347 case I40E_DEV_FUNC_CAP_TX_QUEUES: 2348 p->num_tx_qp = number; 2349 p->base_queue = phys_id; 2350 break; 2351 case I40E_DEV_FUNC_CAP_MSIX: 2352 p->num_msix_vectors = number; 2353 break; 2354 case I40E_DEV_FUNC_CAP_MSIX_VF: 2355 p->num_msix_vectors_vf = number; 2356 break; 2357 case I40E_DEV_FUNC_CAP_MFP_MODE_1: 2358 if (number == 1) 2359 p->mfp_mode_1 = true; 2360 break; 2361 case I40E_DEV_FUNC_CAP_CEM: 2362 if (number == 1) 2363 p->mgmt_cem = true; 2364 break; 2365 case I40E_DEV_FUNC_CAP_IWARP: 2366 if (number == 1) 2367 p->iwarp = true; 2368 break; 2369 case I40E_DEV_FUNC_CAP_LED: 2370 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2371 p->led[phys_id] = true; 2372 break; 2373 case I40E_DEV_FUNC_CAP_SDP: 2374 if (phys_id < I40E_HW_CAP_MAX_GPIO) 2375 p->sdp[phys_id] = true; 2376 break; 2377 case I40E_DEV_FUNC_CAP_MDIO: 2378 if (number == 1) { 2379 p->mdio_port_num = phys_id; 2380 p->mdio_port_mode = logical_id; 2381 } 2382 break; 2383 case I40E_DEV_FUNC_CAP_IEEE_1588: 2384 if (number == 1) 2385 p->ieee_1588 = true; 2386 break; 2387 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR: 2388 p->fd = true; 2389 p->fd_filters_guaranteed = number; 2390 p->fd_filters_best_effort = logical_id; 2391 break; 2392 default: 2393 break; 2394 } 2395 } 2396 2397 /* Software override ensuring FCoE is disabled if npar or mfp 2398 * mode because it is not supported in these modes. 2399 */ 2400 if (p->npar_enable || p->mfp_mode_1) 2401 p->fcoe = false; 2402 2403 /* additional HW specific goodies that might 2404 * someday be HW version specific 2405 */ 2406 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 2407} 2408 2409/** 2410 * i40e_aq_discover_capabilities 2411 * @hw: pointer to the hw struct 2412 * @buff: a virtual buffer to hold the capabilities 2413 * @buff_size: Size of the virtual buffer 2414 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 2415 * @list_type_opc: capabilities type to discover - pass in the command opcode 2416 * @cmd_details: pointer to command details structure or NULL 2417 * 2418 * Get the device capabilities descriptions from the firmware 2419 **/ 2420i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw, 2421 void *buff, u16 buff_size, u16 *data_size, 2422 enum i40e_admin_queue_opc list_type_opc, 2423 struct i40e_asq_cmd_details *cmd_details) 2424{ 2425 struct i40e_aqc_list_capabilites *cmd; 2426 struct i40e_aq_desc desc; 2427 i40e_status status = 0; 2428 2429 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 2430 2431 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 2432 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 2433 status = I40E_ERR_PARAM; 2434 goto exit; 2435 } 2436 2437 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 2438 2439 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2440 if (buff_size > I40E_AQ_LARGE_BUF) 2441 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2442 2443 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2444 *data_size = le16_to_cpu(desc.datalen); 2445 2446 if (status) 2447 goto exit; 2448 2449 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count), 2450 list_type_opc); 2451 2452exit: 2453 return status; 2454} 2455 2456/** 2457 * i40e_aq_update_nvm 2458 * @hw: pointer to the hw struct 2459 * @module_pointer: module pointer location in words from the NVM beginning 2460 * @offset: byte offset from the module beginning 2461 * @length: length of the section to be written (in bytes from the offset) 2462 * @data: command buffer (size [bytes] = length) 2463 * @last_command: tells if this is the last command in a series 2464 * @cmd_details: pointer to command details structure or NULL 2465 * 2466 * Update the NVM using the admin queue commands 2467 **/ 2468i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 2469 u32 offset, u16 length, void *data, 2470 bool last_command, 2471 struct i40e_asq_cmd_details *cmd_details) 2472{ 2473 struct i40e_aq_desc desc; 2474 struct i40e_aqc_nvm_update *cmd = 2475 (struct i40e_aqc_nvm_update *)&desc.params.raw; 2476 i40e_status status; 2477 2478 /* In offset the highest byte must be zeroed. */ 2479 if (offset & 0xFF000000) { 2480 status = I40E_ERR_PARAM; 2481 goto i40e_aq_update_nvm_exit; 2482 } 2483 2484 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 2485 2486 /* If this is the last command in a series, set the proper flag. */ 2487 if (last_command) 2488 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 2489 cmd->module_pointer = module_pointer; 2490 cmd->offset = cpu_to_le32(offset); 2491 cmd->length = cpu_to_le16(length); 2492 2493 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2494 if (length > I40E_AQ_LARGE_BUF) 2495 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2496 2497 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 2498 2499i40e_aq_update_nvm_exit: 2500 return status; 2501} 2502 2503/** 2504 * i40e_aq_get_lldp_mib 2505 * @hw: pointer to the hw struct 2506 * @bridge_type: type of bridge requested 2507 * @mib_type: Local, Remote or both Local and Remote MIBs 2508 * @buff: pointer to a user supplied buffer to store the MIB block 2509 * @buff_size: size of the buffer (in bytes) 2510 * @local_len : length of the returned Local LLDP MIB 2511 * @remote_len: length of the returned Remote LLDP MIB 2512 * @cmd_details: pointer to command details structure or NULL 2513 * 2514 * Requests the complete LLDP MIB (entire packet). 2515 **/ 2516i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 2517 u8 mib_type, void *buff, u16 buff_size, 2518 u16 *local_len, u16 *remote_len, 2519 struct i40e_asq_cmd_details *cmd_details) 2520{ 2521 struct i40e_aq_desc desc; 2522 struct i40e_aqc_lldp_get_mib *cmd = 2523 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2524 struct i40e_aqc_lldp_get_mib *resp = 2525 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 2526 i40e_status status; 2527 2528 if (buff_size == 0 || !buff) 2529 return I40E_ERR_PARAM; 2530 2531 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 2532 /* Indirect Command */ 2533 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2534 2535 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 2536 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 2537 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 2538 2539 desc.datalen = cpu_to_le16(buff_size); 2540 2541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2542 if (buff_size > I40E_AQ_LARGE_BUF) 2543 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2544 2545 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2546 if (!status) { 2547 if (local_len != NULL) 2548 *local_len = le16_to_cpu(resp->local_len); 2549 if (remote_len != NULL) 2550 *remote_len = le16_to_cpu(resp->remote_len); 2551 } 2552 2553 return status; 2554} 2555 2556/** 2557 * i40e_aq_cfg_lldp_mib_change_event 2558 * @hw: pointer to the hw struct 2559 * @enable_update: Enable or Disable event posting 2560 * @cmd_details: pointer to command details structure or NULL 2561 * 2562 * Enable or Disable posting of an event on ARQ when LLDP MIB 2563 * associated with the interface changes 2564 **/ 2565i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 2566 bool enable_update, 2567 struct i40e_asq_cmd_details *cmd_details) 2568{ 2569 struct i40e_aq_desc desc; 2570 struct i40e_aqc_lldp_update_mib *cmd = 2571 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 2572 i40e_status status; 2573 2574 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 2575 2576 if (!enable_update) 2577 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 2578 2579 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2580 2581 return status; 2582} 2583 2584/** 2585 * i40e_aq_stop_lldp 2586 * @hw: pointer to the hw struct 2587 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 2588 * @cmd_details: pointer to command details structure or NULL 2589 * 2590 * Stop or Shutdown the embedded LLDP Agent 2591 **/ 2592i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 2593 struct i40e_asq_cmd_details *cmd_details) 2594{ 2595 struct i40e_aq_desc desc; 2596 struct i40e_aqc_lldp_stop *cmd = 2597 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 2598 i40e_status status; 2599 2600 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 2601 2602 if (shutdown_agent) 2603 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 2604 2605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2606 2607 return status; 2608} 2609 2610/** 2611 * i40e_aq_start_lldp 2612 * @hw: pointer to the hw struct 2613 * @cmd_details: pointer to command details structure or NULL 2614 * 2615 * Start the embedded LLDP Agent on all ports. 2616 **/ 2617i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, 2618 struct i40e_asq_cmd_details *cmd_details) 2619{ 2620 struct i40e_aq_desc desc; 2621 struct i40e_aqc_lldp_start *cmd = 2622 (struct i40e_aqc_lldp_start *)&desc.params.raw; 2623 i40e_status status; 2624 2625 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 2626 2627 cmd->command = I40E_AQ_LLDP_AGENT_START; 2628 2629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2630 2631 return status; 2632} 2633 2634/** 2635 * i40e_aq_add_udp_tunnel 2636 * @hw: pointer to the hw struct 2637 * @udp_port: the UDP port to add 2638 * @header_len: length of the tunneling header length in DWords 2639 * @protocol_index: protocol index type 2640 * @filter_index: pointer to filter index 2641 * @cmd_details: pointer to command details structure or NULL 2642 **/ 2643i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 2644 u16 udp_port, u8 protocol_index, 2645 u8 *filter_index, 2646 struct i40e_asq_cmd_details *cmd_details) 2647{ 2648 struct i40e_aq_desc desc; 2649 struct i40e_aqc_add_udp_tunnel *cmd = 2650 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 2651 struct i40e_aqc_del_udp_tunnel_completion *resp = 2652 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 2653 i40e_status status; 2654 2655 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 2656 2657 cmd->udp_port = cpu_to_le16(udp_port); 2658 cmd->protocol_type = protocol_index; 2659 2660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2661 2662 if (!status) 2663 *filter_index = resp->index; 2664 2665 return status; 2666} 2667 2668/** 2669 * i40e_aq_del_udp_tunnel 2670 * @hw: pointer to the hw struct 2671 * @index: filter index 2672 * @cmd_details: pointer to command details structure or NULL 2673 **/ 2674i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 2675 struct i40e_asq_cmd_details *cmd_details) 2676{ 2677 struct i40e_aq_desc desc; 2678 struct i40e_aqc_remove_udp_tunnel *cmd = 2679 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 2680 i40e_status status; 2681 2682 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 2683 2684 cmd->index = index; 2685 2686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2687 2688 return status; 2689} 2690 2691/** 2692 * i40e_aq_delete_element - Delete switch element 2693 * @hw: pointer to the hw struct 2694 * @seid: the SEID to delete from the switch 2695 * @cmd_details: pointer to command details structure or NULL 2696 * 2697 * This deletes a switch element from the switch. 2698 **/ 2699i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 2700 struct i40e_asq_cmd_details *cmd_details) 2701{ 2702 struct i40e_aq_desc desc; 2703 struct i40e_aqc_switch_seid *cmd = 2704 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2705 i40e_status status; 2706 2707 if (seid == 0) 2708 return I40E_ERR_PARAM; 2709 2710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 2711 2712 cmd->seid = cpu_to_le16(seid); 2713 2714 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2715 2716 return status; 2717} 2718 2719/** 2720 * i40e_aq_dcb_updated - DCB Updated Command 2721 * @hw: pointer to the hw struct 2722 * @cmd_details: pointer to command details structure or NULL 2723 * 2724 * EMP will return when the shared RPB settings have been 2725 * recomputed and modified. The retval field in the descriptor 2726 * will be set to 0 when RPB is modified. 2727 **/ 2728i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw, 2729 struct i40e_asq_cmd_details *cmd_details) 2730{ 2731 struct i40e_aq_desc desc; 2732 i40e_status status; 2733 2734 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 2735 2736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2737 2738 return status; 2739} 2740 2741/** 2742 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 2743 * @hw: pointer to the hw struct 2744 * @seid: seid for the physical port/switching component/vsi 2745 * @buff: Indirect buffer to hold data parameters and response 2746 * @buff_size: Indirect buffer size 2747 * @opcode: Tx scheduler AQ command opcode 2748 * @cmd_details: pointer to command details structure or NULL 2749 * 2750 * Generic command handler for Tx scheduler AQ commands 2751 **/ 2752static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 2753 void *buff, u16 buff_size, 2754 enum i40e_admin_queue_opc opcode, 2755 struct i40e_asq_cmd_details *cmd_details) 2756{ 2757 struct i40e_aq_desc desc; 2758 struct i40e_aqc_tx_sched_ind *cmd = 2759 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 2760 i40e_status status; 2761 bool cmd_param_flag = false; 2762 2763 switch (opcode) { 2764 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 2765 case i40e_aqc_opc_configure_vsi_tc_bw: 2766 case i40e_aqc_opc_enable_switching_comp_ets: 2767 case i40e_aqc_opc_modify_switching_comp_ets: 2768 case i40e_aqc_opc_disable_switching_comp_ets: 2769 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 2770 case i40e_aqc_opc_configure_switching_comp_bw_config: 2771 cmd_param_flag = true; 2772 break; 2773 case i40e_aqc_opc_query_vsi_bw_config: 2774 case i40e_aqc_opc_query_vsi_ets_sla_config: 2775 case i40e_aqc_opc_query_switching_comp_ets_config: 2776 case i40e_aqc_opc_query_port_ets_config: 2777 case i40e_aqc_opc_query_switching_comp_bw_config: 2778 cmd_param_flag = false; 2779 break; 2780 default: 2781 return I40E_ERR_PARAM; 2782 } 2783 2784 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2785 2786 /* Indirect command */ 2787 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); 2788 if (cmd_param_flag) 2789 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD); 2790 if (buff_size > I40E_AQ_LARGE_BUF) 2791 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); 2792 2793 desc.datalen = cpu_to_le16(buff_size); 2794 2795 cmd->vsi_seid = cpu_to_le16(seid); 2796 2797 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 2798 2799 return status; 2800} 2801 2802/** 2803 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 2804 * @hw: pointer to the hw struct 2805 * @seid: VSI seid 2806 * @credit: BW limit credits (0 = disabled) 2807 * @max_credit: Max BW limit credits 2808 * @cmd_details: pointer to command details structure or NULL 2809 **/ 2810i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 2811 u16 seid, u16 credit, u8 max_credit, 2812 struct i40e_asq_cmd_details *cmd_details) 2813{ 2814 struct i40e_aq_desc desc; 2815 struct i40e_aqc_configure_vsi_bw_limit *cmd = 2816 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 2817 i40e_status status; 2818 2819 i40e_fill_default_direct_cmd_desc(&desc, 2820 i40e_aqc_opc_configure_vsi_bw_limit); 2821 2822 cmd->vsi_seid = cpu_to_le16(seid); 2823 cmd->credit = cpu_to_le16(credit); 2824 cmd->max_credit = max_credit; 2825 2826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2827 2828 return status; 2829} 2830 2831/** 2832 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 2833 * @hw: pointer to the hw struct 2834 * @seid: VSI seid 2835 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 2836 * @cmd_details: pointer to command details structure or NULL 2837 **/ 2838i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 2839 u16 seid, 2840 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 2841 struct i40e_asq_cmd_details *cmd_details) 2842{ 2843 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2844 i40e_aqc_opc_configure_vsi_tc_bw, 2845 cmd_details); 2846} 2847 2848/** 2849 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port 2850 * @hw: pointer to the hw struct 2851 * @seid: seid of the switching component connected to Physical Port 2852 * @ets_data: Buffer holding ETS parameters 2853 * @cmd_details: pointer to command details structure or NULL 2854 **/ 2855i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw, 2856 u16 seid, 2857 struct i40e_aqc_configure_switching_comp_ets_data *ets_data, 2858 enum i40e_admin_queue_opc opcode, 2859 struct i40e_asq_cmd_details *cmd_details) 2860{ 2861 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data, 2862 sizeof(*ets_data), opcode, cmd_details); 2863} 2864 2865/** 2866 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC 2867 * @hw: pointer to the hw struct 2868 * @seid: seid of the switching component 2869 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits 2870 * @cmd_details: pointer to command details structure or NULL 2871 **/ 2872i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw, 2873 u16 seid, 2874 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data, 2875 struct i40e_asq_cmd_details *cmd_details) 2876{ 2877 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2878 i40e_aqc_opc_configure_switching_comp_bw_config, 2879 cmd_details); 2880} 2881 2882/** 2883 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 2884 * @hw: pointer to the hw struct 2885 * @seid: seid of the VSI 2886 * @bw_data: Buffer to hold VSI BW configuration 2887 * @cmd_details: pointer to command details structure or NULL 2888 **/ 2889i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 2890 u16 seid, 2891 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 2892 struct i40e_asq_cmd_details *cmd_details) 2893{ 2894 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2895 i40e_aqc_opc_query_vsi_bw_config, 2896 cmd_details); 2897} 2898 2899/** 2900 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 2901 * @hw: pointer to the hw struct 2902 * @seid: seid of the VSI 2903 * @bw_data: Buffer to hold VSI BW configuration per TC 2904 * @cmd_details: pointer to command details structure or NULL 2905 **/ 2906i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 2907 u16 seid, 2908 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 2909 struct i40e_asq_cmd_details *cmd_details) 2910{ 2911 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2912 i40e_aqc_opc_query_vsi_ets_sla_config, 2913 cmd_details); 2914} 2915 2916/** 2917 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 2918 * @hw: pointer to the hw struct 2919 * @seid: seid of the switching component 2920 * @bw_data: Buffer to hold switching component's per TC BW config 2921 * @cmd_details: pointer to command details structure or NULL 2922 **/ 2923i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 2924 u16 seid, 2925 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 2926 struct i40e_asq_cmd_details *cmd_details) 2927{ 2928 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2929 i40e_aqc_opc_query_switching_comp_ets_config, 2930 cmd_details); 2931} 2932 2933/** 2934 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 2935 * @hw: pointer to the hw struct 2936 * @seid: seid of the VSI or switching component connected to Physical Port 2937 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 2938 * @cmd_details: pointer to command details structure or NULL 2939 **/ 2940i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw, 2941 u16 seid, 2942 struct i40e_aqc_query_port_ets_config_resp *bw_data, 2943 struct i40e_asq_cmd_details *cmd_details) 2944{ 2945 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2946 i40e_aqc_opc_query_port_ets_config, 2947 cmd_details); 2948} 2949 2950/** 2951 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 2952 * @hw: pointer to the hw struct 2953 * @seid: seid of the switching component 2954 * @bw_data: Buffer to hold switching component's BW configuration 2955 * @cmd_details: pointer to command details structure or NULL 2956 **/ 2957i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 2958 u16 seid, 2959 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 2960 struct i40e_asq_cmd_details *cmd_details) 2961{ 2962 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 2963 i40e_aqc_opc_query_switching_comp_bw_config, 2964 cmd_details); 2965} 2966 2967/** 2968 * i40e_validate_filter_settings 2969 * @hw: pointer to the hardware structure 2970 * @settings: Filter control settings 2971 * 2972 * Check and validate the filter control settings passed. 2973 * The function checks for the valid filter/context sizes being 2974 * passed for FCoE and PE. 2975 * 2976 * Returns 0 if the values passed are valid and within 2977 * range else returns an error. 2978 **/ 2979static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw, 2980 struct i40e_filter_control_settings *settings) 2981{ 2982 u32 fcoe_cntx_size, fcoe_filt_size; 2983 u32 pe_cntx_size, pe_filt_size; 2984 u32 fcoe_fmax; 2985 u32 val; 2986 2987 /* Validate FCoE settings passed */ 2988 switch (settings->fcoe_filt_num) { 2989 case I40E_HASH_FILTER_SIZE_1K: 2990 case I40E_HASH_FILTER_SIZE_2K: 2991 case I40E_HASH_FILTER_SIZE_4K: 2992 case I40E_HASH_FILTER_SIZE_8K: 2993 case I40E_HASH_FILTER_SIZE_16K: 2994 case I40E_HASH_FILTER_SIZE_32K: 2995 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 2996 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 2997 break; 2998 default: 2999 return I40E_ERR_PARAM; 3000 } 3001 3002 switch (settings->fcoe_cntx_num) { 3003 case I40E_DMA_CNTX_SIZE_512: 3004 case I40E_DMA_CNTX_SIZE_1K: 3005 case I40E_DMA_CNTX_SIZE_2K: 3006 case I40E_DMA_CNTX_SIZE_4K: 3007 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3008 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 3009 break; 3010 default: 3011 return I40E_ERR_PARAM; 3012 } 3013 3014 /* Validate PE settings passed */ 3015 switch (settings->pe_filt_num) { 3016 case I40E_HASH_FILTER_SIZE_1K: 3017 case I40E_HASH_FILTER_SIZE_2K: 3018 case I40E_HASH_FILTER_SIZE_4K: 3019 case I40E_HASH_FILTER_SIZE_8K: 3020 case I40E_HASH_FILTER_SIZE_16K: 3021 case I40E_HASH_FILTER_SIZE_32K: 3022 case I40E_HASH_FILTER_SIZE_64K: 3023 case I40E_HASH_FILTER_SIZE_128K: 3024 case I40E_HASH_FILTER_SIZE_256K: 3025 case I40E_HASH_FILTER_SIZE_512K: 3026 case I40E_HASH_FILTER_SIZE_1M: 3027 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 3028 pe_filt_size <<= (u32)settings->pe_filt_num; 3029 break; 3030 default: 3031 return I40E_ERR_PARAM; 3032 } 3033 3034 switch (settings->pe_cntx_num) { 3035 case I40E_DMA_CNTX_SIZE_512: 3036 case I40E_DMA_CNTX_SIZE_1K: 3037 case I40E_DMA_CNTX_SIZE_2K: 3038 case I40E_DMA_CNTX_SIZE_4K: 3039 case I40E_DMA_CNTX_SIZE_8K: 3040 case I40E_DMA_CNTX_SIZE_16K: 3041 case I40E_DMA_CNTX_SIZE_32K: 3042 case I40E_DMA_CNTX_SIZE_64K: 3043 case I40E_DMA_CNTX_SIZE_128K: 3044 case I40E_DMA_CNTX_SIZE_256K: 3045 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 3046 pe_cntx_size <<= (u32)settings->pe_cntx_num; 3047 break; 3048 default: 3049 return I40E_ERR_PARAM; 3050 } 3051 3052 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 3053 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 3054 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 3055 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 3056 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 3057 return I40E_ERR_INVALID_SIZE; 3058 3059 return 0; 3060} 3061 3062/** 3063 * i40e_set_filter_control 3064 * @hw: pointer to the hardware structure 3065 * @settings: Filter control settings 3066 * 3067 * Set the Queue Filters for PE/FCoE and enable filters required 3068 * for a single PF. It is expected that these settings are programmed 3069 * at the driver initialization time. 3070 **/ 3071i40e_status i40e_set_filter_control(struct i40e_hw *hw, 3072 struct i40e_filter_control_settings *settings) 3073{ 3074 i40e_status ret = 0; 3075 u32 hash_lut_size = 0; 3076 u32 val; 3077 3078 if (!settings) 3079 return I40E_ERR_PARAM; 3080 3081 /* Validate the input settings */ 3082 ret = i40e_validate_filter_settings(hw, settings); 3083 if (ret) 3084 return ret; 3085 3086 /* Read the PF Queue Filter control register */ 3087 val = rd32(hw, I40E_PFQF_CTL_0); 3088 3089 /* Program required PE hash buckets for the PF */ 3090 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 3091 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 3092 I40E_PFQF_CTL_0_PEHSIZE_MASK; 3093 /* Program required PE contexts for the PF */ 3094 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 3095 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 3096 I40E_PFQF_CTL_0_PEDSIZE_MASK; 3097 3098 /* Program required FCoE hash buckets for the PF */ 3099 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3100 val |= ((u32)settings->fcoe_filt_num << 3101 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 3102 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 3103 /* Program required FCoE DDP contexts for the PF */ 3104 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3105 val |= ((u32)settings->fcoe_cntx_num << 3106 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 3107 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 3108 3109 /* Program Hash LUT size for the PF */ 3110 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3111 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 3112 hash_lut_size = 1; 3113 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 3114 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 3115 3116 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 3117 if (settings->enable_fdir) 3118 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 3119 if (settings->enable_ethtype) 3120 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 3121 if (settings->enable_macvlan) 3122 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 3123 3124 wr32(hw, I40E_PFQF_CTL_0, val); 3125 3126 return 0; 3127} 3128 3129/** 3130 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 3131 * @hw: pointer to the hw struct 3132 * @mac_addr: MAC address to use in the filter 3133 * @ethtype: Ethertype to use in the filter 3134 * @flags: Flags that needs to be applied to the filter 3135 * @vsi_seid: seid of the control VSI 3136 * @queue: VSI queue number to send the packet to 3137 * @is_add: Add control packet filter if True else remove 3138 * @stats: Structure to hold information on control filter counts 3139 * @cmd_details: pointer to command details structure or NULL 3140 * 3141 * This command will Add or Remove control packet filter for a control VSI. 3142 * In return it will update the total number of perfect filter count in 3143 * the stats member. 3144 **/ 3145i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 3146 u8 *mac_addr, u16 ethtype, u16 flags, 3147 u16 vsi_seid, u16 queue, bool is_add, 3148 struct i40e_control_filter_stats *stats, 3149 struct i40e_asq_cmd_details *cmd_details) 3150{ 3151 struct i40e_aq_desc desc; 3152 struct i40e_aqc_add_remove_control_packet_filter *cmd = 3153 (struct i40e_aqc_add_remove_control_packet_filter *) 3154 &desc.params.raw; 3155 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 3156 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 3157 &desc.params.raw; 3158 i40e_status status; 3159 3160 if (vsi_seid == 0) 3161 return I40E_ERR_PARAM; 3162 3163 if (is_add) { 3164 i40e_fill_default_direct_cmd_desc(&desc, 3165 i40e_aqc_opc_add_control_packet_filter); 3166 cmd->queue = cpu_to_le16(queue); 3167 } else { 3168 i40e_fill_default_direct_cmd_desc(&desc, 3169 i40e_aqc_opc_remove_control_packet_filter); 3170 } 3171 3172 if (mac_addr) 3173 memcpy(cmd->mac, mac_addr, ETH_ALEN); 3174 3175 cmd->etype = cpu_to_le16(ethtype); 3176 cmd->flags = cpu_to_le16(flags); 3177 cmd->seid = cpu_to_le16(vsi_seid); 3178 3179 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3180 3181 if (!status && stats) { 3182 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used); 3183 stats->etype_used = le16_to_cpu(resp->etype_used); 3184 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free); 3185 stats->etype_free = le16_to_cpu(resp->etype_free); 3186 } 3187 3188 return status; 3189} 3190 3191/** 3192 * i40e_set_pci_config_data - store PCI bus info 3193 * @hw: pointer to hardware structure 3194 * @link_status: the link status word from PCI config space 3195 * 3196 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 3197 **/ 3198void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 3199{ 3200 hw->bus.type = i40e_bus_type_pci_express; 3201 3202 switch (link_status & PCI_EXP_LNKSTA_NLW) { 3203 case PCI_EXP_LNKSTA_NLW_X1: 3204 hw->bus.width = i40e_bus_width_pcie_x1; 3205 break; 3206 case PCI_EXP_LNKSTA_NLW_X2: 3207 hw->bus.width = i40e_bus_width_pcie_x2; 3208 break; 3209 case PCI_EXP_LNKSTA_NLW_X4: 3210 hw->bus.width = i40e_bus_width_pcie_x4; 3211 break; 3212 case PCI_EXP_LNKSTA_NLW_X8: 3213 hw->bus.width = i40e_bus_width_pcie_x8; 3214 break; 3215 default: 3216 hw->bus.width = i40e_bus_width_unknown; 3217 break; 3218 } 3219 3220 switch (link_status & PCI_EXP_LNKSTA_CLS) { 3221 case PCI_EXP_LNKSTA_CLS_2_5GB: 3222 hw->bus.speed = i40e_bus_speed_2500; 3223 break; 3224 case PCI_EXP_LNKSTA_CLS_5_0GB: 3225 hw->bus.speed = i40e_bus_speed_5000; 3226 break; 3227 case PCI_EXP_LNKSTA_CLS_8_0GB: 3228 hw->bus.speed = i40e_bus_speed_8000; 3229 break; 3230 default: 3231 hw->bus.speed = i40e_bus_speed_unknown; 3232 break; 3233 } 3234} 3235