1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_TYPE_H_ 28#define _I40E_TYPE_H_ 29 30#include "i40e_status.h" 31#include "i40e_osdep.h" 32#include "i40e_register.h" 33#include "i40e_adminq.h" 34#include "i40e_hmc.h" 35#include "i40e_lan_hmc.h" 36 37/* Device IDs */ 38#define I40E_DEV_ID_SFP_XL710 0x1572 39#define I40E_DEV_ID_QEMU 0x1574 40#define I40E_DEV_ID_KX_A 0x157F 41#define I40E_DEV_ID_KX_B 0x1580 42#define I40E_DEV_ID_KX_C 0x1581 43#define I40E_DEV_ID_QSFP_A 0x1583 44#define I40E_DEV_ID_QSFP_B 0x1584 45#define I40E_DEV_ID_QSFP_C 0x1585 46#define I40E_DEV_ID_VF 0x154C 47#define I40E_DEV_ID_VF_HV 0x1571 48 49#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \ 50 (d) == I40E_DEV_ID_QSFP_B || \ 51 (d) == I40E_DEV_ID_QSFP_C) 52 53/* I40E_MASK is a macro used on 32 bit registers */ 54#define I40E_MASK(mask, shift) (mask << shift) 55 56#define I40E_MAX_VSI_QP 16 57#define I40E_MAX_VF_VSI 3 58#define I40E_MAX_CHAINED_RX_BUFFERS 5 59#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 60 61/* Max default timeout in ms, */ 62#define I40E_MAX_NVM_TIMEOUT 18000 63 64/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 65#define I40E_MS_TO_GTIME(time) ((time) * 1000) 66 67/* forward declaration */ 68struct i40e_hw; 69typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 70 71/* Data type manipulation macros. */ 72 73#define I40E_DESC_UNUSED(R) \ 74 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 75 (R)->next_to_clean - (R)->next_to_use - 1) 76 77/* bitfields for Tx queue mapping in QTX_CTL */ 78#define I40E_QTX_CTL_VF_QUEUE 0x0 79#define I40E_QTX_CTL_VM_QUEUE 0x1 80#define I40E_QTX_CTL_PF_QUEUE 0x2 81 82/* debug masks - set these bits in hw->debug_mask to control output */ 83enum i40e_debug_mask { 84 I40E_DEBUG_INIT = 0x00000001, 85 I40E_DEBUG_RELEASE = 0x00000002, 86 87 I40E_DEBUG_LINK = 0x00000010, 88 I40E_DEBUG_PHY = 0x00000020, 89 I40E_DEBUG_HMC = 0x00000040, 90 I40E_DEBUG_NVM = 0x00000080, 91 I40E_DEBUG_LAN = 0x00000100, 92 I40E_DEBUG_FLOW = 0x00000200, 93 I40E_DEBUG_DCB = 0x00000400, 94 I40E_DEBUG_DIAG = 0x00000800, 95 I40E_DEBUG_FD = 0x00001000, 96 97 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 98 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 99 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 100 I40E_DEBUG_AQ_COMMAND = 0x06000000, 101 I40E_DEBUG_AQ = 0x0F000000, 102 103 I40E_DEBUG_USER = 0xF0000000, 104 105 I40E_DEBUG_ALL = 0xFFFFFFFF 106}; 107 108/* These are structs for managing the hardware information and the operations. 109 * The structures of function pointers are filled out at init time when we 110 * know for sure exactly which hardware we're working with. This gives us the 111 * flexibility of using the same main driver code but adapting to slightly 112 * different hardware needs as new parts are developed. For this architecture, 113 * the Firmware and AdminQ are intended to insulate the driver from most of the 114 * future changes, but these structures will also do part of the job. 115 */ 116enum i40e_mac_type { 117 I40E_MAC_UNKNOWN = 0, 118 I40E_MAC_X710, 119 I40E_MAC_XL710, 120 I40E_MAC_VF, 121 I40E_MAC_GENERIC, 122}; 123 124enum i40e_media_type { 125 I40E_MEDIA_TYPE_UNKNOWN = 0, 126 I40E_MEDIA_TYPE_FIBER, 127 I40E_MEDIA_TYPE_BASET, 128 I40E_MEDIA_TYPE_BACKPLANE, 129 I40E_MEDIA_TYPE_CX4, 130 I40E_MEDIA_TYPE_DA, 131 I40E_MEDIA_TYPE_VIRTUAL 132}; 133 134enum i40e_fc_mode { 135 I40E_FC_NONE = 0, 136 I40E_FC_RX_PAUSE, 137 I40E_FC_TX_PAUSE, 138 I40E_FC_FULL, 139 I40E_FC_PFC, 140 I40E_FC_DEFAULT 141}; 142 143enum i40e_set_fc_aq_failures { 144 I40E_SET_FC_AQ_FAIL_NONE = 0, 145 I40E_SET_FC_AQ_FAIL_GET = 1, 146 I40E_SET_FC_AQ_FAIL_SET = 2, 147 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 148 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 149}; 150 151enum i40e_vsi_type { 152 I40E_VSI_MAIN = 0, 153 I40E_VSI_VMDQ1, 154 I40E_VSI_VMDQ2, 155 I40E_VSI_CTRL, 156 I40E_VSI_FCOE, 157 I40E_VSI_MIRROR, 158 I40E_VSI_SRIOV, 159 I40E_VSI_FDIR, 160 I40E_VSI_TYPE_UNKNOWN 161}; 162 163enum i40e_queue_type { 164 I40E_QUEUE_TYPE_RX = 0, 165 I40E_QUEUE_TYPE_TX, 166 I40E_QUEUE_TYPE_PE_CEQ, 167 I40E_QUEUE_TYPE_UNKNOWN 168}; 169 170struct i40e_link_status { 171 enum i40e_aq_phy_type phy_type; 172 enum i40e_aq_link_speed link_speed; 173 u8 link_info; 174 u8 an_info; 175 u8 ext_info; 176 u8 loopback; 177 bool an_enabled; 178 /* is Link Status Event notification to SW enabled */ 179 bool lse_enable; 180 u16 max_frame_size; 181 bool crc_enable; 182 u8 pacing; 183}; 184 185struct i40e_phy_info { 186 struct i40e_link_status link_info; 187 struct i40e_link_status link_info_old; 188 u32 autoneg_advertised; 189 u32 phy_id; 190 u32 module_type; 191 bool get_link_info; 192 enum i40e_media_type media_type; 193}; 194 195#define I40E_HW_CAP_MAX_GPIO 30 196/* Capabilities of a PF or a VF or the whole device */ 197struct i40e_hw_capabilities { 198 u32 switch_mode; 199#define I40E_NVM_IMAGE_TYPE_EVB 0x0 200#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 201#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 202 203 u32 management_mode; 204 u32 npar_enable; 205 u32 os2bmc; 206 u32 valid_functions; 207 bool sr_iov_1_1; 208 bool vmdq; 209 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 210 bool evb_802_1_qbh; /* Bridge Port Extension */ 211 bool dcb; 212 bool fcoe; 213 bool mfp_mode_1; 214 bool mgmt_cem; 215 bool ieee_1588; 216 bool iwarp; 217 bool fd; 218 u32 fd_filters_guaranteed; 219 u32 fd_filters_best_effort; 220 bool rss; 221 u32 rss_table_size; 222 u32 rss_table_entry_width; 223 bool led[I40E_HW_CAP_MAX_GPIO]; 224 bool sdp[I40E_HW_CAP_MAX_GPIO]; 225 u32 nvm_image_type; 226 u32 num_flow_director_filters; 227 u32 num_vfs; 228 u32 vf_base_id; 229 u32 num_vsis; 230 u32 num_rx_qp; 231 u32 num_tx_qp; 232 u32 base_queue; 233 u32 num_msix_vectors; 234 u32 num_msix_vectors_vf; 235 u32 led_pin_num; 236 u32 sdp_pin_num; 237 u32 mdio_port_num; 238 u32 mdio_port_mode; 239 u8 rx_buf_chain_len; 240 u32 enabled_tcmap; 241 u32 maxtc; 242}; 243 244struct i40e_mac_info { 245 enum i40e_mac_type type; 246 u8 addr[ETH_ALEN]; 247 u8 perm_addr[ETH_ALEN]; 248 u8 san_addr[ETH_ALEN]; 249 u16 max_fcoeq; 250}; 251 252enum i40e_aq_resources_ids { 253 I40E_NVM_RESOURCE_ID = 1 254}; 255 256enum i40e_aq_resource_access_type { 257 I40E_RESOURCE_READ = 1, 258 I40E_RESOURCE_WRITE 259}; 260 261struct i40e_nvm_info { 262 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */ 263 u64 hw_semaphore_wait; /* - || - */ 264 u32 timeout; /* [ms] */ 265 u16 sr_size; /* Shadow RAM size in words */ 266 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 267 u16 version; /* NVM package version */ 268 u32 eetrack; /* NVM data version */ 269}; 270 271/* definitions used in NVM update support */ 272 273enum i40e_nvmupd_cmd { 274 I40E_NVMUPD_INVALID, 275 I40E_NVMUPD_READ_CON, 276 I40E_NVMUPD_READ_SNT, 277 I40E_NVMUPD_READ_LCB, 278 I40E_NVMUPD_READ_SA, 279 I40E_NVMUPD_WRITE_ERA, 280 I40E_NVMUPD_WRITE_CON, 281 I40E_NVMUPD_WRITE_SNT, 282 I40E_NVMUPD_WRITE_LCB, 283 I40E_NVMUPD_WRITE_SA, 284 I40E_NVMUPD_CSUM_CON, 285 I40E_NVMUPD_CSUM_SA, 286 I40E_NVMUPD_CSUM_LCB, 287}; 288 289enum i40e_nvmupd_state { 290 I40E_NVMUPD_STATE_INIT, 291 I40E_NVMUPD_STATE_READING, 292 I40E_NVMUPD_STATE_WRITING 293}; 294 295/* nvm_access definition and its masks/shifts need to be accessible to 296 * application, core driver, and shared code. Where is the right file? 297 */ 298#define I40E_NVM_READ 0xB 299#define I40E_NVM_WRITE 0xC 300 301#define I40E_NVM_MOD_PNT_MASK 0xFF 302 303#define I40E_NVM_TRANS_SHIFT 8 304#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 305#define I40E_NVM_CON 0x0 306#define I40E_NVM_SNT 0x1 307#define I40E_NVM_LCB 0x2 308#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 309#define I40E_NVM_ERA 0x4 310#define I40E_NVM_CSUM 0x8 311 312#define I40E_NVM_ADAPT_SHIFT 16 313#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) 314 315#define I40E_NVMUPD_MAX_DATA 4096 316#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 317 318struct i40e_nvm_access { 319 u32 command; 320 u32 config; 321 u32 offset; /* in bytes */ 322 u32 data_size; /* in bytes */ 323 u8 data[1]; 324}; 325 326/* PCI bus types */ 327enum i40e_bus_type { 328 i40e_bus_type_unknown = 0, 329 i40e_bus_type_pci, 330 i40e_bus_type_pcix, 331 i40e_bus_type_pci_express, 332 i40e_bus_type_reserved 333}; 334 335/* PCI bus speeds */ 336enum i40e_bus_speed { 337 i40e_bus_speed_unknown = 0, 338 i40e_bus_speed_33 = 33, 339 i40e_bus_speed_66 = 66, 340 i40e_bus_speed_100 = 100, 341 i40e_bus_speed_120 = 120, 342 i40e_bus_speed_133 = 133, 343 i40e_bus_speed_2500 = 2500, 344 i40e_bus_speed_5000 = 5000, 345 i40e_bus_speed_8000 = 8000, 346 i40e_bus_speed_reserved 347}; 348 349/* PCI bus widths */ 350enum i40e_bus_width { 351 i40e_bus_width_unknown = 0, 352 i40e_bus_width_pcie_x1 = 1, 353 i40e_bus_width_pcie_x2 = 2, 354 i40e_bus_width_pcie_x4 = 4, 355 i40e_bus_width_pcie_x8 = 8, 356 i40e_bus_width_32 = 32, 357 i40e_bus_width_64 = 64, 358 i40e_bus_width_reserved 359}; 360 361/* Bus parameters */ 362struct i40e_bus_info { 363 enum i40e_bus_speed speed; 364 enum i40e_bus_width width; 365 enum i40e_bus_type type; 366 367 u16 func; 368 u16 device; 369 u16 lan_id; 370}; 371 372/* Flow control (FC) parameters */ 373struct i40e_fc_info { 374 enum i40e_fc_mode current_mode; /* FC mode in effect */ 375 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 376}; 377 378#define I40E_MAX_TRAFFIC_CLASS 8 379#define I40E_MAX_USER_PRIORITY 8 380#define I40E_DCBX_MAX_APPS 32 381#define I40E_LLDPDU_SIZE 1500 382 383/* IEEE 802.1Qaz ETS Configuration data */ 384struct i40e_ieee_ets_config { 385 u8 willing; 386 u8 cbs; 387 u8 maxtcs; 388 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 389 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 390 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 391}; 392 393/* IEEE 802.1Qaz ETS Recommendation data */ 394struct i40e_ieee_ets_recommend { 395 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 396 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 397 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 398}; 399 400/* IEEE 802.1Qaz PFC Configuration data */ 401struct i40e_ieee_pfc_config { 402 u8 willing; 403 u8 mbc; 404 u8 pfccap; 405 u8 pfcenable; 406}; 407 408/* IEEE 802.1Qaz Application Priority data */ 409struct i40e_ieee_app_priority_table { 410 u8 priority; 411 u8 selector; 412 u16 protocolid; 413}; 414 415struct i40e_dcbx_config { 416 u32 numapps; 417 struct i40e_ieee_ets_config etscfg; 418 struct i40e_ieee_ets_recommend etsrec; 419 struct i40e_ieee_pfc_config pfc; 420 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; 421}; 422 423/* Port hardware description */ 424struct i40e_hw { 425 u8 __iomem *hw_addr; 426 void *back; 427 428 /* function pointer structs */ 429 struct i40e_phy_info phy; 430 struct i40e_mac_info mac; 431 struct i40e_bus_info bus; 432 struct i40e_nvm_info nvm; 433 struct i40e_fc_info fc; 434 435 /* pci info */ 436 u16 device_id; 437 u16 vendor_id; 438 u16 subsystem_device_id; 439 u16 subsystem_vendor_id; 440 u8 revision_id; 441 u8 port; 442 bool adapter_stopped; 443 444 /* capabilities for entire device and PCI func */ 445 struct i40e_hw_capabilities dev_caps; 446 struct i40e_hw_capabilities func_caps; 447 448 /* Flow Director shared filter space */ 449 u16 fdir_shared_filter_count; 450 451 /* device profile info */ 452 u8 pf_id; 453 u16 main_vsi_seid; 454 455 /* Closest numa node to the device */ 456 u16 numa_node; 457 458 /* Admin Queue info */ 459 struct i40e_adminq_info aq; 460 461 /* state of nvm update process */ 462 enum i40e_nvmupd_state nvmupd_state; 463 464 /* HMC info */ 465 struct i40e_hmc_info hmc; /* HMC info struct */ 466 467 /* LLDP/DCBX Status */ 468 u16 dcbx_status; 469 470 /* DCBX info */ 471 struct i40e_dcbx_config local_dcbx_config; 472 struct i40e_dcbx_config remote_dcbx_config; 473 474 /* debug mask */ 475 u32 debug_mask; 476}; 477 478struct i40e_driver_version { 479 u8 major_version; 480 u8 minor_version; 481 u8 build_version; 482 u8 subbuild_version; 483 u8 driver_string[32]; 484}; 485 486/* RX Descriptors */ 487union i40e_16byte_rx_desc { 488 struct { 489 __le64 pkt_addr; /* Packet buffer address */ 490 __le64 hdr_addr; /* Header buffer address */ 491 } read; 492 struct { 493 struct { 494 struct { 495 union { 496 __le16 mirroring_status; 497 __le16 fcoe_ctx_id; 498 } mirr_fcoe; 499 __le16 l2tag1; 500 } lo_dword; 501 union { 502 __le32 rss; /* RSS Hash */ 503 __le32 fd_id; /* Flow director filter id */ 504 __le32 fcoe_param; /* FCoE DDP Context id */ 505 } hi_dword; 506 } qword0; 507 struct { 508 /* ext status/error/pktype/length */ 509 __le64 status_error_len; 510 } qword1; 511 } wb; /* writeback */ 512}; 513 514union i40e_32byte_rx_desc { 515 struct { 516 __le64 pkt_addr; /* Packet buffer address */ 517 __le64 hdr_addr; /* Header buffer address */ 518 /* bit 0 of hdr_buffer_addr is DD bit */ 519 __le64 rsvd1; 520 __le64 rsvd2; 521 } read; 522 struct { 523 struct { 524 struct { 525 union { 526 __le16 mirroring_status; 527 __le16 fcoe_ctx_id; 528 } mirr_fcoe; 529 __le16 l2tag1; 530 } lo_dword; 531 union { 532 __le32 rss; /* RSS Hash */ 533 __le32 fcoe_param; /* FCoE DDP Context id */ 534 /* Flow director filter id in case of 535 * Programming status desc WB 536 */ 537 __le32 fd_id; 538 } hi_dword; 539 } qword0; 540 struct { 541 /* status/error/pktype/length */ 542 __le64 status_error_len; 543 } qword1; 544 struct { 545 __le16 ext_status; /* extended status */ 546 __le16 rsvd; 547 __le16 l2tag2_1; 548 __le16 l2tag2_2; 549 } qword2; 550 struct { 551 union { 552 __le32 flex_bytes_lo; 553 __le32 pe_status; 554 } lo_dword; 555 union { 556 __le32 flex_bytes_hi; 557 __le32 fd_id; 558 } hi_dword; 559 } qword3; 560 } wb; /* writeback */ 561}; 562 563enum i40e_rx_desc_status_bits { 564 /* Note: These are predefined bit offsets */ 565 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 566 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 567 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 568 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 569 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 570 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 571 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 572 I40E_RX_DESC_STATUS_PIF_SHIFT = 8, 573 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 574 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 575 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 576 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 577 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 578 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 579 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, 580 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 581}; 582 583#define I40E_RXD_QW1_STATUS_SHIFT 0 584#define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \ 585 << I40E_RXD_QW1_STATUS_SHIFT) 586 587#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 588#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 589 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 590 591#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 592#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \ 593 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 594 595enum i40e_rx_desc_fltstat_values { 596 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 597 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 598 I40E_RX_DESC_FLTSTAT_RSV = 2, 599 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 600}; 601 602#define I40E_RXD_QW1_ERROR_SHIFT 19 603#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 604 605enum i40e_rx_desc_error_bits { 606 /* Note: These are predefined bit offsets */ 607 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 608 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 609 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 610 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 611 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 612 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 613 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 614 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 615 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 616}; 617 618enum i40e_rx_desc_error_l3l4e_fcoe_masks { 619 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 620 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 621 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 622 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 623 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 624}; 625 626#define I40E_RXD_QW1_PTYPE_SHIFT 30 627#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 628 629/* Packet type non-ip values */ 630enum i40e_rx_l2_ptype { 631 I40E_RX_PTYPE_L2_RESERVED = 0, 632 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 633 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 634 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 635 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 636 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 637 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 638 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 639 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 640 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 641 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 642 I40E_RX_PTYPE_L2_ARP = 11, 643 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 644 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 645 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 646 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 647 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 648 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 649 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 650 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 651 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 652 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 653 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 654 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 655 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 656 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 657}; 658 659struct i40e_rx_ptype_decoded { 660 u32 ptype:8; 661 u32 known:1; 662 u32 outer_ip:1; 663 u32 outer_ip_ver:1; 664 u32 outer_frag:1; 665 u32 tunnel_type:3; 666 u32 tunnel_end_prot:2; 667 u32 tunnel_end_frag:1; 668 u32 inner_prot:4; 669 u32 payload_layer:3; 670}; 671 672enum i40e_rx_ptype_outer_ip { 673 I40E_RX_PTYPE_OUTER_L2 = 0, 674 I40E_RX_PTYPE_OUTER_IP = 1 675}; 676 677enum i40e_rx_ptype_outer_ip_ver { 678 I40E_RX_PTYPE_OUTER_NONE = 0, 679 I40E_RX_PTYPE_OUTER_IPV4 = 0, 680 I40E_RX_PTYPE_OUTER_IPV6 = 1 681}; 682 683enum i40e_rx_ptype_outer_fragmented { 684 I40E_RX_PTYPE_NOT_FRAG = 0, 685 I40E_RX_PTYPE_FRAG = 1 686}; 687 688enum i40e_rx_ptype_tunnel_type { 689 I40E_RX_PTYPE_TUNNEL_NONE = 0, 690 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 691 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 692 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 693 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 694}; 695 696enum i40e_rx_ptype_tunnel_end_prot { 697 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 698 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 699 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 700}; 701 702enum i40e_rx_ptype_inner_prot { 703 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 704 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 705 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 706 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 707 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 708 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 709}; 710 711enum i40e_rx_ptype_payload_layer { 712 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 713 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 714 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 715 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 716}; 717 718#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 719#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 720 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 721 722#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 723#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 724 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 725 726#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 727#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \ 728 I40E_RXD_QW1_LENGTH_SPH_SHIFT) 729 730enum i40e_rx_desc_ext_status_bits { 731 /* Note: These are predefined bit offsets */ 732 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 733 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 734 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 735 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 736 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 737 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 738 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 739}; 740 741enum i40e_rx_desc_pe_status_bits { 742 /* Note: These are predefined bit offsets */ 743 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 744 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 745 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 746 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 747 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 748 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 749 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 750 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 751 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 752}; 753 754#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 755#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 756 757#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 758#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 759 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 760 761#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 762#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 763 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 764 765enum i40e_rx_prog_status_desc_status_bits { 766 /* Note: These are predefined bit offsets */ 767 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 768 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 769}; 770 771enum i40e_rx_prog_status_desc_prog_id_masks { 772 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 773 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 774 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 775}; 776 777enum i40e_rx_prog_status_desc_error_bits { 778 /* Note: These are predefined bit offsets */ 779 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 780 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 781 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 782 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 783}; 784 785/* TX Descriptor */ 786struct i40e_tx_desc { 787 __le64 buffer_addr; /* Address of descriptor's data buf */ 788 __le64 cmd_type_offset_bsz; 789}; 790 791#define I40E_TXD_QW1_DTYPE_SHIFT 0 792#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 793 794enum i40e_tx_desc_dtype_value { 795 I40E_TX_DESC_DTYPE_DATA = 0x0, 796 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 797 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 798 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 799 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 800 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 801 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 802 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 803 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 804 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 805}; 806 807#define I40E_TXD_QW1_CMD_SHIFT 4 808#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 809 810enum i40e_tx_desc_cmd_bits { 811 I40E_TX_DESC_CMD_EOP = 0x0001, 812 I40E_TX_DESC_CMD_RS = 0x0002, 813 I40E_TX_DESC_CMD_ICRC = 0x0004, 814 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 815 I40E_TX_DESC_CMD_DUMMY = 0x0010, 816 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 817 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 818 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 819 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 820 I40E_TX_DESC_CMD_FCOET = 0x0080, 821 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 822 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 823 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 824 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 825 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 826 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 827 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 828 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 829}; 830 831#define I40E_TXD_QW1_OFFSET_SHIFT 16 832#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 833 I40E_TXD_QW1_OFFSET_SHIFT) 834 835enum i40e_tx_desc_length_fields { 836 /* Note: These are predefined bit offsets */ 837 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 838 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 839 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 840}; 841 842#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 843#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 844 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 845 846#define I40E_TXD_QW1_L2TAG1_SHIFT 48 847#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 848 849/* Context descriptors */ 850struct i40e_tx_context_desc { 851 __le32 tunneling_params; 852 __le16 l2tag2; 853 __le16 rsvd; 854 __le64 type_cmd_tso_mss; 855}; 856 857#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 858#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 859 860#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 861#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 862 863enum i40e_tx_ctx_desc_cmd_bits { 864 I40E_TX_CTX_DESC_TSO = 0x01, 865 I40E_TX_CTX_DESC_TSYN = 0x02, 866 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 867 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 868 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 869 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 870 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 871 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 872 I40E_TX_CTX_DESC_SWPE = 0x40 873}; 874 875#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 876#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 877 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 878 879#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 880#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 881 I40E_TXD_CTX_QW1_MSS_SHIFT) 882 883#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 884#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 885 886#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 887#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 888 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 889 890enum i40e_tx_ctx_desc_eipt_offload { 891 I40E_TX_CTX_EXT_IP_NONE = 0x0, 892 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 893 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 894 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 895}; 896 897#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 898#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 899 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 900 901#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 902#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 903 904#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 905#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 906 907#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 908#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \ 909 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 910 911#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 912 913#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 914#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 915 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 916 917#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 918#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 919 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 920 921struct i40e_filter_program_desc { 922 __le32 qindex_flex_ptype_vsi; 923 __le32 rsvd; 924 __le32 dtype_cmd_cntindex; 925 __le32 fd_id; 926}; 927#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 928#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 929 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 930#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 931#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 932 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 933#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 934#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 935 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 936 937/* Packet Classifier Types for filters */ 938enum i40e_filter_pctype { 939 /* Note: Values 0-30 are reserved for future use */ 940 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 941 /* Note: Value 32 is reserved for future use */ 942 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 943 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 944 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 945 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 946 /* Note: Values 37-40 are reserved for future use */ 947 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 948 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 949 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 950 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 951 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 952 /* Note: Value 47 is reserved for future use */ 953 I40E_FILTER_PCTYPE_FCOE_OX = 48, 954 I40E_FILTER_PCTYPE_FCOE_RX = 49, 955 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 956 /* Note: Values 51-62 are reserved for future use */ 957 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 958}; 959 960enum i40e_filter_program_desc_dest { 961 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 962 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 963 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 964}; 965 966enum i40e_filter_program_desc_fd_status { 967 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 968 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 969 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 970 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 971}; 972 973#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 974#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 975 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 976 977#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 978#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 979 I40E_TXD_FLTR_QW1_CMD_SHIFT) 980 981#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 982#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 983 984enum i40e_filter_program_desc_pcmd { 985 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 986 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 987}; 988 989#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 990#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 991 992#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 993#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \ 994 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 995 996#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 997 I40E_TXD_FLTR_QW1_CMD_SHIFT) 998#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 999 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1000 1001#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1002#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1003 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1004 1005enum i40e_filter_type { 1006 I40E_FLOW_DIRECTOR_FLTR = 0, 1007 I40E_PE_QUAD_HASH_FLTR = 1, 1008 I40E_ETHERTYPE_FLTR, 1009 I40E_FCOE_CTX_FLTR, 1010 I40E_MAC_VLAN_FLTR, 1011 I40E_HASH_FLTR 1012}; 1013 1014struct i40e_vsi_context { 1015 u16 seid; 1016 u16 uplink_seid; 1017 u16 vsi_number; 1018 u16 vsis_allocated; 1019 u16 vsis_unallocated; 1020 u16 flags; 1021 u8 pf_num; 1022 u8 vf_num; 1023 u8 connection_type; 1024 struct i40e_aqc_vsi_properties_data info; 1025}; 1026 1027struct i40e_veb_context { 1028 u16 seid; 1029 u16 uplink_seid; 1030 u16 veb_number; 1031 u16 vebs_allocated; 1032 u16 vebs_unallocated; 1033 u16 flags; 1034 struct i40e_aqc_get_veb_parameters_completion info; 1035}; 1036 1037/* Statistics collected by each port, VSI, VEB, and S-channel */ 1038struct i40e_eth_stats { 1039 u64 rx_bytes; /* gorc */ 1040 u64 rx_unicast; /* uprc */ 1041 u64 rx_multicast; /* mprc */ 1042 u64 rx_broadcast; /* bprc */ 1043 u64 rx_discards; /* rdpc */ 1044 u64 rx_unknown_protocol; /* rupp */ 1045 u64 tx_bytes; /* gotc */ 1046 u64 tx_unicast; /* uptc */ 1047 u64 tx_multicast; /* mptc */ 1048 u64 tx_broadcast; /* bptc */ 1049 u64 tx_discards; /* tdpc */ 1050 u64 tx_errors; /* tepc */ 1051}; 1052 1053/* Statistics collected by the MAC */ 1054struct i40e_hw_port_stats { 1055 /* eth stats collected by the port */ 1056 struct i40e_eth_stats eth; 1057 1058 /* additional port specific stats */ 1059 u64 tx_dropped_link_down; /* tdold */ 1060 u64 crc_errors; /* crcerrs */ 1061 u64 illegal_bytes; /* illerrc */ 1062 u64 error_bytes; /* errbc */ 1063 u64 mac_local_faults; /* mlfc */ 1064 u64 mac_remote_faults; /* mrfc */ 1065 u64 rx_length_errors; /* rlec */ 1066 u64 link_xon_rx; /* lxonrxc */ 1067 u64 link_xoff_rx; /* lxoffrxc */ 1068 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1069 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1070 u64 link_xon_tx; /* lxontxc */ 1071 u64 link_xoff_tx; /* lxofftxc */ 1072 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1073 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1074 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1075 u64 rx_size_64; /* prc64 */ 1076 u64 rx_size_127; /* prc127 */ 1077 u64 rx_size_255; /* prc255 */ 1078 u64 rx_size_511; /* prc511 */ 1079 u64 rx_size_1023; /* prc1023 */ 1080 u64 rx_size_1522; /* prc1522 */ 1081 u64 rx_size_big; /* prc9522 */ 1082 u64 rx_undersize; /* ruc */ 1083 u64 rx_fragments; /* rfc */ 1084 u64 rx_oversize; /* roc */ 1085 u64 rx_jabber; /* rjc */ 1086 u64 tx_size_64; /* ptc64 */ 1087 u64 tx_size_127; /* ptc127 */ 1088 u64 tx_size_255; /* ptc255 */ 1089 u64 tx_size_511; /* ptc511 */ 1090 u64 tx_size_1023; /* ptc1023 */ 1091 u64 tx_size_1522; /* ptc1522 */ 1092 u64 tx_size_big; /* ptc9522 */ 1093 u64 mac_short_packet_dropped; /* mspdc */ 1094 u64 checksum_error; /* xec */ 1095 /* flow director stats */ 1096 u64 fd_atr_match; 1097 u64 fd_sb_match; 1098 /* EEE LPI */ 1099 u32 tx_lpi_status; 1100 u32 rx_lpi_status; 1101 u64 tx_lpi_count; /* etlpic */ 1102 u64 rx_lpi_count; /* erlpic */ 1103}; 1104 1105/* Checksum and Shadow RAM pointers */ 1106#define I40E_SR_NVM_CONTROL_WORD 0x00 1107#define I40E_SR_EMP_MODULE_PTR 0x0F 1108#define I40E_SR_NVM_IMAGE_VERSION 0x18 1109#define I40E_SR_NVM_WAKE_ON_LAN 0x19 1110#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1111#define I40E_SR_NVM_EETRACK_LO 0x2D 1112#define I40E_SR_NVM_EETRACK_HI 0x2E 1113#define I40E_SR_VPD_PTR 0x2F 1114#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1115#define I40E_SR_SW_CHECKSUM_WORD 0x3F 1116 1117/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1118#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1119#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1120#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1121#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1122 1123/* Shadow RAM related */ 1124#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1125#define I40E_SR_WORDS_IN_1KB 512 1126/* Checksum should be calculated such that after adding all the words, 1127 * including the checksum word itself, the sum should be 0xBABA. 1128 */ 1129#define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1130 1131#define I40E_SRRD_SRCTL_ATTEMPTS 100000 1132 1133enum i40e_switch_element_types { 1134 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1135 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1136 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1137 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1138 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1139 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1140 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1141 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1142 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1143}; 1144 1145/* Supported EtherType filters */ 1146enum i40e_ether_type_index { 1147 I40E_ETHER_TYPE_1588 = 0, 1148 I40E_ETHER_TYPE_FIP = 1, 1149 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1150 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1151 I40E_ETHER_TYPE_LLDP = 4, 1152 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1153 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1154 I40E_ETHER_TYPE_QCN_CNM = 7, 1155 I40E_ETHER_TYPE_8021X = 8, 1156 I40E_ETHER_TYPE_ARP = 9, 1157 I40E_ETHER_TYPE_RSV1 = 10, 1158 I40E_ETHER_TYPE_RSV2 = 11, 1159}; 1160 1161/* Filter context base size is 1K */ 1162#define I40E_HASH_FILTER_BASE_SIZE 1024 1163/* Supported Hash filter values */ 1164enum i40e_hash_filter_size { 1165 I40E_HASH_FILTER_SIZE_1K = 0, 1166 I40E_HASH_FILTER_SIZE_2K = 1, 1167 I40E_HASH_FILTER_SIZE_4K = 2, 1168 I40E_HASH_FILTER_SIZE_8K = 3, 1169 I40E_HASH_FILTER_SIZE_16K = 4, 1170 I40E_HASH_FILTER_SIZE_32K = 5, 1171 I40E_HASH_FILTER_SIZE_64K = 6, 1172 I40E_HASH_FILTER_SIZE_128K = 7, 1173 I40E_HASH_FILTER_SIZE_256K = 8, 1174 I40E_HASH_FILTER_SIZE_512K = 9, 1175 I40E_HASH_FILTER_SIZE_1M = 10, 1176}; 1177 1178/* DMA context base size is 0.5K */ 1179#define I40E_DMA_CNTX_BASE_SIZE 512 1180/* Supported DMA context values */ 1181enum i40e_dma_cntx_size { 1182 I40E_DMA_CNTX_SIZE_512 = 0, 1183 I40E_DMA_CNTX_SIZE_1K = 1, 1184 I40E_DMA_CNTX_SIZE_2K = 2, 1185 I40E_DMA_CNTX_SIZE_4K = 3, 1186 I40E_DMA_CNTX_SIZE_8K = 4, 1187 I40E_DMA_CNTX_SIZE_16K = 5, 1188 I40E_DMA_CNTX_SIZE_32K = 6, 1189 I40E_DMA_CNTX_SIZE_64K = 7, 1190 I40E_DMA_CNTX_SIZE_128K = 8, 1191 I40E_DMA_CNTX_SIZE_256K = 9, 1192}; 1193 1194/* Supported Hash look up table (LUT) sizes */ 1195enum i40e_hash_lut_size { 1196 I40E_HASH_LUT_SIZE_128 = 0, 1197 I40E_HASH_LUT_SIZE_512 = 1, 1198}; 1199 1200/* Structure to hold a per PF filter control settings */ 1201struct i40e_filter_control_settings { 1202 /* number of PE Quad Hash filter buckets */ 1203 enum i40e_hash_filter_size pe_filt_num; 1204 /* number of PE Quad Hash contexts */ 1205 enum i40e_dma_cntx_size pe_cntx_num; 1206 /* number of FCoE filter buckets */ 1207 enum i40e_hash_filter_size fcoe_filt_num; 1208 /* number of FCoE DDP contexts */ 1209 enum i40e_dma_cntx_size fcoe_cntx_num; 1210 /* size of the Hash LUT */ 1211 enum i40e_hash_lut_size hash_lut_size; 1212 /* enable FDIR filters for PF and its VFs */ 1213 bool enable_fdir; 1214 /* enable Ethertype filters for PF and its VFs */ 1215 bool enable_ethtype; 1216 /* enable MAC/VLAN filters for PF and its VFs */ 1217 bool enable_macvlan; 1218}; 1219 1220/* Structure to hold device level control filter counts */ 1221struct i40e_control_filter_stats { 1222 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1223 u16 etype_used; /* Used perfect EtherType filters */ 1224 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1225 u16 etype_free; /* Un-used perfect EtherType filters */ 1226}; 1227 1228enum i40e_reset_type { 1229 I40E_RESET_POR = 0, 1230 I40E_RESET_CORER = 1, 1231 I40E_RESET_GLOBR = 2, 1232 I40E_RESET_EMPR = 3, 1233}; 1234 1235/* RSS Hash Table Size */ 1236#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1237#endif /* _I40E_TYPE_H_ */ 1238