e1000_82575.c revision 72b36727080c712859d4b8b363ae5ddadb81a0d3
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27/* e1000_82575 28 * e1000_82576 29 */ 30 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 32 33#include <linux/types.h> 34#include <linux/if_ether.h> 35#include <linux/i2c.h> 36 37#include "e1000_mac.h" 38#include "e1000_82575.h" 39#include "e1000_i210.h" 40 41static s32 igb_get_invariants_82575(struct e1000_hw *); 42static s32 igb_acquire_phy_82575(struct e1000_hw *); 43static void igb_release_phy_82575(struct e1000_hw *); 44static s32 igb_acquire_nvm_82575(struct e1000_hw *); 45static void igb_release_nvm_82575(struct e1000_hw *); 46static s32 igb_check_for_link_82575(struct e1000_hw *); 47static s32 igb_get_cfg_done_82575(struct e1000_hw *); 48static s32 igb_init_hw_82575(struct e1000_hw *); 49static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 50static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 51static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); 52static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); 53static s32 igb_reset_hw_82575(struct e1000_hw *); 54static s32 igb_reset_hw_82580(struct e1000_hw *); 55static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 56static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 57static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 58static s32 igb_setup_copper_link_82575(struct e1000_hw *); 59static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 60static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 61static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 62static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 63static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 64 u16 *); 65static s32 igb_get_phy_id_82575(struct e1000_hw *); 66static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 67static bool igb_sgmii_active_82575(struct e1000_hw *); 68static s32 igb_reset_init_script_82575(struct e1000_hw *); 69static s32 igb_read_mac_addr_82575(struct e1000_hw *); 70static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 71static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 72static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 73static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 74static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 75static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 76static const u16 e1000_82580_rxpbs_table[] = 77 { 36, 72, 144, 1, 2, 4, 8, 16, 78 35, 70, 140 }; 79 80/** 81 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 82 * @hw: pointer to the HW structure 83 * 84 * Called to determine if the I2C pins are being used for I2C or as an 85 * external MDIO interface since the two options are mutually exclusive. 86 **/ 87static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 88{ 89 u32 reg = 0; 90 bool ext_mdio = false; 91 92 switch (hw->mac.type) { 93 case e1000_82575: 94 case e1000_82576: 95 reg = rd32(E1000_MDIC); 96 ext_mdio = !!(reg & E1000_MDIC_DEST); 97 break; 98 case e1000_82580: 99 case e1000_i350: 100 case e1000_i354: 101 case e1000_i210: 102 case e1000_i211: 103 reg = rd32(E1000_MDICNFG); 104 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 105 break; 106 default: 107 break; 108 } 109 return ext_mdio; 110} 111 112/** 113 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 114 * @hw: pointer to the HW structure 115 * 116 * Poll the M88E1112 interfaces to see which interface achieved link. 117 */ 118static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 119{ 120 struct e1000_phy_info *phy = &hw->phy; 121 s32 ret_val; 122 u16 data; 123 u8 port = 0; 124 125 /* Check the copper medium. */ 126 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 127 if (ret_val) 128 return ret_val; 129 130 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 131 if (ret_val) 132 return ret_val; 133 134 if (data & E1000_M88E1112_STATUS_LINK) 135 port = E1000_MEDIA_PORT_COPPER; 136 137 /* Check the other medium. */ 138 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 139 if (ret_val) 140 return ret_val; 141 142 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 143 if (ret_val) 144 return ret_val; 145 146 /* reset page to 0 */ 147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 148 if (ret_val) 149 return ret_val; 150 151 if (data & E1000_M88E1112_STATUS_LINK) 152 port = E1000_MEDIA_PORT_OTHER; 153 154 /* Determine if a swap needs to happen. */ 155 if (port && (hw->dev_spec._82575.media_port != port)) { 156 hw->dev_spec._82575.media_port = port; 157 hw->dev_spec._82575.media_changed = true; 158 } else { 159 ret_val = igb_check_for_link_82575(hw); 160 } 161 162 return E1000_SUCCESS; 163} 164 165/** 166 * igb_init_phy_params_82575 - Init PHY func ptrs. 167 * @hw: pointer to the HW structure 168 **/ 169static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 170{ 171 struct e1000_phy_info *phy = &hw->phy; 172 s32 ret_val = 0; 173 u32 ctrl_ext; 174 175 if (hw->phy.media_type != e1000_media_type_copper) { 176 phy->type = e1000_phy_none; 177 goto out; 178 } 179 180 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 181 phy->reset_delay_us = 100; 182 183 ctrl_ext = rd32(E1000_CTRL_EXT); 184 185 if (igb_sgmii_active_82575(hw)) { 186 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 187 ctrl_ext |= E1000_CTRL_I2C_ENA; 188 } else { 189 phy->ops.reset = igb_phy_hw_reset; 190 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 191 } 192 193 wr32(E1000_CTRL_EXT, ctrl_ext); 194 igb_reset_mdicnfg_82580(hw); 195 196 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 197 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 198 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 199 } else { 200 switch (hw->mac.type) { 201 case e1000_82580: 202 case e1000_i350: 203 case e1000_i354: 204 phy->ops.read_reg = igb_read_phy_reg_82580; 205 phy->ops.write_reg = igb_write_phy_reg_82580; 206 break; 207 case e1000_i210: 208 case e1000_i211: 209 phy->ops.read_reg = igb_read_phy_reg_gs40g; 210 phy->ops.write_reg = igb_write_phy_reg_gs40g; 211 break; 212 default: 213 phy->ops.read_reg = igb_read_phy_reg_igp; 214 phy->ops.write_reg = igb_write_phy_reg_igp; 215 } 216 } 217 218 /* set lan id */ 219 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 220 E1000_STATUS_FUNC_SHIFT; 221 222 /* Set phy->phy_addr and phy->id. */ 223 ret_val = igb_get_phy_id_82575(hw); 224 if (ret_val) 225 return ret_val; 226 227 /* Verify phy id and set remaining function pointers */ 228 switch (phy->id) { 229 case M88E1543_E_PHY_ID: 230 case I347AT4_E_PHY_ID: 231 case M88E1112_E_PHY_ID: 232 case M88E1111_I_PHY_ID: 233 phy->type = e1000_phy_m88; 234 phy->ops.check_polarity = igb_check_polarity_m88; 235 phy->ops.get_phy_info = igb_get_phy_info_m88; 236 if (phy->id != M88E1111_I_PHY_ID) 237 phy->ops.get_cable_length = 238 igb_get_cable_length_m88_gen2; 239 else 240 phy->ops.get_cable_length = igb_get_cable_length_m88; 241 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 242 /* Check if this PHY is confgured for media swap. */ 243 if (phy->id == M88E1112_E_PHY_ID) { 244 u16 data; 245 246 ret_val = phy->ops.write_reg(hw, 247 E1000_M88E1112_PAGE_ADDR, 248 2); 249 if (ret_val) 250 goto out; 251 252 ret_val = phy->ops.read_reg(hw, 253 E1000_M88E1112_MAC_CTRL_1, 254 &data); 255 if (ret_val) 256 goto out; 257 258 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 259 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 260 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 261 data == E1000_M88E1112_AUTO_COPPER_BASEX) 262 hw->mac.ops.check_for_link = 263 igb_check_for_link_media_swap; 264 } 265 break; 266 case IGP03E1000_E_PHY_ID: 267 phy->type = e1000_phy_igp_3; 268 phy->ops.get_phy_info = igb_get_phy_info_igp; 269 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 270 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 271 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 272 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 273 break; 274 case I82580_I_PHY_ID: 275 case I350_I_PHY_ID: 276 phy->type = e1000_phy_82580; 277 phy->ops.force_speed_duplex = 278 igb_phy_force_speed_duplex_82580; 279 phy->ops.get_cable_length = igb_get_cable_length_82580; 280 phy->ops.get_phy_info = igb_get_phy_info_82580; 281 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 282 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 283 break; 284 case I210_I_PHY_ID: 285 phy->type = e1000_phy_i210; 286 phy->ops.check_polarity = igb_check_polarity_m88; 287 phy->ops.get_phy_info = igb_get_phy_info_m88; 288 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 289 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 290 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 291 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 292 break; 293 default: 294 ret_val = -E1000_ERR_PHY; 295 goto out; 296 } 297 298out: 299 return ret_val; 300} 301 302/** 303 * igb_init_nvm_params_82575 - Init NVM func ptrs. 304 * @hw: pointer to the HW structure 305 **/ 306static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 307{ 308 struct e1000_nvm_info *nvm = &hw->nvm; 309 u32 eecd = rd32(E1000_EECD); 310 u16 size; 311 312 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 313 E1000_EECD_SIZE_EX_SHIFT); 314 315 /* Added to a constant, "size" becomes the left-shift value 316 * for setting word_size. 317 */ 318 size += NVM_WORD_SIZE_BASE_SHIFT; 319 320 /* Just in case size is out of range, cap it to the largest 321 * EEPROM size supported 322 */ 323 if (size > 15) 324 size = 15; 325 326 nvm->word_size = 1 << size; 327 nvm->opcode_bits = 8; 328 nvm->delay_usec = 1; 329 330 switch (nvm->override) { 331 case e1000_nvm_override_spi_large: 332 nvm->page_size = 32; 333 nvm->address_bits = 16; 334 break; 335 case e1000_nvm_override_spi_small: 336 nvm->page_size = 8; 337 nvm->address_bits = 8; 338 break; 339 default: 340 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 341 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 342 16 : 8; 343 break; 344 } 345 if (nvm->word_size == (1 << 15)) 346 nvm->page_size = 128; 347 348 nvm->type = e1000_nvm_eeprom_spi; 349 350 /* NVM Function Pointers */ 351 nvm->ops.acquire = igb_acquire_nvm_82575; 352 nvm->ops.release = igb_release_nvm_82575; 353 nvm->ops.write = igb_write_nvm_spi; 354 nvm->ops.validate = igb_validate_nvm_checksum; 355 nvm->ops.update = igb_update_nvm_checksum; 356 if (nvm->word_size < (1 << 15)) 357 nvm->ops.read = igb_read_nvm_eerd; 358 else 359 nvm->ops.read = igb_read_nvm_spi; 360 361 /* override generic family function pointers for specific descendants */ 362 switch (hw->mac.type) { 363 case e1000_82580: 364 nvm->ops.validate = igb_validate_nvm_checksum_82580; 365 nvm->ops.update = igb_update_nvm_checksum_82580; 366 break; 367 case e1000_i354: 368 case e1000_i350: 369 nvm->ops.validate = igb_validate_nvm_checksum_i350; 370 nvm->ops.update = igb_update_nvm_checksum_i350; 371 break; 372 default: 373 break; 374 } 375 376 return 0; 377} 378 379/** 380 * igb_init_mac_params_82575 - Init MAC func ptrs. 381 * @hw: pointer to the HW structure 382 **/ 383static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 384{ 385 struct e1000_mac_info *mac = &hw->mac; 386 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 387 388 /* Set mta register count */ 389 mac->mta_reg_count = 128; 390 /* Set rar entry count */ 391 switch (mac->type) { 392 case e1000_82576: 393 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 394 break; 395 case e1000_82580: 396 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 397 break; 398 case e1000_i350: 399 case e1000_i354: 400 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 401 break; 402 default: 403 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 404 break; 405 } 406 /* reset */ 407 if (mac->type >= e1000_82580) 408 mac->ops.reset_hw = igb_reset_hw_82580; 409 else 410 mac->ops.reset_hw = igb_reset_hw_82575; 411 412 if (mac->type >= e1000_i210) { 413 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 414 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 415 416 } else { 417 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 418 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 419 } 420 421 /* Set if part includes ASF firmware */ 422 mac->asf_firmware_present = true; 423 /* Set if manageability features are enabled. */ 424 mac->arc_subsystem_valid = 425 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 426 ? true : false; 427 /* enable EEE on i350 parts and later parts */ 428 if (mac->type >= e1000_i350) 429 dev_spec->eee_disable = false; 430 else 431 dev_spec->eee_disable = true; 432 /* Allow a single clear of the SW semaphore on I210 and newer */ 433 if (mac->type >= e1000_i210) 434 dev_spec->clear_semaphore_once = true; 435 /* physical interface link setup */ 436 mac->ops.setup_physical_interface = 437 (hw->phy.media_type == e1000_media_type_copper) 438 ? igb_setup_copper_link_82575 439 : igb_setup_serdes_link_82575; 440 441 if (mac->type == e1000_82580) { 442 switch (hw->device_id) { 443 /* feature not supported on these id's */ 444 case E1000_DEV_ID_DH89XXCC_SGMII: 445 case E1000_DEV_ID_DH89XXCC_SERDES: 446 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 447 case E1000_DEV_ID_DH89XXCC_SFP: 448 break; 449 default: 450 hw->dev_spec._82575.mas_capable = true; 451 break; 452 } 453 } 454 return 0; 455} 456 457/** 458 * igb_set_sfp_media_type_82575 - derives SFP module media type. 459 * @hw: pointer to the HW structure 460 * 461 * The media type is chosen based on SFP module. 462 * compatibility flags retrieved from SFP ID EEPROM. 463 **/ 464static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 465{ 466 s32 ret_val = E1000_ERR_CONFIG; 467 u32 ctrl_ext = 0; 468 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 469 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 470 u8 tranceiver_type = 0; 471 s32 timeout = 3; 472 473 /* Turn I2C interface ON and power on sfp cage */ 474 ctrl_ext = rd32(E1000_CTRL_EXT); 475 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 476 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 477 478 wrfl(); 479 480 /* Read SFP module data */ 481 while (timeout) { 482 ret_val = igb_read_sfp_data_byte(hw, 483 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 484 &tranceiver_type); 485 if (ret_val == 0) 486 break; 487 msleep(100); 488 timeout--; 489 } 490 if (ret_val != 0) 491 goto out; 492 493 ret_val = igb_read_sfp_data_byte(hw, 494 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 495 (u8 *)eth_flags); 496 if (ret_val != 0) 497 goto out; 498 499 /* Check if there is some SFP module plugged and powered */ 500 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 501 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 502 dev_spec->module_plugged = true; 503 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 504 hw->phy.media_type = e1000_media_type_internal_serdes; 505 } else if (eth_flags->e100_base_fx) { 506 dev_spec->sgmii_active = true; 507 hw->phy.media_type = e1000_media_type_internal_serdes; 508 } else if (eth_flags->e1000_base_t) { 509 dev_spec->sgmii_active = true; 510 hw->phy.media_type = e1000_media_type_copper; 511 } else { 512 hw->phy.media_type = e1000_media_type_unknown; 513 hw_dbg("PHY module has not been recognized\n"); 514 goto out; 515 } 516 } else { 517 hw->phy.media_type = e1000_media_type_unknown; 518 } 519 ret_val = 0; 520out: 521 /* Restore I2C interface setting */ 522 wr32(E1000_CTRL_EXT, ctrl_ext); 523 return ret_val; 524} 525 526static s32 igb_get_invariants_82575(struct e1000_hw *hw) 527{ 528 struct e1000_mac_info *mac = &hw->mac; 529 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; 530 s32 ret_val; 531 u32 ctrl_ext = 0; 532 u32 link_mode = 0; 533 534 switch (hw->device_id) { 535 case E1000_DEV_ID_82575EB_COPPER: 536 case E1000_DEV_ID_82575EB_FIBER_SERDES: 537 case E1000_DEV_ID_82575GB_QUAD_COPPER: 538 mac->type = e1000_82575; 539 break; 540 case E1000_DEV_ID_82576: 541 case E1000_DEV_ID_82576_NS: 542 case E1000_DEV_ID_82576_NS_SERDES: 543 case E1000_DEV_ID_82576_FIBER: 544 case E1000_DEV_ID_82576_SERDES: 545 case E1000_DEV_ID_82576_QUAD_COPPER: 546 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 547 case E1000_DEV_ID_82576_SERDES_QUAD: 548 mac->type = e1000_82576; 549 break; 550 case E1000_DEV_ID_82580_COPPER: 551 case E1000_DEV_ID_82580_FIBER: 552 case E1000_DEV_ID_82580_QUAD_FIBER: 553 case E1000_DEV_ID_82580_SERDES: 554 case E1000_DEV_ID_82580_SGMII: 555 case E1000_DEV_ID_82580_COPPER_DUAL: 556 case E1000_DEV_ID_DH89XXCC_SGMII: 557 case E1000_DEV_ID_DH89XXCC_SERDES: 558 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 559 case E1000_DEV_ID_DH89XXCC_SFP: 560 mac->type = e1000_82580; 561 break; 562 case E1000_DEV_ID_I350_COPPER: 563 case E1000_DEV_ID_I350_FIBER: 564 case E1000_DEV_ID_I350_SERDES: 565 case E1000_DEV_ID_I350_SGMII: 566 mac->type = e1000_i350; 567 break; 568 case E1000_DEV_ID_I210_COPPER: 569 case E1000_DEV_ID_I210_FIBER: 570 case E1000_DEV_ID_I210_SERDES: 571 case E1000_DEV_ID_I210_SGMII: 572 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 573 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 574 mac->type = e1000_i210; 575 break; 576 case E1000_DEV_ID_I211_COPPER: 577 mac->type = e1000_i211; 578 break; 579 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 580 case E1000_DEV_ID_I354_SGMII: 581 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 582 mac->type = e1000_i354; 583 break; 584 default: 585 return -E1000_ERR_MAC_INIT; 586 break; 587 } 588 589 /* Set media type */ 590 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 591 * based on the EEPROM. We cannot rely upon device ID. There 592 * is no distinguishable difference between fiber and internal 593 * SerDes mode on the 82575. There can be an external PHY attached 594 * on the SGMII interface. For this, we'll set sgmii_active to true. 595 */ 596 hw->phy.media_type = e1000_media_type_copper; 597 dev_spec->sgmii_active = false; 598 dev_spec->module_plugged = false; 599 600 ctrl_ext = rd32(E1000_CTRL_EXT); 601 602 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 603 switch (link_mode) { 604 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 605 hw->phy.media_type = e1000_media_type_internal_serdes; 606 break; 607 case E1000_CTRL_EXT_LINK_MODE_SGMII: 608 /* Get phy control interface type set (MDIO vs. I2C)*/ 609 if (igb_sgmii_uses_mdio_82575(hw)) { 610 hw->phy.media_type = e1000_media_type_copper; 611 dev_spec->sgmii_active = true; 612 break; 613 } 614 /* fall through for I2C based SGMII */ 615 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 616 /* read media type from SFP EEPROM */ 617 ret_val = igb_set_sfp_media_type_82575(hw); 618 if ((ret_val != 0) || 619 (hw->phy.media_type == e1000_media_type_unknown)) { 620 /* If media type was not identified then return media 621 * type defined by the CTRL_EXT settings. 622 */ 623 hw->phy.media_type = e1000_media_type_internal_serdes; 624 625 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 626 hw->phy.media_type = e1000_media_type_copper; 627 dev_spec->sgmii_active = true; 628 } 629 630 break; 631 } 632 633 /* do not change link mode for 100BaseFX */ 634 if (dev_spec->eth_flags.e100_base_fx) 635 break; 636 637 /* change current link mode setting */ 638 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 639 640 if (hw->phy.media_type == e1000_media_type_copper) 641 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 642 else 643 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 644 645 wr32(E1000_CTRL_EXT, ctrl_ext); 646 647 break; 648 default: 649 break; 650 } 651 652 /* mac initialization and operations */ 653 ret_val = igb_init_mac_params_82575(hw); 654 if (ret_val) 655 goto out; 656 657 /* NVM initialization */ 658 ret_val = igb_init_nvm_params_82575(hw); 659 switch (hw->mac.type) { 660 case e1000_i210: 661 case e1000_i211: 662 ret_val = igb_init_nvm_params_i210(hw); 663 break; 664 default: 665 break; 666 } 667 668 if (ret_val) 669 goto out; 670 671 /* if part supports SR-IOV then initialize mailbox parameters */ 672 switch (mac->type) { 673 case e1000_82576: 674 case e1000_i350: 675 igb_init_mbx_params_pf(hw); 676 break; 677 default: 678 break; 679 } 680 681 /* setup PHY parameters */ 682 ret_val = igb_init_phy_params_82575(hw); 683 684out: 685 return ret_val; 686} 687 688/** 689 * igb_acquire_phy_82575 - Acquire rights to access PHY 690 * @hw: pointer to the HW structure 691 * 692 * Acquire access rights to the correct PHY. This is a 693 * function pointer entry point called by the api module. 694 **/ 695static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 696{ 697 u16 mask = E1000_SWFW_PHY0_SM; 698 699 if (hw->bus.func == E1000_FUNC_1) 700 mask = E1000_SWFW_PHY1_SM; 701 else if (hw->bus.func == E1000_FUNC_2) 702 mask = E1000_SWFW_PHY2_SM; 703 else if (hw->bus.func == E1000_FUNC_3) 704 mask = E1000_SWFW_PHY3_SM; 705 706 return hw->mac.ops.acquire_swfw_sync(hw, mask); 707} 708 709/** 710 * igb_release_phy_82575 - Release rights to access PHY 711 * @hw: pointer to the HW structure 712 * 713 * A wrapper to release access rights to the correct PHY. This is a 714 * function pointer entry point called by the api module. 715 **/ 716static void igb_release_phy_82575(struct e1000_hw *hw) 717{ 718 u16 mask = E1000_SWFW_PHY0_SM; 719 720 if (hw->bus.func == E1000_FUNC_1) 721 mask = E1000_SWFW_PHY1_SM; 722 else if (hw->bus.func == E1000_FUNC_2) 723 mask = E1000_SWFW_PHY2_SM; 724 else if (hw->bus.func == E1000_FUNC_3) 725 mask = E1000_SWFW_PHY3_SM; 726 727 hw->mac.ops.release_swfw_sync(hw, mask); 728} 729 730/** 731 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 732 * @hw: pointer to the HW structure 733 * @offset: register offset to be read 734 * @data: pointer to the read data 735 * 736 * Reads the PHY register at offset using the serial gigabit media independent 737 * interface and stores the retrieved information in data. 738 **/ 739static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 740 u16 *data) 741{ 742 s32 ret_val = -E1000_ERR_PARAM; 743 744 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 745 hw_dbg("PHY Address %u is out of range\n", offset); 746 goto out; 747 } 748 749 ret_val = hw->phy.ops.acquire(hw); 750 if (ret_val) 751 goto out; 752 753 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 754 755 hw->phy.ops.release(hw); 756 757out: 758 return ret_val; 759} 760 761/** 762 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 763 * @hw: pointer to the HW structure 764 * @offset: register offset to write to 765 * @data: data to write at register offset 766 * 767 * Writes the data to PHY register at the offset using the serial gigabit 768 * media independent interface. 769 **/ 770static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 771 u16 data) 772{ 773 s32 ret_val = -E1000_ERR_PARAM; 774 775 776 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 777 hw_dbg("PHY Address %d is out of range\n", offset); 778 goto out; 779 } 780 781 ret_val = hw->phy.ops.acquire(hw); 782 if (ret_val) 783 goto out; 784 785 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 786 787 hw->phy.ops.release(hw); 788 789out: 790 return ret_val; 791} 792 793/** 794 * igb_get_phy_id_82575 - Retrieve PHY addr and id 795 * @hw: pointer to the HW structure 796 * 797 * Retrieves the PHY address and ID for both PHY's which do and do not use 798 * sgmi interface. 799 **/ 800static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 801{ 802 struct e1000_phy_info *phy = &hw->phy; 803 s32 ret_val = 0; 804 u16 phy_id; 805 u32 ctrl_ext; 806 u32 mdic; 807 808 /* Extra read required for some PHY's on i354 */ 809 if (hw->mac.type == e1000_i354) 810 igb_get_phy_id(hw); 811 812 /* For SGMII PHYs, we try the list of possible addresses until 813 * we find one that works. For non-SGMII PHYs 814 * (e.g. integrated copper PHYs), an address of 1 should 815 * work. The result of this function should mean phy->phy_addr 816 * and phy->id are set correctly. 817 */ 818 if (!(igb_sgmii_active_82575(hw))) { 819 phy->addr = 1; 820 ret_val = igb_get_phy_id(hw); 821 goto out; 822 } 823 824 if (igb_sgmii_uses_mdio_82575(hw)) { 825 switch (hw->mac.type) { 826 case e1000_82575: 827 case e1000_82576: 828 mdic = rd32(E1000_MDIC); 829 mdic &= E1000_MDIC_PHY_MASK; 830 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 831 break; 832 case e1000_82580: 833 case e1000_i350: 834 case e1000_i354: 835 case e1000_i210: 836 case e1000_i211: 837 mdic = rd32(E1000_MDICNFG); 838 mdic &= E1000_MDICNFG_PHY_MASK; 839 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 840 break; 841 default: 842 ret_val = -E1000_ERR_PHY; 843 goto out; 844 break; 845 } 846 ret_val = igb_get_phy_id(hw); 847 goto out; 848 } 849 850 /* Power on sgmii phy if it is disabled */ 851 ctrl_ext = rd32(E1000_CTRL_EXT); 852 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 853 wrfl(); 854 msleep(300); 855 856 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 857 * Therefore, we need to test 1-7 858 */ 859 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 860 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 861 if (ret_val == 0) { 862 hw_dbg("Vendor ID 0x%08X read at address %u\n", 863 phy_id, phy->addr); 864 /* At the time of this writing, The M88 part is 865 * the only supported SGMII PHY product. 866 */ 867 if (phy_id == M88_VENDOR) 868 break; 869 } else { 870 hw_dbg("PHY address %u was unreadable\n", phy->addr); 871 } 872 } 873 874 /* A valid PHY type couldn't be found. */ 875 if (phy->addr == 8) { 876 phy->addr = 0; 877 ret_val = -E1000_ERR_PHY; 878 goto out; 879 } else { 880 ret_val = igb_get_phy_id(hw); 881 } 882 883 /* restore previous sfp cage power state */ 884 wr32(E1000_CTRL_EXT, ctrl_ext); 885 886out: 887 return ret_val; 888} 889 890/** 891 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 892 * @hw: pointer to the HW structure 893 * 894 * Resets the PHY using the serial gigabit media independent interface. 895 **/ 896static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 897{ 898 s32 ret_val; 899 900 /* This isn't a true "hard" reset, but is the only reset 901 * available to us at this time. 902 */ 903 904 hw_dbg("Soft resetting SGMII attached PHY...\n"); 905 906 /* SFP documentation requires the following to configure the SPF module 907 * to work on SGMII. No further documentation is given. 908 */ 909 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 910 if (ret_val) 911 goto out; 912 913 ret_val = igb_phy_sw_reset(hw); 914 915out: 916 return ret_val; 917} 918 919/** 920 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 921 * @hw: pointer to the HW structure 922 * @active: true to enable LPLU, false to disable 923 * 924 * Sets the LPLU D0 state according to the active flag. When 925 * activating LPLU this function also disables smart speed 926 * and vice versa. LPLU will not be activated unless the 927 * device autonegotiation advertisement meets standards of 928 * either 10 or 10/100 or 10/100/1000 at all duplexes. 929 * This is a function pointer entry point only called by 930 * PHY setup routines. 931 **/ 932static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 933{ 934 struct e1000_phy_info *phy = &hw->phy; 935 s32 ret_val; 936 u16 data; 937 938 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 939 if (ret_val) 940 goto out; 941 942 if (active) { 943 data |= IGP02E1000_PM_D0_LPLU; 944 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 945 data); 946 if (ret_val) 947 goto out; 948 949 /* When LPLU is enabled, we should disable SmartSpeed */ 950 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 951 &data); 952 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 953 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 954 data); 955 if (ret_val) 956 goto out; 957 } else { 958 data &= ~IGP02E1000_PM_D0_LPLU; 959 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 960 data); 961 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 962 * during Dx states where the power conservation is most 963 * important. During driver activity we should enable 964 * SmartSpeed, so performance is maintained. 965 */ 966 if (phy->smart_speed == e1000_smart_speed_on) { 967 ret_val = phy->ops.read_reg(hw, 968 IGP01E1000_PHY_PORT_CONFIG, &data); 969 if (ret_val) 970 goto out; 971 972 data |= IGP01E1000_PSCFR_SMART_SPEED; 973 ret_val = phy->ops.write_reg(hw, 974 IGP01E1000_PHY_PORT_CONFIG, data); 975 if (ret_val) 976 goto out; 977 } else if (phy->smart_speed == e1000_smart_speed_off) { 978 ret_val = phy->ops.read_reg(hw, 979 IGP01E1000_PHY_PORT_CONFIG, &data); 980 if (ret_val) 981 goto out; 982 983 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 984 ret_val = phy->ops.write_reg(hw, 985 IGP01E1000_PHY_PORT_CONFIG, data); 986 if (ret_val) 987 goto out; 988 } 989 } 990 991out: 992 return ret_val; 993} 994 995/** 996 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 997 * @hw: pointer to the HW structure 998 * @active: true to enable LPLU, false to disable 999 * 1000 * Sets the LPLU D0 state according to the active flag. When 1001 * activating LPLU this function also disables smart speed 1002 * and vice versa. LPLU will not be activated unless the 1003 * device autonegotiation advertisement meets standards of 1004 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1005 * This is a function pointer entry point only called by 1006 * PHY setup routines. 1007 **/ 1008static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1009{ 1010 struct e1000_phy_info *phy = &hw->phy; 1011 s32 ret_val = 0; 1012 u16 data; 1013 1014 data = rd32(E1000_82580_PHY_POWER_MGMT); 1015 1016 if (active) { 1017 data |= E1000_82580_PM_D0_LPLU; 1018 1019 /* When LPLU is enabled, we should disable SmartSpeed */ 1020 data &= ~E1000_82580_PM_SPD; 1021 } else { 1022 data &= ~E1000_82580_PM_D0_LPLU; 1023 1024 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1025 * during Dx states where the power conservation is most 1026 * important. During driver activity we should enable 1027 * SmartSpeed, so performance is maintained. 1028 */ 1029 if (phy->smart_speed == e1000_smart_speed_on) 1030 data |= E1000_82580_PM_SPD; 1031 else if (phy->smart_speed == e1000_smart_speed_off) 1032 data &= ~E1000_82580_PM_SPD; } 1033 1034 wr32(E1000_82580_PHY_POWER_MGMT, data); 1035 return ret_val; 1036} 1037 1038/** 1039 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1040 * @hw: pointer to the HW structure 1041 * @active: boolean used to enable/disable lplu 1042 * 1043 * Success returns 0, Failure returns 1 1044 * 1045 * The low power link up (lplu) state is set to the power management level D3 1046 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1047 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1048 * is used during Dx states where the power conservation is most important. 1049 * During driver activity, SmartSpeed should be enabled so performance is 1050 * maintained. 1051 **/ 1052static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1053{ 1054 struct e1000_phy_info *phy = &hw->phy; 1055 s32 ret_val = 0; 1056 u16 data; 1057 1058 data = rd32(E1000_82580_PHY_POWER_MGMT); 1059 1060 if (!active) { 1061 data &= ~E1000_82580_PM_D3_LPLU; 1062 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1063 * during Dx states where the power conservation is most 1064 * important. During driver activity we should enable 1065 * SmartSpeed, so performance is maintained. 1066 */ 1067 if (phy->smart_speed == e1000_smart_speed_on) 1068 data |= E1000_82580_PM_SPD; 1069 else if (phy->smart_speed == e1000_smart_speed_off) 1070 data &= ~E1000_82580_PM_SPD; 1071 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1072 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1073 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1074 data |= E1000_82580_PM_D3_LPLU; 1075 /* When LPLU is enabled, we should disable SmartSpeed */ 1076 data &= ~E1000_82580_PM_SPD; 1077 } 1078 1079 wr32(E1000_82580_PHY_POWER_MGMT, data); 1080 return ret_val; 1081} 1082 1083/** 1084 * igb_acquire_nvm_82575 - Request for access to EEPROM 1085 * @hw: pointer to the HW structure 1086 * 1087 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1088 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1089 * Return successful if access grant bit set, else clear the request for 1090 * EEPROM access and return -E1000_ERR_NVM (-1). 1091 **/ 1092static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1093{ 1094 s32 ret_val; 1095 1096 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1097 if (ret_val) 1098 goto out; 1099 1100 ret_val = igb_acquire_nvm(hw); 1101 1102 if (ret_val) 1103 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1104 1105out: 1106 return ret_val; 1107} 1108 1109/** 1110 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1111 * @hw: pointer to the HW structure 1112 * 1113 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1114 * then release the semaphores acquired. 1115 **/ 1116static void igb_release_nvm_82575(struct e1000_hw *hw) 1117{ 1118 igb_release_nvm(hw); 1119 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1120} 1121 1122/** 1123 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1124 * @hw: pointer to the HW structure 1125 * @mask: specifies which semaphore to acquire 1126 * 1127 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1128 * will also specify which port we're acquiring the lock for. 1129 **/ 1130static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1131{ 1132 u32 swfw_sync; 1133 u32 swmask = mask; 1134 u32 fwmask = mask << 16; 1135 s32 ret_val = 0; 1136 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 1137 1138 while (i < timeout) { 1139 if (igb_get_hw_semaphore(hw)) { 1140 ret_val = -E1000_ERR_SWFW_SYNC; 1141 goto out; 1142 } 1143 1144 swfw_sync = rd32(E1000_SW_FW_SYNC); 1145 if (!(swfw_sync & (fwmask | swmask))) 1146 break; 1147 1148 /* Firmware currently using resource (fwmask) 1149 * or other software thread using resource (swmask) 1150 */ 1151 igb_put_hw_semaphore(hw); 1152 mdelay(5); 1153 i++; 1154 } 1155 1156 if (i == timeout) { 1157 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1158 ret_val = -E1000_ERR_SWFW_SYNC; 1159 goto out; 1160 } 1161 1162 swfw_sync |= swmask; 1163 wr32(E1000_SW_FW_SYNC, swfw_sync); 1164 1165 igb_put_hw_semaphore(hw); 1166 1167out: 1168 return ret_val; 1169} 1170 1171/** 1172 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1173 * @hw: pointer to the HW structure 1174 * @mask: specifies which semaphore to acquire 1175 * 1176 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1177 * will also specify which port we're releasing the lock for. 1178 **/ 1179static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1180{ 1181 u32 swfw_sync; 1182 1183 while (igb_get_hw_semaphore(hw) != 0); 1184 /* Empty */ 1185 1186 swfw_sync = rd32(E1000_SW_FW_SYNC); 1187 swfw_sync &= ~mask; 1188 wr32(E1000_SW_FW_SYNC, swfw_sync); 1189 1190 igb_put_hw_semaphore(hw); 1191} 1192 1193/** 1194 * igb_get_cfg_done_82575 - Read config done bit 1195 * @hw: pointer to the HW structure 1196 * 1197 * Read the management control register for the config done bit for 1198 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1199 * to read the config done bit, so an error is *ONLY* logged and returns 1200 * 0. If we were to return with error, EEPROM-less silicon 1201 * would not be able to be reset or change link. 1202 **/ 1203static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1204{ 1205 s32 timeout = PHY_CFG_TIMEOUT; 1206 s32 ret_val = 0; 1207 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1208 1209 if (hw->bus.func == 1) 1210 mask = E1000_NVM_CFG_DONE_PORT_1; 1211 else if (hw->bus.func == E1000_FUNC_2) 1212 mask = E1000_NVM_CFG_DONE_PORT_2; 1213 else if (hw->bus.func == E1000_FUNC_3) 1214 mask = E1000_NVM_CFG_DONE_PORT_3; 1215 1216 while (timeout) { 1217 if (rd32(E1000_EEMNGCTL) & mask) 1218 break; 1219 msleep(1); 1220 timeout--; 1221 } 1222 if (!timeout) 1223 hw_dbg("MNG configuration cycle has not completed.\n"); 1224 1225 /* If EEPROM is not marked present, init the PHY manually */ 1226 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1227 (hw->phy.type == e1000_phy_igp_3)) 1228 igb_phy_init_script_igp3(hw); 1229 1230 return ret_val; 1231} 1232 1233/** 1234 * igb_get_link_up_info_82575 - Get link speed/duplex info 1235 * @hw: pointer to the HW structure 1236 * @speed: stores the current speed 1237 * @duplex: stores the current duplex 1238 * 1239 * This is a wrapper function, if using the serial gigabit media independent 1240 * interface, use PCS to retrieve the link speed and duplex information. 1241 * Otherwise, use the generic function to get the link speed and duplex info. 1242 **/ 1243static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1244 u16 *duplex) 1245{ 1246 s32 ret_val; 1247 1248 if (hw->phy.media_type != e1000_media_type_copper) 1249 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1250 duplex); 1251 else 1252 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1253 duplex); 1254 1255 return ret_val; 1256} 1257 1258/** 1259 * igb_check_for_link_82575 - Check for link 1260 * @hw: pointer to the HW structure 1261 * 1262 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1263 * use the generic interface for determining link. 1264 **/ 1265static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1266{ 1267 s32 ret_val; 1268 u16 speed, duplex; 1269 1270 if (hw->phy.media_type != e1000_media_type_copper) { 1271 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1272 &duplex); 1273 /* Use this flag to determine if link needs to be checked or 1274 * not. If we have link clear the flag so that we do not 1275 * continue to check for link. 1276 */ 1277 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1278 1279 /* Configure Flow Control now that Auto-Neg has completed. 1280 * First, we need to restore the desired flow control 1281 * settings because we may have had to re-autoneg with a 1282 * different link partner. 1283 */ 1284 ret_val = igb_config_fc_after_link_up(hw); 1285 if (ret_val) 1286 hw_dbg("Error configuring flow control\n"); 1287 } else { 1288 ret_val = igb_check_for_copper_link(hw); 1289 } 1290 1291 return ret_val; 1292} 1293 1294/** 1295 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1296 * @hw: pointer to the HW structure 1297 **/ 1298void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1299{ 1300 u32 reg; 1301 1302 1303 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1304 !igb_sgmii_active_82575(hw)) 1305 return; 1306 1307 /* Enable PCS to turn on link */ 1308 reg = rd32(E1000_PCS_CFG0); 1309 reg |= E1000_PCS_CFG_PCS_EN; 1310 wr32(E1000_PCS_CFG0, reg); 1311 1312 /* Power up the laser */ 1313 reg = rd32(E1000_CTRL_EXT); 1314 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1315 wr32(E1000_CTRL_EXT, reg); 1316 1317 /* flush the write to verify completion */ 1318 wrfl(); 1319 msleep(1); 1320} 1321 1322/** 1323 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1324 * @hw: pointer to the HW structure 1325 * @speed: stores the current speed 1326 * @duplex: stores the current duplex 1327 * 1328 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1329 * duplex, then store the values in the pointers provided. 1330 **/ 1331static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1332 u16 *duplex) 1333{ 1334 struct e1000_mac_info *mac = &hw->mac; 1335 u32 pcs, status; 1336 1337 /* Set up defaults for the return values of this function */ 1338 mac->serdes_has_link = false; 1339 *speed = 0; 1340 *duplex = 0; 1341 1342 /* Read the PCS Status register for link state. For non-copper mode, 1343 * the status register is not accurate. The PCS status register is 1344 * used instead. 1345 */ 1346 pcs = rd32(E1000_PCS_LSTAT); 1347 1348 /* The link up bit determines when link is up on autoneg. The sync ok 1349 * gets set once both sides sync up and agree upon link. Stable link 1350 * can be determined by checking for both link up and link sync ok 1351 */ 1352 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1353 mac->serdes_has_link = true; 1354 1355 /* Detect and store PCS speed */ 1356 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1357 *speed = SPEED_1000; 1358 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1359 *speed = SPEED_100; 1360 else 1361 *speed = SPEED_10; 1362 1363 /* Detect and store PCS duplex */ 1364 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1365 *duplex = FULL_DUPLEX; 1366 else 1367 *duplex = HALF_DUPLEX; 1368 1369 /* Check if it is an I354 2.5Gb backplane connection. */ 1370 if (mac->type == e1000_i354) { 1371 status = rd32(E1000_STATUS); 1372 if ((status & E1000_STATUS_2P5_SKU) && 1373 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1374 *speed = SPEED_2500; 1375 *duplex = FULL_DUPLEX; 1376 hw_dbg("2500 Mbs, "); 1377 hw_dbg("Full Duplex\n"); 1378 } 1379 } 1380 1381 } 1382 1383 return 0; 1384} 1385 1386/** 1387 * igb_shutdown_serdes_link_82575 - Remove link during power down 1388 * @hw: pointer to the HW structure 1389 * 1390 * In the case of fiber serdes, shut down optics and PCS on driver unload 1391 * when management pass thru is not enabled. 1392 **/ 1393void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1394{ 1395 u32 reg; 1396 1397 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1398 igb_sgmii_active_82575(hw)) 1399 return; 1400 1401 if (!igb_enable_mng_pass_thru(hw)) { 1402 /* Disable PCS to turn off link */ 1403 reg = rd32(E1000_PCS_CFG0); 1404 reg &= ~E1000_PCS_CFG_PCS_EN; 1405 wr32(E1000_PCS_CFG0, reg); 1406 1407 /* shutdown the laser */ 1408 reg = rd32(E1000_CTRL_EXT); 1409 reg |= E1000_CTRL_EXT_SDP3_DATA; 1410 wr32(E1000_CTRL_EXT, reg); 1411 1412 /* flush the write to verify completion */ 1413 wrfl(); 1414 msleep(1); 1415 } 1416} 1417 1418/** 1419 * igb_reset_hw_82575 - Reset hardware 1420 * @hw: pointer to the HW structure 1421 * 1422 * This resets the hardware into a known state. This is a 1423 * function pointer entry point called by the api module. 1424 **/ 1425static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1426{ 1427 u32 ctrl; 1428 s32 ret_val; 1429 1430 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1431 * on the last TLP read/write transaction when MAC is reset. 1432 */ 1433 ret_val = igb_disable_pcie_master(hw); 1434 if (ret_val) 1435 hw_dbg("PCI-E Master disable polling has failed.\n"); 1436 1437 /* set the completion timeout for interface */ 1438 ret_val = igb_set_pcie_completion_timeout(hw); 1439 if (ret_val) { 1440 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1441 } 1442 1443 hw_dbg("Masking off all interrupts\n"); 1444 wr32(E1000_IMC, 0xffffffff); 1445 1446 wr32(E1000_RCTL, 0); 1447 wr32(E1000_TCTL, E1000_TCTL_PSP); 1448 wrfl(); 1449 1450 msleep(10); 1451 1452 ctrl = rd32(E1000_CTRL); 1453 1454 hw_dbg("Issuing a global reset to MAC\n"); 1455 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1456 1457 ret_val = igb_get_auto_rd_done(hw); 1458 if (ret_val) { 1459 /* When auto config read does not complete, do not 1460 * return with an error. This can happen in situations 1461 * where there is no eeprom and prevents getting link. 1462 */ 1463 hw_dbg("Auto Read Done did not complete\n"); 1464 } 1465 1466 /* If EEPROM is not present, run manual init scripts */ 1467 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1468 igb_reset_init_script_82575(hw); 1469 1470 /* Clear any pending interrupt events. */ 1471 wr32(E1000_IMC, 0xffffffff); 1472 rd32(E1000_ICR); 1473 1474 /* Install any alternate MAC address into RAR0 */ 1475 ret_val = igb_check_alt_mac_addr(hw); 1476 1477 return ret_val; 1478} 1479 1480/** 1481 * igb_init_hw_82575 - Initialize hardware 1482 * @hw: pointer to the HW structure 1483 * 1484 * This inits the hardware readying it for operation. 1485 **/ 1486static s32 igb_init_hw_82575(struct e1000_hw *hw) 1487{ 1488 struct e1000_mac_info *mac = &hw->mac; 1489 s32 ret_val; 1490 u16 i, rar_count = mac->rar_entry_count; 1491 1492 /* Initialize identification LED */ 1493 ret_val = igb_id_led_init(hw); 1494 if (ret_val) { 1495 hw_dbg("Error initializing identification LED\n"); 1496 /* This is not fatal and we should not stop init due to this */ 1497 } 1498 1499 /* Disabling VLAN filtering */ 1500 hw_dbg("Initializing the IEEE VLAN\n"); 1501 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 1502 igb_clear_vfta_i350(hw); 1503 else 1504 igb_clear_vfta(hw); 1505 1506 /* Setup the receive address */ 1507 igb_init_rx_addrs(hw, rar_count); 1508 1509 /* Zero out the Multicast HASH table */ 1510 hw_dbg("Zeroing the MTA\n"); 1511 for (i = 0; i < mac->mta_reg_count; i++) 1512 array_wr32(E1000_MTA, i, 0); 1513 1514 /* Zero out the Unicast HASH table */ 1515 hw_dbg("Zeroing the UTA\n"); 1516 for (i = 0; i < mac->uta_reg_count; i++) 1517 array_wr32(E1000_UTA, i, 0); 1518 1519 /* Setup link and flow control */ 1520 ret_val = igb_setup_link(hw); 1521 1522 /* Clear all of the statistics registers (clear on read). It is 1523 * important that we do this after we have tried to establish link 1524 * because the symbol error count will increment wildly if there 1525 * is no link. 1526 */ 1527 igb_clear_hw_cntrs_82575(hw); 1528 return ret_val; 1529} 1530 1531/** 1532 * igb_setup_copper_link_82575 - Configure copper link settings 1533 * @hw: pointer to the HW structure 1534 * 1535 * Configures the link for auto-neg or forced speed and duplex. Then we check 1536 * for link, once link is established calls to configure collision distance 1537 * and flow control are called. 1538 **/ 1539static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1540{ 1541 u32 ctrl; 1542 s32 ret_val; 1543 u32 phpm_reg; 1544 1545 ctrl = rd32(E1000_CTRL); 1546 ctrl |= E1000_CTRL_SLU; 1547 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1548 wr32(E1000_CTRL, ctrl); 1549 1550 /* Clear Go Link Disconnect bit on supported devices */ 1551 switch (hw->mac.type) { 1552 case e1000_82580: 1553 case e1000_i350: 1554 case e1000_i210: 1555 case e1000_i211: 1556 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1557 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1558 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 ret_val = igb_setup_serdes_link_82575(hw); 1565 if (ret_val) 1566 goto out; 1567 1568 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1569 /* allow time for SFP cage time to power up phy */ 1570 msleep(300); 1571 1572 ret_val = hw->phy.ops.reset(hw); 1573 if (ret_val) { 1574 hw_dbg("Error resetting the PHY.\n"); 1575 goto out; 1576 } 1577 } 1578 switch (hw->phy.type) { 1579 case e1000_phy_i210: 1580 case e1000_phy_m88: 1581 switch (hw->phy.id) { 1582 case I347AT4_E_PHY_ID: 1583 case M88E1112_E_PHY_ID: 1584 case M88E1543_E_PHY_ID: 1585 case I210_I_PHY_ID: 1586 ret_val = igb_copper_link_setup_m88_gen2(hw); 1587 break; 1588 default: 1589 ret_val = igb_copper_link_setup_m88(hw); 1590 break; 1591 } 1592 break; 1593 case e1000_phy_igp_3: 1594 ret_val = igb_copper_link_setup_igp(hw); 1595 break; 1596 case e1000_phy_82580: 1597 ret_val = igb_copper_link_setup_82580(hw); 1598 break; 1599 default: 1600 ret_val = -E1000_ERR_PHY; 1601 break; 1602 } 1603 1604 if (ret_val) 1605 goto out; 1606 1607 ret_val = igb_setup_copper_link(hw); 1608out: 1609 return ret_val; 1610} 1611 1612/** 1613 * igb_setup_serdes_link_82575 - Setup link for serdes 1614 * @hw: pointer to the HW structure 1615 * 1616 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1617 * used on copper connections where the serialized gigabit media independent 1618 * interface (sgmii), or serdes fiber is being used. Configures the link 1619 * for auto-negotiation or forces speed/duplex. 1620 **/ 1621static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1622{ 1623 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1624 bool pcs_autoneg; 1625 s32 ret_val = E1000_SUCCESS; 1626 u16 data; 1627 1628 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1629 !igb_sgmii_active_82575(hw)) 1630 return ret_val; 1631 1632 1633 /* On the 82575, SerDes loopback mode persists until it is 1634 * explicitly turned off or a power cycle is performed. A read to 1635 * the register does not indicate its status. Therefore, we ensure 1636 * loopback mode is disabled during initialization. 1637 */ 1638 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1639 1640 /* power on the sfp cage if present and turn on I2C */ 1641 ctrl_ext = rd32(E1000_CTRL_EXT); 1642 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1643 ctrl_ext |= E1000_CTRL_I2C_ENA; 1644 wr32(E1000_CTRL_EXT, ctrl_ext); 1645 1646 ctrl_reg = rd32(E1000_CTRL); 1647 ctrl_reg |= E1000_CTRL_SLU; 1648 1649 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1650 /* set both sw defined pins */ 1651 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1652 1653 /* Set switch control to serdes energy detect */ 1654 reg = rd32(E1000_CONNSW); 1655 reg |= E1000_CONNSW_ENRGSRC; 1656 wr32(E1000_CONNSW, reg); 1657 } 1658 1659 reg = rd32(E1000_PCS_LCTL); 1660 1661 /* default pcs_autoneg to the same setting as mac autoneg */ 1662 pcs_autoneg = hw->mac.autoneg; 1663 1664 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1665 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1666 /* sgmii mode lets the phy handle forcing speed/duplex */ 1667 pcs_autoneg = true; 1668 /* autoneg time out should be disabled for SGMII mode */ 1669 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1670 break; 1671 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1672 /* disable PCS autoneg and support parallel detect only */ 1673 pcs_autoneg = false; 1674 default: 1675 if (hw->mac.type == e1000_82575 || 1676 hw->mac.type == e1000_82576) { 1677 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1678 if (ret_val) { 1679 printk(KERN_DEBUG "NVM Read Error\n\n"); 1680 return ret_val; 1681 } 1682 1683 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1684 pcs_autoneg = false; 1685 } 1686 1687 /* non-SGMII modes only supports a speed of 1000/Full for the 1688 * link so it is best to just force the MAC and let the pcs 1689 * link either autoneg or be forced to 1000/Full 1690 */ 1691 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1692 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1693 1694 /* set speed of 1000/Full if speed/duplex is forced */ 1695 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1696 break; 1697 } 1698 1699 wr32(E1000_CTRL, ctrl_reg); 1700 1701 /* New SerDes mode allows for forcing speed or autonegotiating speed 1702 * at 1gb. Autoneg should be default set by most drivers. This is the 1703 * mode that will be compatible with older link partners and switches. 1704 * However, both are supported by the hardware and some drivers/tools. 1705 */ 1706 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1707 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1708 1709 if (pcs_autoneg) { 1710 /* Set PCS register for autoneg */ 1711 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1712 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1713 1714 /* Disable force flow control for autoneg */ 1715 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1716 1717 /* Configure flow control advertisement for autoneg */ 1718 anadv_reg = rd32(E1000_PCS_ANADV); 1719 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1720 switch (hw->fc.requested_mode) { 1721 case e1000_fc_full: 1722 case e1000_fc_rx_pause: 1723 anadv_reg |= E1000_TXCW_ASM_DIR; 1724 anadv_reg |= E1000_TXCW_PAUSE; 1725 break; 1726 case e1000_fc_tx_pause: 1727 anadv_reg |= E1000_TXCW_ASM_DIR; 1728 break; 1729 default: 1730 break; 1731 } 1732 wr32(E1000_PCS_ANADV, anadv_reg); 1733 1734 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1735 } else { 1736 /* Set PCS register for forced link */ 1737 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1738 1739 /* Force flow control for forced link */ 1740 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1741 1742 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1743 } 1744 1745 wr32(E1000_PCS_LCTL, reg); 1746 1747 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1748 igb_force_mac_fc(hw); 1749 1750 return ret_val; 1751} 1752 1753/** 1754 * igb_sgmii_active_82575 - Return sgmii state 1755 * @hw: pointer to the HW structure 1756 * 1757 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1758 * which can be enabled for use in the embedded applications. Simply 1759 * return the current state of the sgmii interface. 1760 **/ 1761static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1762{ 1763 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1764 return dev_spec->sgmii_active; 1765} 1766 1767/** 1768 * igb_reset_init_script_82575 - Inits HW defaults after reset 1769 * @hw: pointer to the HW structure 1770 * 1771 * Inits recommended HW defaults after a reset when there is no EEPROM 1772 * detected. This is only for the 82575. 1773 **/ 1774static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1775{ 1776 if (hw->mac.type == e1000_82575) { 1777 hw_dbg("Running reset init script for 82575\n"); 1778 /* SerDes configuration via SERDESCTRL */ 1779 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1780 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1781 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1782 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1783 1784 /* CCM configuration via CCMCTL register */ 1785 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1786 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1787 1788 /* PCIe lanes configuration */ 1789 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1790 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1791 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1792 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1793 1794 /* PCIe PLL Configuration */ 1795 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1796 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1797 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1798 } 1799 1800 return 0; 1801} 1802 1803/** 1804 * igb_read_mac_addr_82575 - Read device MAC address 1805 * @hw: pointer to the HW structure 1806 **/ 1807static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1808{ 1809 s32 ret_val = 0; 1810 1811 /* If there's an alternate MAC address place it in RAR0 1812 * so that it will override the Si installed default perm 1813 * address. 1814 */ 1815 ret_val = igb_check_alt_mac_addr(hw); 1816 if (ret_val) 1817 goto out; 1818 1819 ret_val = igb_read_mac_addr(hw); 1820 1821out: 1822 return ret_val; 1823} 1824 1825/** 1826 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1827 * @hw: pointer to the HW structure 1828 * 1829 * In the case of a PHY power down to save power, or to turn off link during a 1830 * driver unload, or wake on lan is not enabled, remove the link. 1831 **/ 1832void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1833{ 1834 /* If the management interface is not enabled, then power down */ 1835 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1836 igb_power_down_phy_copper(hw); 1837} 1838 1839/** 1840 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1841 * @hw: pointer to the HW structure 1842 * 1843 * Clears the hardware counters by reading the counter registers. 1844 **/ 1845static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1846{ 1847 igb_clear_hw_cntrs_base(hw); 1848 1849 rd32(E1000_PRC64); 1850 rd32(E1000_PRC127); 1851 rd32(E1000_PRC255); 1852 rd32(E1000_PRC511); 1853 rd32(E1000_PRC1023); 1854 rd32(E1000_PRC1522); 1855 rd32(E1000_PTC64); 1856 rd32(E1000_PTC127); 1857 rd32(E1000_PTC255); 1858 rd32(E1000_PTC511); 1859 rd32(E1000_PTC1023); 1860 rd32(E1000_PTC1522); 1861 1862 rd32(E1000_ALGNERRC); 1863 rd32(E1000_RXERRC); 1864 rd32(E1000_TNCRS); 1865 rd32(E1000_CEXTERR); 1866 rd32(E1000_TSCTC); 1867 rd32(E1000_TSCTFC); 1868 1869 rd32(E1000_MGTPRC); 1870 rd32(E1000_MGTPDC); 1871 rd32(E1000_MGTPTC); 1872 1873 rd32(E1000_IAC); 1874 rd32(E1000_ICRXOC); 1875 1876 rd32(E1000_ICRXPTC); 1877 rd32(E1000_ICRXATC); 1878 rd32(E1000_ICTXPTC); 1879 rd32(E1000_ICTXATC); 1880 rd32(E1000_ICTXQEC); 1881 rd32(E1000_ICTXQMTC); 1882 rd32(E1000_ICRXDMTC); 1883 1884 rd32(E1000_CBTMPC); 1885 rd32(E1000_HTDPMC); 1886 rd32(E1000_CBRMPC); 1887 rd32(E1000_RPTHC); 1888 rd32(E1000_HGPTC); 1889 rd32(E1000_HTCBDPC); 1890 rd32(E1000_HGORCL); 1891 rd32(E1000_HGORCH); 1892 rd32(E1000_HGOTCL); 1893 rd32(E1000_HGOTCH); 1894 rd32(E1000_LENERRS); 1895 1896 /* This register should not be read in copper configurations */ 1897 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1898 igb_sgmii_active_82575(hw)) 1899 rd32(E1000_SCVPC); 1900} 1901 1902/** 1903 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1904 * @hw: pointer to the HW structure 1905 * 1906 * After rx enable if managability is enabled then there is likely some 1907 * bad data at the start of the fifo and possibly in the DMA fifo. This 1908 * function clears the fifos and flushes any packets that came in as rx was 1909 * being enabled. 1910 **/ 1911void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1912{ 1913 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1914 int i, ms_wait; 1915 1916 if (hw->mac.type != e1000_82575 || 1917 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1918 return; 1919 1920 /* Disable all RX queues */ 1921 for (i = 0; i < 4; i++) { 1922 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1923 wr32(E1000_RXDCTL(i), 1924 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1925 } 1926 /* Poll all queues to verify they have shut down */ 1927 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1928 msleep(1); 1929 rx_enabled = 0; 1930 for (i = 0; i < 4; i++) 1931 rx_enabled |= rd32(E1000_RXDCTL(i)); 1932 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1933 break; 1934 } 1935 1936 if (ms_wait == 10) 1937 hw_dbg("Queue disable timed out after 10ms\n"); 1938 1939 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1940 * incoming packets are rejected. Set enable and wait 2ms so that 1941 * any packet that was coming in as RCTL.EN was set is flushed 1942 */ 1943 rfctl = rd32(E1000_RFCTL); 1944 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1945 1946 rlpml = rd32(E1000_RLPML); 1947 wr32(E1000_RLPML, 0); 1948 1949 rctl = rd32(E1000_RCTL); 1950 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1951 temp_rctl |= E1000_RCTL_LPE; 1952 1953 wr32(E1000_RCTL, temp_rctl); 1954 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1955 wrfl(); 1956 msleep(2); 1957 1958 /* Enable RX queues that were previously enabled and restore our 1959 * previous state 1960 */ 1961 for (i = 0; i < 4; i++) 1962 wr32(E1000_RXDCTL(i), rxdctl[i]); 1963 wr32(E1000_RCTL, rctl); 1964 wrfl(); 1965 1966 wr32(E1000_RLPML, rlpml); 1967 wr32(E1000_RFCTL, rfctl); 1968 1969 /* Flush receive errors generated by workaround */ 1970 rd32(E1000_ROC); 1971 rd32(E1000_RNBC); 1972 rd32(E1000_MPC); 1973} 1974 1975/** 1976 * igb_set_pcie_completion_timeout - set pci-e completion timeout 1977 * @hw: pointer to the HW structure 1978 * 1979 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1980 * however the hardware default for these parts is 500us to 1ms which is less 1981 * than the 10ms recommended by the pci-e spec. To address this we need to 1982 * increase the value to either 10ms to 200ms for capability version 1 config, 1983 * or 16ms to 55ms for version 2. 1984 **/ 1985static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 1986{ 1987 u32 gcr = rd32(E1000_GCR); 1988 s32 ret_val = 0; 1989 u16 pcie_devctl2; 1990 1991 /* only take action if timeout value is defaulted to 0 */ 1992 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1993 goto out; 1994 1995 /* if capabilities version is type 1 we can write the 1996 * timeout of 10ms to 200ms through the GCR register 1997 */ 1998 if (!(gcr & E1000_GCR_CAP_VER2)) { 1999 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2000 goto out; 2001 } 2002 2003 /* for version 2 capabilities we need to write the config space 2004 * directly in order to set the completion timeout value for 2005 * 16ms to 55ms 2006 */ 2007 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2008 &pcie_devctl2); 2009 if (ret_val) 2010 goto out; 2011 2012 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2013 2014 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2015 &pcie_devctl2); 2016out: 2017 /* disable completion timeout resend */ 2018 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2019 2020 wr32(E1000_GCR, gcr); 2021 return ret_val; 2022} 2023 2024/** 2025 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2026 * @hw: pointer to the hardware struct 2027 * @enable: state to enter, either enabled or disabled 2028 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2029 * 2030 * enables/disables L2 switch anti-spoofing functionality. 2031 **/ 2032void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2033{ 2034 u32 reg_val, reg_offset; 2035 2036 switch (hw->mac.type) { 2037 case e1000_82576: 2038 reg_offset = E1000_DTXSWC; 2039 break; 2040 case e1000_i350: 2041 case e1000_i354: 2042 reg_offset = E1000_TXSWC; 2043 break; 2044 default: 2045 return; 2046 } 2047 2048 reg_val = rd32(reg_offset); 2049 if (enable) { 2050 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2051 E1000_DTXSWC_VLAN_SPOOF_MASK); 2052 /* The PF can spoof - it has to in order to 2053 * support emulation mode NICs 2054 */ 2055 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2056 } else { 2057 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2058 E1000_DTXSWC_VLAN_SPOOF_MASK); 2059 } 2060 wr32(reg_offset, reg_val); 2061} 2062 2063/** 2064 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2065 * @hw: pointer to the hardware struct 2066 * @enable: state to enter, either enabled or disabled 2067 * 2068 * enables/disables L2 switch loopback functionality. 2069 **/ 2070void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2071{ 2072 u32 dtxswc; 2073 2074 switch (hw->mac.type) { 2075 case e1000_82576: 2076 dtxswc = rd32(E1000_DTXSWC); 2077 if (enable) 2078 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2079 else 2080 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2081 wr32(E1000_DTXSWC, dtxswc); 2082 break; 2083 case e1000_i354: 2084 case e1000_i350: 2085 dtxswc = rd32(E1000_TXSWC); 2086 if (enable) 2087 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2088 else 2089 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2090 wr32(E1000_TXSWC, dtxswc); 2091 break; 2092 default: 2093 /* Currently no other hardware supports loopback */ 2094 break; 2095 } 2096 2097} 2098 2099/** 2100 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2101 * @hw: pointer to the hardware struct 2102 * @enable: state to enter, either enabled or disabled 2103 * 2104 * enables/disables replication of packets across multiple pools. 2105 **/ 2106void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2107{ 2108 u32 vt_ctl = rd32(E1000_VT_CTL); 2109 2110 if (enable) 2111 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2112 else 2113 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2114 2115 wr32(E1000_VT_CTL, vt_ctl); 2116} 2117 2118/** 2119 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2120 * @hw: pointer to the HW structure 2121 * @offset: register offset to be read 2122 * @data: pointer to the read data 2123 * 2124 * Reads the MDI control register in the PHY at offset and stores the 2125 * information read to data. 2126 **/ 2127static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2128{ 2129 s32 ret_val; 2130 2131 ret_val = hw->phy.ops.acquire(hw); 2132 if (ret_val) 2133 goto out; 2134 2135 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2136 2137 hw->phy.ops.release(hw); 2138 2139out: 2140 return ret_val; 2141} 2142 2143/** 2144 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2145 * @hw: pointer to the HW structure 2146 * @offset: register offset to write to 2147 * @data: data to write to register at offset 2148 * 2149 * Writes data to MDI control register in the PHY at offset. 2150 **/ 2151static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2152{ 2153 s32 ret_val; 2154 2155 2156 ret_val = hw->phy.ops.acquire(hw); 2157 if (ret_val) 2158 goto out; 2159 2160 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2161 2162 hw->phy.ops.release(hw); 2163 2164out: 2165 return ret_val; 2166} 2167 2168/** 2169 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2170 * @hw: pointer to the HW structure 2171 * 2172 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2173 * the values found in the EEPROM. This addresses an issue in which these 2174 * bits are not restored from EEPROM after reset. 2175 **/ 2176static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2177{ 2178 s32 ret_val = 0; 2179 u32 mdicnfg; 2180 u16 nvm_data = 0; 2181 2182 if (hw->mac.type != e1000_82580) 2183 goto out; 2184 if (!igb_sgmii_active_82575(hw)) 2185 goto out; 2186 2187 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2188 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2189 &nvm_data); 2190 if (ret_val) { 2191 hw_dbg("NVM Read Error\n"); 2192 goto out; 2193 } 2194 2195 mdicnfg = rd32(E1000_MDICNFG); 2196 if (nvm_data & NVM_WORD24_EXT_MDIO) 2197 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2198 if (nvm_data & NVM_WORD24_COM_MDIO) 2199 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2200 wr32(E1000_MDICNFG, mdicnfg); 2201out: 2202 return ret_val; 2203} 2204 2205/** 2206 * igb_reset_hw_82580 - Reset hardware 2207 * @hw: pointer to the HW structure 2208 * 2209 * This resets function or entire device (all ports, etc.) 2210 * to a known state. 2211 **/ 2212static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2213{ 2214 s32 ret_val = 0; 2215 /* BH SW mailbox bit in SW_FW_SYNC */ 2216 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2217 u32 ctrl; 2218 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2219 2220 hw->dev_spec._82575.global_device_reset = false; 2221 2222 /* due to hw errata, global device reset doesn't always 2223 * work on 82580 2224 */ 2225 if (hw->mac.type == e1000_82580) 2226 global_device_reset = false; 2227 2228 /* Get current control state. */ 2229 ctrl = rd32(E1000_CTRL); 2230 2231 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2232 * on the last TLP read/write transaction when MAC is reset. 2233 */ 2234 ret_val = igb_disable_pcie_master(hw); 2235 if (ret_val) 2236 hw_dbg("PCI-E Master disable polling has failed.\n"); 2237 2238 hw_dbg("Masking off all interrupts\n"); 2239 wr32(E1000_IMC, 0xffffffff); 2240 wr32(E1000_RCTL, 0); 2241 wr32(E1000_TCTL, E1000_TCTL_PSP); 2242 wrfl(); 2243 2244 msleep(10); 2245 2246 /* Determine whether or not a global dev reset is requested */ 2247 if (global_device_reset && 2248 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2249 global_device_reset = false; 2250 2251 if (global_device_reset && 2252 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2253 ctrl |= E1000_CTRL_DEV_RST; 2254 else 2255 ctrl |= E1000_CTRL_RST; 2256 2257 wr32(E1000_CTRL, ctrl); 2258 wrfl(); 2259 2260 /* Add delay to insure DEV_RST has time to complete */ 2261 if (global_device_reset) 2262 msleep(5); 2263 2264 ret_val = igb_get_auto_rd_done(hw); 2265 if (ret_val) { 2266 /* When auto config read does not complete, do not 2267 * return with an error. This can happen in situations 2268 * where there is no eeprom and prevents getting link. 2269 */ 2270 hw_dbg("Auto Read Done did not complete\n"); 2271 } 2272 2273 /* clear global device reset status bit */ 2274 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2275 2276 /* Clear any pending interrupt events. */ 2277 wr32(E1000_IMC, 0xffffffff); 2278 rd32(E1000_ICR); 2279 2280 ret_val = igb_reset_mdicnfg_82580(hw); 2281 if (ret_val) 2282 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2283 2284 /* Install any alternate MAC address into RAR0 */ 2285 ret_val = igb_check_alt_mac_addr(hw); 2286 2287 /* Release semaphore */ 2288 if (global_device_reset) 2289 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2290 2291 return ret_val; 2292} 2293 2294/** 2295 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2296 * @data: data received by reading RXPBS register 2297 * 2298 * The 82580 uses a table based approach for packet buffer allocation sizes. 2299 * This function converts the retrieved value into the correct table value 2300 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2301 * 0x0 36 72 144 1 2 4 8 16 2302 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2303 */ 2304u16 igb_rxpbs_adjust_82580(u32 data) 2305{ 2306 u16 ret_val = 0; 2307 2308 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2309 ret_val = e1000_82580_rxpbs_table[data]; 2310 2311 return ret_val; 2312} 2313 2314/** 2315 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2316 * checksum 2317 * @hw: pointer to the HW structure 2318 * @offset: offset in words of the checksum protected region 2319 * 2320 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2321 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2322 **/ 2323static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2324 u16 offset) 2325{ 2326 s32 ret_val = 0; 2327 u16 checksum = 0; 2328 u16 i, nvm_data; 2329 2330 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2331 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2332 if (ret_val) { 2333 hw_dbg("NVM Read Error\n"); 2334 goto out; 2335 } 2336 checksum += nvm_data; 2337 } 2338 2339 if (checksum != (u16) NVM_SUM) { 2340 hw_dbg("NVM Checksum Invalid\n"); 2341 ret_val = -E1000_ERR_NVM; 2342 goto out; 2343 } 2344 2345out: 2346 return ret_val; 2347} 2348 2349/** 2350 * igb_update_nvm_checksum_with_offset - Update EEPROM 2351 * checksum 2352 * @hw: pointer to the HW structure 2353 * @offset: offset in words of the checksum protected region 2354 * 2355 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2356 * up to the checksum. Then calculates the EEPROM checksum and writes the 2357 * value to the EEPROM. 2358 **/ 2359static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2360{ 2361 s32 ret_val; 2362 u16 checksum = 0; 2363 u16 i, nvm_data; 2364 2365 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2366 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2367 if (ret_val) { 2368 hw_dbg("NVM Read Error while updating checksum.\n"); 2369 goto out; 2370 } 2371 checksum += nvm_data; 2372 } 2373 checksum = (u16) NVM_SUM - checksum; 2374 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2375 &checksum); 2376 if (ret_val) 2377 hw_dbg("NVM Write Error while updating checksum.\n"); 2378 2379out: 2380 return ret_val; 2381} 2382 2383/** 2384 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2385 * @hw: pointer to the HW structure 2386 * 2387 * Calculates the EEPROM section checksum by reading/adding each word of 2388 * the EEPROM and then verifies that the sum of the EEPROM is 2389 * equal to 0xBABA. 2390 **/ 2391static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2392{ 2393 s32 ret_val = 0; 2394 u16 eeprom_regions_count = 1; 2395 u16 j, nvm_data; 2396 u16 nvm_offset; 2397 2398 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2399 if (ret_val) { 2400 hw_dbg("NVM Read Error\n"); 2401 goto out; 2402 } 2403 2404 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2405 /* if checksums compatibility bit is set validate checksums 2406 * for all 4 ports. 2407 */ 2408 eeprom_regions_count = 4; 2409 } 2410 2411 for (j = 0; j < eeprom_regions_count; j++) { 2412 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2413 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2414 nvm_offset); 2415 if (ret_val != 0) 2416 goto out; 2417 } 2418 2419out: 2420 return ret_val; 2421} 2422 2423/** 2424 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2425 * @hw: pointer to the HW structure 2426 * 2427 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2428 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2429 * checksum and writes the value to the EEPROM. 2430 **/ 2431static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2432{ 2433 s32 ret_val; 2434 u16 j, nvm_data; 2435 u16 nvm_offset; 2436 2437 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2438 if (ret_val) { 2439 hw_dbg("NVM Read Error while updating checksum" 2440 " compatibility bit.\n"); 2441 goto out; 2442 } 2443 2444 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2445 /* set compatibility bit to validate checksums appropriately */ 2446 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2447 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2448 &nvm_data); 2449 if (ret_val) { 2450 hw_dbg("NVM Write Error while updating checksum" 2451 " compatibility bit.\n"); 2452 goto out; 2453 } 2454 } 2455 2456 for (j = 0; j < 4; j++) { 2457 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2458 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2459 if (ret_val) 2460 goto out; 2461 } 2462 2463out: 2464 return ret_val; 2465} 2466 2467/** 2468 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2469 * @hw: pointer to the HW structure 2470 * 2471 * Calculates the EEPROM section checksum by reading/adding each word of 2472 * the EEPROM and then verifies that the sum of the EEPROM is 2473 * equal to 0xBABA. 2474 **/ 2475static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2476{ 2477 s32 ret_val = 0; 2478 u16 j; 2479 u16 nvm_offset; 2480 2481 for (j = 0; j < 4; j++) { 2482 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2483 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2484 nvm_offset); 2485 if (ret_val != 0) 2486 goto out; 2487 } 2488 2489out: 2490 return ret_val; 2491} 2492 2493/** 2494 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2495 * @hw: pointer to the HW structure 2496 * 2497 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2498 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2499 * checksum and writes the value to the EEPROM. 2500 **/ 2501static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2502{ 2503 s32 ret_val = 0; 2504 u16 j; 2505 u16 nvm_offset; 2506 2507 for (j = 0; j < 4; j++) { 2508 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2509 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2510 if (ret_val != 0) 2511 goto out; 2512 } 2513 2514out: 2515 return ret_val; 2516} 2517 2518/** 2519 * __igb_access_emi_reg - Read/write EMI register 2520 * @hw: pointer to the HW structure 2521 * @addr: EMI address to program 2522 * @data: pointer to value to read/write from/to the EMI address 2523 * @read: boolean flag to indicate read or write 2524 **/ 2525static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2526 u16 *data, bool read) 2527{ 2528 s32 ret_val = E1000_SUCCESS; 2529 2530 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2531 if (ret_val) 2532 return ret_val; 2533 2534 if (read) 2535 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2536 else 2537 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2538 2539 return ret_val; 2540} 2541 2542/** 2543 * igb_read_emi_reg - Read Extended Management Interface register 2544 * @hw: pointer to the HW structure 2545 * @addr: EMI address to program 2546 * @data: value to be read from the EMI address 2547 **/ 2548s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2549{ 2550 return __igb_access_emi_reg(hw, addr, data, true); 2551} 2552 2553/** 2554 * igb_set_eee_i350 - Enable/disable EEE support 2555 * @hw: pointer to the HW structure 2556 * 2557 * Enable/disable EEE based on setting in dev_spec structure. 2558 * 2559 **/ 2560s32 igb_set_eee_i350(struct e1000_hw *hw) 2561{ 2562 s32 ret_val = 0; 2563 u32 ipcnfg, eeer; 2564 2565 if ((hw->mac.type < e1000_i350) || 2566 (hw->phy.media_type != e1000_media_type_copper)) 2567 goto out; 2568 ipcnfg = rd32(E1000_IPCNFG); 2569 eeer = rd32(E1000_EEER); 2570 2571 /* enable or disable per user setting */ 2572 if (!(hw->dev_spec._82575.eee_disable)) { 2573 u32 eee_su = rd32(E1000_EEE_SU); 2574 2575 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2576 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2577 E1000_EEER_LPI_FC); 2578 2579 /* This bit should not be set in normal operation. */ 2580 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2581 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2582 2583 } else { 2584 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2585 E1000_IPCNFG_EEE_100M_AN); 2586 eeer &= ~(E1000_EEER_TX_LPI_EN | 2587 E1000_EEER_RX_LPI_EN | 2588 E1000_EEER_LPI_FC); 2589 } 2590 wr32(E1000_IPCNFG, ipcnfg); 2591 wr32(E1000_EEER, eeer); 2592 rd32(E1000_IPCNFG); 2593 rd32(E1000_EEER); 2594out: 2595 2596 return ret_val; 2597} 2598 2599/** 2600 * igb_set_eee_i354 - Enable/disable EEE support 2601 * @hw: pointer to the HW structure 2602 * 2603 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2604 * 2605 **/ 2606s32 igb_set_eee_i354(struct e1000_hw *hw) 2607{ 2608 struct e1000_phy_info *phy = &hw->phy; 2609 s32 ret_val = 0; 2610 u16 phy_data; 2611 2612 if ((hw->phy.media_type != e1000_media_type_copper) || 2613 (phy->id != M88E1543_E_PHY_ID)) 2614 goto out; 2615 2616 if (!hw->dev_spec._82575.eee_disable) { 2617 /* Switch to PHY page 18. */ 2618 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2619 if (ret_val) 2620 goto out; 2621 2622 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2623 &phy_data); 2624 if (ret_val) 2625 goto out; 2626 2627 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2628 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2629 phy_data); 2630 if (ret_val) 2631 goto out; 2632 2633 /* Return the PHY to page 0. */ 2634 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2635 if (ret_val) 2636 goto out; 2637 2638 /* Turn on EEE advertisement. */ 2639 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2640 E1000_EEE_ADV_DEV_I354, 2641 &phy_data); 2642 if (ret_val) 2643 goto out; 2644 2645 phy_data |= E1000_EEE_ADV_100_SUPPORTED | 2646 E1000_EEE_ADV_1000_SUPPORTED; 2647 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2648 E1000_EEE_ADV_DEV_I354, 2649 phy_data); 2650 } else { 2651 /* Turn off EEE advertisement. */ 2652 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2653 E1000_EEE_ADV_DEV_I354, 2654 &phy_data); 2655 if (ret_val) 2656 goto out; 2657 2658 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2659 E1000_EEE_ADV_1000_SUPPORTED); 2660 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2661 E1000_EEE_ADV_DEV_I354, 2662 phy_data); 2663 } 2664 2665out: 2666 return ret_val; 2667} 2668 2669/** 2670 * igb_get_eee_status_i354 - Get EEE status 2671 * @hw: pointer to the HW structure 2672 * @status: EEE status 2673 * 2674 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2675 * been received. 2676 **/ 2677s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2678{ 2679 struct e1000_phy_info *phy = &hw->phy; 2680 s32 ret_val = 0; 2681 u16 phy_data; 2682 2683 /* Check if EEE is supported on this device. */ 2684 if ((hw->phy.media_type != e1000_media_type_copper) || 2685 (phy->id != M88E1543_E_PHY_ID)) 2686 goto out; 2687 2688 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2689 E1000_PCS_STATUS_DEV_I354, 2690 &phy_data); 2691 if (ret_val) 2692 goto out; 2693 2694 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2695 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2696 2697out: 2698 return ret_val; 2699} 2700 2701static const u8 e1000_emc_temp_data[4] = { 2702 E1000_EMC_INTERNAL_DATA, 2703 E1000_EMC_DIODE1_DATA, 2704 E1000_EMC_DIODE2_DATA, 2705 E1000_EMC_DIODE3_DATA 2706}; 2707static const u8 e1000_emc_therm_limit[4] = { 2708 E1000_EMC_INTERNAL_THERM_LIMIT, 2709 E1000_EMC_DIODE1_THERM_LIMIT, 2710 E1000_EMC_DIODE2_THERM_LIMIT, 2711 E1000_EMC_DIODE3_THERM_LIMIT 2712}; 2713 2714/** 2715 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2716 * @hw: pointer to hardware structure 2717 * 2718 * Updates the temperatures in mac.thermal_sensor_data 2719 **/ 2720static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2721{ 2722 s32 status = E1000_SUCCESS; 2723 u16 ets_offset; 2724 u16 ets_cfg; 2725 u16 ets_sensor; 2726 u8 num_sensors; 2727 u8 sensor_index; 2728 u8 sensor_location; 2729 u8 i; 2730 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2731 2732 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2733 return E1000_NOT_IMPLEMENTED; 2734 2735 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2736 2737 /* Return the internal sensor only if ETS is unsupported */ 2738 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2739 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2740 return status; 2741 2742 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2743 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2744 != NVM_ETS_TYPE_EMC) 2745 return E1000_NOT_IMPLEMENTED; 2746 2747 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2748 if (num_sensors > E1000_MAX_SENSORS) 2749 num_sensors = E1000_MAX_SENSORS; 2750 2751 for (i = 1; i < num_sensors; i++) { 2752 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2753 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2754 NVM_ETS_DATA_INDEX_SHIFT); 2755 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2756 NVM_ETS_DATA_LOC_SHIFT); 2757 2758 if (sensor_location != 0) 2759 hw->phy.ops.read_i2c_byte(hw, 2760 e1000_emc_temp_data[sensor_index], 2761 E1000_I2C_THERMAL_SENSOR_ADDR, 2762 &data->sensor[i].temp); 2763 } 2764 return status; 2765} 2766 2767/** 2768 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2769 * @hw: pointer to hardware structure 2770 * 2771 * Sets the thermal sensor thresholds according to the NVM map 2772 * and save off the threshold and location values into mac.thermal_sensor_data 2773 **/ 2774static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2775{ 2776 s32 status = E1000_SUCCESS; 2777 u16 ets_offset; 2778 u16 ets_cfg; 2779 u16 ets_sensor; 2780 u8 low_thresh_delta; 2781 u8 num_sensors; 2782 u8 sensor_index; 2783 u8 sensor_location; 2784 u8 therm_limit; 2785 u8 i; 2786 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2787 2788 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2789 return E1000_NOT_IMPLEMENTED; 2790 2791 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2792 2793 data->sensor[0].location = 0x1; 2794 data->sensor[0].caution_thresh = 2795 (rd32(E1000_THHIGHTC) & 0xFF); 2796 data->sensor[0].max_op_thresh = 2797 (rd32(E1000_THLOWTC) & 0xFF); 2798 2799 /* Return the internal sensor only if ETS is unsupported */ 2800 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2801 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2802 return status; 2803 2804 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2805 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2806 != NVM_ETS_TYPE_EMC) 2807 return E1000_NOT_IMPLEMENTED; 2808 2809 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2810 NVM_ETS_LTHRES_DELTA_SHIFT); 2811 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2812 2813 for (i = 1; i <= num_sensors; i++) { 2814 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2815 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2816 NVM_ETS_DATA_INDEX_SHIFT); 2817 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2818 NVM_ETS_DATA_LOC_SHIFT); 2819 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2820 2821 hw->phy.ops.write_i2c_byte(hw, 2822 e1000_emc_therm_limit[sensor_index], 2823 E1000_I2C_THERMAL_SENSOR_ADDR, 2824 therm_limit); 2825 2826 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2827 data->sensor[i].location = sensor_location; 2828 data->sensor[i].caution_thresh = therm_limit; 2829 data->sensor[i].max_op_thresh = therm_limit - 2830 low_thresh_delta; 2831 } 2832 } 2833 return status; 2834} 2835 2836static struct e1000_mac_operations e1000_mac_ops_82575 = { 2837 .init_hw = igb_init_hw_82575, 2838 .check_for_link = igb_check_for_link_82575, 2839 .rar_set = igb_rar_set, 2840 .read_mac_addr = igb_read_mac_addr_82575, 2841 .get_speed_and_duplex = igb_get_link_up_info_82575, 2842#ifdef CONFIG_IGB_HWMON 2843 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2844 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2845#endif 2846}; 2847 2848static struct e1000_phy_operations e1000_phy_ops_82575 = { 2849 .acquire = igb_acquire_phy_82575, 2850 .get_cfg_done = igb_get_cfg_done_82575, 2851 .release = igb_release_phy_82575, 2852 .write_i2c_byte = igb_write_i2c_byte, 2853 .read_i2c_byte = igb_read_i2c_byte, 2854}; 2855 2856static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2857 .acquire = igb_acquire_nvm_82575, 2858 .read = igb_read_nvm_eerd, 2859 .release = igb_release_nvm_82575, 2860 .write = igb_write_nvm_spi, 2861}; 2862 2863const struct e1000_info e1000_82575_info = { 2864 .get_invariants = igb_get_invariants_82575, 2865 .mac_ops = &e1000_mac_ops_82575, 2866 .phy_ops = &e1000_phy_ops_82575, 2867 .nvm_ops = &e1000_nvm_ops_82575, 2868}; 2869 2870