e1000_defines.h revision 9005df38615bb3545cb6e4db59db73b27b6c0140
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#ifndef _E1000_DEFINES_H_ 28#define _E1000_DEFINES_H_ 29 30/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 31#define REQ_TX_DESCRIPTOR_MULTIPLE 8 32#define REQ_RX_DESCRIPTOR_MULTIPLE 8 33 34/* Definitions for power management and wakeup registers */ 35/* Wake Up Control */ 36#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 37 38/* Wake Up Filter Control */ 39#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 40#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 41#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 42#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 43#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 44 45/* Extended Device Control */ 46#define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */ 47#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 48#define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 49#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */ 50 51/* Physical Func Reset Done Indication */ 52#define E1000_CTRL_EXT_PFRSTD 0x00004000 53#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 54#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 55#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 56#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 57#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 58#define E1000_CTRL_EXT_EIAME 0x01000000 59#define E1000_CTRL_EXT_IRCA 0x00000001 60/* Interrupt delay cancellation */ 61/* Driver loaded bit for FW */ 62#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 63/* Interrupt acknowledge Auto-mask */ 64/* Clear Interrupt timers after IMS clear */ 65/* packet buffer parity error detection enabled */ 66/* descriptor FIFO parity error detection enable */ 67#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 68#define E1000_I2CCMD_REG_ADDR_SHIFT 16 69#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 70#define E1000_I2CCMD_OPCODE_READ 0x08000000 71#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 72#define E1000_I2CCMD_READY 0x20000000 73#define E1000_I2CCMD_ERROR 0x80000000 74#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 75#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 76#define E1000_MAX_SGMII_PHY_REG_ADDR 255 77#define E1000_I2CCMD_PHY_TIMEOUT 200 78#define E1000_IVAR_VALID 0x80 79#define E1000_GPIE_NSICR 0x00000001 80#define E1000_GPIE_MSIX_MODE 0x00000010 81#define E1000_GPIE_EIAME 0x40000000 82#define E1000_GPIE_PBA 0x80000000 83 84/* Receive Descriptor bit definitions */ 85#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 86#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 87#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 88#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 89#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 90#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 91#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 92 93#define E1000_RXDEXT_STATERR_LB 0x00040000 94#define E1000_RXDEXT_STATERR_CE 0x01000000 95#define E1000_RXDEXT_STATERR_SE 0x02000000 96#define E1000_RXDEXT_STATERR_SEQ 0x04000000 97#define E1000_RXDEXT_STATERR_CXE 0x10000000 98#define E1000_RXDEXT_STATERR_TCPE 0x20000000 99#define E1000_RXDEXT_STATERR_IPE 0x40000000 100#define E1000_RXDEXT_STATERR_RXE 0x80000000 101 102/* Same mask, but for extended and packet split descriptors */ 103#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 104 E1000_RXDEXT_STATERR_CE | \ 105 E1000_RXDEXT_STATERR_SE | \ 106 E1000_RXDEXT_STATERR_SEQ | \ 107 E1000_RXDEXT_STATERR_CXE | \ 108 E1000_RXDEXT_STATERR_RXE) 109 110#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 111#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 112#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 113#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 114#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 115 116 117/* Management Control */ 118#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 119#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 120#define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ 121/* Enable Neighbor Discovery Filtering */ 122#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 123#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 124/* Enable MAC address filtering */ 125#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 126 127/* Receive Control */ 128#define E1000_RCTL_EN 0x00000002 /* enable */ 129#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 130#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 131#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 132#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 133#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 134#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 135#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 136#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 137#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 138#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 139#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 140#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 141#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 142#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 143#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 144#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 145 146/* Use byte values for the following shift parameters 147 * Usage: 148 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 149 * E1000_PSRCTL_BSIZE0_MASK) | 150 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 151 * E1000_PSRCTL_BSIZE1_MASK) | 152 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 153 * E1000_PSRCTL_BSIZE2_MASK) | 154 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 155 * E1000_PSRCTL_BSIZE3_MASK)) 156 * where value0 = [128..16256], default=256 157 * value1 = [1024..64512], default=4096 158 * value2 = [0..64512], default=4096 159 * value3 = [0..64512], default=0 160 */ 161 162#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 163#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 164#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 165#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 166 167#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 168#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 169#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 170#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 171 172/* SWFW_SYNC Definitions */ 173#define E1000_SWFW_EEP_SM 0x1 174#define E1000_SWFW_PHY0_SM 0x2 175#define E1000_SWFW_PHY1_SM 0x4 176#define E1000_SWFW_PHY2_SM 0x20 177#define E1000_SWFW_PHY3_SM 0x40 178 179/* FACTPS Definitions */ 180/* Device Control */ 181#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 182#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 183#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 184#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 185#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 186#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 187#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 188#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 189#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 190#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 191#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 192/* Defined polarity of Dock/Undock indication in SDP[0] */ 193/* Reset both PHY ports, through PHYRST_N pin */ 194/* enable link status from external LINK_0 and LINK_1 pins */ 195#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 196#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 197#define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 198#define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 199#define E1000_CTRL_RST 0x04000000 /* Global reset */ 200#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 201#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 202#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 203#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 204/* Initiate an interrupt to manageability engine */ 205#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 206 207/* Bit definitions for the Management Data IO (MDIO) and Management Data 208 * Clock (MDC) pins in the Device Control Register. 209 */ 210 211#define E1000_CONNSW_ENRGSRC 0x4 212#define E1000_CONNSW_PHYSD 0x400 213#define E1000_CONNSW_PHY_PDN 0x800 214#define E1000_CONNSW_SERDESD 0x200 215#define E1000_CONNSW_AUTOSENSE_CONF 0x2 216#define E1000_CONNSW_AUTOSENSE_EN 0x1 217#define E1000_PCS_CFG_PCS_EN 8 218#define E1000_PCS_LCTL_FLV_LINK_UP 1 219#define E1000_PCS_LCTL_FSV_100 2 220#define E1000_PCS_LCTL_FSV_1000 4 221#define E1000_PCS_LCTL_FDV_FULL 8 222#define E1000_PCS_LCTL_FSD 0x10 223#define E1000_PCS_LCTL_FORCE_LINK 0x20 224#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 225#define E1000_PCS_LCTL_AN_ENABLE 0x10000 226#define E1000_PCS_LCTL_AN_RESTART 0x20000 227#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 228#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 229 230#define E1000_PCS_LSTS_LINK_OK 1 231#define E1000_PCS_LSTS_SPEED_100 2 232#define E1000_PCS_LSTS_SPEED_1000 4 233#define E1000_PCS_LSTS_DUPLEX_FULL 8 234#define E1000_PCS_LSTS_SYNK_OK 0x10 235 236/* Device Status */ 237#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 238#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 239#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 240#define E1000_STATUS_FUNC_SHIFT 2 241#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 242#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 243#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 244#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 245/* Change in Dock/Undock state. Clear on write '0'. */ 246/* Status of Master requests. */ 247#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 248/* BMC external code execution disabled */ 249 250#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 251#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 252/* Constants used to intrepret the masked PCI-X bus speed. */ 253 254#define SPEED_10 10 255#define SPEED_100 100 256#define SPEED_1000 1000 257#define SPEED_2500 2500 258#define HALF_DUPLEX 1 259#define FULL_DUPLEX 2 260 261 262#define ADVERTISE_10_HALF 0x0001 263#define ADVERTISE_10_FULL 0x0002 264#define ADVERTISE_100_HALF 0x0004 265#define ADVERTISE_100_FULL 0x0008 266#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 267#define ADVERTISE_1000_FULL 0x0020 268 269/* 1000/H is not supported, nor spec-compliant. */ 270#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 271 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 272 ADVERTISE_1000_FULL) 273#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 274 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 275#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 276#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 277#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 278 ADVERTISE_1000_FULL) 279#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 280 281#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 282 283/* LED Control */ 284#define E1000_LEDCTL_LED0_MODE_SHIFT 0 285#define E1000_LEDCTL_LED0_BLINK 0x00000080 286#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 287#define E1000_LEDCTL_LED0_IVRT 0x00000040 288 289#define E1000_LEDCTL_MODE_LED_ON 0xE 290#define E1000_LEDCTL_MODE_LED_OFF 0xF 291 292/* Transmit Descriptor bit definitions */ 293#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 294#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 295#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 296#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 297#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 298#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 299#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 300/* Extended desc bits for Linksec and timesync */ 301 302/* Transmit Control */ 303#define E1000_TCTL_EN 0x00000002 /* enable tx */ 304#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 305#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 306#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 307#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 308 309/* DMA Coalescing register fields */ 310#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing 311 * Watchdog Timer */ 312#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive 313 * Threshold */ 314#define E1000_DMACR_DMACTHR_SHIFT 16 315#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe 316 * transactions */ 317#define E1000_DMACR_DMAC_LX_SHIFT 28 318#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 319/* DMA Coalescing BMC-to-OS Watchdog Enable */ 320#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 321 322#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit 323 * Threshold */ 324 325#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 326 327#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate 328 * Threshold */ 329#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in 330 * current window */ 331 332#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic 333 * Current Cnt */ 334 335#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold 336 * High val */ 337#define E1000_FCRTC_RTH_COAL_SHIFT 4 338#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ 339 340/* Timestamp in Rx buffer */ 341#define E1000_RXPBS_CFG_TS_EN 0x80000000 342 343/* SerDes Control */ 344#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 345 346/* Receive Checksum Control */ 347#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 348#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 349#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 350#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 351 352/* Header split receive */ 353#define E1000_RFCTL_LEF 0x00040000 354 355/* Collision related configuration parameters */ 356#define E1000_COLLISION_THRESHOLD 15 357#define E1000_CT_SHIFT 4 358#define E1000_COLLISION_DISTANCE 63 359#define E1000_COLD_SHIFT 12 360 361/* Ethertype field values */ 362#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 363 364#define MAX_JUMBO_FRAME_SIZE 0x3F00 365 366/* PBA constants */ 367#define E1000_PBA_34K 0x0022 368#define E1000_PBA_64K 0x0040 /* 64KB */ 369 370/* SW Semaphore Register */ 371#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 372#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 373 374/* Interrupt Cause Read */ 375#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 376#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 377#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 378#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 379#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 380#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 381#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 382#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 383/* If this bit asserted, the driver should claim the interrupt */ 384#define E1000_ICR_INT_ASSERTED 0x80000000 385/* LAN connected device generates an interrupt */ 386#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 387 388/* Extended Interrupt Cause Read */ 389#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 390#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 391#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 392#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 393#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 394#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 395#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 396#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 397#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 398/* TCP Timer */ 399 400/* This defines the bits that are set in the Interrupt Mask 401 * Set/Read Register. Each bit is documented below: 402 * o RXT0 = Receiver Timer Interrupt (ring 0) 403 * o TXDW = Transmit Descriptor Written Back 404 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 405 * o RXSEQ = Receive Sequence Error 406 * o LSC = Link Status Change 407 */ 408#define IMS_ENABLE_MASK ( \ 409 E1000_IMS_RXT0 | \ 410 E1000_IMS_TXDW | \ 411 E1000_IMS_RXDMT0 | \ 412 E1000_IMS_RXSEQ | \ 413 E1000_IMS_LSC | \ 414 E1000_IMS_DOUTSYNC) 415 416/* Interrupt Mask Set */ 417#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 418#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 419#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 420#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 421#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 422#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 423#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 424#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 425#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 426 427/* Extended Interrupt Mask Set */ 428#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 429 430/* Interrupt Cause Set */ 431#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 432#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 433#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 434 435/* Extended Interrupt Cause Set */ 436/* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 437#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 438 439 440/* Transmit Descriptor Control */ 441/* Enable the counting of descriptors still to be processed. */ 442 443/* Flow Control Constants */ 444#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 445#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 446#define FLOW_CONTROL_TYPE 0x8808 447 448/* Transmit Config Word */ 449#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 450#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 451 452/* 802.1q VLAN Packet Size */ 453#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 454#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 455 456/* Receive Address */ 457/* Number of high/low register pairs in the RAR. The RAR (Receive Address 458 * Registers) holds the directed and multicast addresses that we monitor. 459 * Technically, we have 16 spots. However, we reserve one of these spots 460 * (RAR[15]) for our directed address used by controllers with 461 * manageability enabled, allowing us room for 15 multicast addresses. 462 */ 463#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 464#define E1000_RAL_MAC_ADDR_LEN 4 465#define E1000_RAH_MAC_ADDR_LEN 2 466#define E1000_RAH_POOL_MASK 0x03FC0000 467#define E1000_RAH_POOL_1 0x00040000 468 469/* Error Codes */ 470#define E1000_SUCCESS 0 471#define E1000_ERR_NVM 1 472#define E1000_ERR_PHY 2 473#define E1000_ERR_CONFIG 3 474#define E1000_ERR_PARAM 4 475#define E1000_ERR_MAC_INIT 5 476#define E1000_ERR_RESET 9 477#define E1000_ERR_MASTER_REQUESTS_PENDING 10 478#define E1000_BLK_PHY_RESET 12 479#define E1000_ERR_SWFW_SYNC 13 480#define E1000_NOT_IMPLEMENTED 14 481#define E1000_ERR_MBX 15 482#define E1000_ERR_INVALID_ARGUMENT 16 483#define E1000_ERR_NO_SPACE 17 484#define E1000_ERR_NVM_PBA_SECTION 18 485#define E1000_ERR_INVM_VALUE_NOT_FOUND 19 486#define E1000_ERR_I2C 20 487 488/* Loop limit on how long we wait for auto-negotiation to complete */ 489#define COPPER_LINK_UP_LIMIT 10 490#define PHY_AUTO_NEG_LIMIT 45 491#define PHY_FORCE_LIMIT 20 492/* Number of 100 microseconds we wait for PCI Express master disable */ 493#define MASTER_DISABLE_TIMEOUT 800 494/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 495#define PHY_CFG_TIMEOUT 100 496/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 497/* Number of milliseconds for NVM auto read done after MAC reset. */ 498#define AUTO_READ_DONE_TIMEOUT 10 499 500/* Flow Control */ 501#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 502 503#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 504#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 505 506#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 507#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 508#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 509#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 510#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 511#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 512#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 513#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 514 515#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 516#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 517#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 518#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 519#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 520#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 521 522#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 523#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 524#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 525#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 526#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 527#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 528#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 529#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 530#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 531#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 532#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 533 534#define E1000_TIMINCA_16NS_SHIFT 24 535 536/* Time Sync Interrupt Cause/Mask Register Bits */ 537 538#define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 539#define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 540#define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */ 541#define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 542#define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 543#define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 544#define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 545#define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */ 546 547#define TSYNC_INTERRUPTS TSINTR_TXTS 548#define E1000_TSICR_TXTS TSINTR_TXTS 549 550/* TSAUXC Configuration Bits */ 551#define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 552#define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 553#define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 554#define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */ 555#define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 556#define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 557#define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */ 558#define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 559#define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 560#define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */ 561#define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 562#define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */ 563#define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */ 564#define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */ 565 566/* SDP Configuration Bits */ 567#define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 568#define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 569#define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 570#define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 571#define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */ 572#define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 573#define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 574#define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 575#define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 576#define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */ 577#define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */ 578#define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */ 579#define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */ 580#define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */ 581#define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */ 582#define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */ 583#define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */ 584#define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */ 585#define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */ 586#define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */ 587#define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */ 588#define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */ 589#define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */ 590#define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */ 591#define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */ 592#define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */ 593#define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */ 594#define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */ 595#define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */ 596#define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */ 597 598#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 599#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 600#define E1000_MDICNFG_PHY_MASK 0x03E00000 601#define E1000_MDICNFG_PHY_SHIFT 21 602 603#define E1000_MEDIA_PORT_COPPER 1 604#define E1000_MEDIA_PORT_OTHER 2 605#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 606#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 607#define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 608#define E1000_M88E1112_MAC_CTRL_1 0x10 609#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 610#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 611#define E1000_M88E1112_PAGE_ADDR 0x16 612#define E1000_M88E1112_STATUS 0x01 613 614/* PCI Express Control */ 615#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 616#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 617#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 618#define E1000_GCR_CAP_VER2 0x00040000 619 620/* mPHY Address Control and Data Registers */ 621#define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ 622#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 623#define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ 624 625/* mPHY PCS CLK Register */ 626#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ 627/* mPHY Near End Digital Loopback Override Bit */ 628#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 629 630#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 631#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 632 633/* PHY Control Register */ 634#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 635#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 636#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 637#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 638#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 639#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 640#define MII_CR_SPEED_1000 0x0040 641#define MII_CR_SPEED_100 0x2000 642#define MII_CR_SPEED_10 0x0000 643 644/* PHY Status Register */ 645#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 646#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 647 648/* Autoneg Advertisement Register */ 649#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 650#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 651#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 652#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 653#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 654#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 655 656/* Link Partner Ability Register (Base Page) */ 657#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 658#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 659 660/* Autoneg Expansion Register */ 661 662/* 1000BASE-T Control Register */ 663#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 664#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 665#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 666 /* 0=Configure PHY as Slave */ 667#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 668 /* 0=Automatic Master/Slave config */ 669 670/* 1000BASE-T Status Register */ 671#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 672#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 673 674 675/* PHY 1000 MII Register/Bit Definitions */ 676/* PHY Registers defined by IEEE */ 677#define PHY_CONTROL 0x00 /* Control Register */ 678#define PHY_STATUS 0x01 /* Status Register */ 679#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 680#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 681#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 682#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 683#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 684#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 685 686/* NVM Control */ 687#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 688#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 689#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 690#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 691#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 692#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 693#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 694/* NVM Addressing bits based on type 0=small, 1=large */ 695#define E1000_EECD_ADDR_BITS 0x00000400 696#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 697#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 698#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 699#define E1000_EECD_SIZE_EX_SHIFT 11 700#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 701#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 702#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 703#define E1000_FLUDONE_ATTEMPTS 20000 704#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 705#define E1000_I210_FIFO_SEL_RX 0x00 706#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 707#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 708#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 709#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 710#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 711/* Secure FLASH mode requires removing MSb */ 712#define E1000_I210_FW_PTR_MASK 0x7FFF 713/* Firmware code revision field word offset*/ 714#define E1000_I210_FW_VER_OFFSET 328 715#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 716#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 717#define E1000_FLUDONE_ATTEMPTS 20000 718#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 719#define E1000_I210_FIFO_SEL_RX 0x00 720#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 721#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 722#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 723#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 724 725 726/* Offset to data in NVM read/write registers */ 727#define E1000_NVM_RW_REG_DATA 16 728#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 729#define E1000_NVM_RW_REG_START 1 /* Start operation */ 730#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 731#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 732 733/* NVM Word Offsets */ 734#define NVM_COMPAT 0x0003 735#define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ 736#define NVM_VERSION 0x0005 737#define NVM_INIT_CONTROL2_REG 0x000F 738#define NVM_INIT_CONTROL3_PORT_B 0x0014 739#define NVM_INIT_CONTROL3_PORT_A 0x0024 740#define NVM_ALT_MAC_ADDR_PTR 0x0037 741#define NVM_CHECKSUM_REG 0x003F 742#define NVM_COMPATIBILITY_REG_3 0x0003 743#define NVM_COMPATIBILITY_BIT_MASK 0x8000 744#define NVM_MAC_ADDR 0x0000 745#define NVM_SUB_DEV_ID 0x000B 746#define NVM_SUB_VEN_ID 0x000C 747#define NVM_DEV_ID 0x000D 748#define NVM_VEN_ID 0x000E 749#define NVM_INIT_CTRL_2 0x000F 750#define NVM_INIT_CTRL_4 0x0013 751#define NVM_LED_1_CFG 0x001C 752#define NVM_LED_0_2_CFG 0x001F 753#define NVM_ETRACK_WORD 0x0042 754#define NVM_ETRACK_HIWORD 0x0043 755#define NVM_COMB_VER_OFF 0x0083 756#define NVM_COMB_VER_PTR 0x003d 757 758/* NVM version defines */ 759#define NVM_MAJOR_MASK 0xF000 760#define NVM_MINOR_MASK 0x0FF0 761#define NVM_IMAGE_ID_MASK 0x000F 762#define NVM_COMB_VER_MASK 0x00FF 763#define NVM_MAJOR_SHIFT 12 764#define NVM_MINOR_SHIFT 4 765#define NVM_COMB_VER_SHFT 8 766#define NVM_VER_INVALID 0xFFFF 767#define NVM_ETRACK_SHIFT 16 768#define NVM_ETRACK_VALID 0x8000 769#define NVM_NEW_DEC_MASK 0x0F00 770#define NVM_HEX_CONV 16 771#define NVM_HEX_TENS 10 772 773#define NVM_ETS_CFG 0x003E 774#define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 775#define NVM_ETS_LTHRES_DELTA_SHIFT 6 776#define NVM_ETS_TYPE_MASK 0x0038 777#define NVM_ETS_TYPE_SHIFT 3 778#define NVM_ETS_TYPE_EMC 0x000 779#define NVM_ETS_NUM_SENSORS_MASK 0x0007 780#define NVM_ETS_DATA_LOC_MASK 0x3C00 781#define NVM_ETS_DATA_LOC_SHIFT 10 782#define NVM_ETS_DATA_INDEX_MASK 0x0300 783#define NVM_ETS_DATA_INDEX_SHIFT 8 784#define NVM_ETS_DATA_HTHRESH_MASK 0x00FF 785 786#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 787#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 788#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 789#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 790 791#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 792 793/* Mask bits for fields in Word 0x24 of the NVM */ 794#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 795#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 796 797/* Mask bits for fields in Word 0x0f of the NVM */ 798#define NVM_WORD0F_PAUSE_MASK 0x3000 799#define NVM_WORD0F_ASM_DIR 0x2000 800 801/* Mask bits for fields in Word 0x1a of the NVM */ 802 803/* length of string needed to store part num */ 804#define E1000_PBANUM_LENGTH 11 805 806/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 807#define NVM_SUM 0xBABA 808 809#define NVM_PBA_OFFSET_0 8 810#define NVM_PBA_OFFSET_1 9 811#define NVM_RESERVED_WORD 0xFFFF 812#define NVM_PBA_PTR_GUARD 0xFAFA 813#define NVM_WORD_SIZE_BASE_SHIFT 6 814 815/* NVM Commands - Microwire */ 816 817/* NVM Commands - SPI */ 818#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 819#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 820#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 821#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 822#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 823#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 824 825/* SPI NVM Status Register */ 826#define NVM_STATUS_RDY_SPI 0x01 827 828/* Word definitions for ID LED Settings */ 829#define ID_LED_RESERVED_0000 0x0000 830#define ID_LED_RESERVED_FFFF 0xFFFF 831#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 832 (ID_LED_OFF1_OFF2 << 8) | \ 833 (ID_LED_DEF1_DEF2 << 4) | \ 834 (ID_LED_DEF1_DEF2)) 835#define ID_LED_DEF1_DEF2 0x1 836#define ID_LED_DEF1_ON2 0x2 837#define ID_LED_DEF1_OFF2 0x3 838#define ID_LED_ON1_DEF2 0x4 839#define ID_LED_ON1_ON2 0x5 840#define ID_LED_ON1_OFF2 0x6 841#define ID_LED_OFF1_DEF2 0x7 842#define ID_LED_OFF1_ON2 0x8 843#define ID_LED_OFF1_OFF2 0x9 844 845#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 846#define IGP_ACTIVITY_LED_ENABLE 0x0300 847#define IGP_LED3_MODE 0x07000000 848 849/* PCI/PCI-X/PCI-EX Config space */ 850#define PCIE_DEVICE_CONTROL2 0x28 851#define PCIE_DEVICE_CONTROL2_16ms 0x0005 852 853#define PHY_REVISION_MASK 0xFFFFFFF0 854#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 855#define MAX_PHY_MULTI_PAGE_REG 0xF 856 857/* Bit definitions for valid PHY IDs. */ 858/* I = Integrated 859 * E = External 860 */ 861#define M88E1111_I_PHY_ID 0x01410CC0 862#define M88E1112_E_PHY_ID 0x01410C90 863#define I347AT4_E_PHY_ID 0x01410DC0 864#define IGP03E1000_E_PHY_ID 0x02A80390 865#define I82580_I_PHY_ID 0x015403A0 866#define I350_I_PHY_ID 0x015403B0 867#define M88_VENDOR 0x0141 868#define I210_I_PHY_ID 0x01410C00 869#define M88E1543_E_PHY_ID 0x01410EA0 870 871/* M88E1000 Specific Registers */ 872#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 873#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 874#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 875 876#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 877#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 878 879/* M88E1000 PHY Specific Control Register */ 880#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 881/* 1=CLK125 low, 0=CLK125 toggling */ 882#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 883 /* Manual MDI configuration */ 884#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 885/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 886#define M88E1000_PSCR_AUTO_X_1000T 0x0040 887/* Auto crossover enabled all speeds */ 888#define M88E1000_PSCR_AUTO_X_MODE 0x0060 889/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 890 * 0=Normal 10BASE-T Rx Threshold 891 */ 892/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 893#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 894 895/* M88E1000 PHY Specific Status Register */ 896#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 897#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 898#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 899/* 0 = <50M 900 * 1 = 50-80M 901 * 2 = 80-110M 902 * 3 = 110-140M 903 * 4 = >140M 904 */ 905#define M88E1000_PSSR_CABLE_LENGTH 0x0380 906#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 907#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 908 909#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 910 911/* M88E1000 Extended PHY Specific Control Register */ 912/* 1 = Lost lock detect enabled. 913 * Will assert lost lock and bring 914 * link down if idle not seen 915 * within 1ms in 1000BASE-T 916 */ 917/* Number of times we will attempt to autonegotiate before downshifting if we 918 * are the master 919 */ 920#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 921#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 922/* Number of times we will attempt to autonegotiate before downshifting if we 923 * are the slave 924 */ 925#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 926#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 927#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 928 929/* Intel i347-AT4 Registers */ 930 931#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 932#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 933#define I347AT4_PAGE_SELECT 0x16 934 935/* i347-AT4 Extended PHY Specific Control Register */ 936 937/* Number of times we will attempt to autonegotiate before downshifting if we 938 * are the master 939 */ 940#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 941#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 942#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 943#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 944#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 945#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 946#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 947#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 948#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 949#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 950 951/* i347-AT4 PHY Cable Diagnostics Control */ 952#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 953 954/* Marvell 1112 only registers */ 955#define M88E1112_VCT_DSP_DISTANCE 0x001A 956 957/* M88EC018 Rev 2 specific DownShift settings */ 958#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 959#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 960 961/* MDI Control */ 962#define E1000_MDIC_DATA_MASK 0x0000FFFF 963#define E1000_MDIC_REG_MASK 0x001F0000 964#define E1000_MDIC_REG_SHIFT 16 965#define E1000_MDIC_PHY_MASK 0x03E00000 966#define E1000_MDIC_PHY_SHIFT 21 967#define E1000_MDIC_OP_WRITE 0x04000000 968#define E1000_MDIC_OP_READ 0x08000000 969#define E1000_MDIC_READY 0x10000000 970#define E1000_MDIC_INT_EN 0x20000000 971#define E1000_MDIC_ERROR 0x40000000 972#define E1000_MDIC_DEST 0x80000000 973 974/* Thermal Sensor */ 975#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 976#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ 977 978/* Energy Efficient Ethernet */ 979#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ 980#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 981#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 982#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 983#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ 984#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 985#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ 986#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 987#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 988#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 989#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 990#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 991#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 992#define E1000_M88E1543_EEE_CTRL_1 0x0 993#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 994#define E1000_EEE_ADV_DEV_I354 7 995#define E1000_EEE_ADV_ADDR_I354 60 996#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 997#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 998#define E1000_PCS_STATUS_DEV_I354 3 999#define E1000_PCS_STATUS_ADDR_I354 1 1000#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 1001#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 1002#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 1003 1004/* SerDes Control */ 1005#define E1000_GEN_CTL_READY 0x80000000 1006#define E1000_GEN_CTL_ADDRESS_SHIFT 8 1007#define E1000_GEN_POLL_TIMEOUT 640 1008 1009#define E1000_VFTA_ENTRY_SHIFT 5 1010#define E1000_VFTA_ENTRY_MASK 0x7F 1011#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 1012 1013/* DMA Coalescing register fields */ 1014#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */ 1015 1016/* Tx Rate-Scheduler Config fields */ 1017#define E1000_RTTBCNRC_RS_ENA 0x80000000 1018#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1019#define E1000_RTTBCNRC_RF_INT_SHIFT 14 1020#define E1000_RTTBCNRC_RF_INT_MASK \ 1021 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1022 1023#endif 1024