e1000_defines.h revision 24a372cd0b87c15f8d98275d045326249155af55
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#ifndef _E1000_DEFINES_H_ 29#define _E1000_DEFINES_H_ 30 31/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 32#define REQ_TX_DESCRIPTOR_MULTIPLE 8 33#define REQ_RX_DESCRIPTOR_MULTIPLE 8 34 35/* Definitions for power management and wakeup registers */ 36/* Wake Up Control */ 37#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 38 39/* Wake Up Filter Control */ 40#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 41#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 42#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 43#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 44#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 45 46/* Extended Device Control */ 47#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 48/* Physical Func Reset Done Indication */ 49#define E1000_CTRL_EXT_PFRSTD 0x00004000 50#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 51#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 52#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 53#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 54#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 55#define E1000_CTRL_EXT_EIAME 0x01000000 56#define E1000_CTRL_EXT_IRCA 0x00000001 57/* Interrupt delay cancellation */ 58/* Driver loaded bit for FW */ 59#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 60/* Interrupt acknowledge Auto-mask */ 61/* Clear Interrupt timers after IMS clear */ 62/* packet buffer parity error detection enabled */ 63/* descriptor FIFO parity error detection enable */ 64#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 65#define E1000_I2CCMD_REG_ADDR_SHIFT 16 66#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 67#define E1000_I2CCMD_OPCODE_READ 0x08000000 68#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 69#define E1000_I2CCMD_READY 0x20000000 70#define E1000_I2CCMD_ERROR 0x80000000 71#define E1000_MAX_SGMII_PHY_REG_ADDR 255 72#define E1000_I2CCMD_PHY_TIMEOUT 200 73#define E1000_IVAR_VALID 0x80 74#define E1000_GPIE_NSICR 0x00000001 75#define E1000_GPIE_MSIX_MODE 0x00000010 76#define E1000_GPIE_EIAME 0x40000000 77#define E1000_GPIE_PBA 0x80000000 78 79/* Receive Descriptor bit definitions */ 80#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 81#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 82#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 83#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 84#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 85#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 86#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 87 88#define E1000_RXDEXT_STATERR_LB 0x00040000 89#define E1000_RXDEXT_STATERR_CE 0x01000000 90#define E1000_RXDEXT_STATERR_SE 0x02000000 91#define E1000_RXDEXT_STATERR_SEQ 0x04000000 92#define E1000_RXDEXT_STATERR_CXE 0x10000000 93#define E1000_RXDEXT_STATERR_TCPE 0x20000000 94#define E1000_RXDEXT_STATERR_IPE 0x40000000 95#define E1000_RXDEXT_STATERR_RXE 0x80000000 96 97/* Same mask, but for extended and packet split descriptors */ 98#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 99 E1000_RXDEXT_STATERR_CE | \ 100 E1000_RXDEXT_STATERR_SE | \ 101 E1000_RXDEXT_STATERR_SEQ | \ 102 E1000_RXDEXT_STATERR_CXE | \ 103 E1000_RXDEXT_STATERR_RXE) 104 105#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 106#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 107#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 108#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 109#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 110 111 112/* Management Control */ 113#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 114#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 115#define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ 116/* Enable Neighbor Discovery Filtering */ 117#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 118#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 119/* Enable MAC address filtering */ 120#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 121 122/* Receive Control */ 123#define E1000_RCTL_EN 0x00000002 /* enable */ 124#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 125#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 126#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 127#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 128#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 129#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 130#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 131#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 132#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 133#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 134#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 135#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 136#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 137#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 138#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 139#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 140 141/* 142 * Use byte values for the following shift parameters 143 * Usage: 144 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 145 * E1000_PSRCTL_BSIZE0_MASK) | 146 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 147 * E1000_PSRCTL_BSIZE1_MASK) | 148 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 149 * E1000_PSRCTL_BSIZE2_MASK) | 150 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 151 * E1000_PSRCTL_BSIZE3_MASK)) 152 * where value0 = [128..16256], default=256 153 * value1 = [1024..64512], default=4096 154 * value2 = [0..64512], default=4096 155 * value3 = [0..64512], default=0 156 */ 157 158#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 159#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 160#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 161#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 162 163#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 164#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 165#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 166#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 167 168/* SWFW_SYNC Definitions */ 169#define E1000_SWFW_EEP_SM 0x1 170#define E1000_SWFW_PHY0_SM 0x2 171#define E1000_SWFW_PHY1_SM 0x4 172#define E1000_SWFW_PHY2_SM 0x20 173#define E1000_SWFW_PHY3_SM 0x40 174 175/* FACTPS Definitions */ 176/* Device Control */ 177#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 178#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 179#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 180#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 181#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 182#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 183#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 184#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 185#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 186#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 187#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 188/* Defined polarity of Dock/Undock indication in SDP[0] */ 189/* Reset both PHY ports, through PHYRST_N pin */ 190/* enable link status from external LINK_0 and LINK_1 pins */ 191#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 192#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 193#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 194#define E1000_CTRL_RST 0x04000000 /* Global reset */ 195#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 196#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 197#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 198#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 199/* Initiate an interrupt to manageability engine */ 200#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 201 202/* Bit definitions for the Management Data IO (MDIO) and Management Data 203 * Clock (MDC) pins in the Device Control Register. 204 */ 205 206#define E1000_CONNSW_ENRGSRC 0x4 207#define E1000_PCS_CFG_PCS_EN 8 208#define E1000_PCS_LCTL_FLV_LINK_UP 1 209#define E1000_PCS_LCTL_FSV_100 2 210#define E1000_PCS_LCTL_FSV_1000 4 211#define E1000_PCS_LCTL_FDV_FULL 8 212#define E1000_PCS_LCTL_FSD 0x10 213#define E1000_PCS_LCTL_FORCE_LINK 0x20 214#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 215#define E1000_PCS_LCTL_AN_ENABLE 0x10000 216#define E1000_PCS_LCTL_AN_RESTART 0x20000 217#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 218#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 219 220#define E1000_PCS_LSTS_LINK_OK 1 221#define E1000_PCS_LSTS_SPEED_100 2 222#define E1000_PCS_LSTS_SPEED_1000 4 223#define E1000_PCS_LSTS_DUPLEX_FULL 8 224#define E1000_PCS_LSTS_SYNK_OK 0x10 225 226/* Device Status */ 227#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 228#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 229#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 230#define E1000_STATUS_FUNC_SHIFT 2 231#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 232#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 233#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 234#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 235/* Change in Dock/Undock state. Clear on write '0'. */ 236/* Status of Master requests. */ 237#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 238/* BMC external code execution disabled */ 239 240/* Constants used to intrepret the masked PCI-X bus speed. */ 241 242#define SPEED_10 10 243#define SPEED_100 100 244#define SPEED_1000 1000 245#define HALF_DUPLEX 1 246#define FULL_DUPLEX 2 247 248 249#define ADVERTISE_10_HALF 0x0001 250#define ADVERTISE_10_FULL 0x0002 251#define ADVERTISE_100_HALF 0x0004 252#define ADVERTISE_100_FULL 0x0008 253#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 254#define ADVERTISE_1000_FULL 0x0020 255 256/* 1000/H is not supported, nor spec-compliant. */ 257#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 258 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 259 ADVERTISE_1000_FULL) 260#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 261 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 262#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 263#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 264#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 265 ADVERTISE_1000_FULL) 266#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 267 268#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 269 270/* LED Control */ 271#define E1000_LEDCTL_LED0_MODE_SHIFT 0 272#define E1000_LEDCTL_LED0_BLINK 0x00000080 273 274#define E1000_LEDCTL_MODE_LED_ON 0xE 275#define E1000_LEDCTL_MODE_LED_OFF 0xF 276 277/* Transmit Descriptor bit definitions */ 278#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 279#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 280#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 281#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 282#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 283#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 284#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 285/* Extended desc bits for Linksec and timesync */ 286 287/* Transmit Control */ 288#define E1000_TCTL_EN 0x00000002 /* enable tx */ 289#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 290#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 291#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 292#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 293 294/* DMA Coalescing register fields */ 295#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing 296 * Watchdog Timer */ 297#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive 298 * Threshold */ 299#define E1000_DMACR_DMACTHR_SHIFT 16 300#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe 301 * transactions */ 302#define E1000_DMACR_DMAC_LX_SHIFT 28 303#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 304/* DMA Coalescing BMC-to-OS Watchdog Enable */ 305#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 306 307#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit 308 * Threshold */ 309 310#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 311 312#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate 313 * Threshold */ 314#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in 315 * current window */ 316 317#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic 318 * Current Cnt */ 319 320#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold 321 * High val */ 322#define E1000_FCRTC_RTH_COAL_SHIFT 4 323#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ 324 325/* Timestamp in Rx buffer */ 326#define E1000_RXPBS_CFG_TS_EN 0x80000000 327 328/* SerDes Control */ 329#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 330 331/* Receive Checksum Control */ 332#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 333#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 334#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 335#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 336 337/* Header split receive */ 338#define E1000_RFCTL_LEF 0x00040000 339 340/* Collision related configuration parameters */ 341#define E1000_COLLISION_THRESHOLD 15 342#define E1000_CT_SHIFT 4 343#define E1000_COLLISION_DISTANCE 63 344#define E1000_COLD_SHIFT 12 345 346/* Ethertype field values */ 347#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 348 349#define MAX_JUMBO_FRAME_SIZE 0x3F00 350 351/* PBA constants */ 352#define E1000_PBA_34K 0x0022 353#define E1000_PBA_64K 0x0040 /* 64KB */ 354 355/* SW Semaphore Register */ 356#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 357#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 358 359/* Interrupt Cause Read */ 360#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 361#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 362#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 363#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 364#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 365#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 366#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 367#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 368/* If this bit asserted, the driver should claim the interrupt */ 369#define E1000_ICR_INT_ASSERTED 0x80000000 370/* LAN connected device generates an interrupt */ 371#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 372 373/* Extended Interrupt Cause Read */ 374#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 375#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 376#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 377#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 378#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 379#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 380#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 381#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 382#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 383/* TCP Timer */ 384 385/* 386 * This defines the bits that are set in the Interrupt Mask 387 * Set/Read Register. Each bit is documented below: 388 * o RXT0 = Receiver Timer Interrupt (ring 0) 389 * o TXDW = Transmit Descriptor Written Back 390 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 391 * o RXSEQ = Receive Sequence Error 392 * o LSC = Link Status Change 393 */ 394#define IMS_ENABLE_MASK ( \ 395 E1000_IMS_RXT0 | \ 396 E1000_IMS_TXDW | \ 397 E1000_IMS_RXDMT0 | \ 398 E1000_IMS_RXSEQ | \ 399 E1000_IMS_LSC | \ 400 E1000_IMS_DOUTSYNC) 401 402/* Interrupt Mask Set */ 403#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 404#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 405#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 406#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 407#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 408#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 409#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 410#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 411#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 412 413/* Extended Interrupt Mask Set */ 414#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 415 416/* Interrupt Cause Set */ 417#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 418#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 419#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 420 421/* Extended Interrupt Cause Set */ 422/* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 423#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 424 425 426/* Transmit Descriptor Control */ 427/* Enable the counting of descriptors still to be processed. */ 428 429/* Flow Control Constants */ 430#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 431#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 432#define FLOW_CONTROL_TYPE 0x8808 433 434/* 802.1q VLAN Packet Size */ 435#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 436#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 437 438/* Receive Address */ 439/* 440 * Number of high/low register pairs in the RAR. The RAR (Receive Address 441 * Registers) holds the directed and multicast addresses that we monitor. 442 * Technically, we have 16 spots. However, we reserve one of these spots 443 * (RAR[15]) for our directed address used by controllers with 444 * manageability enabled, allowing us room for 15 multicast addresses. 445 */ 446#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 447#define E1000_RAL_MAC_ADDR_LEN 4 448#define E1000_RAH_MAC_ADDR_LEN 2 449#define E1000_RAH_POOL_MASK 0x03FC0000 450#define E1000_RAH_POOL_1 0x00040000 451 452/* Error Codes */ 453#define E1000_SUCCESS 0 454#define E1000_ERR_NVM 1 455#define E1000_ERR_PHY 2 456#define E1000_ERR_CONFIG 3 457#define E1000_ERR_PARAM 4 458#define E1000_ERR_MAC_INIT 5 459#define E1000_ERR_RESET 9 460#define E1000_ERR_MASTER_REQUESTS_PENDING 10 461#define E1000_BLK_PHY_RESET 12 462#define E1000_ERR_SWFW_SYNC 13 463#define E1000_NOT_IMPLEMENTED 14 464#define E1000_ERR_MBX 15 465#define E1000_ERR_INVALID_ARGUMENT 16 466#define E1000_ERR_NO_SPACE 17 467#define E1000_ERR_NVM_PBA_SECTION 18 468#define E1000_ERR_INVM_VALUE_NOT_FOUND 19 469 470/* Loop limit on how long we wait for auto-negotiation to complete */ 471#define COPPER_LINK_UP_LIMIT 10 472#define PHY_AUTO_NEG_LIMIT 45 473#define PHY_FORCE_LIMIT 20 474/* Number of 100 microseconds we wait for PCI Express master disable */ 475#define MASTER_DISABLE_TIMEOUT 800 476/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 477#define PHY_CFG_TIMEOUT 100 478/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 479/* Number of milliseconds for NVM auto read done after MAC reset. */ 480#define AUTO_READ_DONE_TIMEOUT 10 481 482/* Flow Control */ 483#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 484 485#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 486#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 487 488#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 489#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 490#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 491#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 492#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 493#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 494#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 495#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 496 497#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 498#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 499#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 500#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 501#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 502#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 503 504#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 505#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 506#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 507#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 508#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 509#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 510#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 511#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 512#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 513#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 514#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 515 516#define E1000_TIMINCA_16NS_SHIFT 24 517 518#define E1000_TSICR_TXTS 0x00000002 519#define E1000_TSIM_TXTS 0x00000002 520 521#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 522#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 523#define E1000_MDICNFG_PHY_MASK 0x03E00000 524#define E1000_MDICNFG_PHY_SHIFT 21 525 526/* PCI Express Control */ 527#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 528#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 529#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 530#define E1000_GCR_CAP_VER2 0x00040000 531 532/* mPHY Address Control and Data Registers */ 533#define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ 534#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 535#define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ 536 537/* mPHY PCS CLK Register */ 538#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ 539/* mPHY Near End Digital Loopback Override Bit */ 540#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 541 542/* PHY Control Register */ 543#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 544#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 545#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 546#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 547#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 548#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 549#define MII_CR_SPEED_1000 0x0040 550#define MII_CR_SPEED_100 0x2000 551#define MII_CR_SPEED_10 0x0000 552 553/* PHY Status Register */ 554#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 555#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 556 557/* Autoneg Advertisement Register */ 558#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 559#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 560#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 561#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 562#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 563#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 564 565/* Link Partner Ability Register (Base Page) */ 566#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 567#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 568 569/* Autoneg Expansion Register */ 570 571/* 1000BASE-T Control Register */ 572#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 573#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 574#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 575 /* 0=Configure PHY as Slave */ 576#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 577 /* 0=Automatic Master/Slave config */ 578 579/* 1000BASE-T Status Register */ 580#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 581#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 582 583 584/* PHY 1000 MII Register/Bit Definitions */ 585/* PHY Registers defined by IEEE */ 586#define PHY_CONTROL 0x00 /* Control Register */ 587#define PHY_STATUS 0x01 /* Status Register */ 588#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 589#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 590#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 591#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 592#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 593#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 594 595/* NVM Control */ 596#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 597#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 598#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 599#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 600#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 601#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 602#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 603/* NVM Addressing bits based on type 0=small, 1=large */ 604#define E1000_EECD_ADDR_BITS 0x00000400 605#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 606#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 607#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 608#define E1000_EECD_SIZE_EX_SHIFT 11 609#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 610#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 611#define E1000_FLUDONE_ATTEMPTS 20000 612#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 613#define E1000_I210_FIFO_SEL_RX 0x00 614#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 615#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 616#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 617#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 618#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 619#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 620#define E1000_FLUDONE_ATTEMPTS 20000 621#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 622#define E1000_I210_FIFO_SEL_RX 0x00 623#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 624#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 625#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 626#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 627 628 629/* Offset to data in NVM read/write registers */ 630#define E1000_NVM_RW_REG_DATA 16 631#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 632#define E1000_NVM_RW_REG_START 1 /* Start operation */ 633#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 634#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 635 636/* NVM Word Offsets */ 637#define NVM_COMPAT 0x0003 638#define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ 639#define NVM_VERSION 0x0005 640#define NVM_INIT_CONTROL2_REG 0x000F 641#define NVM_INIT_CONTROL3_PORT_B 0x0014 642#define NVM_INIT_CONTROL3_PORT_A 0x0024 643#define NVM_ALT_MAC_ADDR_PTR 0x0037 644#define NVM_CHECKSUM_REG 0x003F 645#define NVM_COMPATIBILITY_REG_3 0x0003 646#define NVM_COMPATIBILITY_BIT_MASK 0x8000 647#define NVM_MAC_ADDR 0x0000 648#define NVM_SUB_DEV_ID 0x000B 649#define NVM_SUB_VEN_ID 0x000C 650#define NVM_DEV_ID 0x000D 651#define NVM_VEN_ID 0x000E 652#define NVM_INIT_CTRL_2 0x000F 653#define NVM_INIT_CTRL_4 0x0013 654#define NVM_LED_1_CFG 0x001C 655#define NVM_LED_0_2_CFG 0x001F 656 657/* NVM version defines */ 658#define NVM_ETRACK_WORD 0x0042 659#define NVM_COMB_VER_OFF 0x0083 660#define NVM_COMB_VER_PTR 0x003d 661#define NVM_MAJOR_MASK 0xF000 662#define NVM_MINOR_MASK 0x0FF0 663#define NVM_BUILD_MASK 0x000F 664#define NVM_COMB_VER_MASK 0x00FF 665#define NVM_MAJOR_SHIFT 12 666#define NVM_MINOR_SHIFT 4 667#define NVM_COMB_VER_SHFT 8 668#define NVM_VER_INVALID 0xFFFF 669#define NVM_ETRACK_SHIFT 16 670 671#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 672#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 673#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 674#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 675 676#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 677 678/* Mask bits for fields in Word 0x24 of the NVM */ 679#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 680#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 681 682/* Mask bits for fields in Word 0x0f of the NVM */ 683#define NVM_WORD0F_PAUSE_MASK 0x3000 684#define NVM_WORD0F_ASM_DIR 0x2000 685 686/* Mask bits for fields in Word 0x1a of the NVM */ 687 688/* length of string needed to store part num */ 689#define E1000_PBANUM_LENGTH 11 690 691/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 692#define NVM_SUM 0xBABA 693 694#define NVM_PBA_OFFSET_0 8 695#define NVM_PBA_OFFSET_1 9 696#define NVM_RESERVED_WORD 0xFFFF 697#define NVM_PBA_PTR_GUARD 0xFAFA 698#define NVM_WORD_SIZE_BASE_SHIFT 6 699 700/* NVM Commands - Microwire */ 701 702/* NVM Commands - SPI */ 703#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 704#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 705#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 706#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 707#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 708#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 709 710/* SPI NVM Status Register */ 711#define NVM_STATUS_RDY_SPI 0x01 712 713/* Word definitions for ID LED Settings */ 714#define ID_LED_RESERVED_0000 0x0000 715#define ID_LED_RESERVED_FFFF 0xFFFF 716#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 717 (ID_LED_OFF1_OFF2 << 8) | \ 718 (ID_LED_DEF1_DEF2 << 4) | \ 719 (ID_LED_DEF1_DEF2)) 720#define ID_LED_DEF1_DEF2 0x1 721#define ID_LED_DEF1_ON2 0x2 722#define ID_LED_DEF1_OFF2 0x3 723#define ID_LED_ON1_DEF2 0x4 724#define ID_LED_ON1_ON2 0x5 725#define ID_LED_ON1_OFF2 0x6 726#define ID_LED_OFF1_DEF2 0x7 727#define ID_LED_OFF1_ON2 0x8 728#define ID_LED_OFF1_OFF2 0x9 729 730#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 731#define IGP_ACTIVITY_LED_ENABLE 0x0300 732#define IGP_LED3_MODE 0x07000000 733 734/* PCI/PCI-X/PCI-EX Config space */ 735#define PCIE_DEVICE_CONTROL2 0x28 736#define PCIE_DEVICE_CONTROL2_16ms 0x0005 737 738#define PHY_REVISION_MASK 0xFFFFFFF0 739#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 740#define MAX_PHY_MULTI_PAGE_REG 0xF 741 742/* Bit definitions for valid PHY IDs. */ 743/* 744 * I = Integrated 745 * E = External 746 */ 747#define M88E1111_I_PHY_ID 0x01410CC0 748#define M88E1112_E_PHY_ID 0x01410C90 749#define I347AT4_E_PHY_ID 0x01410DC0 750#define IGP03E1000_E_PHY_ID 0x02A80390 751#define I82580_I_PHY_ID 0x015403A0 752#define I350_I_PHY_ID 0x015403B0 753#define M88_VENDOR 0x0141 754#define I210_I_PHY_ID 0x01410C00 755 756/* M88E1000 Specific Registers */ 757#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 758#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 759#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 760 761#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 762#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 763 764/* M88E1000 PHY Specific Control Register */ 765#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 766/* 1=CLK125 low, 0=CLK125 toggling */ 767#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 768 /* Manual MDI configuration */ 769#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 770/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 771#define M88E1000_PSCR_AUTO_X_1000T 0x0040 772/* Auto crossover enabled all speeds */ 773#define M88E1000_PSCR_AUTO_X_MODE 0x0060 774/* 775 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 776 * 0=Normal 10BASE-T Rx Threshold 777 */ 778/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 779#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 780 781/* M88E1000 PHY Specific Status Register */ 782#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 783#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 784#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 785/* 786 * 0 = <50M 787 * 1 = 50-80M 788 * 2 = 80-110M 789 * 3 = 110-140M 790 * 4 = >140M 791 */ 792#define M88E1000_PSSR_CABLE_LENGTH 0x0380 793#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 794#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 795 796#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 797 798/* M88E1000 Extended PHY Specific Control Register */ 799/* 800 * 1 = Lost lock detect enabled. 801 * Will assert lost lock and bring 802 * link down if idle not seen 803 * within 1ms in 1000BASE-T 804 */ 805/* 806 * Number of times we will attempt to autonegotiate before downshifting if we 807 * are the master 808 */ 809#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 810#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 811/* 812 * Number of times we will attempt to autonegotiate before downshifting if we 813 * are the slave 814 */ 815#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 816#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 817#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 818 819/* Intel i347-AT4 Registers */ 820 821#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 822#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 823#define I347AT4_PAGE_SELECT 0x16 824 825/* i347-AT4 Extended PHY Specific Control Register */ 826 827/* 828 * Number of times we will attempt to autonegotiate before downshifting if we 829 * are the master 830 */ 831#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 832#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 833#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 834#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 835#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 836#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 837#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 838#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 839#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 840#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 841 842/* i347-AT4 PHY Cable Diagnostics Control */ 843#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 844 845/* Marvell 1112 only registers */ 846#define M88E1112_VCT_DSP_DISTANCE 0x001A 847 848/* M88EC018 Rev 2 specific DownShift settings */ 849#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 850#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 851 852/* MDI Control */ 853#define E1000_MDIC_DATA_MASK 0x0000FFFF 854#define E1000_MDIC_REG_MASK 0x001F0000 855#define E1000_MDIC_REG_SHIFT 16 856#define E1000_MDIC_PHY_MASK 0x03E00000 857#define E1000_MDIC_PHY_SHIFT 21 858#define E1000_MDIC_OP_WRITE 0x04000000 859#define E1000_MDIC_OP_READ 0x08000000 860#define E1000_MDIC_READY 0x10000000 861#define E1000_MDIC_INT_EN 0x20000000 862#define E1000_MDIC_ERROR 0x40000000 863#define E1000_MDIC_DEST 0x80000000 864 865/* Thermal Sensor */ 866#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 867#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ 868 869/* Energy Efficient Ethernet */ 870#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ 871#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 872#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 873#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 874#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ 875#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 876#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ 877#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 878 879/* SerDes Control */ 880#define E1000_GEN_CTL_READY 0x80000000 881#define E1000_GEN_CTL_ADDRESS_SHIFT 8 882#define E1000_GEN_POLL_TIMEOUT 640 883 884#define E1000_VFTA_ENTRY_SHIFT 5 885#define E1000_VFTA_ENTRY_MASK 0x7F 886#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 887 888/* DMA Coalescing register fields */ 889#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based 890 on DMA coal */ 891 892/* Tx Rate-Scheduler Config fields */ 893#define E1000_RTTBCNRC_RS_ENA 0x80000000 894#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 895#define E1000_RTTBCNRC_RF_INT_SHIFT 14 896#define E1000_RTTBCNRC_RF_INT_MASK \ 897 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 898 899#endif 900