e1000_phy.c revision c75c4edfc38da8235d110a8f28b596193de787ab
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#include <linux/if_ether.h> 28#include <linux/delay.h> 29 30#include "e1000_mac.h" 31#include "e1000_phy.h" 32 33static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 34static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 35 u16 *phy_ctrl); 36static s32 igb_wait_autoneg(struct e1000_hw *hw); 37static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 38 39/* Cable length tables */ 40static const u16 e1000_m88_cable_length_table[] = { 41 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 42#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 43 (sizeof(e1000_m88_cable_length_table) / \ 44 sizeof(e1000_m88_cable_length_table[0])) 45 46static const u16 e1000_igp_2_cable_length_table[] = { 47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 48 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 49 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 50 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 51 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 52 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 53 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 54 104, 109, 114, 118, 121, 124}; 55#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 56 (sizeof(e1000_igp_2_cable_length_table) / \ 57 sizeof(e1000_igp_2_cable_length_table[0])) 58 59/** 60 * igb_check_reset_block - Check if PHY reset is blocked 61 * @hw: pointer to the HW structure 62 * 63 * Read the PHY management control register and check whether a PHY reset 64 * is blocked. If a reset is not blocked return 0, otherwise 65 * return E1000_BLK_PHY_RESET (12). 66 **/ 67s32 igb_check_reset_block(struct e1000_hw *hw) 68{ 69 u32 manc; 70 71 manc = rd32(E1000_MANC); 72 73 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 74} 75 76/** 77 * igb_get_phy_id - Retrieve the PHY ID and revision 78 * @hw: pointer to the HW structure 79 * 80 * Reads the PHY registers and stores the PHY ID and possibly the PHY 81 * revision in the hardware structure. 82 **/ 83s32 igb_get_phy_id(struct e1000_hw *hw) 84{ 85 struct e1000_phy_info *phy = &hw->phy; 86 s32 ret_val = 0; 87 u16 phy_id; 88 89 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 90 if (ret_val) 91 goto out; 92 93 phy->id = (u32)(phy_id << 16); 94 udelay(20); 95 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 96 if (ret_val) 97 goto out; 98 99 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 100 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 101 102out: 103 return ret_val; 104} 105 106/** 107 * igb_phy_reset_dsp - Reset PHY DSP 108 * @hw: pointer to the HW structure 109 * 110 * Reset the digital signal processor. 111 **/ 112static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 113{ 114 s32 ret_val = 0; 115 116 if (!(hw->phy.ops.write_reg)) 117 goto out; 118 119 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 120 if (ret_val) 121 goto out; 122 123 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 124 125out: 126 return ret_val; 127} 128 129/** 130 * igb_read_phy_reg_mdic - Read MDI control register 131 * @hw: pointer to the HW structure 132 * @offset: register offset to be read 133 * @data: pointer to the read data 134 * 135 * Reads the MDI control regsiter in the PHY at offset and stores the 136 * information read to data. 137 **/ 138s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 139{ 140 struct e1000_phy_info *phy = &hw->phy; 141 u32 i, mdic = 0; 142 s32 ret_val = 0; 143 144 if (offset > MAX_PHY_REG_ADDRESS) { 145 hw_dbg("PHY Address %d is out of range\n", offset); 146 ret_val = -E1000_ERR_PARAM; 147 goto out; 148 } 149 150 /* Set up Op-code, Phy Address, and register offset in the MDI 151 * Control register. The MAC will take care of interfacing with the 152 * PHY to retrieve the desired data. 153 */ 154 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 155 (phy->addr << E1000_MDIC_PHY_SHIFT) | 156 (E1000_MDIC_OP_READ)); 157 158 wr32(E1000_MDIC, mdic); 159 160 /* Poll the ready bit to see if the MDI read completed 161 * Increasing the time out as testing showed failures with 162 * the lower time out 163 */ 164 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 165 udelay(50); 166 mdic = rd32(E1000_MDIC); 167 if (mdic & E1000_MDIC_READY) 168 break; 169 } 170 if (!(mdic & E1000_MDIC_READY)) { 171 hw_dbg("MDI Read did not complete\n"); 172 ret_val = -E1000_ERR_PHY; 173 goto out; 174 } 175 if (mdic & E1000_MDIC_ERROR) { 176 hw_dbg("MDI Error\n"); 177 ret_val = -E1000_ERR_PHY; 178 goto out; 179 } 180 *data = (u16) mdic; 181 182out: 183 return ret_val; 184} 185 186/** 187 * igb_write_phy_reg_mdic - Write MDI control register 188 * @hw: pointer to the HW structure 189 * @offset: register offset to write to 190 * @data: data to write to register at offset 191 * 192 * Writes data to MDI control register in the PHY at offset. 193 **/ 194s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 195{ 196 struct e1000_phy_info *phy = &hw->phy; 197 u32 i, mdic = 0; 198 s32 ret_val = 0; 199 200 if (offset > MAX_PHY_REG_ADDRESS) { 201 hw_dbg("PHY Address %d is out of range\n", offset); 202 ret_val = -E1000_ERR_PARAM; 203 goto out; 204 } 205 206 /* Set up Op-code, Phy Address, and register offset in the MDI 207 * Control register. The MAC will take care of interfacing with the 208 * PHY to retrieve the desired data. 209 */ 210 mdic = (((u32)data) | 211 (offset << E1000_MDIC_REG_SHIFT) | 212 (phy->addr << E1000_MDIC_PHY_SHIFT) | 213 (E1000_MDIC_OP_WRITE)); 214 215 wr32(E1000_MDIC, mdic); 216 217 /* Poll the ready bit to see if the MDI read completed 218 * Increasing the time out as testing showed failures with 219 * the lower time out 220 */ 221 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 222 udelay(50); 223 mdic = rd32(E1000_MDIC); 224 if (mdic & E1000_MDIC_READY) 225 break; 226 } 227 if (!(mdic & E1000_MDIC_READY)) { 228 hw_dbg("MDI Write did not complete\n"); 229 ret_val = -E1000_ERR_PHY; 230 goto out; 231 } 232 if (mdic & E1000_MDIC_ERROR) { 233 hw_dbg("MDI Error\n"); 234 ret_val = -E1000_ERR_PHY; 235 goto out; 236 } 237 238out: 239 return ret_val; 240} 241 242/** 243 * igb_read_phy_reg_i2c - Read PHY register using i2c 244 * @hw: pointer to the HW structure 245 * @offset: register offset to be read 246 * @data: pointer to the read data 247 * 248 * Reads the PHY register at offset using the i2c interface and stores the 249 * retrieved information in data. 250 **/ 251s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 252{ 253 struct e1000_phy_info *phy = &hw->phy; 254 u32 i, i2ccmd = 0; 255 256 /* Set up Op-code, Phy Address, and register address in the I2CCMD 257 * register. The MAC will take care of interfacing with the 258 * PHY to retrieve the desired data. 259 */ 260 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 261 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 262 (E1000_I2CCMD_OPCODE_READ)); 263 264 wr32(E1000_I2CCMD, i2ccmd); 265 266 /* Poll the ready bit to see if the I2C read completed */ 267 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 268 udelay(50); 269 i2ccmd = rd32(E1000_I2CCMD); 270 if (i2ccmd & E1000_I2CCMD_READY) 271 break; 272 } 273 if (!(i2ccmd & E1000_I2CCMD_READY)) { 274 hw_dbg("I2CCMD Read did not complete\n"); 275 return -E1000_ERR_PHY; 276 } 277 if (i2ccmd & E1000_I2CCMD_ERROR) { 278 hw_dbg("I2CCMD Error bit set\n"); 279 return -E1000_ERR_PHY; 280 } 281 282 /* Need to byte-swap the 16-bit value. */ 283 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 284 285 return 0; 286} 287 288/** 289 * igb_write_phy_reg_i2c - Write PHY register using i2c 290 * @hw: pointer to the HW structure 291 * @offset: register offset to write to 292 * @data: data to write at register offset 293 * 294 * Writes the data to PHY register at the offset using the i2c interface. 295 **/ 296s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 297{ 298 struct e1000_phy_info *phy = &hw->phy; 299 u32 i, i2ccmd = 0; 300 u16 phy_data_swapped; 301 302 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 303 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 304 hw_dbg("PHY I2C Address %d is out of range.\n", 305 hw->phy.addr); 306 return -E1000_ERR_CONFIG; 307 } 308 309 /* Swap the data bytes for the I2C interface */ 310 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 311 312 /* Set up Op-code, Phy Address, and register address in the I2CCMD 313 * register. The MAC will take care of interfacing with the 314 * PHY to retrieve the desired data. 315 */ 316 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 317 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 318 E1000_I2CCMD_OPCODE_WRITE | 319 phy_data_swapped); 320 321 wr32(E1000_I2CCMD, i2ccmd); 322 323 /* Poll the ready bit to see if the I2C read completed */ 324 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 325 udelay(50); 326 i2ccmd = rd32(E1000_I2CCMD); 327 if (i2ccmd & E1000_I2CCMD_READY) 328 break; 329 } 330 if (!(i2ccmd & E1000_I2CCMD_READY)) { 331 hw_dbg("I2CCMD Write did not complete\n"); 332 return -E1000_ERR_PHY; 333 } 334 if (i2ccmd & E1000_I2CCMD_ERROR) { 335 hw_dbg("I2CCMD Error bit set\n"); 336 return -E1000_ERR_PHY; 337 } 338 339 return 0; 340} 341 342/** 343 * igb_read_sfp_data_byte - Reads SFP module data. 344 * @hw: pointer to the HW structure 345 * @offset: byte location offset to be read 346 * @data: read data buffer pointer 347 * 348 * Reads one byte from SFP module data stored 349 * in SFP resided EEPROM memory or SFP diagnostic area. 350 * Function should be called with 351 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 352 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 353 * access 354 **/ 355s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 356{ 357 u32 i = 0; 358 u32 i2ccmd = 0; 359 u32 data_local = 0; 360 361 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 362 hw_dbg("I2CCMD command address exceeds upper limit\n"); 363 return -E1000_ERR_PHY; 364 } 365 366 /* Set up Op-code, EEPROM Address,in the I2CCMD 367 * register. The MAC will take care of interfacing with the 368 * EEPROM to retrieve the desired data. 369 */ 370 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 371 E1000_I2CCMD_OPCODE_READ); 372 373 wr32(E1000_I2CCMD, i2ccmd); 374 375 /* Poll the ready bit to see if the I2C read completed */ 376 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 377 udelay(50); 378 data_local = rd32(E1000_I2CCMD); 379 if (data_local & E1000_I2CCMD_READY) 380 break; 381 } 382 if (!(data_local & E1000_I2CCMD_READY)) { 383 hw_dbg("I2CCMD Read did not complete\n"); 384 return -E1000_ERR_PHY; 385 } 386 if (data_local & E1000_I2CCMD_ERROR) { 387 hw_dbg("I2CCMD Error bit set\n"); 388 return -E1000_ERR_PHY; 389 } 390 *data = (u8) data_local & 0xFF; 391 392 return 0; 393} 394 395/** 396 * igb_read_phy_reg_igp - Read igp PHY register 397 * @hw: pointer to the HW structure 398 * @offset: register offset to be read 399 * @data: pointer to the read data 400 * 401 * Acquires semaphore, if necessary, then reads the PHY register at offset 402 * and storing the retrieved information in data. Release any acquired 403 * semaphores before exiting. 404 **/ 405s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 406{ 407 s32 ret_val = 0; 408 409 if (!(hw->phy.ops.acquire)) 410 goto out; 411 412 ret_val = hw->phy.ops.acquire(hw); 413 if (ret_val) 414 goto out; 415 416 if (offset > MAX_PHY_MULTI_PAGE_REG) { 417 ret_val = igb_write_phy_reg_mdic(hw, 418 IGP01E1000_PHY_PAGE_SELECT, 419 (u16)offset); 420 if (ret_val) { 421 hw->phy.ops.release(hw); 422 goto out; 423 } 424 } 425 426 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 427 data); 428 429 hw->phy.ops.release(hw); 430 431out: 432 return ret_val; 433} 434 435/** 436 * igb_write_phy_reg_igp - Write igp PHY register 437 * @hw: pointer to the HW structure 438 * @offset: register offset to write to 439 * @data: data to write at register offset 440 * 441 * Acquires semaphore, if necessary, then writes the data to PHY register 442 * at the offset. Release any acquired semaphores before exiting. 443 **/ 444s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 445{ 446 s32 ret_val = 0; 447 448 if (!(hw->phy.ops.acquire)) 449 goto out; 450 451 ret_val = hw->phy.ops.acquire(hw); 452 if (ret_val) 453 goto out; 454 455 if (offset > MAX_PHY_MULTI_PAGE_REG) { 456 ret_val = igb_write_phy_reg_mdic(hw, 457 IGP01E1000_PHY_PAGE_SELECT, 458 (u16)offset); 459 if (ret_val) { 460 hw->phy.ops.release(hw); 461 goto out; 462 } 463 } 464 465 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 466 data); 467 468 hw->phy.ops.release(hw); 469 470out: 471 return ret_val; 472} 473 474/** 475 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 476 * @hw: pointer to the HW structure 477 * 478 * Sets up Carrier-sense on Transmit and downshift values. 479 **/ 480s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 481{ 482 struct e1000_phy_info *phy = &hw->phy; 483 s32 ret_val; 484 u16 phy_data; 485 486 if (phy->reset_disable) { 487 ret_val = 0; 488 goto out; 489 } 490 491 if (phy->type == e1000_phy_82580) { 492 ret_val = hw->phy.ops.reset(hw); 493 if (ret_val) { 494 hw_dbg("Error resetting the PHY.\n"); 495 goto out; 496 } 497 } 498 499 /* Enable CRS on TX. This must be set for half-duplex operation. */ 500 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 501 if (ret_val) 502 goto out; 503 504 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 505 506 /* Enable downshift */ 507 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 508 509 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 510 if (ret_val) 511 goto out; 512 513 /* Set MDI/MDIX mode */ 514 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 515 if (ret_val) 516 goto out; 517 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 518 /* Options: 519 * 0 - Auto (default) 520 * 1 - MDI mode 521 * 2 - MDI-X mode 522 */ 523 switch (hw->phy.mdix) { 524 case 1: 525 break; 526 case 2: 527 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 528 break; 529 case 0: 530 default: 531 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 532 break; 533 } 534 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 535 536out: 537 return ret_val; 538} 539 540/** 541 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 542 * @hw: pointer to the HW structure 543 * 544 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 545 * and downshift values are set also. 546 **/ 547s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 548{ 549 struct e1000_phy_info *phy = &hw->phy; 550 s32 ret_val; 551 u16 phy_data; 552 553 if (phy->reset_disable) { 554 ret_val = 0; 555 goto out; 556 } 557 558 /* Enable CRS on TX. This must be set for half-duplex operation. */ 559 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 560 if (ret_val) 561 goto out; 562 563 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 564 565 /* Options: 566 * MDI/MDI-X = 0 (default) 567 * 0 - Auto for all speeds 568 * 1 - MDI mode 569 * 2 - MDI-X mode 570 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 571 */ 572 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 573 574 switch (phy->mdix) { 575 case 1: 576 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 577 break; 578 case 2: 579 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 580 break; 581 case 3: 582 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 583 break; 584 case 0: 585 default: 586 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 587 break; 588 } 589 590 /* Options: 591 * disable_polarity_correction = 0 (default) 592 * Automatic Correction for Reversed Cable Polarity 593 * 0 - Disabled 594 * 1 - Enabled 595 */ 596 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 597 if (phy->disable_polarity_correction == 1) 598 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 599 600 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 601 if (ret_val) 602 goto out; 603 604 if (phy->revision < E1000_REVISION_4) { 605 /* Force TX_CLK in the Extended PHY Specific Control Register 606 * to 25MHz clock. 607 */ 608 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 609 &phy_data); 610 if (ret_val) 611 goto out; 612 613 phy_data |= M88E1000_EPSCR_TX_CLK_25; 614 615 if ((phy->revision == E1000_REVISION_2) && 616 (phy->id == M88E1111_I_PHY_ID)) { 617 /* 82573L PHY - set the downshift counter to 5x. */ 618 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 619 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 620 } else { 621 /* Configure Master and Slave downshift values */ 622 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 623 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 624 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 625 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 626 } 627 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 628 phy_data); 629 if (ret_val) 630 goto out; 631 } 632 633 /* Commit the changes. */ 634 ret_val = igb_phy_sw_reset(hw); 635 if (ret_val) { 636 hw_dbg("Error committing the PHY changes\n"); 637 goto out; 638 } 639 640out: 641 return ret_val; 642} 643 644/** 645 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 646 * @hw: pointer to the HW structure 647 * 648 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 649 * Also enables and sets the downshift parameters. 650 **/ 651s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 652{ 653 struct e1000_phy_info *phy = &hw->phy; 654 s32 ret_val; 655 u16 phy_data; 656 657 if (phy->reset_disable) 658 return 0; 659 660 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 661 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 662 if (ret_val) 663 return ret_val; 664 665 /* Options: 666 * MDI/MDI-X = 0 (default) 667 * 0 - Auto for all speeds 668 * 1 - MDI mode 669 * 2 - MDI-X mode 670 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 671 */ 672 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 673 674 switch (phy->mdix) { 675 case 1: 676 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 677 break; 678 case 2: 679 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 680 break; 681 case 3: 682 /* M88E1112 does not support this mode) */ 683 if (phy->id != M88E1112_E_PHY_ID) { 684 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 685 break; 686 } 687 case 0: 688 default: 689 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 690 break; 691 } 692 693 /* Options: 694 * disable_polarity_correction = 0 (default) 695 * Automatic Correction for Reversed Cable Polarity 696 * 0 - Disabled 697 * 1 - Enabled 698 */ 699 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 700 if (phy->disable_polarity_correction == 1) 701 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 702 703 /* Enable downshift and setting it to X6 */ 704 if (phy->id == M88E1543_E_PHY_ID) { 705 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 706 ret_val = 707 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 708 if (ret_val) 709 return ret_val; 710 711 ret_val = igb_phy_sw_reset(hw); 712 if (ret_val) { 713 hw_dbg("Error committing the PHY changes\n"); 714 return ret_val; 715 } 716 } 717 718 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 719 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 720 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 721 722 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 723 if (ret_val) 724 return ret_val; 725 726 /* Commit the changes. */ 727 ret_val = igb_phy_sw_reset(hw); 728 if (ret_val) { 729 hw_dbg("Error committing the PHY changes\n"); 730 return ret_val; 731 } 732 ret_val = igb_set_master_slave_mode(hw); 733 if (ret_val) 734 return ret_val; 735 736 return 0; 737} 738 739/** 740 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 741 * @hw: pointer to the HW structure 742 * 743 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 744 * igp PHY's. 745 **/ 746s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 747{ 748 struct e1000_phy_info *phy = &hw->phy; 749 s32 ret_val; 750 u16 data; 751 752 if (phy->reset_disable) { 753 ret_val = 0; 754 goto out; 755 } 756 757 ret_val = phy->ops.reset(hw); 758 if (ret_val) { 759 hw_dbg("Error resetting the PHY.\n"); 760 goto out; 761 } 762 763 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 764 * timeout issues when LFS is enabled. 765 */ 766 msleep(100); 767 768 /* The NVM settings will configure LPLU in D3 for 769 * non-IGP1 PHYs. 770 */ 771 if (phy->type == e1000_phy_igp) { 772 /* disable lplu d3 during driver init */ 773 if (phy->ops.set_d3_lplu_state) 774 ret_val = phy->ops.set_d3_lplu_state(hw, false); 775 if (ret_val) { 776 hw_dbg("Error Disabling LPLU D3\n"); 777 goto out; 778 } 779 } 780 781 /* disable lplu d0 during driver init */ 782 ret_val = phy->ops.set_d0_lplu_state(hw, false); 783 if (ret_val) { 784 hw_dbg("Error Disabling LPLU D0\n"); 785 goto out; 786 } 787 /* Configure mdi-mdix settings */ 788 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 789 if (ret_val) 790 goto out; 791 792 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 793 794 switch (phy->mdix) { 795 case 1: 796 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 797 break; 798 case 2: 799 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 800 break; 801 case 0: 802 default: 803 data |= IGP01E1000_PSCR_AUTO_MDIX; 804 break; 805 } 806 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 807 if (ret_val) 808 goto out; 809 810 /* set auto-master slave resolution settings */ 811 if (hw->mac.autoneg) { 812 /* when autonegotiation advertisement is only 1000Mbps then we 813 * should disable SmartSpeed and enable Auto MasterSlave 814 * resolution as hardware default. 815 */ 816 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 817 /* Disable SmartSpeed */ 818 ret_val = phy->ops.read_reg(hw, 819 IGP01E1000_PHY_PORT_CONFIG, 820 &data); 821 if (ret_val) 822 goto out; 823 824 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 825 ret_val = phy->ops.write_reg(hw, 826 IGP01E1000_PHY_PORT_CONFIG, 827 data); 828 if (ret_val) 829 goto out; 830 831 /* Set auto Master/Slave resolution process */ 832 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 833 if (ret_val) 834 goto out; 835 836 data &= ~CR_1000T_MS_ENABLE; 837 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 838 if (ret_val) 839 goto out; 840 } 841 842 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 843 if (ret_val) 844 goto out; 845 846 /* load defaults for future use */ 847 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 848 ((data & CR_1000T_MS_VALUE) ? 849 e1000_ms_force_master : 850 e1000_ms_force_slave) : 851 e1000_ms_auto; 852 853 switch (phy->ms_type) { 854 case e1000_ms_force_master: 855 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 856 break; 857 case e1000_ms_force_slave: 858 data |= CR_1000T_MS_ENABLE; 859 data &= ~(CR_1000T_MS_VALUE); 860 break; 861 case e1000_ms_auto: 862 data &= ~CR_1000T_MS_ENABLE; 863 default: 864 break; 865 } 866 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 867 if (ret_val) 868 goto out; 869 } 870 871out: 872 return ret_val; 873} 874 875/** 876 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 877 * @hw: pointer to the HW structure 878 * 879 * Performs initial bounds checking on autoneg advertisement parameter, then 880 * configure to advertise the full capability. Setup the PHY to autoneg 881 * and restart the negotiation process between the link partner. If 882 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 883 **/ 884static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 885{ 886 struct e1000_phy_info *phy = &hw->phy; 887 s32 ret_val; 888 u16 phy_ctrl; 889 890 /* Perform some bounds checking on the autoneg advertisement 891 * parameter. 892 */ 893 phy->autoneg_advertised &= phy->autoneg_mask; 894 895 /* If autoneg_advertised is zero, we assume it was not defaulted 896 * by the calling code so we set to advertise full capability. 897 */ 898 if (phy->autoneg_advertised == 0) 899 phy->autoneg_advertised = phy->autoneg_mask; 900 901 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 902 ret_val = igb_phy_setup_autoneg(hw); 903 if (ret_val) { 904 hw_dbg("Error Setting up Auto-Negotiation\n"); 905 goto out; 906 } 907 hw_dbg("Restarting Auto-Neg\n"); 908 909 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 910 * the Auto Neg Restart bit in the PHY control register. 911 */ 912 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 913 if (ret_val) 914 goto out; 915 916 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 917 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 918 if (ret_val) 919 goto out; 920 921 /* Does the user want to wait for Auto-Neg to complete here, or 922 * check at a later time (for example, callback routine). 923 */ 924 if (phy->autoneg_wait_to_complete) { 925 ret_val = igb_wait_autoneg(hw); 926 if (ret_val) { 927 hw_dbg("Error while waiting for autoneg to complete\n"); 928 goto out; 929 } 930 } 931 932 hw->mac.get_link_status = true; 933 934out: 935 return ret_val; 936} 937 938/** 939 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 940 * @hw: pointer to the HW structure 941 * 942 * Reads the MII auto-neg advertisement register and/or the 1000T control 943 * register and if the PHY is already setup for auto-negotiation, then 944 * return successful. Otherwise, setup advertisement and flow control to 945 * the appropriate values for the wanted auto-negotiation. 946 **/ 947static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 948{ 949 struct e1000_phy_info *phy = &hw->phy; 950 s32 ret_val; 951 u16 mii_autoneg_adv_reg; 952 u16 mii_1000t_ctrl_reg = 0; 953 954 phy->autoneg_advertised &= phy->autoneg_mask; 955 956 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 957 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 958 if (ret_val) 959 goto out; 960 961 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 962 /* Read the MII 1000Base-T Control Register (Address 9). */ 963 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 964 &mii_1000t_ctrl_reg); 965 if (ret_val) 966 goto out; 967 } 968 969 /* Need to parse both autoneg_advertised and fc and set up 970 * the appropriate PHY registers. First we will parse for 971 * autoneg_advertised software override. Since we can advertise 972 * a plethora of combinations, we need to check each bit 973 * individually. 974 */ 975 976 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 977 * Advertisement Register (Address 4) and the 1000 mb speed bits in 978 * the 1000Base-T Control Register (Address 9). 979 */ 980 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 981 NWAY_AR_100TX_HD_CAPS | 982 NWAY_AR_10T_FD_CAPS | 983 NWAY_AR_10T_HD_CAPS); 984 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 985 986 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 987 988 /* Do we want to advertise 10 Mb Half Duplex? */ 989 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 990 hw_dbg("Advertise 10mb Half duplex\n"); 991 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 992 } 993 994 /* Do we want to advertise 10 Mb Full Duplex? */ 995 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 996 hw_dbg("Advertise 10mb Full duplex\n"); 997 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 998 } 999 1000 /* Do we want to advertise 100 Mb Half Duplex? */ 1001 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1002 hw_dbg("Advertise 100mb Half duplex\n"); 1003 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1004 } 1005 1006 /* Do we want to advertise 100 Mb Full Duplex? */ 1007 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1008 hw_dbg("Advertise 100mb Full duplex\n"); 1009 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1010 } 1011 1012 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1013 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1014 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 1015 1016 /* Do we want to advertise 1000 Mb Full Duplex? */ 1017 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1018 hw_dbg("Advertise 1000mb Full duplex\n"); 1019 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1020 } 1021 1022 /* Check for a software override of the flow control settings, and 1023 * setup the PHY advertisement registers accordingly. If 1024 * auto-negotiation is enabled, then software will have to set the 1025 * "PAUSE" bits to the correct value in the Auto-Negotiation 1026 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1027 * negotiation. 1028 * 1029 * The possible values of the "fc" parameter are: 1030 * 0: Flow control is completely disabled 1031 * 1: Rx flow control is enabled (we can receive pause frames 1032 * but not send pause frames). 1033 * 2: Tx flow control is enabled (we can send pause frames 1034 * but we do not support receiving pause frames). 1035 * 3: Both Rx and TX flow control (symmetric) are enabled. 1036 * other: No software override. The flow control configuration 1037 * in the EEPROM is used. 1038 */ 1039 switch (hw->fc.current_mode) { 1040 case e1000_fc_none: 1041 /* Flow control (RX & TX) is completely disabled by a 1042 * software over-ride. 1043 */ 1044 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1045 break; 1046 case e1000_fc_rx_pause: 1047 /* RX Flow control is enabled, and TX Flow control is 1048 * disabled, by a software over-ride. 1049 * 1050 * Since there really isn't a way to advertise that we are 1051 * capable of RX Pause ONLY, we will advertise that we 1052 * support both symmetric and asymmetric RX PAUSE. Later 1053 * (in e1000_config_fc_after_link_up) we will disable the 1054 * hw's ability to send PAUSE frames. 1055 */ 1056 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1057 break; 1058 case e1000_fc_tx_pause: 1059 /* TX Flow control is enabled, and RX Flow control is 1060 * disabled, by a software over-ride. 1061 */ 1062 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1063 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1064 break; 1065 case e1000_fc_full: 1066 /* Flow control (both RX and TX) is enabled by a software 1067 * over-ride. 1068 */ 1069 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1070 break; 1071 default: 1072 hw_dbg("Flow control param set incorrectly\n"); 1073 ret_val = -E1000_ERR_CONFIG; 1074 goto out; 1075 } 1076 1077 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1078 if (ret_val) 1079 goto out; 1080 1081 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1082 1083 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1084 ret_val = phy->ops.write_reg(hw, 1085 PHY_1000T_CTRL, 1086 mii_1000t_ctrl_reg); 1087 if (ret_val) 1088 goto out; 1089 } 1090 1091out: 1092 return ret_val; 1093} 1094 1095/** 1096 * igb_setup_copper_link - Configure copper link settings 1097 * @hw: pointer to the HW structure 1098 * 1099 * Calls the appropriate function to configure the link for auto-neg or forced 1100 * speed and duplex. Then we check for link, once link is established calls 1101 * to configure collision distance and flow control are called. If link is 1102 * not established, we return -E1000_ERR_PHY (-2). 1103 **/ 1104s32 igb_setup_copper_link(struct e1000_hw *hw) 1105{ 1106 s32 ret_val; 1107 bool link; 1108 1109 if (hw->mac.autoneg) { 1110 /* Setup autoneg and flow control advertisement and perform 1111 * autonegotiation. 1112 */ 1113 ret_val = igb_copper_link_autoneg(hw); 1114 if (ret_val) 1115 goto out; 1116 } else { 1117 /* PHY will be set to 10H, 10F, 100H or 100F 1118 * depending on user settings. 1119 */ 1120 hw_dbg("Forcing Speed and Duplex\n"); 1121 ret_val = hw->phy.ops.force_speed_duplex(hw); 1122 if (ret_val) { 1123 hw_dbg("Error Forcing Speed and Duplex\n"); 1124 goto out; 1125 } 1126 } 1127 1128 /* Check link status. Wait up to 100 microseconds for link to become 1129 * valid. 1130 */ 1131 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 1132 if (ret_val) 1133 goto out; 1134 1135 if (link) { 1136 hw_dbg("Valid link established!!!\n"); 1137 igb_config_collision_dist(hw); 1138 ret_val = igb_config_fc_after_link_up(hw); 1139 } else { 1140 hw_dbg("Unable to establish link!!!\n"); 1141 } 1142 1143out: 1144 return ret_val; 1145} 1146 1147/** 1148 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1149 * @hw: pointer to the HW structure 1150 * 1151 * Calls the PHY setup function to force speed and duplex. Clears the 1152 * auto-crossover to force MDI manually. Waits for link and returns 1153 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1154 **/ 1155s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1156{ 1157 struct e1000_phy_info *phy = &hw->phy; 1158 s32 ret_val; 1159 u16 phy_data; 1160 bool link; 1161 1162 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1163 if (ret_val) 1164 goto out; 1165 1166 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1167 1168 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1169 if (ret_val) 1170 goto out; 1171 1172 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1173 * forced whenever speed and duplex are forced. 1174 */ 1175 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1176 if (ret_val) 1177 goto out; 1178 1179 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1180 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1181 1182 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1183 if (ret_val) 1184 goto out; 1185 1186 hw_dbg("IGP PSCR: %X\n", phy_data); 1187 1188 udelay(1); 1189 1190 if (phy->autoneg_wait_to_complete) { 1191 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1192 1193 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1194 if (ret_val) 1195 goto out; 1196 1197 if (!link) 1198 hw_dbg("Link taking longer than expected.\n"); 1199 1200 /* Try once more */ 1201 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1202 if (ret_val) 1203 goto out; 1204 } 1205 1206out: 1207 return ret_val; 1208} 1209 1210/** 1211 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1212 * @hw: pointer to the HW structure 1213 * 1214 * Calls the PHY setup function to force speed and duplex. Clears the 1215 * auto-crossover to force MDI manually. Resets the PHY to commit the 1216 * changes. If time expires while waiting for link up, we reset the DSP. 1217 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1218 * successful completion, else return corresponding error code. 1219 **/ 1220s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1221{ 1222 struct e1000_phy_info *phy = &hw->phy; 1223 s32 ret_val; 1224 u16 phy_data; 1225 bool link; 1226 1227 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1228 if (phy->type != e1000_phy_i210) { 1229 /* Clear Auto-Crossover to force MDI manually. M88E1000 1230 * requires MDI forced whenever speed and duplex are forced. 1231 */ 1232 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1233 &phy_data); 1234 if (ret_val) 1235 goto out; 1236 1237 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1238 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1239 phy_data); 1240 if (ret_val) 1241 goto out; 1242 1243 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1244 } 1245 1246 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1247 if (ret_val) 1248 goto out; 1249 1250 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1251 1252 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1253 if (ret_val) 1254 goto out; 1255 1256 /* Reset the phy to commit changes. */ 1257 ret_val = igb_phy_sw_reset(hw); 1258 if (ret_val) 1259 goto out; 1260 1261 if (phy->autoneg_wait_to_complete) { 1262 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1263 1264 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1265 if (ret_val) 1266 goto out; 1267 1268 if (!link) { 1269 bool reset_dsp = true; 1270 1271 switch (hw->phy.id) { 1272 case I347AT4_E_PHY_ID: 1273 case M88E1112_E_PHY_ID: 1274 case I210_I_PHY_ID: 1275 reset_dsp = false; 1276 break; 1277 default: 1278 if (hw->phy.type != e1000_phy_m88) 1279 reset_dsp = false; 1280 break; 1281 } 1282 if (!reset_dsp) 1283 hw_dbg("Link taking longer than expected.\n"); 1284 else { 1285 /* We didn't get link. 1286 * Reset the DSP and cross our fingers. 1287 */ 1288 ret_val = phy->ops.write_reg(hw, 1289 M88E1000_PHY_PAGE_SELECT, 1290 0x001d); 1291 if (ret_val) 1292 goto out; 1293 ret_val = igb_phy_reset_dsp(hw); 1294 if (ret_val) 1295 goto out; 1296 } 1297 } 1298 1299 /* Try once more */ 1300 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1301 100000, &link); 1302 if (ret_val) 1303 goto out; 1304 } 1305 1306 if (hw->phy.type != e1000_phy_m88 || 1307 hw->phy.id == I347AT4_E_PHY_ID || 1308 hw->phy.id == M88E1112_E_PHY_ID || 1309 hw->phy.id == I210_I_PHY_ID) 1310 goto out; 1311 1312 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1313 if (ret_val) 1314 goto out; 1315 1316 /* Resetting the phy means we need to re-force TX_CLK in the 1317 * Extended PHY Specific Control Register to 25MHz clock from 1318 * the reset value of 2.5MHz. 1319 */ 1320 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1321 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1322 if (ret_val) 1323 goto out; 1324 1325 /* In addition, we must re-enable CRS on Tx for both half and full 1326 * duplex. 1327 */ 1328 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1329 if (ret_val) 1330 goto out; 1331 1332 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1333 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1334 1335out: 1336 return ret_val; 1337} 1338 1339/** 1340 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1341 * @hw: pointer to the HW structure 1342 * @phy_ctrl: pointer to current value of PHY_CONTROL 1343 * 1344 * Forces speed and duplex on the PHY by doing the following: disable flow 1345 * control, force speed/duplex on the MAC, disable auto speed detection, 1346 * disable auto-negotiation, configure duplex, configure speed, configure 1347 * the collision distance, write configuration to CTRL register. The 1348 * caller must write to the PHY_CONTROL register for these settings to 1349 * take affect. 1350 **/ 1351static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1352 u16 *phy_ctrl) 1353{ 1354 struct e1000_mac_info *mac = &hw->mac; 1355 u32 ctrl; 1356 1357 /* Turn off flow control when forcing speed/duplex */ 1358 hw->fc.current_mode = e1000_fc_none; 1359 1360 /* Force speed/duplex on the mac */ 1361 ctrl = rd32(E1000_CTRL); 1362 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1363 ctrl &= ~E1000_CTRL_SPD_SEL; 1364 1365 /* Disable Auto Speed Detection */ 1366 ctrl &= ~E1000_CTRL_ASDE; 1367 1368 /* Disable autoneg on the phy */ 1369 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1370 1371 /* Forcing Full or Half Duplex? */ 1372 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1373 ctrl &= ~E1000_CTRL_FD; 1374 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1375 hw_dbg("Half Duplex\n"); 1376 } else { 1377 ctrl |= E1000_CTRL_FD; 1378 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1379 hw_dbg("Full Duplex\n"); 1380 } 1381 1382 /* Forcing 10mb or 100mb? */ 1383 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1384 ctrl |= E1000_CTRL_SPD_100; 1385 *phy_ctrl |= MII_CR_SPEED_100; 1386 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1387 hw_dbg("Forcing 100mb\n"); 1388 } else { 1389 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1390 *phy_ctrl |= MII_CR_SPEED_10; 1391 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1392 hw_dbg("Forcing 10mb\n"); 1393 } 1394 1395 igb_config_collision_dist(hw); 1396 1397 wr32(E1000_CTRL, ctrl); 1398} 1399 1400/** 1401 * igb_set_d3_lplu_state - Sets low power link up state for D3 1402 * @hw: pointer to the HW structure 1403 * @active: boolean used to enable/disable lplu 1404 * 1405 * Success returns 0, Failure returns 1 1406 * 1407 * The low power link up (lplu) state is set to the power management level D3 1408 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1409 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1410 * is used during Dx states where the power conservation is most important. 1411 * During driver activity, SmartSpeed should be enabled so performance is 1412 * maintained. 1413 **/ 1414s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1415{ 1416 struct e1000_phy_info *phy = &hw->phy; 1417 s32 ret_val = 0; 1418 u16 data; 1419 1420 if (!(hw->phy.ops.read_reg)) 1421 goto out; 1422 1423 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1424 if (ret_val) 1425 goto out; 1426 1427 if (!active) { 1428 data &= ~IGP02E1000_PM_D3_LPLU; 1429 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1430 data); 1431 if (ret_val) 1432 goto out; 1433 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1434 * during Dx states where the power conservation is most 1435 * important. During driver activity we should enable 1436 * SmartSpeed, so performance is maintained. 1437 */ 1438 if (phy->smart_speed == e1000_smart_speed_on) { 1439 ret_val = phy->ops.read_reg(hw, 1440 IGP01E1000_PHY_PORT_CONFIG, 1441 &data); 1442 if (ret_val) 1443 goto out; 1444 1445 data |= IGP01E1000_PSCFR_SMART_SPEED; 1446 ret_val = phy->ops.write_reg(hw, 1447 IGP01E1000_PHY_PORT_CONFIG, 1448 data); 1449 if (ret_val) 1450 goto out; 1451 } else if (phy->smart_speed == e1000_smart_speed_off) { 1452 ret_val = phy->ops.read_reg(hw, 1453 IGP01E1000_PHY_PORT_CONFIG, 1454 &data); 1455 if (ret_val) 1456 goto out; 1457 1458 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1459 ret_val = phy->ops.write_reg(hw, 1460 IGP01E1000_PHY_PORT_CONFIG, 1461 data); 1462 if (ret_val) 1463 goto out; 1464 } 1465 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1466 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1467 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1468 data |= IGP02E1000_PM_D3_LPLU; 1469 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1470 data); 1471 if (ret_val) 1472 goto out; 1473 1474 /* When LPLU is enabled, we should disable SmartSpeed */ 1475 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1476 &data); 1477 if (ret_val) 1478 goto out; 1479 1480 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1481 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1482 data); 1483 } 1484 1485out: 1486 return ret_val; 1487} 1488 1489/** 1490 * igb_check_downshift - Checks whether a downshift in speed occurred 1491 * @hw: pointer to the HW structure 1492 * 1493 * Success returns 0, Failure returns 1 1494 * 1495 * A downshift is detected by querying the PHY link health. 1496 **/ 1497s32 igb_check_downshift(struct e1000_hw *hw) 1498{ 1499 struct e1000_phy_info *phy = &hw->phy; 1500 s32 ret_val; 1501 u16 phy_data, offset, mask; 1502 1503 switch (phy->type) { 1504 case e1000_phy_i210: 1505 case e1000_phy_m88: 1506 case e1000_phy_gg82563: 1507 offset = M88E1000_PHY_SPEC_STATUS; 1508 mask = M88E1000_PSSR_DOWNSHIFT; 1509 break; 1510 case e1000_phy_igp_2: 1511 case e1000_phy_igp: 1512 case e1000_phy_igp_3: 1513 offset = IGP01E1000_PHY_LINK_HEALTH; 1514 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1515 break; 1516 default: 1517 /* speed downshift not supported */ 1518 phy->speed_downgraded = false; 1519 ret_val = 0; 1520 goto out; 1521 } 1522 1523 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1524 1525 if (!ret_val) 1526 phy->speed_downgraded = (phy_data & mask) ? true : false; 1527 1528out: 1529 return ret_val; 1530} 1531 1532/** 1533 * igb_check_polarity_m88 - Checks the polarity. 1534 * @hw: pointer to the HW structure 1535 * 1536 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1537 * 1538 * Polarity is determined based on the PHY specific status register. 1539 **/ 1540s32 igb_check_polarity_m88(struct e1000_hw *hw) 1541{ 1542 struct e1000_phy_info *phy = &hw->phy; 1543 s32 ret_val; 1544 u16 data; 1545 1546 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1547 1548 if (!ret_val) 1549 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1550 ? e1000_rev_polarity_reversed 1551 : e1000_rev_polarity_normal; 1552 1553 return ret_val; 1554} 1555 1556/** 1557 * igb_check_polarity_igp - Checks the polarity. 1558 * @hw: pointer to the HW structure 1559 * 1560 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1561 * 1562 * Polarity is determined based on the PHY port status register, and the 1563 * current speed (since there is no polarity at 100Mbps). 1564 **/ 1565static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1566{ 1567 struct e1000_phy_info *phy = &hw->phy; 1568 s32 ret_val; 1569 u16 data, offset, mask; 1570 1571 /* Polarity is determined based on the speed of 1572 * our connection. 1573 */ 1574 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1575 if (ret_val) 1576 goto out; 1577 1578 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1579 IGP01E1000_PSSR_SPEED_1000MBPS) { 1580 offset = IGP01E1000_PHY_PCS_INIT_REG; 1581 mask = IGP01E1000_PHY_POLARITY_MASK; 1582 } else { 1583 /* This really only applies to 10Mbps since 1584 * there is no polarity for 100Mbps (always 0). 1585 */ 1586 offset = IGP01E1000_PHY_PORT_STATUS; 1587 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1588 } 1589 1590 ret_val = phy->ops.read_reg(hw, offset, &data); 1591 1592 if (!ret_val) 1593 phy->cable_polarity = (data & mask) 1594 ? e1000_rev_polarity_reversed 1595 : e1000_rev_polarity_normal; 1596 1597out: 1598 return ret_val; 1599} 1600 1601/** 1602 * igb_wait_autoneg - Wait for auto-neg completion 1603 * @hw: pointer to the HW structure 1604 * 1605 * Waits for auto-negotiation to complete or for the auto-negotiation time 1606 * limit to expire, which ever happens first. 1607 **/ 1608static s32 igb_wait_autoneg(struct e1000_hw *hw) 1609{ 1610 s32 ret_val = 0; 1611 u16 i, phy_status; 1612 1613 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1614 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1615 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1616 if (ret_val) 1617 break; 1618 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1619 if (ret_val) 1620 break; 1621 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1622 break; 1623 msleep(100); 1624 } 1625 1626 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1627 * has completed. 1628 */ 1629 return ret_val; 1630} 1631 1632/** 1633 * igb_phy_has_link - Polls PHY for link 1634 * @hw: pointer to the HW structure 1635 * @iterations: number of times to poll for link 1636 * @usec_interval: delay between polling attempts 1637 * @success: pointer to whether polling was successful or not 1638 * 1639 * Polls the PHY status register for link, 'iterations' number of times. 1640 **/ 1641s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1642 u32 usec_interval, bool *success) 1643{ 1644 s32 ret_val = 0; 1645 u16 i, phy_status; 1646 1647 for (i = 0; i < iterations; i++) { 1648 /* Some PHYs require the PHY_STATUS register to be read 1649 * twice due to the link bit being sticky. No harm doing 1650 * it across the board. 1651 */ 1652 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1653 if (ret_val && usec_interval > 0) { 1654 /* If the first read fails, another entity may have 1655 * ownership of the resources, wait and try again to 1656 * see if they have relinquished the resources yet. 1657 */ 1658 if (usec_interval >= 1000) 1659 mdelay(usec_interval/1000); 1660 else 1661 udelay(usec_interval); 1662 } 1663 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1664 if (ret_val) 1665 break; 1666 if (phy_status & MII_SR_LINK_STATUS) 1667 break; 1668 if (usec_interval >= 1000) 1669 mdelay(usec_interval/1000); 1670 else 1671 udelay(usec_interval); 1672 } 1673 1674 *success = (i < iterations) ? true : false; 1675 1676 return ret_val; 1677} 1678 1679/** 1680 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1681 * @hw: pointer to the HW structure 1682 * 1683 * Reads the PHY specific status register to retrieve the cable length 1684 * information. The cable length is determined by averaging the minimum and 1685 * maximum values to get the "average" cable length. The m88 PHY has four 1686 * possible cable length values, which are: 1687 * Register Value Cable Length 1688 * 0 < 50 meters 1689 * 1 50 - 80 meters 1690 * 2 80 - 110 meters 1691 * 3 110 - 140 meters 1692 * 4 > 140 meters 1693 **/ 1694s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1695{ 1696 struct e1000_phy_info *phy = &hw->phy; 1697 s32 ret_val; 1698 u16 phy_data, index; 1699 1700 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1701 if (ret_val) 1702 goto out; 1703 1704 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1705 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1706 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1707 ret_val = -E1000_ERR_PHY; 1708 goto out; 1709 } 1710 1711 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1712 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1713 1714 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1715 1716out: 1717 return ret_val; 1718} 1719 1720s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1721{ 1722 struct e1000_phy_info *phy = &hw->phy; 1723 s32 ret_val; 1724 u16 phy_data, phy_data2, index, default_page, is_cm; 1725 1726 switch (hw->phy.id) { 1727 case I210_I_PHY_ID: 1728 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1729 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1730 (I347AT4_PCDL + phy->addr), 1731 &phy_data); 1732 if (ret_val) 1733 return ret_val; 1734 1735 /* Check if the unit of cable length is meters or cm */ 1736 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1737 I347AT4_PCDC, &phy_data2); 1738 if (ret_val) 1739 return ret_val; 1740 1741 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1742 1743 /* Populate the phy structure with cable length in meters */ 1744 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1745 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1746 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1747 break; 1748 case M88E1543_E_PHY_ID: 1749 case I347AT4_E_PHY_ID: 1750 /* Remember the original page select and set it to 7 */ 1751 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1752 &default_page); 1753 if (ret_val) 1754 goto out; 1755 1756 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1757 if (ret_val) 1758 goto out; 1759 1760 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1761 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1762 &phy_data); 1763 if (ret_val) 1764 goto out; 1765 1766 /* Check if the unit of cable length is meters or cm */ 1767 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1768 if (ret_val) 1769 goto out; 1770 1771 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1772 1773 /* Populate the phy structure with cable length in meters */ 1774 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1775 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1776 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1777 1778 /* Reset the page selec to its original value */ 1779 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1780 default_page); 1781 if (ret_val) 1782 goto out; 1783 break; 1784 case M88E1112_E_PHY_ID: 1785 /* Remember the original page select and set it to 5 */ 1786 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1787 &default_page); 1788 if (ret_val) 1789 goto out; 1790 1791 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1792 if (ret_val) 1793 goto out; 1794 1795 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1796 &phy_data); 1797 if (ret_val) 1798 goto out; 1799 1800 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1801 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1802 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1803 ret_val = -E1000_ERR_PHY; 1804 goto out; 1805 } 1806 1807 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1808 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1809 1810 phy->cable_length = (phy->min_cable_length + 1811 phy->max_cable_length) / 2; 1812 1813 /* Reset the page select to its original value */ 1814 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1815 default_page); 1816 if (ret_val) 1817 goto out; 1818 1819 break; 1820 default: 1821 ret_val = -E1000_ERR_PHY; 1822 goto out; 1823 } 1824 1825out: 1826 return ret_val; 1827} 1828 1829/** 1830 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1831 * @hw: pointer to the HW structure 1832 * 1833 * The automatic gain control (agc) normalizes the amplitude of the 1834 * received signal, adjusting for the attenuation produced by the 1835 * cable. By reading the AGC registers, which represent the 1836 * combination of coarse and fine gain value, the value can be put 1837 * into a lookup table to obtain the approximate cable length 1838 * for each channel. 1839 **/ 1840s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1841{ 1842 struct e1000_phy_info *phy = &hw->phy; 1843 s32 ret_val = 0; 1844 u16 phy_data, i, agc_value = 0; 1845 u16 cur_agc_index, max_agc_index = 0; 1846 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1847 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1848 IGP02E1000_PHY_AGC_A, 1849 IGP02E1000_PHY_AGC_B, 1850 IGP02E1000_PHY_AGC_C, 1851 IGP02E1000_PHY_AGC_D 1852 }; 1853 1854 /* Read the AGC registers for all channels */ 1855 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1856 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1857 if (ret_val) 1858 goto out; 1859 1860 /* Getting bits 15:9, which represent the combination of 1861 * coarse and fine gain values. The result is a number 1862 * that can be put into the lookup table to obtain the 1863 * approximate cable length. 1864 */ 1865 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1866 IGP02E1000_AGC_LENGTH_MASK; 1867 1868 /* Array index bound check. */ 1869 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1870 (cur_agc_index == 0)) { 1871 ret_val = -E1000_ERR_PHY; 1872 goto out; 1873 } 1874 1875 /* Remove min & max AGC values from calculation. */ 1876 if (e1000_igp_2_cable_length_table[min_agc_index] > 1877 e1000_igp_2_cable_length_table[cur_agc_index]) 1878 min_agc_index = cur_agc_index; 1879 if (e1000_igp_2_cable_length_table[max_agc_index] < 1880 e1000_igp_2_cable_length_table[cur_agc_index]) 1881 max_agc_index = cur_agc_index; 1882 1883 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1884 } 1885 1886 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1887 e1000_igp_2_cable_length_table[max_agc_index]); 1888 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1889 1890 /* Calculate cable length with the error range of +/- 10 meters. */ 1891 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1892 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1893 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1894 1895 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1896 1897out: 1898 return ret_val; 1899} 1900 1901/** 1902 * igb_get_phy_info_m88 - Retrieve PHY information 1903 * @hw: pointer to the HW structure 1904 * 1905 * Valid for only copper links. Read the PHY status register (sticky read) 1906 * to verify that link is up. Read the PHY special control register to 1907 * determine the polarity and 10base-T extended distance. Read the PHY 1908 * special status register to determine MDI/MDIx and current speed. If 1909 * speed is 1000, then determine cable length, local and remote receiver. 1910 **/ 1911s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1912{ 1913 struct e1000_phy_info *phy = &hw->phy; 1914 s32 ret_val; 1915 u16 phy_data; 1916 bool link; 1917 1918 if (phy->media_type != e1000_media_type_copper) { 1919 hw_dbg("Phy info is only valid for copper media\n"); 1920 ret_val = -E1000_ERR_CONFIG; 1921 goto out; 1922 } 1923 1924 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1925 if (ret_val) 1926 goto out; 1927 1928 if (!link) { 1929 hw_dbg("Phy info is only valid if link is up\n"); 1930 ret_val = -E1000_ERR_CONFIG; 1931 goto out; 1932 } 1933 1934 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1935 if (ret_val) 1936 goto out; 1937 1938 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1939 ? true : false; 1940 1941 ret_val = igb_check_polarity_m88(hw); 1942 if (ret_val) 1943 goto out; 1944 1945 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1946 if (ret_val) 1947 goto out; 1948 1949 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1950 1951 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1952 ret_val = phy->ops.get_cable_length(hw); 1953 if (ret_val) 1954 goto out; 1955 1956 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1957 if (ret_val) 1958 goto out; 1959 1960 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1961 ? e1000_1000t_rx_status_ok 1962 : e1000_1000t_rx_status_not_ok; 1963 1964 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1965 ? e1000_1000t_rx_status_ok 1966 : e1000_1000t_rx_status_not_ok; 1967 } else { 1968 /* Set values to "undefined" */ 1969 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1970 phy->local_rx = e1000_1000t_rx_status_undefined; 1971 phy->remote_rx = e1000_1000t_rx_status_undefined; 1972 } 1973 1974out: 1975 return ret_val; 1976} 1977 1978/** 1979 * igb_get_phy_info_igp - Retrieve igp PHY information 1980 * @hw: pointer to the HW structure 1981 * 1982 * Read PHY status to determine if link is up. If link is up, then 1983 * set/determine 10base-T extended distance and polarity correction. Read 1984 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1985 * determine on the cable length, local and remote receiver. 1986 **/ 1987s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1988{ 1989 struct e1000_phy_info *phy = &hw->phy; 1990 s32 ret_val; 1991 u16 data; 1992 bool link; 1993 1994 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1995 if (ret_val) 1996 goto out; 1997 1998 if (!link) { 1999 hw_dbg("Phy info is only valid if link is up\n"); 2000 ret_val = -E1000_ERR_CONFIG; 2001 goto out; 2002 } 2003 2004 phy->polarity_correction = true; 2005 2006 ret_val = igb_check_polarity_igp(hw); 2007 if (ret_val) 2008 goto out; 2009 2010 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2011 if (ret_val) 2012 goto out; 2013 2014 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2015 2016 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2017 IGP01E1000_PSSR_SPEED_1000MBPS) { 2018 ret_val = phy->ops.get_cable_length(hw); 2019 if (ret_val) 2020 goto out; 2021 2022 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2023 if (ret_val) 2024 goto out; 2025 2026 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2027 ? e1000_1000t_rx_status_ok 2028 : e1000_1000t_rx_status_not_ok; 2029 2030 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2031 ? e1000_1000t_rx_status_ok 2032 : e1000_1000t_rx_status_not_ok; 2033 } else { 2034 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2035 phy->local_rx = e1000_1000t_rx_status_undefined; 2036 phy->remote_rx = e1000_1000t_rx_status_undefined; 2037 } 2038 2039out: 2040 return ret_val; 2041} 2042 2043/** 2044 * igb_phy_sw_reset - PHY software reset 2045 * @hw: pointer to the HW structure 2046 * 2047 * Does a software reset of the PHY by reading the PHY control register and 2048 * setting/write the control register reset bit to the PHY. 2049 **/ 2050s32 igb_phy_sw_reset(struct e1000_hw *hw) 2051{ 2052 s32 ret_val = 0; 2053 u16 phy_ctrl; 2054 2055 if (!(hw->phy.ops.read_reg)) 2056 goto out; 2057 2058 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2059 if (ret_val) 2060 goto out; 2061 2062 phy_ctrl |= MII_CR_RESET; 2063 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2064 if (ret_val) 2065 goto out; 2066 2067 udelay(1); 2068 2069out: 2070 return ret_val; 2071} 2072 2073/** 2074 * igb_phy_hw_reset - PHY hardware reset 2075 * @hw: pointer to the HW structure 2076 * 2077 * Verify the reset block is not blocking us from resetting. Acquire 2078 * semaphore (if necessary) and read/set/write the device control reset 2079 * bit in the PHY. Wait the appropriate delay time for the device to 2080 * reset and release the semaphore (if necessary). 2081 **/ 2082s32 igb_phy_hw_reset(struct e1000_hw *hw) 2083{ 2084 struct e1000_phy_info *phy = &hw->phy; 2085 s32 ret_val; 2086 u32 ctrl; 2087 2088 ret_val = igb_check_reset_block(hw); 2089 if (ret_val) { 2090 ret_val = 0; 2091 goto out; 2092 } 2093 2094 ret_val = phy->ops.acquire(hw); 2095 if (ret_val) 2096 goto out; 2097 2098 ctrl = rd32(E1000_CTRL); 2099 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2100 wrfl(); 2101 2102 udelay(phy->reset_delay_us); 2103 2104 wr32(E1000_CTRL, ctrl); 2105 wrfl(); 2106 2107 udelay(150); 2108 2109 phy->ops.release(hw); 2110 2111 ret_val = phy->ops.get_cfg_done(hw); 2112 2113out: 2114 return ret_val; 2115} 2116 2117/** 2118 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2119 * @hw: pointer to the HW structure 2120 * 2121 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2122 **/ 2123s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2124{ 2125 hw_dbg("Running IGP 3 PHY init script\n"); 2126 2127 /* PHY init IGP 3 */ 2128 /* Enable rise/fall, 10-mode work in class-A */ 2129 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2130 /* Remove all caps from Replica path filter */ 2131 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2132 /* Bias trimming for ADC, AFE and Driver (Default) */ 2133 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2134 /* Increase Hybrid poly bias */ 2135 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2136 /* Add 4% to TX amplitude in Giga mode */ 2137 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2138 /* Disable trimming (TTT) */ 2139 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2140 /* Poly DC correction to 94.6% + 2% for all channels */ 2141 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2142 /* ABS DC correction to 95.9% */ 2143 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2144 /* BG temp curve trim */ 2145 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2146 /* Increasing ADC OPAMP stage 1 currents to max */ 2147 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2148 /* Force 1000 ( required for enabling PHY regs configuration) */ 2149 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2150 /* Set upd_freq to 6 */ 2151 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2152 /* Disable NPDFE */ 2153 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2154 /* Disable adaptive fixed FFE (Default) */ 2155 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2156 /* Enable FFE hysteresis */ 2157 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2158 /* Fixed FFE for short cable lengths */ 2159 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2160 /* Fixed FFE for medium cable lengths */ 2161 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2162 /* Fixed FFE for long cable lengths */ 2163 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2164 /* Enable Adaptive Clip Threshold */ 2165 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2166 /* AHT reset limit to 1 */ 2167 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2168 /* Set AHT master delay to 127 msec */ 2169 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2170 /* Set scan bits for AHT */ 2171 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2172 /* Set AHT Preset bits */ 2173 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2174 /* Change integ_factor of channel A to 3 */ 2175 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2176 /* Change prop_factor of channels BCD to 8 */ 2177 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2178 /* Change cg_icount + enable integbp for channels BCD */ 2179 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2180 /* Change cg_icount + enable integbp + change prop_factor_master 2181 * to 8 for channel A 2182 */ 2183 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2184 /* Disable AHT in Slave mode on channel A */ 2185 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2186 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2187 * Enable SPD+B2B 2188 */ 2189 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2190 /* Enable restart AN on an1000_dis change */ 2191 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2192 /* Enable wh_fifo read clock in 10/100 modes */ 2193 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2194 /* Restart AN, Speed selection is 1000 */ 2195 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2196 2197 return 0; 2198} 2199 2200/** 2201 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2202 * @hw: pointer to the HW structure 2203 * 2204 * In the case of a PHY power down to save power, or to turn off link during a 2205 * driver unload, restore the link to previous settings. 2206 **/ 2207void igb_power_up_phy_copper(struct e1000_hw *hw) 2208{ 2209 u16 mii_reg = 0; 2210 u16 power_reg = 0; 2211 2212 /* The PHY will retain its settings across a power down/up cycle */ 2213 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2214 mii_reg &= ~MII_CR_POWER_DOWN; 2215 if (hw->phy.type == e1000_phy_i210) { 2216 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2217 power_reg &= ~GS40G_CS_POWER_DOWN; 2218 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2219 } 2220 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2221} 2222 2223/** 2224 * igb_power_down_phy_copper - Power down copper PHY 2225 * @hw: pointer to the HW structure 2226 * 2227 * Power down PHY to save power when interface is down and wake on lan 2228 * is not enabled. 2229 **/ 2230void igb_power_down_phy_copper(struct e1000_hw *hw) 2231{ 2232 u16 mii_reg = 0; 2233 u16 power_reg = 0; 2234 2235 /* The PHY will retain its settings across a power down/up cycle */ 2236 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2237 mii_reg |= MII_CR_POWER_DOWN; 2238 2239 /* i210 Phy requires an additional bit for power up/down */ 2240 if (hw->phy.type == e1000_phy_i210) { 2241 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2242 power_reg |= GS40G_CS_POWER_DOWN; 2243 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2244 } 2245 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2246 msleep(1); 2247} 2248 2249/** 2250 * igb_check_polarity_82580 - Checks the polarity. 2251 * @hw: pointer to the HW structure 2252 * 2253 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2254 * 2255 * Polarity is determined based on the PHY specific status register. 2256 **/ 2257static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2258{ 2259 struct e1000_phy_info *phy = &hw->phy; 2260 s32 ret_val; 2261 u16 data; 2262 2263 2264 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2265 2266 if (!ret_val) 2267 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2268 ? e1000_rev_polarity_reversed 2269 : e1000_rev_polarity_normal; 2270 2271 return ret_val; 2272} 2273 2274/** 2275 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2276 * @hw: pointer to the HW structure 2277 * 2278 * Calls the PHY setup function to force speed and duplex. Clears the 2279 * auto-crossover to force MDI manually. Waits for link and returns 2280 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2281 **/ 2282s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2283{ 2284 struct e1000_phy_info *phy = &hw->phy; 2285 s32 ret_val; 2286 u16 phy_data; 2287 bool link; 2288 2289 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2290 if (ret_val) 2291 goto out; 2292 2293 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2294 2295 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2296 if (ret_val) 2297 goto out; 2298 2299 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2300 * forced whenever speed and duplex are forced. 2301 */ 2302 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2303 if (ret_val) 2304 goto out; 2305 2306 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2307 2308 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2309 if (ret_val) 2310 goto out; 2311 2312 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2313 2314 udelay(1); 2315 2316 if (phy->autoneg_wait_to_complete) { 2317 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2318 2319 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2320 if (ret_val) 2321 goto out; 2322 2323 if (!link) 2324 hw_dbg("Link taking longer than expected.\n"); 2325 2326 /* Try once more */ 2327 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2328 if (ret_val) 2329 goto out; 2330 } 2331 2332out: 2333 return ret_val; 2334} 2335 2336/** 2337 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2338 * @hw: pointer to the HW structure 2339 * 2340 * Read PHY status to determine if link is up. If link is up, then 2341 * set/determine 10base-T extended distance and polarity correction. Read 2342 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2343 * determine on the cable length, local and remote receiver. 2344 **/ 2345s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2346{ 2347 struct e1000_phy_info *phy = &hw->phy; 2348 s32 ret_val; 2349 u16 data; 2350 bool link; 2351 2352 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2353 if (ret_val) 2354 goto out; 2355 2356 if (!link) { 2357 hw_dbg("Phy info is only valid if link is up\n"); 2358 ret_val = -E1000_ERR_CONFIG; 2359 goto out; 2360 } 2361 2362 phy->polarity_correction = true; 2363 2364 ret_val = igb_check_polarity_82580(hw); 2365 if (ret_val) 2366 goto out; 2367 2368 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2369 if (ret_val) 2370 goto out; 2371 2372 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2373 2374 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2375 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2376 ret_val = hw->phy.ops.get_cable_length(hw); 2377 if (ret_val) 2378 goto out; 2379 2380 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2381 if (ret_val) 2382 goto out; 2383 2384 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2385 ? e1000_1000t_rx_status_ok 2386 : e1000_1000t_rx_status_not_ok; 2387 2388 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2389 ? e1000_1000t_rx_status_ok 2390 : e1000_1000t_rx_status_not_ok; 2391 } else { 2392 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2393 phy->local_rx = e1000_1000t_rx_status_undefined; 2394 phy->remote_rx = e1000_1000t_rx_status_undefined; 2395 } 2396 2397out: 2398 return ret_val; 2399} 2400 2401/** 2402 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2403 * @hw: pointer to the HW structure 2404 * 2405 * Reads the diagnostic status register and verifies result is valid before 2406 * placing it in the phy_cable_length field. 2407 **/ 2408s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2409{ 2410 struct e1000_phy_info *phy = &hw->phy; 2411 s32 ret_val; 2412 u16 phy_data, length; 2413 2414 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2415 if (ret_val) 2416 goto out; 2417 2418 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2419 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2420 2421 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2422 ret_val = -E1000_ERR_PHY; 2423 2424 phy->cable_length = length; 2425 2426out: 2427 return ret_val; 2428} 2429 2430/** 2431 * igb_write_phy_reg_gs40g - Write GS40G PHY register 2432 * @hw: pointer to the HW structure 2433 * @offset: lower half is register offset to write to 2434 * upper half is page to use. 2435 * @data: data to write at register offset 2436 * 2437 * Acquires semaphore, if necessary, then writes the data to PHY register 2438 * at the offset. Release any acquired semaphores before exiting. 2439 **/ 2440s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 2441{ 2442 s32 ret_val; 2443 u16 page = offset >> GS40G_PAGE_SHIFT; 2444 2445 offset = offset & GS40G_OFFSET_MASK; 2446 ret_val = hw->phy.ops.acquire(hw); 2447 if (ret_val) 2448 return ret_val; 2449 2450 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2451 if (ret_val) 2452 goto release; 2453 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2454 2455release: 2456 hw->phy.ops.release(hw); 2457 return ret_val; 2458} 2459 2460/** 2461 * igb_read_phy_reg_gs40g - Read GS40G PHY register 2462 * @hw: pointer to the HW structure 2463 * @offset: lower half is register offset to read to 2464 * upper half is page to use. 2465 * @data: data to read at register offset 2466 * 2467 * Acquires semaphore, if necessary, then reads the data in the PHY register 2468 * at the offset. Release any acquired semaphores before exiting. 2469 **/ 2470s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 2471{ 2472 s32 ret_val; 2473 u16 page = offset >> GS40G_PAGE_SHIFT; 2474 2475 offset = offset & GS40G_OFFSET_MASK; 2476 ret_val = hw->phy.ops.acquire(hw); 2477 if (ret_val) 2478 return ret_val; 2479 2480 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2481 if (ret_val) 2482 goto release; 2483 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2484 2485release: 2486 hw->phy.ops.release(hw); 2487 return ret_val; 2488} 2489 2490/** 2491 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2492 * @hw: pointer to the HW structure 2493 * 2494 * Sets up Master/slave mode 2495 **/ 2496static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2497{ 2498 s32 ret_val; 2499 u16 phy_data; 2500 2501 /* Resolve Master/Slave mode */ 2502 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2503 if (ret_val) 2504 return ret_val; 2505 2506 /* load defaults for future use */ 2507 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2508 ((phy_data & CR_1000T_MS_VALUE) ? 2509 e1000_ms_force_master : 2510 e1000_ms_force_slave) : e1000_ms_auto; 2511 2512 switch (hw->phy.ms_type) { 2513 case e1000_ms_force_master: 2514 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2515 break; 2516 case e1000_ms_force_slave: 2517 phy_data |= CR_1000T_MS_ENABLE; 2518 phy_data &= ~(CR_1000T_MS_VALUE); 2519 break; 2520 case e1000_ms_auto: 2521 phy_data &= ~CR_1000T_MS_ENABLE; 2522 /* fall-through */ 2523 default: 2524 break; 2525 } 2526 2527 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2528} 2529