igb.h revision 4b9ea4626b52c113c367c4776c9bb11b7231393d
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28 29/* Linux PRO/1000 Ethernet Driver main header file */ 30 31#ifndef _IGB_H_ 32#define _IGB_H_ 33 34#include "e1000_mac.h" 35#include "e1000_82575.h" 36 37#include <linux/clocksource.h> 38#include <linux/net_tstamp.h> 39#include <linux/ptp_clock_kernel.h> 40#include <linux/bitops.h> 41#include <linux/if_vlan.h> 42#include <linux/i2c.h> 43#include <linux/i2c-algo-bit.h> 44 45struct igb_adapter; 46 47#define E1000_PCS_CFG_IGN_SD 1 48 49/* Interrupt defines */ 50#define IGB_START_ITR 648 /* ~6000 ints/sec */ 51#define IGB_4K_ITR 980 52#define IGB_20K_ITR 196 53#define IGB_70K_ITR 56 54 55/* TX/RX descriptor defines */ 56#define IGB_DEFAULT_TXD 256 57#define IGB_DEFAULT_TX_WORK 128 58#define IGB_MIN_TXD 80 59#define IGB_MAX_TXD 4096 60 61#define IGB_DEFAULT_RXD 256 62#define IGB_MIN_RXD 80 63#define IGB_MAX_RXD 4096 64 65#define IGB_DEFAULT_ITR 3 /* dynamic */ 66#define IGB_MAX_ITR_USECS 10000 67#define IGB_MIN_ITR_USECS 10 68#define NON_Q_VECTORS 1 69#define MAX_Q_VECTORS 8 70 71/* Transmit and receive queues */ 72#define IGB_MAX_RX_QUEUES 8 73#define IGB_MAX_RX_QUEUES_82575 4 74#define IGB_MAX_RX_QUEUES_I211 2 75#define IGB_MAX_TX_QUEUES 8 76#define IGB_MAX_VF_MC_ENTRIES 30 77#define IGB_MAX_VF_FUNCTIONS 8 78#define IGB_MAX_VFTA_ENTRIES 128 79#define IGB_82576_VF_DEV_ID 0x10CA 80#define IGB_I350_VF_DEV_ID 0x1520 81 82/* NVM version defines */ 83#define IGB_MAJOR_MASK 0xF000 84#define IGB_MINOR_MASK 0x0FF0 85#define IGB_BUILD_MASK 0x000F 86#define IGB_COMB_VER_MASK 0x00FF 87#define IGB_MAJOR_SHIFT 12 88#define IGB_MINOR_SHIFT 4 89#define IGB_COMB_VER_SHFT 8 90#define IGB_NVM_VER_INVALID 0xFFFF 91#define IGB_ETRACK_SHIFT 16 92#define NVM_ETRACK_WORD 0x0042 93#define NVM_COMB_VER_OFF 0x0083 94#define NVM_COMB_VER_PTR 0x003d 95 96struct vf_data_storage { 97 unsigned char vf_mac_addresses[ETH_ALEN]; 98 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 99 u16 num_vf_mc_hashes; 100 u16 vlans_enabled; 101 u32 flags; 102 unsigned long last_nack; 103 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 104 u16 pf_qos; 105 u16 tx_rate; 106}; 107 108#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 109#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 110#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 111#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 112 113/* RX descriptor control thresholds. 114 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 115 * descriptors available in its onboard memory. 116 * Setting this to 0 disables RX descriptor prefetch. 117 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 118 * available in host memory. 119 * If PTHRESH is 0, this should also be 0. 120 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 121 * descriptors until either it has this many to write back, or the 122 * ITR timer expires. 123 */ 124#define IGB_RX_PTHRESH 8 125#define IGB_RX_HTHRESH 8 126#define IGB_TX_PTHRESH 8 127#define IGB_TX_HTHRESH 1 128#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 129 adapter->msix_entries) ? 1 : 4) 130#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 131 adapter->msix_entries) ? 1 : 16) 132 133/* this is the size past which hardware will drop packets when setting LPE=0 */ 134#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 135 136/* Supported Rx Buffer Sizes */ 137#define IGB_RXBUFFER_256 256 138#define IGB_RXBUFFER_2048 2048 139#define IGB_RX_HDR_LEN IGB_RXBUFFER_256 140#define IGB_RX_BUFSZ IGB_RXBUFFER_2048 141 142/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 143#define IGB_TX_QUEUE_WAKE 16 144/* How many Rx Buffers do we bundle into one write to the hardware ? */ 145#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 146 147#define AUTO_ALL_MODES 0 148#define IGB_EEPROM_APME 0x0400 149 150#ifndef IGB_MASTER_SLAVE 151/* Switch to override PHY master/slave setting */ 152#define IGB_MASTER_SLAVE e1000_ms_hw_default 153#endif 154 155#define IGB_MNG_VLAN_NONE -1 156 157enum igb_tx_flags { 158 /* cmd_type flags */ 159 IGB_TX_FLAGS_VLAN = 0x01, 160 IGB_TX_FLAGS_TSO = 0x02, 161 IGB_TX_FLAGS_TSTAMP = 0x04, 162 163 /* olinfo flags */ 164 IGB_TX_FLAGS_IPV4 = 0x10, 165 IGB_TX_FLAGS_CSUM = 0x20, 166}; 167 168/* VLAN info */ 169#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 170#define IGB_TX_FLAGS_VLAN_SHIFT 16 171 172/* wrapper around a pointer to a socket buffer, 173 * so a DMA handle can be stored along with the buffer */ 174struct igb_tx_buffer { 175 union e1000_adv_tx_desc *next_to_watch; 176 unsigned long time_stamp; 177 struct sk_buff *skb; 178 unsigned int bytecount; 179 u16 gso_segs; 180 __be16 protocol; 181 DEFINE_DMA_UNMAP_ADDR(dma); 182 DEFINE_DMA_UNMAP_LEN(len); 183 u32 tx_flags; 184}; 185 186struct igb_rx_buffer { 187 dma_addr_t dma; 188 struct page *page; 189 unsigned int page_offset; 190}; 191 192struct igb_tx_queue_stats { 193 u64 packets; 194 u64 bytes; 195 u64 restart_queue; 196 u64 restart_queue2; 197}; 198 199struct igb_rx_queue_stats { 200 u64 packets; 201 u64 bytes; 202 u64 drops; 203 u64 csum_err; 204 u64 alloc_failed; 205}; 206 207struct igb_ring_container { 208 struct igb_ring *ring; /* pointer to linked list of rings */ 209 unsigned int total_bytes; /* total bytes processed this int */ 210 unsigned int total_packets; /* total packets processed this int */ 211 u16 work_limit; /* total work allowed per interrupt */ 212 u8 count; /* total number of rings in vector */ 213 u8 itr; /* current ITR setting for ring */ 214}; 215 216struct igb_ring { 217 struct igb_q_vector *q_vector; /* backlink to q_vector */ 218 struct net_device *netdev; /* back pointer to net_device */ 219 struct device *dev; /* device pointer for dma mapping */ 220 union { /* array of buffer info structs */ 221 struct igb_tx_buffer *tx_buffer_info; 222 struct igb_rx_buffer *rx_buffer_info; 223 }; 224 unsigned long last_rx_timestamp; 225 void *desc; /* descriptor ring memory */ 226 unsigned long flags; /* ring specific flags */ 227 void __iomem *tail; /* pointer to ring tail register */ 228 dma_addr_t dma; /* phys address of the ring */ 229 unsigned int size; /* length of desc. ring in bytes */ 230 231 u16 count; /* number of desc. in the ring */ 232 u8 queue_index; /* logical index of the ring*/ 233 u8 reg_idx; /* physical index of the ring */ 234 235 /* everything past this point are written often */ 236 u16 next_to_clean; 237 u16 next_to_use; 238 u16 next_to_alloc; 239 240 union { 241 /* TX */ 242 struct { 243 struct igb_tx_queue_stats tx_stats; 244 struct u64_stats_sync tx_syncp; 245 struct u64_stats_sync tx_syncp2; 246 }; 247 /* RX */ 248 struct { 249 struct sk_buff *skb; 250 struct igb_rx_queue_stats rx_stats; 251 struct u64_stats_sync rx_syncp; 252 }; 253 }; 254} ____cacheline_internodealigned_in_smp; 255 256struct igb_q_vector { 257 struct igb_adapter *adapter; /* backlink */ 258 int cpu; /* CPU for DCA */ 259 u32 eims_value; /* EIMS mask value */ 260 261 u16 itr_val; 262 u8 set_itr; 263 void __iomem *itr_register; 264 265 struct igb_ring_container rx, tx; 266 267 struct napi_struct napi; 268 struct rcu_head rcu; /* to avoid race with update stats on free */ 269 char name[IFNAMSIZ + 9]; 270 271 /* for dynamic allocation of rings associated with this q_vector */ 272 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 273}; 274 275enum e1000_ring_flags_t { 276 IGB_RING_FLAG_RX_SCTP_CSUM, 277 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 278 IGB_RING_FLAG_TX_CTX_IDX, 279 IGB_RING_FLAG_TX_DETECT_HANG 280}; 281 282#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 283 284#define IGB_RX_DESC(R, i) \ 285 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 286#define IGB_TX_DESC(R, i) \ 287 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 288#define IGB_TX_CTXTDESC(R, i) \ 289 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 290 291/* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 292static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 293 const u32 stat_err_bits) 294{ 295 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 296} 297 298/* igb_desc_unused - calculate if we have unused descriptors */ 299static inline int igb_desc_unused(struct igb_ring *ring) 300{ 301 if (ring->next_to_clean > ring->next_to_use) 302 return ring->next_to_clean - ring->next_to_use - 1; 303 304 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 305} 306 307struct igb_i2c_client_list { 308 struct i2c_client *client; 309 struct igb_i2c_client_list *next; 310}; 311 312#ifdef CONFIG_IGB_HWMON 313 314#define IGB_HWMON_TYPE_LOC 0 315#define IGB_HWMON_TYPE_TEMP 1 316#define IGB_HWMON_TYPE_CAUTION 2 317#define IGB_HWMON_TYPE_MAX 3 318 319struct hwmon_attr { 320 struct device_attribute dev_attr; 321 struct e1000_hw *hw; 322 struct e1000_thermal_diode_data *sensor; 323 char name[12]; 324 }; 325 326struct hwmon_buff { 327 struct device *device; 328 struct hwmon_attr *hwmon_list; 329 unsigned int n_hwmon; 330 }; 331#endif 332 333/* board specific private data structure */ 334struct igb_adapter { 335 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 336 337 struct net_device *netdev; 338 339 unsigned long state; 340 unsigned int flags; 341 342 unsigned int num_q_vectors; 343 struct msix_entry *msix_entries; 344 345 /* Interrupt Throttle Rate */ 346 u32 rx_itr_setting; 347 u32 tx_itr_setting; 348 u16 tx_itr; 349 u16 rx_itr; 350 351 /* TX */ 352 u16 tx_work_limit; 353 u32 tx_timeout_count; 354 int num_tx_queues; 355 struct igb_ring *tx_ring[16]; 356 357 /* RX */ 358 int num_rx_queues; 359 struct igb_ring *rx_ring[16]; 360 361 u32 max_frame_size; 362 u32 min_frame_size; 363 364 struct timer_list watchdog_timer; 365 struct timer_list phy_info_timer; 366 367 u16 mng_vlan_id; 368 u32 bd_number; 369 u32 wol; 370 u32 en_mng_pt; 371 u16 link_speed; 372 u16 link_duplex; 373 374 struct work_struct reset_task; 375 struct work_struct watchdog_task; 376 bool fc_autoneg; 377 u8 tx_timeout_factor; 378 struct timer_list blink_timer; 379 unsigned long led_status; 380 381 /* OS defined structs */ 382 struct pci_dev *pdev; 383 384 spinlock_t stats64_lock; 385 struct rtnl_link_stats64 stats64; 386 387 /* structs defined in e1000_hw.h */ 388 struct e1000_hw hw; 389 struct e1000_hw_stats stats; 390 struct e1000_phy_info phy_info; 391 struct e1000_phy_stats phy_stats; 392 393 u32 test_icr; 394 struct igb_ring test_tx_ring; 395 struct igb_ring test_rx_ring; 396 397 int msg_enable; 398 399 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 400 u32 eims_enable_mask; 401 u32 eims_other; 402 403 /* to not mess up cache alignment, always add to the bottom */ 404 u16 tx_ring_count; 405 u16 rx_ring_count; 406 unsigned int vfs_allocated_count; 407 struct vf_data_storage *vf_data; 408 int vf_rate_link_speed; 409 u32 rss_queues; 410 u32 wvbr; 411 u32 *shadow_vfta; 412 413 struct ptp_clock *ptp_clock; 414 struct ptp_clock_info ptp_caps; 415 struct delayed_work ptp_overflow_work; 416 struct work_struct ptp_tx_work; 417 struct sk_buff *ptp_tx_skb; 418 unsigned long ptp_tx_start; 419 unsigned long last_rx_ptp_check; 420 spinlock_t tmreg_lock; 421 struct cyclecounter cc; 422 struct timecounter tc; 423 u32 tx_hwtstamp_timeouts; 424 u32 rx_hwtstamp_cleared; 425 426 char fw_version[32]; 427#ifdef CONFIG_IGB_HWMON 428 struct hwmon_buff igb_hwmon_buff; 429 bool ets; 430#endif 431 struct i2c_algo_bit_data i2c_algo; 432 struct i2c_adapter i2c_adap; 433 struct igb_i2c_client_list *i2c_clients; 434}; 435 436#define IGB_FLAG_HAS_MSI (1 << 0) 437#define IGB_FLAG_DCA_ENABLED (1 << 1) 438#define IGB_FLAG_QUAD_PORT_A (1 << 2) 439#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 440#define IGB_FLAG_DMAC (1 << 4) 441#define IGB_FLAG_PTP (1 << 5) 442#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) 443#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) 444#define IGB_FLAG_WOL_SUPPORTED (1 << 8) 445 446/* DMA Coalescing defines */ 447#define IGB_MIN_TXPBSIZE 20408 448#define IGB_TX_BUF_4096 4096 449#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 450 451#define IGB_82576_TSYNC_SHIFT 19 452#define IGB_TS_HDR_LEN 16 453enum e1000_state_t { 454 __IGB_TESTING, 455 __IGB_RESETTING, 456 __IGB_DOWN 457}; 458 459enum igb_boards { 460 board_82575, 461}; 462 463extern char igb_driver_name[]; 464extern char igb_driver_version[]; 465 466extern int igb_up(struct igb_adapter *); 467extern void igb_down(struct igb_adapter *); 468extern void igb_reinit_locked(struct igb_adapter *); 469extern void igb_reset(struct igb_adapter *); 470extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 471extern int igb_setup_tx_resources(struct igb_ring *); 472extern int igb_setup_rx_resources(struct igb_ring *); 473extern void igb_free_tx_resources(struct igb_ring *); 474extern void igb_free_rx_resources(struct igb_ring *); 475extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 476extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 477extern void igb_setup_tctl(struct igb_adapter *); 478extern void igb_setup_rctl(struct igb_adapter *); 479extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 480extern void igb_unmap_and_free_tx_resource(struct igb_ring *, 481 struct igb_tx_buffer *); 482extern void igb_alloc_rx_buffers(struct igb_ring *, u16); 483extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 484extern bool igb_has_link(struct igb_adapter *adapter); 485extern void igb_set_ethtool_ops(struct net_device *); 486extern void igb_power_up_link(struct igb_adapter *); 487extern void igb_set_fw_version(struct igb_adapter *); 488extern void igb_ptp_init(struct igb_adapter *adapter); 489extern void igb_ptp_stop(struct igb_adapter *adapter); 490extern void igb_ptp_reset(struct igb_adapter *adapter); 491extern void igb_ptp_tx_work(struct work_struct *work); 492extern void igb_ptp_rx_hang(struct igb_adapter *adapter); 493extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 494extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 495 struct sk_buff *skb); 496extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 497 unsigned char *va, 498 struct sk_buff *skb); 499static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector, 500 union e1000_adv_rx_desc *rx_desc, 501 struct sk_buff *skb) 502{ 503 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 504 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 505 igb_ptp_rx_rgtstamp(q_vector, skb); 506} 507 508extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 509 struct ifreq *ifr, int cmd); 510#ifdef CONFIG_IGB_HWMON 511extern void igb_sysfs_exit(struct igb_adapter *adapter); 512extern int igb_sysfs_init(struct igb_adapter *adapter); 513#endif 514static inline s32 igb_reset_phy(struct e1000_hw *hw) 515{ 516 if (hw->phy.ops.reset) 517 return hw->phy.ops.reset(hw); 518 519 return 0; 520} 521 522static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 523{ 524 if (hw->phy.ops.read_reg) 525 return hw->phy.ops.read_reg(hw, offset, data); 526 527 return 0; 528} 529 530static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 531{ 532 if (hw->phy.ops.write_reg) 533 return hw->phy.ops.write_reg(hw, offset, data); 534 535 return 0; 536} 537 538static inline s32 igb_get_phy_info(struct e1000_hw *hw) 539{ 540 if (hw->phy.ops.get_phy_info) 541 return hw->phy.ops.get_phy_info(hw); 542 543 return 0; 544} 545 546static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 547{ 548 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 549} 550 551#endif /* _IGB_H_ */ 552