igb.h revision c9f14bf3a49f86e6402a6e3476a180f2bdc8a71b
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28 29/* Linux PRO/1000 Ethernet Driver main header file */ 30 31#ifndef _IGB_H_ 32#define _IGB_H_ 33 34#include "e1000_mac.h" 35#include "e1000_82575.h" 36 37#ifdef CONFIG_IGB_PTP 38#include <linux/clocksource.h> 39#include <linux/net_tstamp.h> 40#include <linux/ptp_clock_kernel.h> 41#endif /* CONFIG_IGB_PTP */ 42#include <linux/bitops.h> 43#include <linux/if_vlan.h> 44 45struct igb_adapter; 46 47/* Interrupt defines */ 48#define IGB_START_ITR 648 /* ~6000 ints/sec */ 49#define IGB_4K_ITR 980 50#define IGB_20K_ITR 196 51#define IGB_70K_ITR 56 52 53/* TX/RX descriptor defines */ 54#define IGB_DEFAULT_TXD 256 55#define IGB_DEFAULT_TX_WORK 128 56#define IGB_MIN_TXD 80 57#define IGB_MAX_TXD 4096 58 59#define IGB_DEFAULT_RXD 256 60#define IGB_MIN_RXD 80 61#define IGB_MAX_RXD 4096 62 63#define IGB_DEFAULT_ITR 3 /* dynamic */ 64#define IGB_MAX_ITR_USECS 10000 65#define IGB_MIN_ITR_USECS 10 66#define NON_Q_VECTORS 1 67#define MAX_Q_VECTORS 8 68 69/* Transmit and receive queues */ 70#define IGB_MAX_RX_QUEUES 8 71#define IGB_MAX_RX_QUEUES_82575 4 72#define IGB_MAX_RX_QUEUES_I211 2 73#define IGB_MAX_TX_QUEUES 8 74#define IGB_MAX_VF_MC_ENTRIES 30 75#define IGB_MAX_VF_FUNCTIONS 8 76#define IGB_MAX_VFTA_ENTRIES 128 77#define IGB_82576_VF_DEV_ID 0x10CA 78#define IGB_I350_VF_DEV_ID 0x1520 79 80/* NVM version defines */ 81#define IGB_MAJOR_MASK 0xF000 82#define IGB_MINOR_MASK 0x0FF0 83#define IGB_BUILD_MASK 0x000F 84#define IGB_COMB_VER_MASK 0x00FF 85#define IGB_MAJOR_SHIFT 12 86#define IGB_MINOR_SHIFT 4 87#define IGB_COMB_VER_SHFT 8 88#define IGB_NVM_VER_INVALID 0xFFFF 89#define IGB_ETRACK_SHIFT 16 90#define NVM_ETRACK_WORD 0x0042 91#define NVM_COMB_VER_OFF 0x0083 92#define NVM_COMB_VER_PTR 0x003d 93 94struct vf_data_storage { 95 unsigned char vf_mac_addresses[ETH_ALEN]; 96 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 97 u16 num_vf_mc_hashes; 98 u16 vlans_enabled; 99 u32 flags; 100 unsigned long last_nack; 101 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 102 u16 pf_qos; 103 u16 tx_rate; 104}; 105 106#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 107#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 108#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 109#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 110 111/* RX descriptor control thresholds. 112 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 113 * descriptors available in its onboard memory. 114 * Setting this to 0 disables RX descriptor prefetch. 115 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 116 * available in host memory. 117 * If PTHRESH is 0, this should also be 0. 118 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 119 * descriptors until either it has this many to write back, or the 120 * ITR timer expires. 121 */ 122#define IGB_RX_PTHRESH 8 123#define IGB_RX_HTHRESH 8 124#define IGB_TX_PTHRESH 8 125#define IGB_TX_HTHRESH 1 126#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 127 adapter->msix_entries) ? 1 : 4) 128#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 129 adapter->msix_entries) ? 1 : 16) 130 131/* this is the size past which hardware will drop packets when setting LPE=0 */ 132#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 133 134/* Supported Rx Buffer Sizes */ 135#define IGB_RXBUFFER_256 256 136#define IGB_RXBUFFER_16384 16384 137#define IGB_RX_HDR_LEN IGB_RXBUFFER_256 138 139/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 140#define IGB_TX_QUEUE_WAKE 16 141/* How many Rx Buffers do we bundle into one write to the hardware ? */ 142#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 143 144#define AUTO_ALL_MODES 0 145#define IGB_EEPROM_APME 0x0400 146 147#ifndef IGB_MASTER_SLAVE 148/* Switch to override PHY master/slave setting */ 149#define IGB_MASTER_SLAVE e1000_ms_hw_default 150#endif 151 152#define IGB_MNG_VLAN_NONE -1 153 154#define IGB_TX_FLAGS_CSUM 0x00000001 155#define IGB_TX_FLAGS_VLAN 0x00000002 156#define IGB_TX_FLAGS_TSO 0x00000004 157#define IGB_TX_FLAGS_IPV4 0x00000008 158#define IGB_TX_FLAGS_TSTAMP 0x00000010 159#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 160#define IGB_TX_FLAGS_VLAN_SHIFT 16 161 162/* wrapper around a pointer to a socket buffer, 163 * so a DMA handle can be stored along with the buffer */ 164struct igb_tx_buffer { 165 union e1000_adv_tx_desc *next_to_watch; 166 unsigned long time_stamp; 167 struct sk_buff *skb; 168 unsigned int bytecount; 169 u16 gso_segs; 170 __be16 protocol; 171 DEFINE_DMA_UNMAP_ADDR(dma); 172 DEFINE_DMA_UNMAP_LEN(len); 173 u32 tx_flags; 174}; 175 176struct igb_rx_buffer { 177 struct sk_buff *skb; 178 dma_addr_t dma; 179 struct page *page; 180 dma_addr_t page_dma; 181 u32 page_offset; 182}; 183 184struct igb_tx_queue_stats { 185 u64 packets; 186 u64 bytes; 187 u64 restart_queue; 188 u64 restart_queue2; 189}; 190 191struct igb_rx_queue_stats { 192 u64 packets; 193 u64 bytes; 194 u64 drops; 195 u64 csum_err; 196 u64 alloc_failed; 197}; 198 199struct igb_ring_container { 200 struct igb_ring *ring; /* pointer to linked list of rings */ 201 unsigned int total_bytes; /* total bytes processed this int */ 202 unsigned int total_packets; /* total packets processed this int */ 203 u16 work_limit; /* total work allowed per interrupt */ 204 u8 count; /* total number of rings in vector */ 205 u8 itr; /* current ITR setting for ring */ 206}; 207 208struct igb_q_vector { 209 struct igb_adapter *adapter; /* backlink */ 210 int cpu; /* CPU for DCA */ 211 u32 eims_value; /* EIMS mask value */ 212 213 struct igb_ring_container rx, tx; 214 215 struct napi_struct napi; 216 217 u16 itr_val; 218 u8 set_itr; 219 void __iomem *itr_register; 220 221 char name[IFNAMSIZ + 9]; 222}; 223 224struct igb_ring { 225 struct igb_q_vector *q_vector; /* backlink to q_vector */ 226 struct net_device *netdev; /* back pointer to net_device */ 227 struct device *dev; /* device pointer for dma mapping */ 228 union { /* array of buffer info structs */ 229 struct igb_tx_buffer *tx_buffer_info; 230 struct igb_rx_buffer *rx_buffer_info; 231 }; 232 void *desc; /* descriptor ring memory */ 233 unsigned long flags; /* ring specific flags */ 234 void __iomem *tail; /* pointer to ring tail register */ 235 236 u16 count; /* number of desc. in the ring */ 237 u8 queue_index; /* logical index of the ring*/ 238 u8 reg_idx; /* physical index of the ring */ 239 u32 size; /* length of desc. ring in bytes */ 240 241 /* everything past this point are written often */ 242 u16 next_to_clean ____cacheline_aligned_in_smp; 243 u16 next_to_use; 244 245 union { 246 /* TX */ 247 struct { 248 struct igb_tx_queue_stats tx_stats; 249 struct u64_stats_sync tx_syncp; 250 struct u64_stats_sync tx_syncp2; 251 }; 252 /* RX */ 253 struct { 254 struct igb_rx_queue_stats rx_stats; 255 struct u64_stats_sync rx_syncp; 256 }; 257 }; 258 /* Items past this point are only used during ring alloc / free */ 259 dma_addr_t dma; /* phys address of the ring */ 260}; 261 262enum e1000_ring_flags_t { 263 IGB_RING_FLAG_RX_SCTP_CSUM, 264 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 265 IGB_RING_FLAG_TX_CTX_IDX, 266 IGB_RING_FLAG_TX_DETECT_HANG 267}; 268 269#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 270 271#define IGB_RX_DESC(R, i) \ 272 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 273#define IGB_TX_DESC(R, i) \ 274 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 275#define IGB_TX_CTXTDESC(R, i) \ 276 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 277 278/* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 279static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 280 const u32 stat_err_bits) 281{ 282 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 283} 284 285/* igb_desc_unused - calculate if we have unused descriptors */ 286static inline int igb_desc_unused(struct igb_ring *ring) 287{ 288 if (ring->next_to_clean > ring->next_to_use) 289 return ring->next_to_clean - ring->next_to_use - 1; 290 291 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 292} 293 294/* board specific private data structure */ 295struct igb_adapter { 296 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 297 298 struct net_device *netdev; 299 300 unsigned long state; 301 unsigned int flags; 302 303 unsigned int num_q_vectors; 304 struct msix_entry *msix_entries; 305 306 /* Interrupt Throttle Rate */ 307 u32 rx_itr_setting; 308 u32 tx_itr_setting; 309 u16 tx_itr; 310 u16 rx_itr; 311 312 /* TX */ 313 u16 tx_work_limit; 314 u32 tx_timeout_count; 315 int num_tx_queues; 316 struct igb_ring *tx_ring[16]; 317 318 /* RX */ 319 int num_rx_queues; 320 struct igb_ring *rx_ring[16]; 321 322 u32 max_frame_size; 323 u32 min_frame_size; 324 325 struct timer_list watchdog_timer; 326 struct timer_list phy_info_timer; 327 328 u16 mng_vlan_id; 329 u32 bd_number; 330 u32 wol; 331 u32 en_mng_pt; 332 u16 link_speed; 333 u16 link_duplex; 334 335 struct work_struct reset_task; 336 struct work_struct watchdog_task; 337 bool fc_autoneg; 338 u8 tx_timeout_factor; 339 struct timer_list blink_timer; 340 unsigned long led_status; 341 342 /* OS defined structs */ 343 struct pci_dev *pdev; 344 345 spinlock_t stats64_lock; 346 struct rtnl_link_stats64 stats64; 347 348 /* structs defined in e1000_hw.h */ 349 struct e1000_hw hw; 350 struct e1000_hw_stats stats; 351 struct e1000_phy_info phy_info; 352 struct e1000_phy_stats phy_stats; 353 354 u32 test_icr; 355 struct igb_ring test_tx_ring; 356 struct igb_ring test_rx_ring; 357 358 int msg_enable; 359 360 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 361 u32 eims_enable_mask; 362 u32 eims_other; 363 364 /* to not mess up cache alignment, always add to the bottom */ 365 u32 eeprom_wol; 366 367 u16 tx_ring_count; 368 u16 rx_ring_count; 369 unsigned int vfs_allocated_count; 370 struct vf_data_storage *vf_data; 371 int vf_rate_link_speed; 372 u32 rss_queues; 373 u32 wvbr; 374 u32 *shadow_vfta; 375 376#ifdef CONFIG_IGB_PTP 377 struct ptp_clock *ptp_clock; 378 struct ptp_clock_info ptp_caps; 379 struct delayed_work ptp_overflow_work; 380 struct work_struct ptp_tx_work; 381 struct sk_buff *ptp_tx_skb; 382 spinlock_t tmreg_lock; 383 struct cyclecounter cc; 384 struct timecounter tc; 385#endif /* CONFIG_IGB_PTP */ 386 387 char fw_version[32]; 388}; 389 390#define IGB_FLAG_HAS_MSI (1 << 0) 391#define IGB_FLAG_DCA_ENABLED (1 << 1) 392#define IGB_FLAG_QUAD_PORT_A (1 << 2) 393#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 394#define IGB_FLAG_DMAC (1 << 4) 395#define IGB_FLAG_PTP (1 << 5) 396 397/* DMA Coalescing defines */ 398#define IGB_MIN_TXPBSIZE 20408 399#define IGB_TX_BUF_4096 4096 400#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 401 402#define IGB_82576_TSYNC_SHIFT 19 403#define IGB_TS_HDR_LEN 16 404enum e1000_state_t { 405 __IGB_TESTING, 406 __IGB_RESETTING, 407 __IGB_DOWN 408}; 409 410enum igb_boards { 411 board_82575, 412}; 413 414extern char igb_driver_name[]; 415extern char igb_driver_version[]; 416 417extern int igb_up(struct igb_adapter *); 418extern void igb_down(struct igb_adapter *); 419extern void igb_reinit_locked(struct igb_adapter *); 420extern void igb_reset(struct igb_adapter *); 421extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 422extern int igb_setup_tx_resources(struct igb_ring *); 423extern int igb_setup_rx_resources(struct igb_ring *); 424extern void igb_free_tx_resources(struct igb_ring *); 425extern void igb_free_rx_resources(struct igb_ring *); 426extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 427extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 428extern void igb_setup_tctl(struct igb_adapter *); 429extern void igb_setup_rctl(struct igb_adapter *); 430extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 431extern void igb_unmap_and_free_tx_resource(struct igb_ring *, 432 struct igb_tx_buffer *); 433extern void igb_alloc_rx_buffers(struct igb_ring *, u16); 434extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 435extern bool igb_has_link(struct igb_adapter *adapter); 436extern void igb_set_ethtool_ops(struct net_device *); 437extern void igb_power_up_link(struct igb_adapter *); 438extern void igb_set_fw_version(struct igb_adapter *); 439#ifdef CONFIG_IGB_PTP 440extern void igb_ptp_init(struct igb_adapter *adapter); 441extern void igb_ptp_stop(struct igb_adapter *adapter); 442extern void igb_ptp_reset(struct igb_adapter *adapter); 443extern void igb_ptp_tx_work(struct work_struct *work); 444extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 445extern void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector, 446 union e1000_adv_rx_desc *rx_desc, 447 struct sk_buff *skb); 448extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 449 struct ifreq *ifr, int cmd); 450#endif /* CONFIG_IGB_PTP */ 451 452static inline s32 igb_reset_phy(struct e1000_hw *hw) 453{ 454 if (hw->phy.ops.reset) 455 return hw->phy.ops.reset(hw); 456 457 return 0; 458} 459 460static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 461{ 462 if (hw->phy.ops.read_reg) 463 return hw->phy.ops.read_reg(hw, offset, data); 464 465 return 0; 466} 467 468static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 469{ 470 if (hw->phy.ops.write_reg) 471 return hw->phy.ops.write_reg(hw, offset, data); 472 473 return 0; 474} 475 476static inline s32 igb_get_phy_info(struct e1000_hw *hw) 477{ 478 if (hw->phy.ops.get_phy_info) 479 return hw->phy.ops.get_phy_info(hw); 480 481 return 0; 482} 483 484static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 485{ 486 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 487} 488 489#endif /* _IGB_H_ */ 490