igb.h revision ebe42d169bd0b4c3e2e355374d07ba7d51744601
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28 29/* Linux PRO/1000 Ethernet Driver main header file */ 30 31#ifndef _IGB_H_ 32#define _IGB_H_ 33 34#include "e1000_mac.h" 35#include "e1000_82575.h" 36 37#include <linux/clocksource.h> 38#include <linux/timecompare.h> 39#include <linux/net_tstamp.h> 40#include <linux/bitops.h> 41#include <linux/if_vlan.h> 42 43struct igb_adapter; 44 45/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ 46#define IGB_START_ITR 648 47 48/* TX/RX descriptor defines */ 49#define IGB_DEFAULT_TXD 256 50#define IGB_DEFAULT_TX_WORK 128 51#define IGB_MIN_TXD 80 52#define IGB_MAX_TXD 4096 53 54#define IGB_DEFAULT_RXD 256 55#define IGB_MIN_RXD 80 56#define IGB_MAX_RXD 4096 57 58#define IGB_DEFAULT_ITR 3 /* dynamic */ 59#define IGB_MAX_ITR_USECS 10000 60#define IGB_MIN_ITR_USECS 10 61#define NON_Q_VECTORS 1 62#define MAX_Q_VECTORS 8 63 64/* Transmit and receive queues */ 65#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ 66 (hw->mac.type > e1000_82575 ? 8 : 4)) 67#define IGB_MAX_TX_QUEUES 16 68 69#define IGB_MAX_VF_MC_ENTRIES 30 70#define IGB_MAX_VF_FUNCTIONS 8 71#define IGB_MAX_VFTA_ENTRIES 128 72 73struct vf_data_storage { 74 unsigned char vf_mac_addresses[ETH_ALEN]; 75 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 76 u16 num_vf_mc_hashes; 77 u16 vlans_enabled; 78 u32 flags; 79 unsigned long last_nack; 80 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 81 u16 pf_qos; 82 u16 tx_rate; 83}; 84 85#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 86#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 87#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 88#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 89 90/* RX descriptor control thresholds. 91 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 92 * descriptors available in its onboard memory. 93 * Setting this to 0 disables RX descriptor prefetch. 94 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 95 * available in host memory. 96 * If PTHRESH is 0, this should also be 0. 97 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 98 * descriptors until either it has this many to write back, or the 99 * ITR timer expires. 100 */ 101#define IGB_RX_PTHRESH 8 102#define IGB_RX_HTHRESH 8 103#define IGB_TX_PTHRESH 8 104#define IGB_TX_HTHRESH 1 105#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 106 adapter->msix_entries) ? 1 : 4) 107#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 108 adapter->msix_entries) ? 1 : 16) 109 110/* this is the size past which hardware will drop packets when setting LPE=0 */ 111#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 112 113/* Supported Rx Buffer Sizes */ 114#define IGB_RXBUFFER_512 512 115#define IGB_RXBUFFER_16384 16384 116#define IGB_RX_HDR_LEN IGB_RXBUFFER_512 117 118/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 119#define IGB_TX_QUEUE_WAKE 16 120/* How many Rx Buffers do we bundle into one write to the hardware ? */ 121#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 122 123#define AUTO_ALL_MODES 0 124#define IGB_EEPROM_APME 0x0400 125 126#ifndef IGB_MASTER_SLAVE 127/* Switch to override PHY master/slave setting */ 128#define IGB_MASTER_SLAVE e1000_ms_hw_default 129#endif 130 131#define IGB_MNG_VLAN_NONE -1 132 133#define IGB_TX_FLAGS_CSUM 0x00000001 134#define IGB_TX_FLAGS_VLAN 0x00000002 135#define IGB_TX_FLAGS_TSO 0x00000004 136#define IGB_TX_FLAGS_IPV4 0x00000008 137#define IGB_TX_FLAGS_TSTAMP 0x00000010 138#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 139#define IGB_TX_FLAGS_VLAN_SHIFT 16 140 141/* wrapper around a pointer to a socket buffer, 142 * so a DMA handle can be stored along with the buffer */ 143struct igb_tx_buffer { 144 union e1000_adv_tx_desc *next_to_watch; 145 unsigned long time_stamp; 146 struct sk_buff *skb; 147 unsigned int bytecount; 148 u16 gso_segs; 149 dma_addr_t dma; 150 u32 length; 151 u32 tx_flags; 152}; 153 154struct igb_rx_buffer { 155 struct sk_buff *skb; 156 dma_addr_t dma; 157 struct page *page; 158 dma_addr_t page_dma; 159 u32 page_offset; 160}; 161 162struct igb_tx_queue_stats { 163 u64 packets; 164 u64 bytes; 165 u64 restart_queue; 166 u64 restart_queue2; 167}; 168 169struct igb_rx_queue_stats { 170 u64 packets; 171 u64 bytes; 172 u64 drops; 173 u64 csum_err; 174 u64 alloc_failed; 175}; 176 177struct igb_q_vector { 178 struct igb_adapter *adapter; /* backlink */ 179 struct igb_ring *rx_ring; 180 struct igb_ring *tx_ring; 181 struct napi_struct napi; 182 183 u32 eims_value; 184 u16 cpu; 185 u16 tx_work_limit; 186 187 u16 itr_val; 188 u8 set_itr; 189 void __iomem *itr_register; 190 191 char name[IFNAMSIZ + 9]; 192}; 193 194struct igb_ring { 195 struct igb_q_vector *q_vector; /* backlink to q_vector */ 196 struct net_device *netdev; /* back pointer to net_device */ 197 struct device *dev; /* device pointer for dma mapping */ 198 union { /* array of buffer info structs */ 199 struct igb_tx_buffer *tx_buffer_info; 200 struct igb_rx_buffer *rx_buffer_info; 201 }; 202 void *desc; /* descriptor ring memory */ 203 unsigned long flags; /* ring specific flags */ 204 void __iomem *tail; /* pointer to ring tail register */ 205 206 u16 count; /* number of desc. in the ring */ 207 u8 queue_index; /* logical index of the ring*/ 208 u8 reg_idx; /* physical index of the ring */ 209 u32 size; /* length of desc. ring in bytes */ 210 211 /* everything past this point are written often */ 212 u16 next_to_clean ____cacheline_aligned_in_smp; 213 u16 next_to_use; 214 215 unsigned int total_bytes; 216 unsigned int total_packets; 217 218 union { 219 /* TX */ 220 struct { 221 struct igb_tx_queue_stats tx_stats; 222 struct u64_stats_sync tx_syncp; 223 struct u64_stats_sync tx_syncp2; 224 bool detect_tx_hung; 225 }; 226 /* RX */ 227 struct { 228 struct igb_rx_queue_stats rx_stats; 229 struct u64_stats_sync rx_syncp; 230 }; 231 }; 232 /* Items past this point are only used during ring alloc / free */ 233 dma_addr_t dma; /* phys address of the ring */ 234}; 235 236#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ 237#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */ 238 239#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */ 240 241#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 242 243#define IGB_RX_DESC(R, i) \ 244 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 245#define IGB_TX_DESC(R, i) \ 246 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 247#define IGB_TX_CTXTDESC(R, i) \ 248 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 249 250/* igb_desc_unused - calculate if we have unused descriptors */ 251static inline int igb_desc_unused(struct igb_ring *ring) 252{ 253 if (ring->next_to_clean > ring->next_to_use) 254 return ring->next_to_clean - ring->next_to_use - 1; 255 256 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 257} 258 259/* board specific private data structure */ 260struct igb_adapter { 261 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 262 263 struct net_device *netdev; 264 265 unsigned long state; 266 unsigned int flags; 267 268 unsigned int num_q_vectors; 269 struct msix_entry *msix_entries; 270 271 /* Interrupt Throttle Rate */ 272 u32 rx_itr_setting; 273 u32 tx_itr_setting; 274 u16 tx_itr; 275 u16 rx_itr; 276 277 /* TX */ 278 u16 tx_work_limit; 279 u32 tx_timeout_count; 280 int num_tx_queues; 281 struct igb_ring *tx_ring[16]; 282 283 /* RX */ 284 int num_rx_queues; 285 struct igb_ring *rx_ring[16]; 286 287 u32 max_frame_size; 288 u32 min_frame_size; 289 290 struct timer_list watchdog_timer; 291 struct timer_list phy_info_timer; 292 293 u16 mng_vlan_id; 294 u32 bd_number; 295 u32 wol; 296 u32 en_mng_pt; 297 u16 link_speed; 298 u16 link_duplex; 299 300 struct work_struct reset_task; 301 struct work_struct watchdog_task; 302 bool fc_autoneg; 303 u8 tx_timeout_factor; 304 struct timer_list blink_timer; 305 unsigned long led_status; 306 307 /* OS defined structs */ 308 struct pci_dev *pdev; 309 struct cyclecounter cycles; 310 struct timecounter clock; 311 struct timecompare compare; 312 struct hwtstamp_config hwtstamp_config; 313 314 spinlock_t stats64_lock; 315 struct rtnl_link_stats64 stats64; 316 317 /* structs defined in e1000_hw.h */ 318 struct e1000_hw hw; 319 struct e1000_hw_stats stats; 320 struct e1000_phy_info phy_info; 321 struct e1000_phy_stats phy_stats; 322 323 u32 test_icr; 324 struct igb_ring test_tx_ring; 325 struct igb_ring test_rx_ring; 326 327 int msg_enable; 328 329 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 330 u32 eims_enable_mask; 331 u32 eims_other; 332 333 /* to not mess up cache alignment, always add to the bottom */ 334 u32 eeprom_wol; 335 336 u16 tx_ring_count; 337 u16 rx_ring_count; 338 unsigned int vfs_allocated_count; 339 struct vf_data_storage *vf_data; 340 int vf_rate_link_speed; 341 u32 rss_queues; 342 u32 wvbr; 343}; 344 345#define IGB_FLAG_HAS_MSI (1 << 0) 346#define IGB_FLAG_DCA_ENABLED (1 << 1) 347#define IGB_FLAG_QUAD_PORT_A (1 << 2) 348#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 349#define IGB_FLAG_DMAC (1 << 4) 350 351/* DMA Coalescing defines */ 352#define IGB_MIN_TXPBSIZE 20408 353#define IGB_TX_BUF_4096 4096 354#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 355 356#define IGB_82576_TSYNC_SHIFT 19 357#define IGB_82580_TSYNC_SHIFT 24 358#define IGB_TS_HDR_LEN 16 359enum e1000_state_t { 360 __IGB_TESTING, 361 __IGB_RESETTING, 362 __IGB_DOWN 363}; 364 365enum igb_boards { 366 board_82575, 367}; 368 369extern char igb_driver_name[]; 370extern char igb_driver_version[]; 371 372extern int igb_up(struct igb_adapter *); 373extern void igb_down(struct igb_adapter *); 374extern void igb_reinit_locked(struct igb_adapter *); 375extern void igb_reset(struct igb_adapter *); 376extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 377extern int igb_setup_tx_resources(struct igb_ring *); 378extern int igb_setup_rx_resources(struct igb_ring *); 379extern void igb_free_tx_resources(struct igb_ring *); 380extern void igb_free_rx_resources(struct igb_ring *); 381extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 382extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 383extern void igb_setup_tctl(struct igb_adapter *); 384extern void igb_setup_rctl(struct igb_adapter *); 385extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 386extern void igb_unmap_and_free_tx_resource(struct igb_ring *, 387 struct igb_tx_buffer *); 388extern void igb_alloc_rx_buffers(struct igb_ring *, u16); 389extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 390extern bool igb_has_link(struct igb_adapter *adapter); 391extern void igb_set_ethtool_ops(struct net_device *); 392extern void igb_power_up_link(struct igb_adapter *); 393 394static inline s32 igb_reset_phy(struct e1000_hw *hw) 395{ 396 if (hw->phy.ops.reset) 397 return hw->phy.ops.reset(hw); 398 399 return 0; 400} 401 402static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 403{ 404 if (hw->phy.ops.read_reg) 405 return hw->phy.ops.read_reg(hw, offset, data); 406 407 return 0; 408} 409 410static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 411{ 412 if (hw->phy.ops.write_reg) 413 return hw->phy.ops.write_reg(hw, offset, data); 414 415 return 0; 416} 417 418static inline s32 igb_get_phy_info(struct e1000_hw *hw) 419{ 420 if (hw->phy.ops.get_phy_info) 421 return hw->phy.ops.get_phy_info(hw); 422 423 return 0; 424} 425 426#endif /* _IGB_H_ */ 427