igb_ethtool.c revision 87371b9de5becc32af2f9be84008b8a8a424c58a
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* ethtool support for igb */ 29 30#include <linux/vmalloc.h> 31#include <linux/netdevice.h> 32#include <linux/pci.h> 33#include <linux/delay.h> 34#include <linux/interrupt.h> 35#include <linux/if_ether.h> 36#include <linux/ethtool.h> 37#include <linux/sched.h> 38#include <linux/slab.h> 39#include <linux/pm_runtime.h> 40#include <linux/highmem.h> 41#include <linux/mdio.h> 42 43#include "igb.h" 44 45struct igb_stats { 46 char stat_string[ETH_GSTRING_LEN]; 47 int sizeof_stat; 48 int stat_offset; 49}; 50 51#define IGB_STAT(_name, _stat) { \ 52 .stat_string = _name, \ 53 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 54 .stat_offset = offsetof(struct igb_adapter, _stat) \ 55} 56static const struct igb_stats igb_gstrings_stats[] = { 57 IGB_STAT("rx_packets", stats.gprc), 58 IGB_STAT("tx_packets", stats.gptc), 59 IGB_STAT("rx_bytes", stats.gorc), 60 IGB_STAT("tx_bytes", stats.gotc), 61 IGB_STAT("rx_broadcast", stats.bprc), 62 IGB_STAT("tx_broadcast", stats.bptc), 63 IGB_STAT("rx_multicast", stats.mprc), 64 IGB_STAT("tx_multicast", stats.mptc), 65 IGB_STAT("multicast", stats.mprc), 66 IGB_STAT("collisions", stats.colc), 67 IGB_STAT("rx_crc_errors", stats.crcerrs), 68 IGB_STAT("rx_no_buffer_count", stats.rnbc), 69 IGB_STAT("rx_missed_errors", stats.mpc), 70 IGB_STAT("tx_aborted_errors", stats.ecol), 71 IGB_STAT("tx_carrier_errors", stats.tncrs), 72 IGB_STAT("tx_window_errors", stats.latecol), 73 IGB_STAT("tx_abort_late_coll", stats.latecol), 74 IGB_STAT("tx_deferred_ok", stats.dc), 75 IGB_STAT("tx_single_coll_ok", stats.scc), 76 IGB_STAT("tx_multi_coll_ok", stats.mcc), 77 IGB_STAT("tx_timeout_count", tx_timeout_count), 78 IGB_STAT("rx_long_length_errors", stats.roc), 79 IGB_STAT("rx_short_length_errors", stats.ruc), 80 IGB_STAT("rx_align_errors", stats.algnerrc), 81 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 82 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 83 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 84 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 85 IGB_STAT("tx_flow_control_xon", stats.xontxc), 86 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 87 IGB_STAT("rx_long_byte_count", stats.gorc), 88 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 89 IGB_STAT("tx_smbus", stats.mgptc), 90 IGB_STAT("rx_smbus", stats.mgprc), 91 IGB_STAT("dropped_smbus", stats.mgpdc), 92 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 93 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 94 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 95 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 96 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 97 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), 98}; 99 100#define IGB_NETDEV_STAT(_net_stat) { \ 101 .stat_string = __stringify(_net_stat), \ 102 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 103 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 104} 105static const struct igb_stats igb_gstrings_net_stats[] = { 106 IGB_NETDEV_STAT(rx_errors), 107 IGB_NETDEV_STAT(tx_errors), 108 IGB_NETDEV_STAT(tx_dropped), 109 IGB_NETDEV_STAT(rx_length_errors), 110 IGB_NETDEV_STAT(rx_over_errors), 111 IGB_NETDEV_STAT(rx_frame_errors), 112 IGB_NETDEV_STAT(rx_fifo_errors), 113 IGB_NETDEV_STAT(tx_fifo_errors), 114 IGB_NETDEV_STAT(tx_heartbeat_errors) 115}; 116 117#define IGB_GLOBAL_STATS_LEN \ 118 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 119#define IGB_NETDEV_STATS_LEN \ 120 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 121#define IGB_RX_QUEUE_STATS_LEN \ 122 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 123 124#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 125 126#define IGB_QUEUE_STATS_LEN \ 127 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 128 IGB_RX_QUEUE_STATS_LEN) + \ 129 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 130 IGB_TX_QUEUE_STATS_LEN)) 131#define IGB_STATS_LEN \ 132 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 133 134static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 135 "Register test (offline)", "Eeprom test (offline)", 136 "Interrupt test (offline)", "Loopback test (offline)", 137 "Link test (on/offline)" 138}; 139#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 140 141static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 142{ 143 struct igb_adapter *adapter = netdev_priv(netdev); 144 struct e1000_hw *hw = &adapter->hw; 145 u32 status; 146 147 if (hw->phy.media_type == e1000_media_type_copper) { 148 149 ecmd->supported = (SUPPORTED_10baseT_Half | 150 SUPPORTED_10baseT_Full | 151 SUPPORTED_100baseT_Half | 152 SUPPORTED_100baseT_Full | 153 SUPPORTED_1000baseT_Full| 154 SUPPORTED_Autoneg | 155 SUPPORTED_TP | 156 SUPPORTED_Pause); 157 ecmd->advertising = ADVERTISED_TP; 158 159 if (hw->mac.autoneg == 1) { 160 ecmd->advertising |= ADVERTISED_Autoneg; 161 /* the e1000 autoneg seems to match ethtool nicely */ 162 ecmd->advertising |= hw->phy.autoneg_advertised; 163 } 164 165 if (hw->mac.autoneg != 1) 166 ecmd->advertising &= ~(ADVERTISED_Pause | 167 ADVERTISED_Asym_Pause); 168 169 if (hw->fc.requested_mode == e1000_fc_full) 170 ecmd->advertising |= ADVERTISED_Pause; 171 else if (hw->fc.requested_mode == e1000_fc_rx_pause) 172 ecmd->advertising |= (ADVERTISED_Pause | 173 ADVERTISED_Asym_Pause); 174 else if (hw->fc.requested_mode == e1000_fc_tx_pause) 175 ecmd->advertising |= ADVERTISED_Asym_Pause; 176 else 177 ecmd->advertising &= ~(ADVERTISED_Pause | 178 ADVERTISED_Asym_Pause); 179 180 ecmd->port = PORT_TP; 181 ecmd->phy_address = hw->phy.addr; 182 ecmd->transceiver = XCVR_INTERNAL; 183 } else { 184 ecmd->supported = (SUPPORTED_1000baseT_Full | 185 SUPPORTED_100baseT_Full | 186 SUPPORTED_Autoneg | 187 SUPPORTED_FIBRE | 188 SUPPORTED_Pause); 189 190 ecmd->advertising = ADVERTISED_FIBRE; 191 192 if (adapter->link_speed == SPEED_100) 193 ecmd->advertising = ADVERTISED_100baseT_Full; 194 else if (adapter->link_speed == SPEED_1000) 195 ecmd->advertising = ADVERTISED_1000baseT_Full; 196 197 if (hw->mac.autoneg == 1) 198 ecmd->advertising |= ADVERTISED_Autoneg; 199 200 ecmd->port = PORT_FIBRE; 201 ecmd->transceiver = XCVR_EXTERNAL; 202 } 203 204 status = rd32(E1000_STATUS); 205 206 if (status & E1000_STATUS_LU) { 207 208 if (status & E1000_STATUS_SPEED_1000) 209 ethtool_cmd_speed_set(ecmd, SPEED_1000); 210 else if (status & E1000_STATUS_SPEED_100) 211 ethtool_cmd_speed_set(ecmd, SPEED_100); 212 else 213 ethtool_cmd_speed_set(ecmd, SPEED_10); 214 215 if ((status & E1000_STATUS_FD) || 216 hw->phy.media_type != e1000_media_type_copper) 217 ecmd->duplex = DUPLEX_FULL; 218 else 219 ecmd->duplex = DUPLEX_HALF; 220 } else { 221 ethtool_cmd_speed_set(ecmd, -1); 222 ecmd->duplex = -1; 223 } 224 225 if ((hw->phy.media_type == e1000_media_type_fiber) || 226 hw->mac.autoneg) 227 ecmd->autoneg = AUTONEG_ENABLE; 228 else 229 ecmd->autoneg = AUTONEG_DISABLE; 230 231 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 232 if (hw->phy.media_type == e1000_media_type_copper) 233 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 234 ETH_TP_MDI; 235 else 236 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 237 238 if (hw->phy.mdix == AUTO_ALL_MODES) 239 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 240 else 241 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; 242 243 return 0; 244} 245 246static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 247{ 248 struct igb_adapter *adapter = netdev_priv(netdev); 249 struct e1000_hw *hw = &adapter->hw; 250 251 /* When SoL/IDER sessions are active, autoneg/speed/duplex 252 * cannot be changed 253 */ 254 if (igb_check_reset_block(hw)) { 255 dev_err(&adapter->pdev->dev, 256 "Cannot change link characteristics when SoL/IDER is active.\n"); 257 return -EINVAL; 258 } 259 260 /* MDI setting is only allowed when autoneg enabled because 261 * some hardware doesn't allow MDI setting when speed or 262 * duplex is forced. 263 */ 264 if (ecmd->eth_tp_mdix_ctrl) { 265 if (hw->phy.media_type != e1000_media_type_copper) 266 return -EOPNOTSUPP; 267 268 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 269 (ecmd->autoneg != AUTONEG_ENABLE)) { 270 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 271 return -EINVAL; 272 } 273 } 274 275 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 276 msleep(1); 277 278 if (ecmd->autoneg == AUTONEG_ENABLE) { 279 hw->mac.autoneg = 1; 280 if (hw->phy.media_type == e1000_media_type_fiber) { 281 hw->phy.autoneg_advertised = ecmd->advertising | 282 ADVERTISED_FIBRE | 283 ADVERTISED_Autoneg; 284 if (adapter->link_speed == SPEED_1000) 285 hw->phy.autoneg_advertised = 286 ADVERTISED_1000baseT_Full; 287 else if (adapter->link_speed == SPEED_100) 288 hw->phy.autoneg_advertised = 289 ADVERTISED_100baseT_Full; 290 } else { 291 hw->phy.autoneg_advertised = ecmd->advertising | 292 ADVERTISED_TP | 293 ADVERTISED_Autoneg; 294 } 295 ecmd->advertising = hw->phy.autoneg_advertised; 296 if (adapter->fc_autoneg) 297 hw->fc.requested_mode = e1000_fc_default; 298 } else { 299 u32 speed = ethtool_cmd_speed(ecmd); 300 /* calling this overrides forced MDI setting */ 301 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 302 clear_bit(__IGB_RESETTING, &adapter->state); 303 return -EINVAL; 304 } 305 } 306 307 /* MDI-X => 2; MDI => 1; Auto => 3 */ 308 if (ecmd->eth_tp_mdix_ctrl) { 309 /* fix up the value for auto (3 => 0) as zero is mapped 310 * internally to auto 311 */ 312 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 313 hw->phy.mdix = AUTO_ALL_MODES; 314 else 315 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl; 316 } 317 318 /* reset the link */ 319 if (netif_running(adapter->netdev)) { 320 igb_down(adapter); 321 igb_up(adapter); 322 } else 323 igb_reset(adapter); 324 325 clear_bit(__IGB_RESETTING, &adapter->state); 326 return 0; 327} 328 329static u32 igb_get_link(struct net_device *netdev) 330{ 331 struct igb_adapter *adapter = netdev_priv(netdev); 332 struct e1000_mac_info *mac = &adapter->hw.mac; 333 334 /* If the link is not reported up to netdev, interrupts are disabled, 335 * and so the physical link state may have changed since we last 336 * looked. Set get_link_status to make sure that the true link 337 * state is interrogated, rather than pulling a cached and possibly 338 * stale link state from the driver. 339 */ 340 if (!netif_carrier_ok(netdev)) 341 mac->get_link_status = 1; 342 343 return igb_has_link(adapter); 344} 345 346static void igb_get_pauseparam(struct net_device *netdev, 347 struct ethtool_pauseparam *pause) 348{ 349 struct igb_adapter *adapter = netdev_priv(netdev); 350 struct e1000_hw *hw = &adapter->hw; 351 352 pause->autoneg = 353 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 354 355 if (hw->fc.current_mode == e1000_fc_rx_pause) 356 pause->rx_pause = 1; 357 else if (hw->fc.current_mode == e1000_fc_tx_pause) 358 pause->tx_pause = 1; 359 else if (hw->fc.current_mode == e1000_fc_full) { 360 pause->rx_pause = 1; 361 pause->tx_pause = 1; 362 } 363} 364 365static int igb_set_pauseparam(struct net_device *netdev, 366 struct ethtool_pauseparam *pause) 367{ 368 struct igb_adapter *adapter = netdev_priv(netdev); 369 struct e1000_hw *hw = &adapter->hw; 370 int retval = 0; 371 372 adapter->fc_autoneg = pause->autoneg; 373 374 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 375 msleep(1); 376 377 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 378 hw->fc.requested_mode = e1000_fc_default; 379 if (netif_running(adapter->netdev)) { 380 igb_down(adapter); 381 igb_up(adapter); 382 } else { 383 igb_reset(adapter); 384 } 385 } else { 386 if (pause->rx_pause && pause->tx_pause) 387 hw->fc.requested_mode = e1000_fc_full; 388 else if (pause->rx_pause && !pause->tx_pause) 389 hw->fc.requested_mode = e1000_fc_rx_pause; 390 else if (!pause->rx_pause && pause->tx_pause) 391 hw->fc.requested_mode = e1000_fc_tx_pause; 392 else if (!pause->rx_pause && !pause->tx_pause) 393 hw->fc.requested_mode = e1000_fc_none; 394 395 hw->fc.current_mode = hw->fc.requested_mode; 396 397 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 398 igb_force_mac_fc(hw) : igb_setup_link(hw)); 399 } 400 401 clear_bit(__IGB_RESETTING, &adapter->state); 402 return retval; 403} 404 405static u32 igb_get_msglevel(struct net_device *netdev) 406{ 407 struct igb_adapter *adapter = netdev_priv(netdev); 408 return adapter->msg_enable; 409} 410 411static void igb_set_msglevel(struct net_device *netdev, u32 data) 412{ 413 struct igb_adapter *adapter = netdev_priv(netdev); 414 adapter->msg_enable = data; 415} 416 417static int igb_get_regs_len(struct net_device *netdev) 418{ 419#define IGB_REGS_LEN 739 420 return IGB_REGS_LEN * sizeof(u32); 421} 422 423static void igb_get_regs(struct net_device *netdev, 424 struct ethtool_regs *regs, void *p) 425{ 426 struct igb_adapter *adapter = netdev_priv(netdev); 427 struct e1000_hw *hw = &adapter->hw; 428 u32 *regs_buff = p; 429 u8 i; 430 431 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 432 433 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 434 435 /* General Registers */ 436 regs_buff[0] = rd32(E1000_CTRL); 437 regs_buff[1] = rd32(E1000_STATUS); 438 regs_buff[2] = rd32(E1000_CTRL_EXT); 439 regs_buff[3] = rd32(E1000_MDIC); 440 regs_buff[4] = rd32(E1000_SCTL); 441 regs_buff[5] = rd32(E1000_CONNSW); 442 regs_buff[6] = rd32(E1000_VET); 443 regs_buff[7] = rd32(E1000_LEDCTL); 444 regs_buff[8] = rd32(E1000_PBA); 445 regs_buff[9] = rd32(E1000_PBS); 446 regs_buff[10] = rd32(E1000_FRTIMER); 447 regs_buff[11] = rd32(E1000_TCPTIMER); 448 449 /* NVM Register */ 450 regs_buff[12] = rd32(E1000_EECD); 451 452 /* Interrupt */ 453 /* Reading EICS for EICR because they read the 454 * same but EICS does not clear on read 455 */ 456 regs_buff[13] = rd32(E1000_EICS); 457 regs_buff[14] = rd32(E1000_EICS); 458 regs_buff[15] = rd32(E1000_EIMS); 459 regs_buff[16] = rd32(E1000_EIMC); 460 regs_buff[17] = rd32(E1000_EIAC); 461 regs_buff[18] = rd32(E1000_EIAM); 462 /* Reading ICS for ICR because they read the 463 * same but ICS does not clear on read 464 */ 465 regs_buff[19] = rd32(E1000_ICS); 466 regs_buff[20] = rd32(E1000_ICS); 467 regs_buff[21] = rd32(E1000_IMS); 468 regs_buff[22] = rd32(E1000_IMC); 469 regs_buff[23] = rd32(E1000_IAC); 470 regs_buff[24] = rd32(E1000_IAM); 471 regs_buff[25] = rd32(E1000_IMIRVP); 472 473 /* Flow Control */ 474 regs_buff[26] = rd32(E1000_FCAL); 475 regs_buff[27] = rd32(E1000_FCAH); 476 regs_buff[28] = rd32(E1000_FCTTV); 477 regs_buff[29] = rd32(E1000_FCRTL); 478 regs_buff[30] = rd32(E1000_FCRTH); 479 regs_buff[31] = rd32(E1000_FCRTV); 480 481 /* Receive */ 482 regs_buff[32] = rd32(E1000_RCTL); 483 regs_buff[33] = rd32(E1000_RXCSUM); 484 regs_buff[34] = rd32(E1000_RLPML); 485 regs_buff[35] = rd32(E1000_RFCTL); 486 regs_buff[36] = rd32(E1000_MRQC); 487 regs_buff[37] = rd32(E1000_VT_CTL); 488 489 /* Transmit */ 490 regs_buff[38] = rd32(E1000_TCTL); 491 regs_buff[39] = rd32(E1000_TCTL_EXT); 492 regs_buff[40] = rd32(E1000_TIPG); 493 regs_buff[41] = rd32(E1000_DTXCTL); 494 495 /* Wake Up */ 496 regs_buff[42] = rd32(E1000_WUC); 497 regs_buff[43] = rd32(E1000_WUFC); 498 regs_buff[44] = rd32(E1000_WUS); 499 regs_buff[45] = rd32(E1000_IPAV); 500 regs_buff[46] = rd32(E1000_WUPL); 501 502 /* MAC */ 503 regs_buff[47] = rd32(E1000_PCS_CFG0); 504 regs_buff[48] = rd32(E1000_PCS_LCTL); 505 regs_buff[49] = rd32(E1000_PCS_LSTAT); 506 regs_buff[50] = rd32(E1000_PCS_ANADV); 507 regs_buff[51] = rd32(E1000_PCS_LPAB); 508 regs_buff[52] = rd32(E1000_PCS_NPTX); 509 regs_buff[53] = rd32(E1000_PCS_LPABNP); 510 511 /* Statistics */ 512 regs_buff[54] = adapter->stats.crcerrs; 513 regs_buff[55] = adapter->stats.algnerrc; 514 regs_buff[56] = adapter->stats.symerrs; 515 regs_buff[57] = adapter->stats.rxerrc; 516 regs_buff[58] = adapter->stats.mpc; 517 regs_buff[59] = adapter->stats.scc; 518 regs_buff[60] = adapter->stats.ecol; 519 regs_buff[61] = adapter->stats.mcc; 520 regs_buff[62] = adapter->stats.latecol; 521 regs_buff[63] = adapter->stats.colc; 522 regs_buff[64] = adapter->stats.dc; 523 regs_buff[65] = adapter->stats.tncrs; 524 regs_buff[66] = adapter->stats.sec; 525 regs_buff[67] = adapter->stats.htdpmc; 526 regs_buff[68] = adapter->stats.rlec; 527 regs_buff[69] = adapter->stats.xonrxc; 528 regs_buff[70] = adapter->stats.xontxc; 529 regs_buff[71] = adapter->stats.xoffrxc; 530 regs_buff[72] = adapter->stats.xofftxc; 531 regs_buff[73] = adapter->stats.fcruc; 532 regs_buff[74] = adapter->stats.prc64; 533 regs_buff[75] = adapter->stats.prc127; 534 regs_buff[76] = adapter->stats.prc255; 535 regs_buff[77] = adapter->stats.prc511; 536 regs_buff[78] = adapter->stats.prc1023; 537 regs_buff[79] = adapter->stats.prc1522; 538 regs_buff[80] = adapter->stats.gprc; 539 regs_buff[81] = adapter->stats.bprc; 540 regs_buff[82] = adapter->stats.mprc; 541 regs_buff[83] = adapter->stats.gptc; 542 regs_buff[84] = adapter->stats.gorc; 543 regs_buff[86] = adapter->stats.gotc; 544 regs_buff[88] = adapter->stats.rnbc; 545 regs_buff[89] = adapter->stats.ruc; 546 regs_buff[90] = adapter->stats.rfc; 547 regs_buff[91] = adapter->stats.roc; 548 regs_buff[92] = adapter->stats.rjc; 549 regs_buff[93] = adapter->stats.mgprc; 550 regs_buff[94] = adapter->stats.mgpdc; 551 regs_buff[95] = adapter->stats.mgptc; 552 regs_buff[96] = adapter->stats.tor; 553 regs_buff[98] = adapter->stats.tot; 554 regs_buff[100] = adapter->stats.tpr; 555 regs_buff[101] = adapter->stats.tpt; 556 regs_buff[102] = adapter->stats.ptc64; 557 regs_buff[103] = adapter->stats.ptc127; 558 regs_buff[104] = adapter->stats.ptc255; 559 regs_buff[105] = adapter->stats.ptc511; 560 regs_buff[106] = adapter->stats.ptc1023; 561 regs_buff[107] = adapter->stats.ptc1522; 562 regs_buff[108] = adapter->stats.mptc; 563 regs_buff[109] = adapter->stats.bptc; 564 regs_buff[110] = adapter->stats.tsctc; 565 regs_buff[111] = adapter->stats.iac; 566 regs_buff[112] = adapter->stats.rpthc; 567 regs_buff[113] = adapter->stats.hgptc; 568 regs_buff[114] = adapter->stats.hgorc; 569 regs_buff[116] = adapter->stats.hgotc; 570 regs_buff[118] = adapter->stats.lenerrs; 571 regs_buff[119] = adapter->stats.scvpc; 572 regs_buff[120] = adapter->stats.hrmpc; 573 574 for (i = 0; i < 4; i++) 575 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 576 for (i = 0; i < 4; i++) 577 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 578 for (i = 0; i < 4; i++) 579 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 580 for (i = 0; i < 4; i++) 581 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 582 for (i = 0; i < 4; i++) 583 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 584 for (i = 0; i < 4; i++) 585 regs_buff[141 + i] = rd32(E1000_RDH(i)); 586 for (i = 0; i < 4; i++) 587 regs_buff[145 + i] = rd32(E1000_RDT(i)); 588 for (i = 0; i < 4; i++) 589 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 590 591 for (i = 0; i < 10; i++) 592 regs_buff[153 + i] = rd32(E1000_EITR(i)); 593 for (i = 0; i < 8; i++) 594 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 595 for (i = 0; i < 8; i++) 596 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 597 for (i = 0; i < 16; i++) 598 regs_buff[179 + i] = rd32(E1000_RAL(i)); 599 for (i = 0; i < 16; i++) 600 regs_buff[195 + i] = rd32(E1000_RAH(i)); 601 602 for (i = 0; i < 4; i++) 603 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 604 for (i = 0; i < 4; i++) 605 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 606 for (i = 0; i < 4; i++) 607 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 608 for (i = 0; i < 4; i++) 609 regs_buff[223 + i] = rd32(E1000_TDH(i)); 610 for (i = 0; i < 4; i++) 611 regs_buff[227 + i] = rd32(E1000_TDT(i)); 612 for (i = 0; i < 4; i++) 613 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 614 for (i = 0; i < 4; i++) 615 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 616 for (i = 0; i < 4; i++) 617 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 618 for (i = 0; i < 4; i++) 619 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 620 621 for (i = 0; i < 4; i++) 622 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 623 for (i = 0; i < 4; i++) 624 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 625 for (i = 0; i < 32; i++) 626 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 627 for (i = 0; i < 128; i++) 628 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 629 for (i = 0; i < 128; i++) 630 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 631 for (i = 0; i < 4; i++) 632 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 633 634 regs_buff[547] = rd32(E1000_TDFH); 635 regs_buff[548] = rd32(E1000_TDFT); 636 regs_buff[549] = rd32(E1000_TDFHS); 637 regs_buff[550] = rd32(E1000_TDFPC); 638 639 if (hw->mac.type > e1000_82580) { 640 regs_buff[551] = adapter->stats.o2bgptc; 641 regs_buff[552] = adapter->stats.b2ospc; 642 regs_buff[553] = adapter->stats.o2bspc; 643 regs_buff[554] = adapter->stats.b2ogprc; 644 } 645 646 if (hw->mac.type != e1000_82576) 647 return; 648 for (i = 0; i < 12; i++) 649 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 650 for (i = 0; i < 4; i++) 651 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 652 for (i = 0; i < 12; i++) 653 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 654 for (i = 0; i < 12; i++) 655 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 656 for (i = 0; i < 12; i++) 657 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 658 for (i = 0; i < 12; i++) 659 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 660 for (i = 0; i < 12; i++) 661 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 662 for (i = 0; i < 12; i++) 663 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 664 665 for (i = 0; i < 12; i++) 666 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 667 for (i = 0; i < 12; i++) 668 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 669 for (i = 0; i < 12; i++) 670 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 671 for (i = 0; i < 12; i++) 672 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 673 for (i = 0; i < 12; i++) 674 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 675 for (i = 0; i < 12; i++) 676 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 677 for (i = 0; i < 12; i++) 678 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 679 for (i = 0; i < 12; i++) 680 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 681} 682 683static int igb_get_eeprom_len(struct net_device *netdev) 684{ 685 struct igb_adapter *adapter = netdev_priv(netdev); 686 return adapter->hw.nvm.word_size * 2; 687} 688 689static int igb_get_eeprom(struct net_device *netdev, 690 struct ethtool_eeprom *eeprom, u8 *bytes) 691{ 692 struct igb_adapter *adapter = netdev_priv(netdev); 693 struct e1000_hw *hw = &adapter->hw; 694 u16 *eeprom_buff; 695 int first_word, last_word; 696 int ret_val = 0; 697 u16 i; 698 699 if (eeprom->len == 0) 700 return -EINVAL; 701 702 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 703 704 first_word = eeprom->offset >> 1; 705 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 706 707 eeprom_buff = kmalloc(sizeof(u16) * 708 (last_word - first_word + 1), GFP_KERNEL); 709 if (!eeprom_buff) 710 return -ENOMEM; 711 712 if (hw->nvm.type == e1000_nvm_eeprom_spi) 713 ret_val = hw->nvm.ops.read(hw, first_word, 714 last_word - first_word + 1, 715 eeprom_buff); 716 else { 717 for (i = 0; i < last_word - first_word + 1; i++) { 718 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 719 &eeprom_buff[i]); 720 if (ret_val) 721 break; 722 } 723 } 724 725 /* Device's eeprom is always little-endian, word addressable */ 726 for (i = 0; i < last_word - first_word + 1; i++) 727 le16_to_cpus(&eeprom_buff[i]); 728 729 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 730 eeprom->len); 731 kfree(eeprom_buff); 732 733 return ret_val; 734} 735 736static int igb_set_eeprom(struct net_device *netdev, 737 struct ethtool_eeprom *eeprom, u8 *bytes) 738{ 739 struct igb_adapter *adapter = netdev_priv(netdev); 740 struct e1000_hw *hw = &adapter->hw; 741 u16 *eeprom_buff; 742 void *ptr; 743 int max_len, first_word, last_word, ret_val = 0; 744 u16 i; 745 746 if (eeprom->len == 0) 747 return -EOPNOTSUPP; 748 749 if (hw->mac.type == e1000_i211) 750 return -EOPNOTSUPP; 751 752 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 753 return -EFAULT; 754 755 max_len = hw->nvm.word_size * 2; 756 757 first_word = eeprom->offset >> 1; 758 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 759 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 760 if (!eeprom_buff) 761 return -ENOMEM; 762 763 ptr = (void *)eeprom_buff; 764 765 if (eeprom->offset & 1) { 766 /* need read/modify/write of first changed EEPROM word 767 * only the second byte of the word is being modified 768 */ 769 ret_val = hw->nvm.ops.read(hw, first_word, 1, 770 &eeprom_buff[0]); 771 ptr++; 772 } 773 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 774 /* need read/modify/write of last changed EEPROM word 775 * only the first byte of the word is being modified 776 */ 777 ret_val = hw->nvm.ops.read(hw, last_word, 1, 778 &eeprom_buff[last_word - first_word]); 779 } 780 781 /* Device's eeprom is always little-endian, word addressable */ 782 for (i = 0; i < last_word - first_word + 1; i++) 783 le16_to_cpus(&eeprom_buff[i]); 784 785 memcpy(ptr, bytes, eeprom->len); 786 787 for (i = 0; i < last_word - first_word + 1; i++) 788 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 789 790 ret_val = hw->nvm.ops.write(hw, first_word, 791 last_word - first_word + 1, eeprom_buff); 792 793 /* Update the checksum over the first part of the EEPROM if needed 794 * and flush shadow RAM for 82573 controllers 795 */ 796 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) 797 hw->nvm.ops.update(hw); 798 799 igb_set_fw_version(adapter); 800 kfree(eeprom_buff); 801 return ret_val; 802} 803 804static void igb_get_drvinfo(struct net_device *netdev, 805 struct ethtool_drvinfo *drvinfo) 806{ 807 struct igb_adapter *adapter = netdev_priv(netdev); 808 809 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 810 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 811 812 /* EEPROM image version # is reported as firmware version # for 813 * 82575 controllers 814 */ 815 strlcpy(drvinfo->fw_version, adapter->fw_version, 816 sizeof(drvinfo->fw_version)); 817 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 818 sizeof(drvinfo->bus_info)); 819 drvinfo->n_stats = IGB_STATS_LEN; 820 drvinfo->testinfo_len = IGB_TEST_LEN; 821 drvinfo->regdump_len = igb_get_regs_len(netdev); 822 drvinfo->eedump_len = igb_get_eeprom_len(netdev); 823} 824 825static void igb_get_ringparam(struct net_device *netdev, 826 struct ethtool_ringparam *ring) 827{ 828 struct igb_adapter *adapter = netdev_priv(netdev); 829 830 ring->rx_max_pending = IGB_MAX_RXD; 831 ring->tx_max_pending = IGB_MAX_TXD; 832 ring->rx_pending = adapter->rx_ring_count; 833 ring->tx_pending = adapter->tx_ring_count; 834} 835 836static int igb_set_ringparam(struct net_device *netdev, 837 struct ethtool_ringparam *ring) 838{ 839 struct igb_adapter *adapter = netdev_priv(netdev); 840 struct igb_ring *temp_ring; 841 int i, err = 0; 842 u16 new_rx_count, new_tx_count; 843 844 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 845 return -EINVAL; 846 847 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 848 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 849 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 850 851 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 852 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 853 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 854 855 if ((new_tx_count == adapter->tx_ring_count) && 856 (new_rx_count == adapter->rx_ring_count)) { 857 /* nothing to do */ 858 return 0; 859 } 860 861 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 862 msleep(1); 863 864 if (!netif_running(adapter->netdev)) { 865 for (i = 0; i < adapter->num_tx_queues; i++) 866 adapter->tx_ring[i]->count = new_tx_count; 867 for (i = 0; i < adapter->num_rx_queues; i++) 868 adapter->rx_ring[i]->count = new_rx_count; 869 adapter->tx_ring_count = new_tx_count; 870 adapter->rx_ring_count = new_rx_count; 871 goto clear_reset; 872 } 873 874 if (adapter->num_tx_queues > adapter->num_rx_queues) 875 temp_ring = vmalloc(adapter->num_tx_queues * 876 sizeof(struct igb_ring)); 877 else 878 temp_ring = vmalloc(adapter->num_rx_queues * 879 sizeof(struct igb_ring)); 880 881 if (!temp_ring) { 882 err = -ENOMEM; 883 goto clear_reset; 884 } 885 886 igb_down(adapter); 887 888 /* We can't just free everything and then setup again, 889 * because the ISRs in MSI-X mode get passed pointers 890 * to the Tx and Rx ring structs. 891 */ 892 if (new_tx_count != adapter->tx_ring_count) { 893 for (i = 0; i < adapter->num_tx_queues; i++) { 894 memcpy(&temp_ring[i], adapter->tx_ring[i], 895 sizeof(struct igb_ring)); 896 897 temp_ring[i].count = new_tx_count; 898 err = igb_setup_tx_resources(&temp_ring[i]); 899 if (err) { 900 while (i) { 901 i--; 902 igb_free_tx_resources(&temp_ring[i]); 903 } 904 goto err_setup; 905 } 906 } 907 908 for (i = 0; i < adapter->num_tx_queues; i++) { 909 igb_free_tx_resources(adapter->tx_ring[i]); 910 911 memcpy(adapter->tx_ring[i], &temp_ring[i], 912 sizeof(struct igb_ring)); 913 } 914 915 adapter->tx_ring_count = new_tx_count; 916 } 917 918 if (new_rx_count != adapter->rx_ring_count) { 919 for (i = 0; i < adapter->num_rx_queues; i++) { 920 memcpy(&temp_ring[i], adapter->rx_ring[i], 921 sizeof(struct igb_ring)); 922 923 temp_ring[i].count = new_rx_count; 924 err = igb_setup_rx_resources(&temp_ring[i]); 925 if (err) { 926 while (i) { 927 i--; 928 igb_free_rx_resources(&temp_ring[i]); 929 } 930 goto err_setup; 931 } 932 933 } 934 935 for (i = 0; i < adapter->num_rx_queues; i++) { 936 igb_free_rx_resources(adapter->rx_ring[i]); 937 938 memcpy(adapter->rx_ring[i], &temp_ring[i], 939 sizeof(struct igb_ring)); 940 } 941 942 adapter->rx_ring_count = new_rx_count; 943 } 944err_setup: 945 igb_up(adapter); 946 vfree(temp_ring); 947clear_reset: 948 clear_bit(__IGB_RESETTING, &adapter->state); 949 return err; 950} 951 952/* ethtool register test data */ 953struct igb_reg_test { 954 u16 reg; 955 u16 reg_offset; 956 u16 array_len; 957 u16 test_type; 958 u32 mask; 959 u32 write; 960}; 961 962/* In the hardware, registers are laid out either singly, in arrays 963 * spaced 0x100 bytes apart, or in contiguous tables. We assume 964 * most tests take place on arrays or single registers (handled 965 * as a single-element array) and special-case the tables. 966 * Table tests are always pattern tests. 967 * 968 * We also make provision for some required setup steps by specifying 969 * registers to be written without any read-back testing. 970 */ 971 972#define PATTERN_TEST 1 973#define SET_READ_TEST 2 974#define WRITE_NO_TEST 3 975#define TABLE32_TEST 4 976#define TABLE64_TEST_LO 5 977#define TABLE64_TEST_HI 6 978 979/* i210 reg test */ 980static struct igb_reg_test reg_test_i210[] = { 981 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 982 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 983 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 984 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 985 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 986 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 987 /* RDH is read-only for i210, only test RDT. */ 988 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 989 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 990 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 991 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 992 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 993 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 994 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 995 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 996 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 997 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 998 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 999 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1000 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1001 0xFFFFFFFF, 0xFFFFFFFF }, 1002 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1003 0x900FFFFF, 0xFFFFFFFF }, 1004 { E1000_MTA, 0, 128, TABLE32_TEST, 1005 0xFFFFFFFF, 0xFFFFFFFF }, 1006 { 0, 0, 0, 0, 0 } 1007}; 1008 1009/* i350 reg test */ 1010static struct igb_reg_test reg_test_i350[] = { 1011 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1012 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1013 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1014 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 1015 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1016 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1017 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1018 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1019 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1020 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1021 /* RDH is read-only for i350, only test RDT. */ 1022 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1023 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1024 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1025 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1026 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1027 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1028 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1029 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1030 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1031 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1032 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1033 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1034 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1035 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1036 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1037 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1038 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1039 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1040 0xFFFFFFFF, 0xFFFFFFFF }, 1041 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1042 0xC3FFFFFF, 0xFFFFFFFF }, 1043 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1044 0xFFFFFFFF, 0xFFFFFFFF }, 1045 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1046 0xC3FFFFFF, 0xFFFFFFFF }, 1047 { E1000_MTA, 0, 128, TABLE32_TEST, 1048 0xFFFFFFFF, 0xFFFFFFFF }, 1049 { 0, 0, 0, 0 } 1050}; 1051 1052/* 82580 reg test */ 1053static struct igb_reg_test reg_test_82580[] = { 1054 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1055 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1056 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1057 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1058 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1059 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1060 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1061 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1062 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1063 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1064 /* RDH is read-only for 82580, only test RDT. */ 1065 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1066 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1067 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1068 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1069 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1070 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1071 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1072 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1073 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1074 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1075 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1076 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1077 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1078 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1079 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1080 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1081 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1082 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1083 0xFFFFFFFF, 0xFFFFFFFF }, 1084 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1085 0x83FFFFFF, 0xFFFFFFFF }, 1086 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1087 0xFFFFFFFF, 0xFFFFFFFF }, 1088 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1089 0x83FFFFFF, 0xFFFFFFFF }, 1090 { E1000_MTA, 0, 128, TABLE32_TEST, 1091 0xFFFFFFFF, 0xFFFFFFFF }, 1092 { 0, 0, 0, 0 } 1093}; 1094 1095/* 82576 reg test */ 1096static struct igb_reg_test reg_test_82576[] = { 1097 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1098 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1099 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1100 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1101 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1102 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1103 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1104 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1105 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1106 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1107 /* Enable all RX queues before testing. */ 1108 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1109 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1110 /* RDH is read-only for 82576, only test RDT. */ 1111 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1112 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1113 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1114 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1115 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1116 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1117 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1118 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1119 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1120 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1121 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1122 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1123 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1124 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1125 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1126 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1127 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1128 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1129 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1130 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1131 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1132 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1133 { 0, 0, 0, 0 } 1134}; 1135 1136/* 82575 register test */ 1137static struct igb_reg_test reg_test_82575[] = { 1138 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1139 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1140 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1141 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1142 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1143 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1144 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1145 /* Enable all four RX queues before testing. */ 1146 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1147 /* RDH is read-only for 82575, only test RDT. */ 1148 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1149 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1150 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1151 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1152 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1153 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1154 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1155 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1156 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1157 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1158 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1159 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1160 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1161 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1162 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1163 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1164 { 0, 0, 0, 0 } 1165}; 1166 1167static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1168 int reg, u32 mask, u32 write) 1169{ 1170 struct e1000_hw *hw = &adapter->hw; 1171 u32 pat, val; 1172 static const u32 _test[] = 1173 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1174 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1175 wr32(reg, (_test[pat] & write)); 1176 val = rd32(reg) & mask; 1177 if (val != (_test[pat] & write & mask)) { 1178 dev_err(&adapter->pdev->dev, 1179 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1180 reg, val, (_test[pat] & write & mask)); 1181 *data = reg; 1182 return 1; 1183 } 1184 } 1185 1186 return 0; 1187} 1188 1189static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1190 int reg, u32 mask, u32 write) 1191{ 1192 struct e1000_hw *hw = &adapter->hw; 1193 u32 val; 1194 wr32(reg, write & mask); 1195 val = rd32(reg); 1196 if ((write & mask) != (val & mask)) { 1197 dev_err(&adapter->pdev->dev, 1198 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg, 1199 (val & mask), (write & mask)); 1200 *data = reg; 1201 return 1; 1202 } 1203 1204 return 0; 1205} 1206 1207#define REG_PATTERN_TEST(reg, mask, write) \ 1208 do { \ 1209 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1210 return 1; \ 1211 } while (0) 1212 1213#define REG_SET_AND_CHECK(reg, mask, write) \ 1214 do { \ 1215 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1216 return 1; \ 1217 } while (0) 1218 1219static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1220{ 1221 struct e1000_hw *hw = &adapter->hw; 1222 struct igb_reg_test *test; 1223 u32 value, before, after; 1224 u32 i, toggle; 1225 1226 switch (adapter->hw.mac.type) { 1227 case e1000_i350: 1228 test = reg_test_i350; 1229 toggle = 0x7FEFF3FF; 1230 break; 1231 case e1000_i210: 1232 case e1000_i211: 1233 test = reg_test_i210; 1234 toggle = 0x7FEFF3FF; 1235 break; 1236 case e1000_82580: 1237 test = reg_test_82580; 1238 toggle = 0x7FEFF3FF; 1239 break; 1240 case e1000_82576: 1241 test = reg_test_82576; 1242 toggle = 0x7FFFF3FF; 1243 break; 1244 default: 1245 test = reg_test_82575; 1246 toggle = 0x7FFFF3FF; 1247 break; 1248 } 1249 1250 /* Because the status register is such a special case, 1251 * we handle it separately from the rest of the register 1252 * tests. Some bits are read-only, some toggle, and some 1253 * are writable on newer MACs. 1254 */ 1255 before = rd32(E1000_STATUS); 1256 value = (rd32(E1000_STATUS) & toggle); 1257 wr32(E1000_STATUS, toggle); 1258 after = rd32(E1000_STATUS) & toggle; 1259 if (value != after) { 1260 dev_err(&adapter->pdev->dev, 1261 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1262 after, value); 1263 *data = 1; 1264 return 1; 1265 } 1266 /* restore previous status */ 1267 wr32(E1000_STATUS, before); 1268 1269 /* Perform the remainder of the register test, looping through 1270 * the test table until we either fail or reach the null entry. 1271 */ 1272 while (test->reg) { 1273 for (i = 0; i < test->array_len; i++) { 1274 switch (test->test_type) { 1275 case PATTERN_TEST: 1276 REG_PATTERN_TEST(test->reg + 1277 (i * test->reg_offset), 1278 test->mask, 1279 test->write); 1280 break; 1281 case SET_READ_TEST: 1282 REG_SET_AND_CHECK(test->reg + 1283 (i * test->reg_offset), 1284 test->mask, 1285 test->write); 1286 break; 1287 case WRITE_NO_TEST: 1288 writel(test->write, 1289 (adapter->hw.hw_addr + test->reg) 1290 + (i * test->reg_offset)); 1291 break; 1292 case TABLE32_TEST: 1293 REG_PATTERN_TEST(test->reg + (i * 4), 1294 test->mask, 1295 test->write); 1296 break; 1297 case TABLE64_TEST_LO: 1298 REG_PATTERN_TEST(test->reg + (i * 8), 1299 test->mask, 1300 test->write); 1301 break; 1302 case TABLE64_TEST_HI: 1303 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1304 test->mask, 1305 test->write); 1306 break; 1307 } 1308 } 1309 test++; 1310 } 1311 1312 *data = 0; 1313 return 0; 1314} 1315 1316static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1317{ 1318 *data = 0; 1319 1320 /* Validate eeprom on all parts but i211 */ 1321 if (adapter->hw.mac.type != e1000_i211) { 1322 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1323 *data = 2; 1324 } 1325 1326 return *data; 1327} 1328 1329static irqreturn_t igb_test_intr(int irq, void *data) 1330{ 1331 struct igb_adapter *adapter = (struct igb_adapter *) data; 1332 struct e1000_hw *hw = &adapter->hw; 1333 1334 adapter->test_icr |= rd32(E1000_ICR); 1335 1336 return IRQ_HANDLED; 1337} 1338 1339static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1340{ 1341 struct e1000_hw *hw = &adapter->hw; 1342 struct net_device *netdev = adapter->netdev; 1343 u32 mask, ics_mask, i = 0, shared_int = true; 1344 u32 irq = adapter->pdev->irq; 1345 1346 *data = 0; 1347 1348 /* Hook up test interrupt handler just for this test */ 1349 if (adapter->msix_entries) { 1350 if (request_irq(adapter->msix_entries[0].vector, 1351 igb_test_intr, 0, netdev->name, adapter)) { 1352 *data = 1; 1353 return -1; 1354 } 1355 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1356 shared_int = false; 1357 if (request_irq(irq, 1358 igb_test_intr, 0, netdev->name, adapter)) { 1359 *data = 1; 1360 return -1; 1361 } 1362 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1363 netdev->name, adapter)) { 1364 shared_int = false; 1365 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1366 netdev->name, adapter)) { 1367 *data = 1; 1368 return -1; 1369 } 1370 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1371 (shared_int ? "shared" : "unshared")); 1372 1373 /* Disable all the interrupts */ 1374 wr32(E1000_IMC, ~0); 1375 wrfl(); 1376 msleep(10); 1377 1378 /* Define all writable bits for ICS */ 1379 switch (hw->mac.type) { 1380 case e1000_82575: 1381 ics_mask = 0x37F47EDD; 1382 break; 1383 case e1000_82576: 1384 ics_mask = 0x77D4FBFD; 1385 break; 1386 case e1000_82580: 1387 ics_mask = 0x77DCFED5; 1388 break; 1389 case e1000_i350: 1390 case e1000_i210: 1391 case e1000_i211: 1392 ics_mask = 0x77DCFED5; 1393 break; 1394 default: 1395 ics_mask = 0x7FFFFFFF; 1396 break; 1397 } 1398 1399 /* Test each interrupt */ 1400 for (; i < 31; i++) { 1401 /* Interrupt to test */ 1402 mask = 1 << i; 1403 1404 if (!(mask & ics_mask)) 1405 continue; 1406 1407 if (!shared_int) { 1408 /* Disable the interrupt to be reported in 1409 * the cause register and then force the same 1410 * interrupt and see if one gets posted. If 1411 * an interrupt was posted to the bus, the 1412 * test failed. 1413 */ 1414 adapter->test_icr = 0; 1415 1416 /* Flush any pending interrupts */ 1417 wr32(E1000_ICR, ~0); 1418 1419 wr32(E1000_IMC, mask); 1420 wr32(E1000_ICS, mask); 1421 wrfl(); 1422 msleep(10); 1423 1424 if (adapter->test_icr & mask) { 1425 *data = 3; 1426 break; 1427 } 1428 } 1429 1430 /* Enable the interrupt to be reported in 1431 * the cause register and then force the same 1432 * interrupt and see if one gets posted. If 1433 * an interrupt was not posted to the bus, the 1434 * test failed. 1435 */ 1436 adapter->test_icr = 0; 1437 1438 /* Flush any pending interrupts */ 1439 wr32(E1000_ICR, ~0); 1440 1441 wr32(E1000_IMS, mask); 1442 wr32(E1000_ICS, mask); 1443 wrfl(); 1444 msleep(10); 1445 1446 if (!(adapter->test_icr & mask)) { 1447 *data = 4; 1448 break; 1449 } 1450 1451 if (!shared_int) { 1452 /* Disable the other interrupts to be reported in 1453 * the cause register and then force the other 1454 * interrupts and see if any get posted. If 1455 * an interrupt was posted to the bus, the 1456 * test failed. 1457 */ 1458 adapter->test_icr = 0; 1459 1460 /* Flush any pending interrupts */ 1461 wr32(E1000_ICR, ~0); 1462 1463 wr32(E1000_IMC, ~mask); 1464 wr32(E1000_ICS, ~mask); 1465 wrfl(); 1466 msleep(10); 1467 1468 if (adapter->test_icr & mask) { 1469 *data = 5; 1470 break; 1471 } 1472 } 1473 } 1474 1475 /* Disable all the interrupts */ 1476 wr32(E1000_IMC, ~0); 1477 wrfl(); 1478 msleep(10); 1479 1480 /* Unhook test interrupt handler */ 1481 if (adapter->msix_entries) 1482 free_irq(adapter->msix_entries[0].vector, adapter); 1483 else 1484 free_irq(irq, adapter); 1485 1486 return *data; 1487} 1488 1489static void igb_free_desc_rings(struct igb_adapter *adapter) 1490{ 1491 igb_free_tx_resources(&adapter->test_tx_ring); 1492 igb_free_rx_resources(&adapter->test_rx_ring); 1493} 1494 1495static int igb_setup_desc_rings(struct igb_adapter *adapter) 1496{ 1497 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1498 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1499 struct e1000_hw *hw = &adapter->hw; 1500 int ret_val; 1501 1502 /* Setup Tx descriptor ring and Tx buffers */ 1503 tx_ring->count = IGB_DEFAULT_TXD; 1504 tx_ring->dev = &adapter->pdev->dev; 1505 tx_ring->netdev = adapter->netdev; 1506 tx_ring->reg_idx = adapter->vfs_allocated_count; 1507 1508 if (igb_setup_tx_resources(tx_ring)) { 1509 ret_val = 1; 1510 goto err_nomem; 1511 } 1512 1513 igb_setup_tctl(adapter); 1514 igb_configure_tx_ring(adapter, tx_ring); 1515 1516 /* Setup Rx descriptor ring and Rx buffers */ 1517 rx_ring->count = IGB_DEFAULT_RXD; 1518 rx_ring->dev = &adapter->pdev->dev; 1519 rx_ring->netdev = adapter->netdev; 1520 rx_ring->reg_idx = adapter->vfs_allocated_count; 1521 1522 if (igb_setup_rx_resources(rx_ring)) { 1523 ret_val = 3; 1524 goto err_nomem; 1525 } 1526 1527 /* set the default queue to queue 0 of PF */ 1528 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1529 1530 /* enable receive ring */ 1531 igb_setup_rctl(adapter); 1532 igb_configure_rx_ring(adapter, rx_ring); 1533 1534 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1535 1536 return 0; 1537 1538err_nomem: 1539 igb_free_desc_rings(adapter); 1540 return ret_val; 1541} 1542 1543static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1544{ 1545 struct e1000_hw *hw = &adapter->hw; 1546 1547 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1548 igb_write_phy_reg(hw, 29, 0x001F); 1549 igb_write_phy_reg(hw, 30, 0x8FFC); 1550 igb_write_phy_reg(hw, 29, 0x001A); 1551 igb_write_phy_reg(hw, 30, 0x8FF0); 1552} 1553 1554static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1555{ 1556 struct e1000_hw *hw = &adapter->hw; 1557 u32 ctrl_reg = 0; 1558 1559 hw->mac.autoneg = false; 1560 1561 if (hw->phy.type == e1000_phy_m88) { 1562 if (hw->phy.id != I210_I_PHY_ID) { 1563 /* Auto-MDI/MDIX Off */ 1564 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1565 /* reset to update Auto-MDI/MDIX */ 1566 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1567 /* autoneg off */ 1568 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1569 } else { 1570 /* force 1000, set loopback */ 1571 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1572 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1573 } 1574 } 1575 1576 /* add small delay to avoid loopback test failure */ 1577 msleep(50); 1578 1579 /* force 1000, set loopback */ 1580 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1581 1582 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1583 ctrl_reg = rd32(E1000_CTRL); 1584 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1585 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1586 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1587 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1588 E1000_CTRL_FD | /* Force Duplex to FULL */ 1589 E1000_CTRL_SLU); /* Set link up enable bit */ 1590 1591 if (hw->phy.type == e1000_phy_m88) 1592 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1593 1594 wr32(E1000_CTRL, ctrl_reg); 1595 1596 /* Disable the receiver on the PHY so when a cable is plugged in, the 1597 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1598 */ 1599 if (hw->phy.type == e1000_phy_m88) 1600 igb_phy_disable_receiver(adapter); 1601 1602 mdelay(500); 1603 return 0; 1604} 1605 1606static int igb_set_phy_loopback(struct igb_adapter *adapter) 1607{ 1608 return igb_integrated_phy_loopback(adapter); 1609} 1610 1611static int igb_setup_loopback_test(struct igb_adapter *adapter) 1612{ 1613 struct e1000_hw *hw = &adapter->hw; 1614 u32 reg; 1615 1616 reg = rd32(E1000_CTRL_EXT); 1617 1618 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1619 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1620 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1621 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1622 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1623 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1624 1625 /* Enable DH89xxCC MPHY for near end loopback */ 1626 reg = rd32(E1000_MPHY_ADDR_CTL); 1627 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1628 E1000_MPHY_PCS_CLK_REG_OFFSET; 1629 wr32(E1000_MPHY_ADDR_CTL, reg); 1630 1631 reg = rd32(E1000_MPHY_DATA); 1632 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1633 wr32(E1000_MPHY_DATA, reg); 1634 } 1635 1636 reg = rd32(E1000_RCTL); 1637 reg |= E1000_RCTL_LBM_TCVR; 1638 wr32(E1000_RCTL, reg); 1639 1640 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1641 1642 reg = rd32(E1000_CTRL); 1643 reg &= ~(E1000_CTRL_RFCE | 1644 E1000_CTRL_TFCE | 1645 E1000_CTRL_LRST); 1646 reg |= E1000_CTRL_SLU | 1647 E1000_CTRL_FD; 1648 wr32(E1000_CTRL, reg); 1649 1650 /* Unset switch control to serdes energy detect */ 1651 reg = rd32(E1000_CONNSW); 1652 reg &= ~E1000_CONNSW_ENRGSRC; 1653 wr32(E1000_CONNSW, reg); 1654 1655 /* Unset sigdetect for SERDES loopback on 1656 * 82580 and i350 devices. 1657 */ 1658 switch (hw->mac.type) { 1659 case e1000_82580: 1660 case e1000_i350: 1661 reg = rd32(E1000_PCS_CFG0); 1662 reg |= E1000_PCS_CFG_IGN_SD; 1663 wr32(E1000_PCS_CFG0, reg); 1664 break; 1665 default: 1666 break; 1667 } 1668 1669 /* Set PCS register for forced speed */ 1670 reg = rd32(E1000_PCS_LCTL); 1671 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1672 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1673 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1674 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1675 E1000_PCS_LCTL_FSD | /* Force Speed */ 1676 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1677 wr32(E1000_PCS_LCTL, reg); 1678 1679 return 0; 1680 } 1681 1682 return igb_set_phy_loopback(adapter); 1683} 1684 1685static void igb_loopback_cleanup(struct igb_adapter *adapter) 1686{ 1687 struct e1000_hw *hw = &adapter->hw; 1688 u32 rctl; 1689 u16 phy_reg; 1690 1691 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1693 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1694 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1695 u32 reg; 1696 1697 /* Disable near end loopback on DH89xxCC */ 1698 reg = rd32(E1000_MPHY_ADDR_CTL); 1699 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1700 E1000_MPHY_PCS_CLK_REG_OFFSET; 1701 wr32(E1000_MPHY_ADDR_CTL, reg); 1702 1703 reg = rd32(E1000_MPHY_DATA); 1704 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1705 wr32(E1000_MPHY_DATA, reg); 1706 } 1707 1708 rctl = rd32(E1000_RCTL); 1709 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1710 wr32(E1000_RCTL, rctl); 1711 1712 hw->mac.autoneg = true; 1713 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1714 if (phy_reg & MII_CR_LOOPBACK) { 1715 phy_reg &= ~MII_CR_LOOPBACK; 1716 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1717 igb_phy_sw_reset(hw); 1718 } 1719} 1720 1721static void igb_create_lbtest_frame(struct sk_buff *skb, 1722 unsigned int frame_size) 1723{ 1724 memset(skb->data, 0xFF, frame_size); 1725 frame_size /= 2; 1726 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1727 memset(&skb->data[frame_size + 10], 0xBE, 1); 1728 memset(&skb->data[frame_size + 12], 0xAF, 1); 1729} 1730 1731static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1732 unsigned int frame_size) 1733{ 1734 unsigned char *data; 1735 bool match = true; 1736 1737 frame_size >>= 1; 1738 1739 data = kmap(rx_buffer->page); 1740 1741 if (data[3] != 0xFF || 1742 data[frame_size + 10] != 0xBE || 1743 data[frame_size + 12] != 0xAF) 1744 match = false; 1745 1746 kunmap(rx_buffer->page); 1747 1748 return match; 1749} 1750 1751static int igb_clean_test_rings(struct igb_ring *rx_ring, 1752 struct igb_ring *tx_ring, 1753 unsigned int size) 1754{ 1755 union e1000_adv_rx_desc *rx_desc; 1756 struct igb_rx_buffer *rx_buffer_info; 1757 struct igb_tx_buffer *tx_buffer_info; 1758 u16 rx_ntc, tx_ntc, count = 0; 1759 1760 /* initialize next to clean and descriptor values */ 1761 rx_ntc = rx_ring->next_to_clean; 1762 tx_ntc = tx_ring->next_to_clean; 1763 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1764 1765 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1766 /* check Rx buffer */ 1767 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1768 1769 /* sync Rx buffer for CPU read */ 1770 dma_sync_single_for_cpu(rx_ring->dev, 1771 rx_buffer_info->dma, 1772 IGB_RX_BUFSZ, 1773 DMA_FROM_DEVICE); 1774 1775 /* verify contents of skb */ 1776 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1777 count++; 1778 1779 /* sync Rx buffer for device write */ 1780 dma_sync_single_for_device(rx_ring->dev, 1781 rx_buffer_info->dma, 1782 IGB_RX_BUFSZ, 1783 DMA_FROM_DEVICE); 1784 1785 /* unmap buffer on Tx side */ 1786 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1787 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1788 1789 /* increment Rx/Tx next to clean counters */ 1790 rx_ntc++; 1791 if (rx_ntc == rx_ring->count) 1792 rx_ntc = 0; 1793 tx_ntc++; 1794 if (tx_ntc == tx_ring->count) 1795 tx_ntc = 0; 1796 1797 /* fetch next descriptor */ 1798 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1799 } 1800 1801 netdev_tx_reset_queue(txring_txq(tx_ring)); 1802 1803 /* re-map buffers to ring, store next to clean values */ 1804 igb_alloc_rx_buffers(rx_ring, count); 1805 rx_ring->next_to_clean = rx_ntc; 1806 tx_ring->next_to_clean = tx_ntc; 1807 1808 return count; 1809} 1810 1811static int igb_run_loopback_test(struct igb_adapter *adapter) 1812{ 1813 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1814 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1815 u16 i, j, lc, good_cnt; 1816 int ret_val = 0; 1817 unsigned int size = IGB_RX_HDR_LEN; 1818 netdev_tx_t tx_ret_val; 1819 struct sk_buff *skb; 1820 1821 /* allocate test skb */ 1822 skb = alloc_skb(size, GFP_KERNEL); 1823 if (!skb) 1824 return 11; 1825 1826 /* place data into test skb */ 1827 igb_create_lbtest_frame(skb, size); 1828 skb_put(skb, size); 1829 1830 /* Calculate the loop count based on the largest descriptor ring 1831 * The idea is to wrap the largest ring a number of times using 64 1832 * send/receive pairs during each loop 1833 */ 1834 1835 if (rx_ring->count <= tx_ring->count) 1836 lc = ((tx_ring->count / 64) * 2) + 1; 1837 else 1838 lc = ((rx_ring->count / 64) * 2) + 1; 1839 1840 for (j = 0; j <= lc; j++) { /* loop count loop */ 1841 /* reset count of good packets */ 1842 good_cnt = 0; 1843 1844 /* place 64 packets on the transmit queue*/ 1845 for (i = 0; i < 64; i++) { 1846 skb_get(skb); 1847 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1848 if (tx_ret_val == NETDEV_TX_OK) 1849 good_cnt++; 1850 } 1851 1852 if (good_cnt != 64) { 1853 ret_val = 12; 1854 break; 1855 } 1856 1857 /* allow 200 milliseconds for packets to go from Tx to Rx */ 1858 msleep(200); 1859 1860 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1861 if (good_cnt != 64) { 1862 ret_val = 13; 1863 break; 1864 } 1865 } /* end loop count loop */ 1866 1867 /* free the original skb */ 1868 kfree_skb(skb); 1869 1870 return ret_val; 1871} 1872 1873static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1874{ 1875 /* PHY loopback cannot be performed if SoL/IDER 1876 * sessions are active 1877 */ 1878 if (igb_check_reset_block(&adapter->hw)) { 1879 dev_err(&adapter->pdev->dev, 1880 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1881 *data = 0; 1882 goto out; 1883 } 1884 *data = igb_setup_desc_rings(adapter); 1885 if (*data) 1886 goto out; 1887 *data = igb_setup_loopback_test(adapter); 1888 if (*data) 1889 goto err_loopback; 1890 *data = igb_run_loopback_test(adapter); 1891 igb_loopback_cleanup(adapter); 1892 1893err_loopback: 1894 igb_free_desc_rings(adapter); 1895out: 1896 return *data; 1897} 1898 1899static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1900{ 1901 struct e1000_hw *hw = &adapter->hw; 1902 *data = 0; 1903 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1904 int i = 0; 1905 hw->mac.serdes_has_link = false; 1906 1907 /* On some blade server designs, link establishment 1908 * could take as long as 2-3 minutes 1909 */ 1910 do { 1911 hw->mac.ops.check_for_link(&adapter->hw); 1912 if (hw->mac.serdes_has_link) 1913 return *data; 1914 msleep(20); 1915 } while (i++ < 3750); 1916 1917 *data = 1; 1918 } else { 1919 hw->mac.ops.check_for_link(&adapter->hw); 1920 if (hw->mac.autoneg) 1921 msleep(5000); 1922 1923 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1924 *data = 1; 1925 } 1926 return *data; 1927} 1928 1929static void igb_diag_test(struct net_device *netdev, 1930 struct ethtool_test *eth_test, u64 *data) 1931{ 1932 struct igb_adapter *adapter = netdev_priv(netdev); 1933 u16 autoneg_advertised; 1934 u8 forced_speed_duplex, autoneg; 1935 bool if_running = netif_running(netdev); 1936 1937 set_bit(__IGB_TESTING, &adapter->state); 1938 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1939 /* Offline tests */ 1940 1941 /* save speed, duplex, autoneg settings */ 1942 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 1943 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 1944 autoneg = adapter->hw.mac.autoneg; 1945 1946 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 1947 1948 /* power up link for link test */ 1949 igb_power_up_link(adapter); 1950 1951 /* Link test performed before hardware reset so autoneg doesn't 1952 * interfere with test result 1953 */ 1954 if (igb_link_test(adapter, &data[4])) 1955 eth_test->flags |= ETH_TEST_FL_FAILED; 1956 1957 if (if_running) 1958 /* indicate we're in test mode */ 1959 dev_close(netdev); 1960 else 1961 igb_reset(adapter); 1962 1963 if (igb_reg_test(adapter, &data[0])) 1964 eth_test->flags |= ETH_TEST_FL_FAILED; 1965 1966 igb_reset(adapter); 1967 if (igb_eeprom_test(adapter, &data[1])) 1968 eth_test->flags |= ETH_TEST_FL_FAILED; 1969 1970 igb_reset(adapter); 1971 if (igb_intr_test(adapter, &data[2])) 1972 eth_test->flags |= ETH_TEST_FL_FAILED; 1973 1974 igb_reset(adapter); 1975 /* power up link for loopback test */ 1976 igb_power_up_link(adapter); 1977 if (igb_loopback_test(adapter, &data[3])) 1978 eth_test->flags |= ETH_TEST_FL_FAILED; 1979 1980 /* restore speed, duplex, autoneg settings */ 1981 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 1982 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 1983 adapter->hw.mac.autoneg = autoneg; 1984 1985 /* force this routine to wait until autoneg complete/timeout */ 1986 adapter->hw.phy.autoneg_wait_to_complete = true; 1987 igb_reset(adapter); 1988 adapter->hw.phy.autoneg_wait_to_complete = false; 1989 1990 clear_bit(__IGB_TESTING, &adapter->state); 1991 if (if_running) 1992 dev_open(netdev); 1993 } else { 1994 dev_info(&adapter->pdev->dev, "online testing starting\n"); 1995 1996 /* PHY is powered down when interface is down */ 1997 if (if_running && igb_link_test(adapter, &data[4])) 1998 eth_test->flags |= ETH_TEST_FL_FAILED; 1999 else 2000 data[4] = 0; 2001 2002 /* Online tests aren't run; pass by default */ 2003 data[0] = 0; 2004 data[1] = 0; 2005 data[2] = 0; 2006 data[3] = 0; 2007 2008 clear_bit(__IGB_TESTING, &adapter->state); 2009 } 2010 msleep_interruptible(4 * 1000); 2011} 2012 2013static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2014{ 2015 struct igb_adapter *adapter = netdev_priv(netdev); 2016 2017 wol->supported = WAKE_UCAST | WAKE_MCAST | 2018 WAKE_BCAST | WAKE_MAGIC | 2019 WAKE_PHY; 2020 wol->wolopts = 0; 2021 2022 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2023 return; 2024 2025 /* apply any specific unsupported masks here */ 2026 switch (adapter->hw.device_id) { 2027 default: 2028 break; 2029 } 2030 2031 if (adapter->wol & E1000_WUFC_EX) 2032 wol->wolopts |= WAKE_UCAST; 2033 if (adapter->wol & E1000_WUFC_MC) 2034 wol->wolopts |= WAKE_MCAST; 2035 if (adapter->wol & E1000_WUFC_BC) 2036 wol->wolopts |= WAKE_BCAST; 2037 if (adapter->wol & E1000_WUFC_MAG) 2038 wol->wolopts |= WAKE_MAGIC; 2039 if (adapter->wol & E1000_WUFC_LNKC) 2040 wol->wolopts |= WAKE_PHY; 2041} 2042 2043static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2044{ 2045 struct igb_adapter *adapter = netdev_priv(netdev); 2046 2047 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2048 return -EOPNOTSUPP; 2049 2050 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2051 return wol->wolopts ? -EOPNOTSUPP : 0; 2052 2053 /* these settings will always override what we currently have */ 2054 adapter->wol = 0; 2055 2056 if (wol->wolopts & WAKE_UCAST) 2057 adapter->wol |= E1000_WUFC_EX; 2058 if (wol->wolopts & WAKE_MCAST) 2059 adapter->wol |= E1000_WUFC_MC; 2060 if (wol->wolopts & WAKE_BCAST) 2061 adapter->wol |= E1000_WUFC_BC; 2062 if (wol->wolopts & WAKE_MAGIC) 2063 adapter->wol |= E1000_WUFC_MAG; 2064 if (wol->wolopts & WAKE_PHY) 2065 adapter->wol |= E1000_WUFC_LNKC; 2066 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2067 2068 return 0; 2069} 2070 2071/* bit defines for adapter->led_status */ 2072#define IGB_LED_ON 0 2073 2074static int igb_set_phys_id(struct net_device *netdev, 2075 enum ethtool_phys_id_state state) 2076{ 2077 struct igb_adapter *adapter = netdev_priv(netdev); 2078 struct e1000_hw *hw = &adapter->hw; 2079 2080 switch (state) { 2081 case ETHTOOL_ID_ACTIVE: 2082 igb_blink_led(hw); 2083 return 2; 2084 case ETHTOOL_ID_ON: 2085 igb_blink_led(hw); 2086 break; 2087 case ETHTOOL_ID_OFF: 2088 igb_led_off(hw); 2089 break; 2090 case ETHTOOL_ID_INACTIVE: 2091 igb_led_off(hw); 2092 clear_bit(IGB_LED_ON, &adapter->led_status); 2093 igb_cleanup_led(hw); 2094 break; 2095 } 2096 2097 return 0; 2098} 2099 2100static int igb_set_coalesce(struct net_device *netdev, 2101 struct ethtool_coalesce *ec) 2102{ 2103 struct igb_adapter *adapter = netdev_priv(netdev); 2104 int i; 2105 2106 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2107 ((ec->rx_coalesce_usecs > 3) && 2108 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2109 (ec->rx_coalesce_usecs == 2)) 2110 return -EINVAL; 2111 2112 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2113 ((ec->tx_coalesce_usecs > 3) && 2114 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2115 (ec->tx_coalesce_usecs == 2)) 2116 return -EINVAL; 2117 2118 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2119 return -EINVAL; 2120 2121 /* If ITR is disabled, disable DMAC */ 2122 if (ec->rx_coalesce_usecs == 0) { 2123 if (adapter->flags & IGB_FLAG_DMAC) 2124 adapter->flags &= ~IGB_FLAG_DMAC; 2125 } 2126 2127 /* convert to rate of irq's per second */ 2128 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2129 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2130 else 2131 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2132 2133 /* convert to rate of irq's per second */ 2134 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2135 adapter->tx_itr_setting = adapter->rx_itr_setting; 2136 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2137 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2138 else 2139 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2140 2141 for (i = 0; i < adapter->num_q_vectors; i++) { 2142 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2143 q_vector->tx.work_limit = adapter->tx_work_limit; 2144 if (q_vector->rx.ring) 2145 q_vector->itr_val = adapter->rx_itr_setting; 2146 else 2147 q_vector->itr_val = adapter->tx_itr_setting; 2148 if (q_vector->itr_val && q_vector->itr_val <= 3) 2149 q_vector->itr_val = IGB_START_ITR; 2150 q_vector->set_itr = 1; 2151 } 2152 2153 return 0; 2154} 2155 2156static int igb_get_coalesce(struct net_device *netdev, 2157 struct ethtool_coalesce *ec) 2158{ 2159 struct igb_adapter *adapter = netdev_priv(netdev); 2160 2161 if (adapter->rx_itr_setting <= 3) 2162 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2163 else 2164 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2165 2166 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2167 if (adapter->tx_itr_setting <= 3) 2168 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2169 else 2170 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2171 } 2172 2173 return 0; 2174} 2175 2176static int igb_nway_reset(struct net_device *netdev) 2177{ 2178 struct igb_adapter *adapter = netdev_priv(netdev); 2179 if (netif_running(netdev)) 2180 igb_reinit_locked(adapter); 2181 return 0; 2182} 2183 2184static int igb_get_sset_count(struct net_device *netdev, int sset) 2185{ 2186 switch (sset) { 2187 case ETH_SS_STATS: 2188 return IGB_STATS_LEN; 2189 case ETH_SS_TEST: 2190 return IGB_TEST_LEN; 2191 default: 2192 return -ENOTSUPP; 2193 } 2194} 2195 2196static void igb_get_ethtool_stats(struct net_device *netdev, 2197 struct ethtool_stats *stats, u64 *data) 2198{ 2199 struct igb_adapter *adapter = netdev_priv(netdev); 2200 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2201 unsigned int start; 2202 struct igb_ring *ring; 2203 int i, j; 2204 char *p; 2205 2206 spin_lock(&adapter->stats64_lock); 2207 igb_update_stats(adapter, net_stats); 2208 2209 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2210 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2211 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2212 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2213 } 2214 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2215 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2216 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2217 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2218 } 2219 for (j = 0; j < adapter->num_tx_queues; j++) { 2220 u64 restart2; 2221 2222 ring = adapter->tx_ring[j]; 2223 do { 2224 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 2225 data[i] = ring->tx_stats.packets; 2226 data[i+1] = ring->tx_stats.bytes; 2227 data[i+2] = ring->tx_stats.restart_queue; 2228 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 2229 do { 2230 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); 2231 restart2 = ring->tx_stats.restart_queue2; 2232 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); 2233 data[i+2] += restart2; 2234 2235 i += IGB_TX_QUEUE_STATS_LEN; 2236 } 2237 for (j = 0; j < adapter->num_rx_queues; j++) { 2238 ring = adapter->rx_ring[j]; 2239 do { 2240 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 2241 data[i] = ring->rx_stats.packets; 2242 data[i+1] = ring->rx_stats.bytes; 2243 data[i+2] = ring->rx_stats.drops; 2244 data[i+3] = ring->rx_stats.csum_err; 2245 data[i+4] = ring->rx_stats.alloc_failed; 2246 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 2247 i += IGB_RX_QUEUE_STATS_LEN; 2248 } 2249 spin_unlock(&adapter->stats64_lock); 2250} 2251 2252static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2253{ 2254 struct igb_adapter *adapter = netdev_priv(netdev); 2255 u8 *p = data; 2256 int i; 2257 2258 switch (stringset) { 2259 case ETH_SS_TEST: 2260 memcpy(data, *igb_gstrings_test, 2261 IGB_TEST_LEN*ETH_GSTRING_LEN); 2262 break; 2263 case ETH_SS_STATS: 2264 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2265 memcpy(p, igb_gstrings_stats[i].stat_string, 2266 ETH_GSTRING_LEN); 2267 p += ETH_GSTRING_LEN; 2268 } 2269 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2270 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2271 ETH_GSTRING_LEN); 2272 p += ETH_GSTRING_LEN; 2273 } 2274 for (i = 0; i < adapter->num_tx_queues; i++) { 2275 sprintf(p, "tx_queue_%u_packets", i); 2276 p += ETH_GSTRING_LEN; 2277 sprintf(p, "tx_queue_%u_bytes", i); 2278 p += ETH_GSTRING_LEN; 2279 sprintf(p, "tx_queue_%u_restart", i); 2280 p += ETH_GSTRING_LEN; 2281 } 2282 for (i = 0; i < adapter->num_rx_queues; i++) { 2283 sprintf(p, "rx_queue_%u_packets", i); 2284 p += ETH_GSTRING_LEN; 2285 sprintf(p, "rx_queue_%u_bytes", i); 2286 p += ETH_GSTRING_LEN; 2287 sprintf(p, "rx_queue_%u_drops", i); 2288 p += ETH_GSTRING_LEN; 2289 sprintf(p, "rx_queue_%u_csum_err", i); 2290 p += ETH_GSTRING_LEN; 2291 sprintf(p, "rx_queue_%u_alloc_failed", i); 2292 p += ETH_GSTRING_LEN; 2293 } 2294 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2295 break; 2296 } 2297} 2298 2299static int igb_get_ts_info(struct net_device *dev, 2300 struct ethtool_ts_info *info) 2301{ 2302 struct igb_adapter *adapter = netdev_priv(dev); 2303 2304 switch (adapter->hw.mac.type) { 2305 case e1000_82575: 2306 info->so_timestamping = 2307 SOF_TIMESTAMPING_TX_SOFTWARE | 2308 SOF_TIMESTAMPING_RX_SOFTWARE | 2309 SOF_TIMESTAMPING_SOFTWARE; 2310 return 0; 2311 case e1000_82576: 2312 case e1000_82580: 2313 case e1000_i350: 2314 case e1000_i210: 2315 case e1000_i211: 2316 info->so_timestamping = 2317 SOF_TIMESTAMPING_TX_SOFTWARE | 2318 SOF_TIMESTAMPING_RX_SOFTWARE | 2319 SOF_TIMESTAMPING_SOFTWARE | 2320 SOF_TIMESTAMPING_TX_HARDWARE | 2321 SOF_TIMESTAMPING_RX_HARDWARE | 2322 SOF_TIMESTAMPING_RAW_HARDWARE; 2323 2324 if (adapter->ptp_clock) 2325 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2326 else 2327 info->phc_index = -1; 2328 2329 info->tx_types = 2330 (1 << HWTSTAMP_TX_OFF) | 2331 (1 << HWTSTAMP_TX_ON); 2332 2333 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE; 2334 2335 /* 82576 does not support timestamping all packets. */ 2336 if (adapter->hw.mac.type >= e1000_82580) 2337 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL; 2338 else 2339 info->rx_filters |= 2340 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2341 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2342 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2343 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2344 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2345 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2346 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2347 2348 return 0; 2349 default: 2350 return -EOPNOTSUPP; 2351 } 2352} 2353 2354static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2355 struct ethtool_rxnfc *cmd) 2356{ 2357 cmd->data = 0; 2358 2359 /* Report default options for RSS on igb */ 2360 switch (cmd->flow_type) { 2361 case TCP_V4_FLOW: 2362 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2363 case UDP_V4_FLOW: 2364 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2365 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2366 case SCTP_V4_FLOW: 2367 case AH_ESP_V4_FLOW: 2368 case AH_V4_FLOW: 2369 case ESP_V4_FLOW: 2370 case IPV4_FLOW: 2371 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2372 break; 2373 case TCP_V6_FLOW: 2374 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2375 case UDP_V6_FLOW: 2376 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2377 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2378 case SCTP_V6_FLOW: 2379 case AH_ESP_V6_FLOW: 2380 case AH_V6_FLOW: 2381 case ESP_V6_FLOW: 2382 case IPV6_FLOW: 2383 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2384 break; 2385 default: 2386 return -EINVAL; 2387 } 2388 2389 return 0; 2390} 2391 2392static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2393 u32 *rule_locs) 2394{ 2395 struct igb_adapter *adapter = netdev_priv(dev); 2396 int ret = -EOPNOTSUPP; 2397 2398 switch (cmd->cmd) { 2399 case ETHTOOL_GRXRINGS: 2400 cmd->data = adapter->num_rx_queues; 2401 ret = 0; 2402 break; 2403 case ETHTOOL_GRXFH: 2404 ret = igb_get_rss_hash_opts(adapter, cmd); 2405 break; 2406 default: 2407 break; 2408 } 2409 2410 return ret; 2411} 2412 2413#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2414 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2415static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2416 struct ethtool_rxnfc *nfc) 2417{ 2418 u32 flags = adapter->flags; 2419 2420 /* RSS does not support anything other than hashing 2421 * to queues on src and dst IPs and ports 2422 */ 2423 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2424 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2425 return -EINVAL; 2426 2427 switch (nfc->flow_type) { 2428 case TCP_V4_FLOW: 2429 case TCP_V6_FLOW: 2430 if (!(nfc->data & RXH_IP_SRC) || 2431 !(nfc->data & RXH_IP_DST) || 2432 !(nfc->data & RXH_L4_B_0_1) || 2433 !(nfc->data & RXH_L4_B_2_3)) 2434 return -EINVAL; 2435 break; 2436 case UDP_V4_FLOW: 2437 if (!(nfc->data & RXH_IP_SRC) || 2438 !(nfc->data & RXH_IP_DST)) 2439 return -EINVAL; 2440 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2441 case 0: 2442 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2443 break; 2444 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2445 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2446 break; 2447 default: 2448 return -EINVAL; 2449 } 2450 break; 2451 case UDP_V6_FLOW: 2452 if (!(nfc->data & RXH_IP_SRC) || 2453 !(nfc->data & RXH_IP_DST)) 2454 return -EINVAL; 2455 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2456 case 0: 2457 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2458 break; 2459 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2460 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2461 break; 2462 default: 2463 return -EINVAL; 2464 } 2465 break; 2466 case AH_ESP_V4_FLOW: 2467 case AH_V4_FLOW: 2468 case ESP_V4_FLOW: 2469 case SCTP_V4_FLOW: 2470 case AH_ESP_V6_FLOW: 2471 case AH_V6_FLOW: 2472 case ESP_V6_FLOW: 2473 case SCTP_V6_FLOW: 2474 if (!(nfc->data & RXH_IP_SRC) || 2475 !(nfc->data & RXH_IP_DST) || 2476 (nfc->data & RXH_L4_B_0_1) || 2477 (nfc->data & RXH_L4_B_2_3)) 2478 return -EINVAL; 2479 break; 2480 default: 2481 return -EINVAL; 2482 } 2483 2484 /* if we changed something we need to update flags */ 2485 if (flags != adapter->flags) { 2486 struct e1000_hw *hw = &adapter->hw; 2487 u32 mrqc = rd32(E1000_MRQC); 2488 2489 if ((flags & UDP_RSS_FLAGS) && 2490 !(adapter->flags & UDP_RSS_FLAGS)) 2491 dev_err(&adapter->pdev->dev, 2492 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2493 2494 adapter->flags = flags; 2495 2496 /* Perform hash on these packet types */ 2497 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2498 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2499 E1000_MRQC_RSS_FIELD_IPV6 | 2500 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2501 2502 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2503 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2504 2505 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2506 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2507 2508 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2509 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2510 2511 wr32(E1000_MRQC, mrqc); 2512 } 2513 2514 return 0; 2515} 2516 2517static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2518{ 2519 struct igb_adapter *adapter = netdev_priv(dev); 2520 int ret = -EOPNOTSUPP; 2521 2522 switch (cmd->cmd) { 2523 case ETHTOOL_SRXFH: 2524 ret = igb_set_rss_hash_opt(adapter, cmd); 2525 break; 2526 default: 2527 break; 2528 } 2529 2530 return ret; 2531} 2532 2533static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 2534{ 2535 struct igb_adapter *adapter = netdev_priv(netdev); 2536 struct e1000_hw *hw = &adapter->hw; 2537 u32 ipcnfg, eeer, ret_val; 2538 u16 phy_data; 2539 2540 if ((hw->mac.type < e1000_i350) || 2541 (hw->phy.media_type != e1000_media_type_copper)) 2542 return -EOPNOTSUPP; 2543 2544 edata->supported = (SUPPORTED_1000baseT_Full | 2545 SUPPORTED_100baseT_Full); 2546 2547 ipcnfg = rd32(E1000_IPCNFG); 2548 eeer = rd32(E1000_EEER); 2549 2550 /* EEE status on negotiated link */ 2551 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN) 2552 edata->advertised = ADVERTISED_1000baseT_Full; 2553 2554 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN) 2555 edata->advertised |= ADVERTISED_100baseT_Full; 2556 2557 /* EEE Link Partner Advertised */ 2558 switch (hw->mac.type) { 2559 case e1000_i350: 2560 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350, 2561 &phy_data); 2562 if (ret_val) 2563 return -ENODATA; 2564 2565 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2566 2567 break; 2568 case e1000_i210: 2569 case e1000_i211: 2570 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210, 2571 E1000_EEE_LP_ADV_DEV_I210, 2572 &phy_data); 2573 if (ret_val) 2574 return -ENODATA; 2575 2576 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data); 2577 2578 break; 2579 default: 2580 break; 2581 } 2582 2583 if (eeer & E1000_EEER_EEE_NEG) 2584 edata->eee_active = true; 2585 2586 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 2587 2588 if (eeer & E1000_EEER_TX_LPI_EN) 2589 edata->tx_lpi_enabled = true; 2590 2591 /* Report correct negotiated EEE status for devices that 2592 * wrongly report EEE at half-duplex 2593 */ 2594 if (adapter->link_duplex == HALF_DUPLEX) { 2595 edata->eee_enabled = false; 2596 edata->eee_active = false; 2597 edata->tx_lpi_enabled = false; 2598 edata->advertised &= ~edata->advertised; 2599 } 2600 2601 return 0; 2602} 2603 2604static int igb_set_eee(struct net_device *netdev, 2605 struct ethtool_eee *edata) 2606{ 2607 struct igb_adapter *adapter = netdev_priv(netdev); 2608 struct e1000_hw *hw = &adapter->hw; 2609 struct ethtool_eee eee_curr; 2610 s32 ret_val; 2611 2612 if ((hw->mac.type < e1000_i350) || 2613 (hw->phy.media_type != e1000_media_type_copper)) 2614 return -EOPNOTSUPP; 2615 2616 ret_val = igb_get_eee(netdev, &eee_curr); 2617 if (ret_val) 2618 return ret_val; 2619 2620 if (eee_curr.eee_enabled) { 2621 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 2622 dev_err(&adapter->pdev->dev, 2623 "Setting EEE tx-lpi is not supported\n"); 2624 return -EINVAL; 2625 } 2626 2627 /* Tx LPI timer is not implemented currently */ 2628 if (edata->tx_lpi_timer) { 2629 dev_err(&adapter->pdev->dev, 2630 "Setting EEE Tx LPI timer is not supported\n"); 2631 return -EINVAL; 2632 } 2633 2634 if (eee_curr.advertised != edata->advertised) { 2635 dev_err(&adapter->pdev->dev, 2636 "Setting EEE Advertisement is not supported\n"); 2637 return -EINVAL; 2638 } 2639 2640 } else if (!edata->eee_enabled) { 2641 dev_err(&adapter->pdev->dev, 2642 "Setting EEE options are not supported with EEE disabled\n"); 2643 return -EINVAL; 2644 } 2645 2646 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 2647 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 2648 igb_set_eee_i350(hw); 2649 2650 /* reset link */ 2651 if (!netif_running(netdev)) 2652 igb_reset(adapter); 2653 } 2654 2655 return 0; 2656} 2657 2658static int igb_get_module_info(struct net_device *netdev, 2659 struct ethtool_modinfo *modinfo) 2660{ 2661 struct igb_adapter *adapter = netdev_priv(netdev); 2662 struct e1000_hw *hw = &adapter->hw; 2663 u32 status = E1000_SUCCESS; 2664 u16 sff8472_rev, addr_mode; 2665 bool page_swap = false; 2666 2667 if ((hw->phy.media_type == e1000_media_type_copper) || 2668 (hw->phy.media_type == e1000_media_type_unknown)) 2669 return -EOPNOTSUPP; 2670 2671 /* Check whether we support SFF-8472 or not */ 2672 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev); 2673 if (status != E1000_SUCCESS) 2674 return -EIO; 2675 2676 /* addressing mode is not supported */ 2677 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode); 2678 if (status != E1000_SUCCESS) 2679 return -EIO; 2680 2681 /* addressing mode is not supported */ 2682 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { 2683 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n"); 2684 page_swap = true; 2685 } 2686 2687 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { 2688 /* We have an SFP, but it does not support SFF-8472 */ 2689 modinfo->type = ETH_MODULE_SFF_8079; 2690 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN; 2691 } else { 2692 /* We have an SFP which supports a revision of SFF-8472 */ 2693 modinfo->type = ETH_MODULE_SFF_8472; 2694 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2695 } 2696 2697 return 0; 2698} 2699 2700static int igb_get_module_eeprom(struct net_device *netdev, 2701 struct ethtool_eeprom *ee, u8 *data) 2702{ 2703 struct igb_adapter *adapter = netdev_priv(netdev); 2704 struct e1000_hw *hw = &adapter->hw; 2705 u32 status = E1000_SUCCESS; 2706 u16 *dataword; 2707 u16 first_word, last_word; 2708 int i = 0; 2709 2710 if (ee->len == 0) 2711 return -EINVAL; 2712 2713 first_word = ee->offset >> 1; 2714 last_word = (ee->offset + ee->len - 1) >> 1; 2715 2716 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1), 2717 GFP_KERNEL); 2718 if (!dataword) 2719 return -ENOMEM; 2720 2721 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */ 2722 for (i = 0; i < last_word - first_word + 1; i++) { 2723 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]); 2724 if (status != E1000_SUCCESS) 2725 /* Error occurred while reading module */ 2726 return -EIO; 2727 2728 be16_to_cpus(&dataword[i]); 2729 } 2730 2731 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len); 2732 kfree(dataword); 2733 2734 return 0; 2735} 2736 2737static int igb_ethtool_begin(struct net_device *netdev) 2738{ 2739 struct igb_adapter *adapter = netdev_priv(netdev); 2740 pm_runtime_get_sync(&adapter->pdev->dev); 2741 return 0; 2742} 2743 2744static void igb_ethtool_complete(struct net_device *netdev) 2745{ 2746 struct igb_adapter *adapter = netdev_priv(netdev); 2747 pm_runtime_put(&adapter->pdev->dev); 2748} 2749 2750static const struct ethtool_ops igb_ethtool_ops = { 2751 .get_settings = igb_get_settings, 2752 .set_settings = igb_set_settings, 2753 .get_drvinfo = igb_get_drvinfo, 2754 .get_regs_len = igb_get_regs_len, 2755 .get_regs = igb_get_regs, 2756 .get_wol = igb_get_wol, 2757 .set_wol = igb_set_wol, 2758 .get_msglevel = igb_get_msglevel, 2759 .set_msglevel = igb_set_msglevel, 2760 .nway_reset = igb_nway_reset, 2761 .get_link = igb_get_link, 2762 .get_eeprom_len = igb_get_eeprom_len, 2763 .get_eeprom = igb_get_eeprom, 2764 .set_eeprom = igb_set_eeprom, 2765 .get_ringparam = igb_get_ringparam, 2766 .set_ringparam = igb_set_ringparam, 2767 .get_pauseparam = igb_get_pauseparam, 2768 .set_pauseparam = igb_set_pauseparam, 2769 .self_test = igb_diag_test, 2770 .get_strings = igb_get_strings, 2771 .set_phys_id = igb_set_phys_id, 2772 .get_sset_count = igb_get_sset_count, 2773 .get_ethtool_stats = igb_get_ethtool_stats, 2774 .get_coalesce = igb_get_coalesce, 2775 .set_coalesce = igb_set_coalesce, 2776 .get_ts_info = igb_get_ts_info, 2777 .get_rxnfc = igb_get_rxnfc, 2778 .set_rxnfc = igb_set_rxnfc, 2779 .get_eee = igb_get_eee, 2780 .set_eee = igb_set_eee, 2781 .get_module_info = igb_get_module_info, 2782 .get_module_eeprom = igb_get_module_eeprom, 2783 .begin = igb_ethtool_begin, 2784 .complete = igb_ethtool_complete, 2785}; 2786 2787void igb_set_ethtool_ops(struct net_device *netdev) 2788{ 2789 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); 2790} 2791