igb_ptp.c revision 74cfb2e1f296b3f962016adf41b316b8cf7d4ed4
1/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 2 * 3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18#include <linux/module.h> 19#include <linux/device.h> 20#include <linux/pci.h> 21#include <linux/ptp_classify.h> 22 23#include "igb.h" 24 25#define INCVALUE_MASK 0x7fffffff 26#define ISGN 0x80000000 27 28/* The 82580 timesync updates the system timer every 8ns by 8ns, 29 * and this update value cannot be reprogrammed. 30 * 31 * Neither the 82576 nor the 82580 offer registers wide enough to hold 32 * nanoseconds time values for very long. For the 82580, SYSTIM always 33 * counts nanoseconds, but the upper 24 bits are not availible. The 34 * frequency is adjusted by changing the 32 bit fractional nanoseconds 35 * register, TIMINCA. 36 * 37 * For the 82576, the SYSTIM register time unit is affect by the 38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 39 * field are needed to provide the nominal 16 nanosecond period, 40 * leaving 19 bits for fractional nanoseconds. 41 * 42 * We scale the NIC clock cycle by a large factor so that relatively 43 * small clock corrections can be added or subtracted at each clock 44 * tick. The drawbacks of a large factor are a) that the clock 45 * register overflows more quickly (not such a big deal) and b) that 46 * the increment per tick has to fit into 24 bits. As a result we 47 * need to use a shift of 19 so we can fit a value of 16 into the 48 * TIMINCA register. 49 * 50 * 51 * SYSTIMH SYSTIML 52 * +--------------+ +---+---+------+ 53 * 82576 | 32 | | 8 | 5 | 19 | 54 * +--------------+ +---+---+------+ 55 * \________ 45 bits _______/ fract 56 * 57 * +----------+---+ +--------------+ 58 * 82580 | 24 | 8 | | 32 | 59 * +----------+---+ +--------------+ 60 * reserved \______ 40 bits _____/ 61 * 62 * 63 * The 45 bit 82576 SYSTIM overflows every 64 * 2^45 * 10^-9 / 3600 = 9.77 hours. 65 * 66 * The 40 bit 82580 SYSTIM overflows every 67 * 2^40 * 10^-9 / 60 = 18.3 minutes. 68 */ 69 70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 71#define IGB_PTP_TX_TIMEOUT (HZ * 15) 72#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 73#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) 74#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 75#define IGB_NBITS_82580 40 76 77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 78 79/* SYSTIM read access for the 82576 */ 80static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) 81{ 82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 83 struct e1000_hw *hw = &igb->hw; 84 u64 val; 85 u32 lo, hi; 86 87 lo = rd32(E1000_SYSTIML); 88 hi = rd32(E1000_SYSTIMH); 89 90 val = ((u64) hi) << 32; 91 val |= lo; 92 93 return val; 94} 95 96/* SYSTIM read access for the 82580 */ 97static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) 98{ 99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 100 struct e1000_hw *hw = &igb->hw; 101 u32 lo, hi; 102 u64 val; 103 104 /* The timestamp latches on lowest register read. For the 82580 105 * the lowest register is SYSTIMR instead of SYSTIML. However we only 106 * need to provide nanosecond resolution, so we just ignore it. 107 */ 108 rd32(E1000_SYSTIMR); 109 lo = rd32(E1000_SYSTIML); 110 hi = rd32(E1000_SYSTIMH); 111 112 val = ((u64) hi) << 32; 113 val |= lo; 114 115 return val; 116} 117 118/* SYSTIM read access for I210/I211 */ 119static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) 120{ 121 struct e1000_hw *hw = &adapter->hw; 122 u32 sec, nsec; 123 124 /* The timestamp latches on lowest register read. For I210/I211, the 125 * lowest register is SYSTIMR. Since we only need to provide nanosecond 126 * resolution, we can ignore it. 127 */ 128 rd32(E1000_SYSTIMR); 129 nsec = rd32(E1000_SYSTIML); 130 sec = rd32(E1000_SYSTIMH); 131 132 ts->tv_sec = sec; 133 ts->tv_nsec = nsec; 134} 135 136static void igb_ptp_write_i210(struct igb_adapter *adapter, 137 const struct timespec *ts) 138{ 139 struct e1000_hw *hw = &adapter->hw; 140 141 /* Writing the SYSTIMR register is not necessary as it only provides 142 * sub-nanosecond resolution. 143 */ 144 wr32(E1000_SYSTIML, ts->tv_nsec); 145 wr32(E1000_SYSTIMH, ts->tv_sec); 146} 147 148/** 149 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 150 * @adapter: board private structure 151 * @hwtstamps: timestamp structure to update 152 * @systim: unsigned 64bit system time value. 153 * 154 * We need to convert the system time value stored in the RX/TXSTMP registers 155 * into a hwtstamp which can be used by the upper level timestamping functions. 156 * 157 * The 'tmreg_lock' spinlock is used to protect the consistency of the 158 * system time value. This is needed because reading the 64 bit time 159 * value involves reading two (or three) 32 bit registers. The first 160 * read latches the value. Ditto for writing. 161 * 162 * In addition, here have extended the system time with an overflow 163 * counter in software. 164 **/ 165static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 166 struct skb_shared_hwtstamps *hwtstamps, 167 u64 systim) 168{ 169 unsigned long flags; 170 u64 ns; 171 172 switch (adapter->hw.mac.type) { 173 case e1000_82576: 174 case e1000_82580: 175 case e1000_i354: 176 case e1000_i350: 177 spin_lock_irqsave(&adapter->tmreg_lock, flags); 178 179 ns = timecounter_cyc2time(&adapter->tc, systim); 180 181 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 182 183 memset(hwtstamps, 0, sizeof(*hwtstamps)); 184 hwtstamps->hwtstamp = ns_to_ktime(ns); 185 break; 186 case e1000_i210: 187 case e1000_i211: 188 memset(hwtstamps, 0, sizeof(*hwtstamps)); 189 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 190 hwtstamps->hwtstamp = ktime_set(systim >> 32, 191 systim & 0xFFFFFFFF); 192 break; 193 default: 194 break; 195 } 196} 197 198/* PTP clock operations */ 199static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 200{ 201 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 202 ptp_caps); 203 struct e1000_hw *hw = &igb->hw; 204 int neg_adj = 0; 205 u64 rate; 206 u32 incvalue; 207 208 if (ppb < 0) { 209 neg_adj = 1; 210 ppb = -ppb; 211 } 212 rate = ppb; 213 rate <<= 14; 214 rate = div_u64(rate, 1953125); 215 216 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 217 218 if (neg_adj) 219 incvalue -= rate; 220 else 221 incvalue += rate; 222 223 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 224 225 return 0; 226} 227 228static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) 229{ 230 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 231 ptp_caps); 232 struct e1000_hw *hw = &igb->hw; 233 int neg_adj = 0; 234 u64 rate; 235 u32 inca; 236 237 if (ppb < 0) { 238 neg_adj = 1; 239 ppb = -ppb; 240 } 241 rate = ppb; 242 rate <<= 26; 243 rate = div_u64(rate, 1953125); 244 245 inca = rate & INCVALUE_MASK; 246 if (neg_adj) 247 inca |= ISGN; 248 249 wr32(E1000_TIMINCA, inca); 250 251 return 0; 252} 253 254static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 255{ 256 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 257 ptp_caps); 258 unsigned long flags; 259 s64 now; 260 261 spin_lock_irqsave(&igb->tmreg_lock, flags); 262 263 now = timecounter_read(&igb->tc); 264 now += delta; 265 timecounter_init(&igb->tc, &igb->cc, now); 266 267 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 268 269 return 0; 270} 271 272static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 273{ 274 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 275 ptp_caps); 276 unsigned long flags; 277 struct timespec now, then = ns_to_timespec(delta); 278 279 spin_lock_irqsave(&igb->tmreg_lock, flags); 280 281 igb_ptp_read_i210(igb, &now); 282 now = timespec_add(now, then); 283 igb_ptp_write_i210(igb, (const struct timespec *)&now); 284 285 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 286 287 return 0; 288} 289 290static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 291 struct timespec *ts) 292{ 293 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 294 ptp_caps); 295 unsigned long flags; 296 u64 ns; 297 u32 remainder; 298 299 spin_lock_irqsave(&igb->tmreg_lock, flags); 300 301 ns = timecounter_read(&igb->tc); 302 303 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 304 305 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); 306 ts->tv_nsec = remainder; 307 308 return 0; 309} 310 311static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 312 struct timespec *ts) 313{ 314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 315 ptp_caps); 316 unsigned long flags; 317 318 spin_lock_irqsave(&igb->tmreg_lock, flags); 319 320 igb_ptp_read_i210(igb, ts); 321 322 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 323 324 return 0; 325} 326 327static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 328 const struct timespec *ts) 329{ 330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 331 ptp_caps); 332 unsigned long flags; 333 u64 ns; 334 335 ns = ts->tv_sec * 1000000000ULL; 336 ns += ts->tv_nsec; 337 338 spin_lock_irqsave(&igb->tmreg_lock, flags); 339 340 timecounter_init(&igb->tc, &igb->cc, ns); 341 342 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 343 344 return 0; 345} 346 347static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 348 const struct timespec *ts) 349{ 350 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 351 ptp_caps); 352 unsigned long flags; 353 354 spin_lock_irqsave(&igb->tmreg_lock, flags); 355 356 igb_ptp_write_i210(igb, ts); 357 358 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 359 360 return 0; 361} 362 363static int igb_ptp_enable(struct ptp_clock_info *ptp, 364 struct ptp_clock_request *rq, int on) 365{ 366 return -EOPNOTSUPP; 367} 368 369/** 370 * igb_ptp_tx_work 371 * @work: pointer to work struct 372 * 373 * This work function polls the TSYNCTXCTL valid bit to determine when a 374 * timestamp has been taken for the current stored skb. 375 **/ 376static void igb_ptp_tx_work(struct work_struct *work) 377{ 378 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 379 ptp_tx_work); 380 struct e1000_hw *hw = &adapter->hw; 381 u32 tsynctxctl; 382 383 if (!adapter->ptp_tx_skb) 384 return; 385 386 if (time_is_before_jiffies(adapter->ptp_tx_start + 387 IGB_PTP_TX_TIMEOUT)) { 388 dev_kfree_skb_any(adapter->ptp_tx_skb); 389 adapter->ptp_tx_skb = NULL; 390 adapter->tx_hwtstamp_timeouts++; 391 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang"); 392 return; 393 } 394 395 tsynctxctl = rd32(E1000_TSYNCTXCTL); 396 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 397 igb_ptp_tx_hwtstamp(adapter); 398 else 399 /* reschedule to check later */ 400 schedule_work(&adapter->ptp_tx_work); 401} 402 403static void igb_ptp_overflow_check(struct work_struct *work) 404{ 405 struct igb_adapter *igb = 406 container_of(work, struct igb_adapter, ptp_overflow_work.work); 407 struct timespec ts; 408 409 igb->ptp_caps.gettime(&igb->ptp_caps, &ts); 410 411 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); 412 413 schedule_delayed_work(&igb->ptp_overflow_work, 414 IGB_SYSTIM_OVERFLOW_PERIOD); 415} 416 417/** 418 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 419 * @adapter: private network adapter structure 420 * 421 * This watchdog task is scheduled to detect error case where hardware has 422 * dropped an Rx packet that was timestamped when the ring is full. The 423 * particular error is rare but leaves the device in a state unable to timestamp 424 * any future packets. 425 **/ 426void igb_ptp_rx_hang(struct igb_adapter *adapter) 427{ 428 struct e1000_hw *hw = &adapter->hw; 429 struct igb_ring *rx_ring; 430 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 431 unsigned long rx_event; 432 int n; 433 434 if (hw->mac.type != e1000_82576) 435 return; 436 437 /* If we don't have a valid timestamp in the registers, just update the 438 * timeout counter and exit 439 */ 440 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 441 adapter->last_rx_ptp_check = jiffies; 442 return; 443 } 444 445 /* Determine the most recent watchdog or rx_timestamp event */ 446 rx_event = adapter->last_rx_ptp_check; 447 for (n = 0; n < adapter->num_rx_queues; n++) { 448 rx_ring = adapter->rx_ring[n]; 449 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 450 rx_event = rx_ring->last_rx_timestamp; 451 } 452 453 /* Only need to read the high RXSTMP register to clear the lock */ 454 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 455 rd32(E1000_RXSTMPH); 456 adapter->last_rx_ptp_check = jiffies; 457 adapter->rx_hwtstamp_cleared++; 458 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang"); 459 } 460} 461 462/** 463 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 464 * @adapter: Board private structure. 465 * 466 * If we were asked to do hardware stamping and such a time stamp is 467 * available, then it must have been for this skb here because we only 468 * allow only one such packet into the queue. 469 **/ 470static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 471{ 472 struct e1000_hw *hw = &adapter->hw; 473 struct skb_shared_hwtstamps shhwtstamps; 474 u64 regval; 475 476 regval = rd32(E1000_TXSTMPL); 477 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 478 479 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 480 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 481 dev_kfree_skb_any(adapter->ptp_tx_skb); 482 adapter->ptp_tx_skb = NULL; 483} 484 485/** 486 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 487 * @q_vector: Pointer to interrupt specific structure 488 * @va: Pointer to address containing Rx buffer 489 * @skb: Buffer containing timestamp and packet 490 * 491 * This function is meant to retrieve a timestamp from the first buffer of an 492 * incoming frame. The value is stored in little endian format starting on 493 * byte 8. 494 **/ 495void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 496 unsigned char *va, 497 struct sk_buff *skb) 498{ 499 __le64 *regval = (__le64 *)va; 500 501 /* The timestamp is recorded in little endian format. 502 * DWORD: 0 1 2 3 503 * Field: Reserved Reserved SYSTIML SYSTIMH 504 */ 505 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), 506 le64_to_cpu(regval[1])); 507} 508 509/** 510 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 511 * @q_vector: Pointer to interrupt specific structure 512 * @skb: Buffer containing timestamp and packet 513 * 514 * This function is meant to retrieve a timestamp from the internal registers 515 * of the adapter and store it in the skb. 516 **/ 517void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 518 struct sk_buff *skb) 519{ 520 struct igb_adapter *adapter = q_vector->adapter; 521 struct e1000_hw *hw = &adapter->hw; 522 u64 regval; 523 524 /* If this bit is set, then the RX registers contain the time stamp. No 525 * other packet will be time stamped until we read these registers, so 526 * read the registers to make them available again. Because only one 527 * packet can be time stamped at a time, we know that the register 528 * values must belong to this one here and therefore we don't need to 529 * compare any of the additional attributes stored for it. 530 * 531 * If nothing went wrong, then it should have a shared tx_flags that we 532 * can turn into a skb_shared_hwtstamps. 533 */ 534 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 535 return; 536 537 regval = rd32(E1000_RXSTMPL); 538 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 539 540 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 541} 542 543/** 544 * igb_ptp_hwtstamp_ioctl - control hardware time stamping 545 * @netdev: 546 * @ifreq: 547 * @cmd: 548 * 549 * Outgoing time stamping can be enabled and disabled. Play nice and 550 * disable it when requested, although it shouldn't case any overhead 551 * when no packet needs it. At most one packet in the queue may be 552 * marked for time stamping, otherwise it would be impossible to tell 553 * for sure to which packet the hardware time stamp belongs. 554 * 555 * Incoming time stamping has to be configured via the hardware 556 * filters. Not all combinations are supported, in particular event 557 * type has to be specified. Matching the kind of event packet is 558 * not supported, with the exception of "all V2 events regardless of 559 * level 2 or 4". 560 **/ 561int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 562 struct ifreq *ifr, int cmd) 563{ 564 struct igb_adapter *adapter = netdev_priv(netdev); 565 struct e1000_hw *hw = &adapter->hw; 566 struct hwtstamp_config config; 567 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 568 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 569 u32 tsync_rx_cfg = 0; 570 bool is_l4 = false; 571 bool is_l2 = false; 572 u32 regval; 573 574 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 575 return -EFAULT; 576 577 /* reserved for future extensions */ 578 if (config.flags) 579 return -EINVAL; 580 581 switch (config.tx_type) { 582 case HWTSTAMP_TX_OFF: 583 tsync_tx_ctl = 0; 584 case HWTSTAMP_TX_ON: 585 break; 586 default: 587 return -ERANGE; 588 } 589 590 switch (config.rx_filter) { 591 case HWTSTAMP_FILTER_NONE: 592 tsync_rx_ctl = 0; 593 break; 594 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 595 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 596 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 597 is_l4 = true; 598 break; 599 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 601 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 602 is_l4 = true; 603 break; 604 case HWTSTAMP_FILTER_PTP_V2_EVENT: 605 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 606 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 607 case HWTSTAMP_FILTER_PTP_V2_SYNC: 608 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 609 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 610 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 611 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 613 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 615 is_l2 = true; 616 is_l4 = true; 617 break; 618 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 619 case HWTSTAMP_FILTER_ALL: 620 /* 82576 cannot timestamp all packets, which it needs to do to 621 * support both V1 Sync and Delay_Req messages 622 */ 623 if (hw->mac.type != e1000_82576) { 624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 625 config.rx_filter = HWTSTAMP_FILTER_ALL; 626 break; 627 } 628 /* fall through */ 629 default: 630 config.rx_filter = HWTSTAMP_FILTER_NONE; 631 return -ERANGE; 632 } 633 634 if (hw->mac.type == e1000_82575) { 635 if (tsync_rx_ctl | tsync_tx_ctl) 636 return -EINVAL; 637 return 0; 638 } 639 640 /* Per-packet timestamping only works if all packets are 641 * timestamped, so enable timestamping in all packets as 642 * long as one Rx filter was configured. 643 */ 644 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 645 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 646 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 647 config.rx_filter = HWTSTAMP_FILTER_ALL; 648 is_l2 = true; 649 is_l4 = true; 650 651 if ((hw->mac.type == e1000_i210) || 652 (hw->mac.type == e1000_i211)) { 653 regval = rd32(E1000_RXPBS); 654 regval |= E1000_RXPBS_CFG_TS_EN; 655 wr32(E1000_RXPBS, regval); 656 } 657 } 658 659 /* enable/disable TX */ 660 regval = rd32(E1000_TSYNCTXCTL); 661 regval &= ~E1000_TSYNCTXCTL_ENABLED; 662 regval |= tsync_tx_ctl; 663 wr32(E1000_TSYNCTXCTL, regval); 664 665 /* enable/disable RX */ 666 regval = rd32(E1000_TSYNCRXCTL); 667 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 668 regval |= tsync_rx_ctl; 669 wr32(E1000_TSYNCRXCTL, regval); 670 671 /* define which PTP packets are time stamped */ 672 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 673 674 /* define ethertype filter for timestamped packets */ 675 if (is_l2) 676 wr32(E1000_ETQF(3), 677 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 678 E1000_ETQF_1588 | /* enable timestamping */ 679 ETH_P_1588)); /* 1588 eth protocol type */ 680 else 681 wr32(E1000_ETQF(3), 0); 682 683 /* L4 Queue Filter[3]: filter by destination port and protocol */ 684 if (is_l4) { 685 u32 ftqf = (IPPROTO_UDP /* UDP */ 686 | E1000_FTQF_VF_BP /* VF not compared */ 687 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 688 | E1000_FTQF_MASK); /* mask all inputs */ 689 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 690 691 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 692 wr32(E1000_IMIREXT(3), 693 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 694 if (hw->mac.type == e1000_82576) { 695 /* enable source port check */ 696 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 697 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 698 } 699 wr32(E1000_FTQF(3), ftqf); 700 } else { 701 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 702 } 703 wrfl(); 704 705 /* clear TX/RX time stamp registers, just to be sure */ 706 regval = rd32(E1000_TXSTMPL); 707 regval = rd32(E1000_TXSTMPH); 708 regval = rd32(E1000_RXSTMPL); 709 regval = rd32(E1000_RXSTMPH); 710 711 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 712 -EFAULT : 0; 713} 714 715void igb_ptp_init(struct igb_adapter *adapter) 716{ 717 struct e1000_hw *hw = &adapter->hw; 718 struct net_device *netdev = adapter->netdev; 719 720 switch (hw->mac.type) { 721 case e1000_82576: 722 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 723 adapter->ptp_caps.owner = THIS_MODULE; 724 adapter->ptp_caps.max_adj = 999999881; 725 adapter->ptp_caps.n_ext_ts = 0; 726 adapter->ptp_caps.pps = 0; 727 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 728 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 729 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 730 adapter->ptp_caps.settime = igb_ptp_settime_82576; 731 adapter->ptp_caps.enable = igb_ptp_enable; 732 adapter->cc.read = igb_ptp_read_82576; 733 adapter->cc.mask = CLOCKSOURCE_MASK(64); 734 adapter->cc.mult = 1; 735 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 736 /* Dial the nominal frequency. */ 737 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 738 break; 739 case e1000_82580: 740 case e1000_i354: 741 case e1000_i350: 742 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 743 adapter->ptp_caps.owner = THIS_MODULE; 744 adapter->ptp_caps.max_adj = 62499999; 745 adapter->ptp_caps.n_ext_ts = 0; 746 adapter->ptp_caps.pps = 0; 747 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 748 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 749 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 750 adapter->ptp_caps.settime = igb_ptp_settime_82576; 751 adapter->ptp_caps.enable = igb_ptp_enable; 752 adapter->cc.read = igb_ptp_read_82580; 753 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); 754 adapter->cc.mult = 1; 755 adapter->cc.shift = 0; 756 /* Enable the timer functions by clearing bit 31. */ 757 wr32(E1000_TSAUXC, 0x0); 758 break; 759 case e1000_i210: 760 case e1000_i211: 761 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 762 adapter->ptp_caps.owner = THIS_MODULE; 763 adapter->ptp_caps.max_adj = 62499999; 764 adapter->ptp_caps.n_ext_ts = 0; 765 adapter->ptp_caps.pps = 0; 766 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 767 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 768 adapter->ptp_caps.gettime = igb_ptp_gettime_i210; 769 adapter->ptp_caps.settime = igb_ptp_settime_i210; 770 adapter->ptp_caps.enable = igb_ptp_enable; 771 /* Enable the timer functions by clearing bit 31. */ 772 wr32(E1000_TSAUXC, 0x0); 773 break; 774 default: 775 adapter->ptp_clock = NULL; 776 return; 777 } 778 779 wrfl(); 780 781 spin_lock_init(&adapter->tmreg_lock); 782 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 783 784 /* Initialize the clock and overflow work for devices that need it. */ 785 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 786 struct timespec ts = ktime_to_timespec(ktime_get_real()); 787 788 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 789 } else { 790 timecounter_init(&adapter->tc, &adapter->cc, 791 ktime_to_ns(ktime_get_real())); 792 793 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 794 igb_ptp_overflow_check); 795 796 schedule_delayed_work(&adapter->ptp_overflow_work, 797 IGB_SYSTIM_OVERFLOW_PERIOD); 798 } 799 800 /* Initialize the time sync interrupts for devices that support it. */ 801 if (hw->mac.type >= e1000_82580) { 802 wr32(E1000_TSIM, E1000_TSIM_TXTS); 803 wr32(E1000_IMS, E1000_IMS_TS); 804 } 805 806 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 807 &adapter->pdev->dev); 808 if (IS_ERR(adapter->ptp_clock)) { 809 adapter->ptp_clock = NULL; 810 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 811 } else { 812 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 813 adapter->netdev->name); 814 adapter->flags |= IGB_FLAG_PTP; 815 } 816} 817 818/** 819 * igb_ptp_stop - Disable PTP device and stop the overflow check. 820 * @adapter: Board private structure. 821 * 822 * This function stops the PTP support and cancels the delayed work. 823 **/ 824void igb_ptp_stop(struct igb_adapter *adapter) 825{ 826 switch (adapter->hw.mac.type) { 827 case e1000_82576: 828 case e1000_82580: 829 case e1000_i354: 830 case e1000_i350: 831 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 832 break; 833 case e1000_i210: 834 case e1000_i211: 835 /* No delayed work to cancel. */ 836 break; 837 default: 838 return; 839 } 840 841 cancel_work_sync(&adapter->ptp_tx_work); 842 if (adapter->ptp_tx_skb) { 843 dev_kfree_skb_any(adapter->ptp_tx_skb); 844 adapter->ptp_tx_skb = NULL; 845 } 846 847 if (adapter->ptp_clock) { 848 ptp_clock_unregister(adapter->ptp_clock); 849 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 850 adapter->netdev->name); 851 adapter->flags &= ~IGB_FLAG_PTP; 852 } 853} 854 855/** 856 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 857 * @adapter: Board private structure. 858 * 859 * This function handles the reset work required to re-enable the PTP device. 860 **/ 861void igb_ptp_reset(struct igb_adapter *adapter) 862{ 863 struct e1000_hw *hw = &adapter->hw; 864 865 if (!(adapter->flags & IGB_FLAG_PTP)) 866 return; 867 868 switch (adapter->hw.mac.type) { 869 case e1000_82576: 870 /* Dial the nominal frequency. */ 871 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 872 break; 873 case e1000_82580: 874 case e1000_i354: 875 case e1000_i350: 876 case e1000_i210: 877 case e1000_i211: 878 /* Enable the timer functions and interrupts. */ 879 wr32(E1000_TSAUXC, 0x0); 880 wr32(E1000_TSIM, E1000_TSIM_TXTS); 881 wr32(E1000_IMS, E1000_IMS_TS); 882 break; 883 default: 884 /* No work to do. */ 885 return; 886 } 887 888 /* Re-initialize the timer. */ 889 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 890 struct timespec ts = ktime_to_timespec(ktime_get_real()); 891 892 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 893 } else { 894 timecounter_init(&adapter->tc, &adapter->cc, 895 ktime_to_ns(ktime_get_real())); 896 } 897} 898