1/* 2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux. 3 * 4 * Based on skelton.c by Donald Becker. 5 * 6 * This driver is a replacement of older and less maintained version. 7 * This is a header of the older version: 8 * -----<snip>----- 9 * Copyright 2001 MontaVista Software Inc. 10 * Author: MontaVista Software, Inc. 11 * ahennessy@mvista.com 12 * Copyright (C) 2000-2001 Toshiba Corporation 13 * static const char *version = 14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n"; 15 * -----<snip>----- 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details. 20 * 21 * (C) Copyright TOSHIBA CORPORATION 2004-2005 22 * All Rights Reserved. 23 */ 24 25#define DRV_VERSION "1.39" 26static const char *version = "tc35815.c:v" DRV_VERSION "\n"; 27#define MODNAME "tc35815" 28 29#include <linux/module.h> 30#include <linux/kernel.h> 31#include <linux/types.h> 32#include <linux/fcntl.h> 33#include <linux/interrupt.h> 34#include <linux/ioport.h> 35#include <linux/in.h> 36#include <linux/if_vlan.h> 37#include <linux/slab.h> 38#include <linux/string.h> 39#include <linux/spinlock.h> 40#include <linux/errno.h> 41#include <linux/netdevice.h> 42#include <linux/etherdevice.h> 43#include <linux/skbuff.h> 44#include <linux/delay.h> 45#include <linux/pci.h> 46#include <linux/phy.h> 47#include <linux/workqueue.h> 48#include <linux/platform_device.h> 49#include <linux/prefetch.h> 50#include <asm/io.h> 51#include <asm/byteorder.h> 52 53enum tc35815_chiptype { 54 TC35815CF = 0, 55 TC35815_NWU, 56 TC35815_TX4939, 57}; 58 59/* indexed by tc35815_chiptype, above */ 60static const struct { 61 const char *name; 62} chip_info[] = { 63 { "TOSHIBA TC35815CF 10/100BaseTX" }, 64 { "TOSHIBA TC35815 with Wake on LAN" }, 65 { "TOSHIBA TC35815/TX4939" }, 66}; 67 68static const struct pci_device_id tc35815_pci_tbl[] = { 69 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF }, 70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU }, 71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 }, 72 {0,} 73}; 74MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl); 75 76/* see MODULE_PARM_DESC */ 77static struct tc35815_options { 78 int speed; 79 int duplex; 80} options; 81 82/* 83 * Registers 84 */ 85struct tc35815_regs { 86 __u32 DMA_Ctl; /* 0x00 */ 87 __u32 TxFrmPtr; 88 __u32 TxThrsh; 89 __u32 TxPollCtr; 90 __u32 BLFrmPtr; 91 __u32 RxFragSize; 92 __u32 Int_En; 93 __u32 FDA_Bas; 94 __u32 FDA_Lim; /* 0x20 */ 95 __u32 Int_Src; 96 __u32 unused0[2]; 97 __u32 PauseCnt; 98 __u32 RemPauCnt; 99 __u32 TxCtlFrmStat; 100 __u32 unused1; 101 __u32 MAC_Ctl; /* 0x40 */ 102 __u32 CAM_Ctl; 103 __u32 Tx_Ctl; 104 __u32 Tx_Stat; 105 __u32 Rx_Ctl; 106 __u32 Rx_Stat; 107 __u32 MD_Data; 108 __u32 MD_CA; 109 __u32 CAM_Adr; /* 0x60 */ 110 __u32 CAM_Data; 111 __u32 CAM_Ena; 112 __u32 PROM_Ctl; 113 __u32 PROM_Data; 114 __u32 Algn_Cnt; 115 __u32 CRC_Cnt; 116 __u32 Miss_Cnt; 117}; 118 119/* 120 * Bit assignments 121 */ 122/* DMA_Ctl bit assign ------------------------------------------------------- */ 123#define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ 124#define DMA_RxAlign_1 0x00400000 125#define DMA_RxAlign_2 0x00800000 126#define DMA_RxAlign_3 0x00c00000 127#define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ 128#define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ 129#define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ 130#define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ 131#define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ 132#define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ 133#define DMA_TestMode 0x00002000 /* 1:Test Mode */ 134#define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ 135#define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ 136 137/* RxFragSize bit assign ---------------------------------------------------- */ 138#define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ 139#define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ 140 141/* MAC_Ctl bit assign ------------------------------------------------------- */ 142#define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ 143#define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ 144#define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ 145#define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ 146#define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ 147#define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ 148#define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ 149#define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ 150#define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ 151#define MAC_Reset 0x00000004 /* 1:Software Reset */ 152#define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ 153#define MAC_HaltReq 0x00000001 /* 1:Halt request */ 154 155/* PROM_Ctl bit assign ------------------------------------------------------ */ 156#define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ 157#define PROM_Read 0x00004000 /*10:Read operation */ 158#define PROM_Write 0x00002000 /*01:Write operation */ 159#define PROM_Erase 0x00006000 /*11:Erase operation */ 160 /*00:Enable or Disable Writting, */ 161 /* as specified in PROM_Addr. */ 162#define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ 163 /*00xxxx: disable */ 164 165/* CAM_Ctl bit assign ------------------------------------------------------- */ 166#define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ 167#define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ 168 /* accept other */ 169#define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ 170#define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ 171#define CAM_StationAcc 0x00000001 /* 1:unicast accept */ 172 173/* CAM_Ena bit assign ------------------------------------------------------- */ 174#define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ 175#define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ 176#define CAM_Ena_Bit(index) (1 << (index)) 177#define CAM_ENTRY_DESTINATION 0 178#define CAM_ENTRY_SOURCE 1 179#define CAM_ENTRY_MACCTL 20 180 181/* Tx_Ctl bit assign -------------------------------------------------------- */ 182#define Tx_En 0x00000001 /* 1:Transmit enable */ 183#define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ 184#define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ 185#define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ 186#define Tx_FBack 0x00000010 /* 1:Fast Back-off */ 187#define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ 188#define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ 189#define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ 190#define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ 191#define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ 192#define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ 193#define Tx_EnComp 0x00004000 /* 1:Enable Completion */ 194 195/* Tx_Stat bit assign ------------------------------------------------------- */ 196#define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ 197#define Tx_ExColl 0x00000010 /* Excessive Collision */ 198#define Tx_TXDefer 0x00000020 /* Transmit Defered */ 199#define Tx_Paused 0x00000040 /* Transmit Paused */ 200#define Tx_IntTx 0x00000080 /* Interrupt on Tx */ 201#define Tx_Under 0x00000100 /* Underrun */ 202#define Tx_Defer 0x00000200 /* Deferral */ 203#define Tx_NCarr 0x00000400 /* No Carrier */ 204#define Tx_10Stat 0x00000800 /* 10Mbps Status */ 205#define Tx_LateColl 0x00001000 /* Late Collision */ 206#define Tx_TxPar 0x00002000 /* Tx Parity Error */ 207#define Tx_Comp 0x00004000 /* Completion */ 208#define Tx_Halted 0x00008000 /* Tx Halted */ 209#define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ 210 211/* Rx_Ctl bit assign -------------------------------------------------------- */ 212#define Rx_EnGood 0x00004000 /* 1:Enable Good */ 213#define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ 214#define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ 215#define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ 216#define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ 217#define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ 218#define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ 219#define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ 220#define Rx_ShortEn 0x00000008 /* 1:Short Enable */ 221#define Rx_LongEn 0x00000004 /* 1:Long Enable */ 222#define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ 223#define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ 224 225/* Rx_Stat bit assign ------------------------------------------------------- */ 226#define Rx_Halted 0x00008000 /* Rx Halted */ 227#define Rx_Good 0x00004000 /* Rx Good */ 228#define Rx_RxPar 0x00002000 /* Rx Parity Error */ 229#define Rx_TypePkt 0x00001000 /* Rx Type Packet */ 230#define Rx_LongErr 0x00000800 /* Rx Long Error */ 231#define Rx_Over 0x00000400 /* Rx Overflow */ 232#define Rx_CRCErr 0x00000200 /* Rx CRC Error */ 233#define Rx_Align 0x00000100 /* Rx Alignment Error */ 234#define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ 235#define Rx_IntRx 0x00000040 /* Rx Interrupt */ 236#define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ 237#define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ 238 239#define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ 240 241/* Int_En bit assign -------------------------------------------------------- */ 242#define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ 243#define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ 244#define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ 245#define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ 246#define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ 247#define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ 248#define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ 249#define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ 250#define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ 251#define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ 252#define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ 253#define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ 254 /* Exhausted Enable */ 255 256/* Int_Src bit assign ------------------------------------------------------- */ 257#define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ 258#define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ 259#define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ 260#define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ 261#define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ 262#define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ 263#define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ 264#define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ 265#define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ 266#define Int_SWInt 0x00000020 /* 1:Software request & Clear */ 267#define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ 268#define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ 269#define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ 270#define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ 271#define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ 272 273/* MD_CA bit assign --------------------------------------------------------- */ 274#define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ 275#define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ 276#define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ 277 278 279/* 280 * Descriptors 281 */ 282 283/* Frame descripter */ 284struct FDesc { 285 volatile __u32 FDNext; 286 volatile __u32 FDSystem; 287 volatile __u32 FDStat; 288 volatile __u32 FDCtl; 289}; 290 291/* Buffer descripter */ 292struct BDesc { 293 volatile __u32 BuffData; 294 volatile __u32 BDCtl; 295}; 296 297#define FD_ALIGN 16 298 299/* Frame Descripter bit assign ---------------------------------------------- */ 300#define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ 301#define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ 302#define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ 303#define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ 304#define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ 305#define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ 306#define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ 307#define FD_FrmOpt_Packing 0x04000000 /* Rx only */ 308#define FD_CownsFD 0x80000000 /* FD Controller owner bit */ 309#define FD_Next_EOL 0x00000001 /* FD EOL indicator */ 310#define FD_BDCnt_SHIFT 16 311 312/* Buffer Descripter bit assign --------------------------------------------- */ 313#define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ 314#define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ 315#define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ 316#define BD_CownsBD 0x80000000 /* BD Controller owner bit */ 317#define BD_RxBDID_SHIFT 16 318#define BD_RxBDSeqN_SHIFT 24 319 320 321/* Some useful constants. */ 322 323#define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \ 324 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \ 325 Tx_En) /* maybe 0x7b01 */ 326/* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */ 327#define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \ 328 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */ 329#define INT_EN_CMD (Int_NRAbtEn | \ 330 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \ 331 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \ 332 Int_STargAbtEn | \ 333 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/ 334#define DMA_CTL_CMD DMA_BURST_SIZE 335#define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) 336 337/* Tuning parameters */ 338#define DMA_BURST_SIZE 32 339#define TX_THRESHOLD 1024 340/* used threshold with packet max byte for low pci transfer ability.*/ 341#define TX_THRESHOLD_MAX 1536 342/* setting threshold max value when overrun error occurred this count. */ 343#define TX_THRESHOLD_KEEP_LIMIT 10 344 345/* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ 346#define FD_PAGE_NUM 4 347#define RX_BUF_NUM 128 /* < 256 */ 348#define RX_FD_NUM 256 /* >= 32 */ 349#define TX_FD_NUM 128 350#if RX_CTL_CMD & Rx_LongEn 351#define RX_BUF_SIZE PAGE_SIZE 352#elif RX_CTL_CMD & Rx_StripCRC 353#define RX_BUF_SIZE \ 354 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN) 355#else 356#define RX_BUF_SIZE \ 357 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) 358#endif 359#define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ 360#define NAPI_WEIGHT 16 361 362struct TxFD { 363 struct FDesc fd; 364 struct BDesc bd; 365 struct BDesc unused; 366}; 367 368struct RxFD { 369 struct FDesc fd; 370 struct BDesc bd[0]; /* variable length */ 371}; 372 373struct FrFD { 374 struct FDesc fd; 375 struct BDesc bd[RX_BUF_NUM]; 376}; 377 378 379#define tc_readl(addr) ioread32(addr) 380#define tc_writel(d, addr) iowrite32(d, addr) 381 382#define TC35815_TX_TIMEOUT msecs_to_jiffies(400) 383 384/* Information that need to be kept for each controller. */ 385struct tc35815_local { 386 struct pci_dev *pci_dev; 387 388 struct net_device *dev; 389 struct napi_struct napi; 390 391 /* statistics */ 392 struct { 393 int max_tx_qlen; 394 int tx_ints; 395 int rx_ints; 396 int tx_underrun; 397 } lstats; 398 399 /* Tx control lock. This protects the transmit buffer ring 400 * state along with the "tx full" state of the driver. This 401 * means all netif_queue flow control actions are protected 402 * by this lock as well. 403 */ 404 spinlock_t lock; 405 spinlock_t rx_lock; 406 407 struct mii_bus *mii_bus; 408 struct phy_device *phy_dev; 409 int duplex; 410 int speed; 411 int link; 412 struct work_struct restart_work; 413 414 /* 415 * Transmitting: Batch Mode. 416 * 1 BD in 1 TxFD. 417 * Receiving: Non-Packing Mode. 418 * 1 circular FD for Free Buffer List. 419 * RX_BUF_NUM BD in Free Buffer FD. 420 * One Free Buffer BD has ETH_FRAME_LEN data buffer. 421 */ 422 void *fd_buf; /* for TxFD, RxFD, FrFD */ 423 dma_addr_t fd_buf_dma; 424 struct TxFD *tfd_base; 425 unsigned int tfd_start; 426 unsigned int tfd_end; 427 struct RxFD *rfd_base; 428 struct RxFD *rfd_limit; 429 struct RxFD *rfd_cur; 430 struct FrFD *fbl_ptr; 431 unsigned int fbl_count; 432 struct { 433 struct sk_buff *skb; 434 dma_addr_t skb_dma; 435 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM]; 436 u32 msg_enable; 437 enum tc35815_chiptype chiptype; 438}; 439 440static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt) 441{ 442 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf); 443} 444#ifdef DEBUG 445static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus) 446{ 447 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma)); 448} 449#endif 450static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev, 451 struct pci_dev *hwdev, 452 dma_addr_t *dma_handle) 453{ 454 struct sk_buff *skb; 455 skb = netdev_alloc_skb(dev, RX_BUF_SIZE); 456 if (!skb) 457 return NULL; 458 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, 459 PCI_DMA_FROMDEVICE); 460 if (pci_dma_mapping_error(hwdev, *dma_handle)) { 461 dev_kfree_skb_any(skb); 462 return NULL; 463 } 464 skb_reserve(skb, 2); /* make IP header 4byte aligned */ 465 return skb; 466} 467 468static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) 469{ 470 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, 471 PCI_DMA_FROMDEVICE); 472 dev_kfree_skb_any(skb); 473} 474 475/* Index to functions, as function prototypes. */ 476 477static int tc35815_open(struct net_device *dev); 478static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev); 479static irqreturn_t tc35815_interrupt(int irq, void *dev_id); 480static int tc35815_rx(struct net_device *dev, int limit); 481static int tc35815_poll(struct napi_struct *napi, int budget); 482static void tc35815_txdone(struct net_device *dev); 483static int tc35815_close(struct net_device *dev); 484static struct net_device_stats *tc35815_get_stats(struct net_device *dev); 485static void tc35815_set_multicast_list(struct net_device *dev); 486static void tc35815_tx_timeout(struct net_device *dev); 487static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 488#ifdef CONFIG_NET_POLL_CONTROLLER 489static void tc35815_poll_controller(struct net_device *dev); 490#endif 491static const struct ethtool_ops tc35815_ethtool_ops; 492 493/* Example routines you must write ;->. */ 494static void tc35815_chip_reset(struct net_device *dev); 495static void tc35815_chip_init(struct net_device *dev); 496 497#ifdef DEBUG 498static void panic_queues(struct net_device *dev); 499#endif 500 501static void tc35815_restart_work(struct work_struct *work); 502 503static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 504{ 505 struct net_device *dev = bus->priv; 506 struct tc35815_regs __iomem *tr = 507 (struct tc35815_regs __iomem *)dev->base_addr; 508 unsigned long timeout = jiffies + HZ; 509 510 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); 511 udelay(12); /* it takes 32 x 400ns at least */ 512 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 513 if (time_after(jiffies, timeout)) 514 return -EIO; 515 cpu_relax(); 516 } 517 return tc_readl(&tr->MD_Data) & 0xffff; 518} 519 520static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) 521{ 522 struct net_device *dev = bus->priv; 523 struct tc35815_regs __iomem *tr = 524 (struct tc35815_regs __iomem *)dev->base_addr; 525 unsigned long timeout = jiffies + HZ; 526 527 tc_writel(val, &tr->MD_Data); 528 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f), 529 &tr->MD_CA); 530 udelay(12); /* it takes 32 x 400ns at least */ 531 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 532 if (time_after(jiffies, timeout)) 533 return -EIO; 534 cpu_relax(); 535 } 536 return 0; 537} 538 539static void tc_handle_link_change(struct net_device *dev) 540{ 541 struct tc35815_local *lp = netdev_priv(dev); 542 struct phy_device *phydev = lp->phy_dev; 543 unsigned long flags; 544 int status_change = 0; 545 546 spin_lock_irqsave(&lp->lock, flags); 547 if (phydev->link && 548 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) { 549 struct tc35815_regs __iomem *tr = 550 (struct tc35815_regs __iomem *)dev->base_addr; 551 u32 reg; 552 553 reg = tc_readl(&tr->MAC_Ctl); 554 reg |= MAC_HaltReq; 555 tc_writel(reg, &tr->MAC_Ctl); 556 if (phydev->duplex == DUPLEX_FULL) 557 reg |= MAC_FullDup; 558 else 559 reg &= ~MAC_FullDup; 560 tc_writel(reg, &tr->MAC_Ctl); 561 reg &= ~MAC_HaltReq; 562 tc_writel(reg, &tr->MAC_Ctl); 563 564 /* 565 * TX4939 PCFG.SPEEDn bit will be changed on 566 * NETDEV_CHANGE event. 567 */ 568 /* 569 * WORKAROUND: enable LostCrS only if half duplex 570 * operation. 571 * (TX4939 does not have EnLCarr) 572 */ 573 if (phydev->duplex == DUPLEX_HALF && 574 lp->chiptype != TC35815_TX4939) 575 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, 576 &tr->Tx_Ctl); 577 578 lp->speed = phydev->speed; 579 lp->duplex = phydev->duplex; 580 status_change = 1; 581 } 582 583 if (phydev->link != lp->link) { 584 if (phydev->link) { 585 /* delayed promiscuous enabling */ 586 if (dev->flags & IFF_PROMISC) 587 tc35815_set_multicast_list(dev); 588 } else { 589 lp->speed = 0; 590 lp->duplex = -1; 591 } 592 lp->link = phydev->link; 593 594 status_change = 1; 595 } 596 spin_unlock_irqrestore(&lp->lock, flags); 597 598 if (status_change && netif_msg_link(lp)) { 599 phy_print_status(phydev); 600 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n", 601 dev->name, 602 phy_read(phydev, MII_BMCR), 603 phy_read(phydev, MII_BMSR), 604 phy_read(phydev, MII_LPA)); 605 } 606} 607 608static int tc_mii_probe(struct net_device *dev) 609{ 610 struct tc35815_local *lp = netdev_priv(dev); 611 struct phy_device *phydev = NULL; 612 int phy_addr; 613 u32 dropmask; 614 615 /* find the first phy */ 616 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 617 if (lp->mii_bus->phy_map[phy_addr]) { 618 if (phydev) { 619 printk(KERN_ERR "%s: multiple PHYs found\n", 620 dev->name); 621 return -EINVAL; 622 } 623 phydev = lp->mii_bus->phy_map[phy_addr]; 624 break; 625 } 626 } 627 628 if (!phydev) { 629 printk(KERN_ERR "%s: no PHY found\n", dev->name); 630 return -ENODEV; 631 } 632 633 /* attach the mac to the phy */ 634 phydev = phy_connect(dev, dev_name(&phydev->dev), 635 &tc_handle_link_change, 636 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII); 637 if (IS_ERR(phydev)) { 638 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 639 return PTR_ERR(phydev); 640 } 641 printk(KERN_INFO "%s: attached PHY driver [%s] " 642 "(mii_bus:phy_addr=%s, id=%x)\n", 643 dev->name, phydev->drv->name, dev_name(&phydev->dev), 644 phydev->phy_id); 645 646 /* mask with MAC supported features */ 647 phydev->supported &= PHY_BASIC_FEATURES; 648 dropmask = 0; 649 if (options.speed == 10) 650 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; 651 else if (options.speed == 100) 652 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full; 653 if (options.duplex == 1) 654 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full; 655 else if (options.duplex == 2) 656 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half; 657 phydev->supported &= ~dropmask; 658 phydev->advertising = phydev->supported; 659 660 lp->link = 0; 661 lp->speed = 0; 662 lp->duplex = -1; 663 lp->phy_dev = phydev; 664 665 return 0; 666} 667 668static int tc_mii_init(struct net_device *dev) 669{ 670 struct tc35815_local *lp = netdev_priv(dev); 671 int err; 672 int i; 673 674 lp->mii_bus = mdiobus_alloc(); 675 if (lp->mii_bus == NULL) { 676 err = -ENOMEM; 677 goto err_out; 678 } 679 680 lp->mii_bus->name = "tc35815_mii_bus"; 681 lp->mii_bus->read = tc_mdio_read; 682 lp->mii_bus->write = tc_mdio_write; 683 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 684 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn); 685 lp->mii_bus->priv = dev; 686 lp->mii_bus->parent = &lp->pci_dev->dev; 687 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 688 if (!lp->mii_bus->irq) { 689 err = -ENOMEM; 690 goto err_out_free_mii_bus; 691 } 692 693 for (i = 0; i < PHY_MAX_ADDR; i++) 694 lp->mii_bus->irq[i] = PHY_POLL; 695 696 err = mdiobus_register(lp->mii_bus); 697 if (err) 698 goto err_out_free_mdio_irq; 699 err = tc_mii_probe(dev); 700 if (err) 701 goto err_out_unregister_bus; 702 return 0; 703 704err_out_unregister_bus: 705 mdiobus_unregister(lp->mii_bus); 706err_out_free_mdio_irq: 707 kfree(lp->mii_bus->irq); 708err_out_free_mii_bus: 709 mdiobus_free(lp->mii_bus); 710err_out: 711 return err; 712} 713 714#ifdef CONFIG_CPU_TX49XX 715/* 716 * Find a platform_device providing a MAC address. The platform code 717 * should provide a "tc35815-mac" device with a MAC address in its 718 * platform_data. 719 */ 720static int tc35815_mac_match(struct device *dev, void *data) 721{ 722 struct platform_device *plat_dev = to_platform_device(dev); 723 struct pci_dev *pci_dev = data; 724 unsigned int id = pci_dev->irq; 725 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id; 726} 727 728static int tc35815_read_plat_dev_addr(struct net_device *dev) 729{ 730 struct tc35815_local *lp = netdev_priv(dev); 731 struct device *pd = bus_find_device(&platform_bus_type, NULL, 732 lp->pci_dev, tc35815_mac_match); 733 if (pd) { 734 if (pd->platform_data) 735 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN); 736 put_device(pd); 737 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV; 738 } 739 return -ENODEV; 740} 741#else 742static int tc35815_read_plat_dev_addr(struct net_device *dev) 743{ 744 return -ENODEV; 745} 746#endif 747 748static int tc35815_init_dev_addr(struct net_device *dev) 749{ 750 struct tc35815_regs __iomem *tr = 751 (struct tc35815_regs __iomem *)dev->base_addr; 752 int i; 753 754 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 755 ; 756 for (i = 0; i < 6; i += 2) { 757 unsigned short data; 758 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); 759 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 760 ; 761 data = tc_readl(&tr->PROM_Data); 762 dev->dev_addr[i] = data & 0xff; 763 dev->dev_addr[i+1] = data >> 8; 764 } 765 if (!is_valid_ether_addr(dev->dev_addr)) 766 return tc35815_read_plat_dev_addr(dev); 767 return 0; 768} 769 770static const struct net_device_ops tc35815_netdev_ops = { 771 .ndo_open = tc35815_open, 772 .ndo_stop = tc35815_close, 773 .ndo_start_xmit = tc35815_send_packet, 774 .ndo_get_stats = tc35815_get_stats, 775 .ndo_set_rx_mode = tc35815_set_multicast_list, 776 .ndo_tx_timeout = tc35815_tx_timeout, 777 .ndo_do_ioctl = tc35815_ioctl, 778 .ndo_validate_addr = eth_validate_addr, 779 .ndo_change_mtu = eth_change_mtu, 780 .ndo_set_mac_address = eth_mac_addr, 781#ifdef CONFIG_NET_POLL_CONTROLLER 782 .ndo_poll_controller = tc35815_poll_controller, 783#endif 784}; 785 786static int tc35815_init_one(struct pci_dev *pdev, 787 const struct pci_device_id *ent) 788{ 789 void __iomem *ioaddr = NULL; 790 struct net_device *dev; 791 struct tc35815_local *lp; 792 int rc; 793 794 static int printed_version; 795 if (!printed_version++) { 796 printk(version); 797 dev_printk(KERN_DEBUG, &pdev->dev, 798 "speed:%d duplex:%d\n", 799 options.speed, options.duplex); 800 } 801 802 if (!pdev->irq) { 803 dev_warn(&pdev->dev, "no IRQ assigned.\n"); 804 return -ENODEV; 805 } 806 807 /* dev zeroed in alloc_etherdev */ 808 dev = alloc_etherdev(sizeof(*lp)); 809 if (dev == NULL) 810 return -ENOMEM; 811 812 SET_NETDEV_DEV(dev, &pdev->dev); 813 lp = netdev_priv(dev); 814 lp->dev = dev; 815 816 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 817 rc = pcim_enable_device(pdev); 818 if (rc) 819 goto err_out; 820 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME); 821 if (rc) 822 goto err_out; 823 pci_set_master(pdev); 824 ioaddr = pcim_iomap_table(pdev)[1]; 825 826 /* Initialize the device structure. */ 827 dev->netdev_ops = &tc35815_netdev_ops; 828 dev->ethtool_ops = &tc35815_ethtool_ops; 829 dev->watchdog_timeo = TC35815_TX_TIMEOUT; 830 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT); 831 832 dev->irq = pdev->irq; 833 dev->base_addr = (unsigned long)ioaddr; 834 835 INIT_WORK(&lp->restart_work, tc35815_restart_work); 836 spin_lock_init(&lp->lock); 837 spin_lock_init(&lp->rx_lock); 838 lp->pci_dev = pdev; 839 lp->chiptype = ent->driver_data; 840 841 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK; 842 pci_set_drvdata(pdev, dev); 843 844 /* Soft reset the chip. */ 845 tc35815_chip_reset(dev); 846 847 /* Retrieve the ethernet address. */ 848 if (tc35815_init_dev_addr(dev)) { 849 dev_warn(&pdev->dev, "not valid ether addr\n"); 850 eth_hw_addr_random(dev); 851 } 852 853 rc = register_netdev(dev); 854 if (rc) 855 goto err_out; 856 857 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n", 858 dev->name, 859 chip_info[ent->driver_data].name, 860 dev->base_addr, 861 dev->dev_addr, 862 dev->irq); 863 864 rc = tc_mii_init(dev); 865 if (rc) 866 goto err_out_unregister; 867 868 return 0; 869 870err_out_unregister: 871 unregister_netdev(dev); 872err_out: 873 free_netdev(dev); 874 return rc; 875} 876 877 878static void tc35815_remove_one(struct pci_dev *pdev) 879{ 880 struct net_device *dev = pci_get_drvdata(pdev); 881 struct tc35815_local *lp = netdev_priv(dev); 882 883 phy_disconnect(lp->phy_dev); 884 mdiobus_unregister(lp->mii_bus); 885 kfree(lp->mii_bus->irq); 886 mdiobus_free(lp->mii_bus); 887 unregister_netdev(dev); 888 free_netdev(dev); 889} 890 891static int 892tc35815_init_queues(struct net_device *dev) 893{ 894 struct tc35815_local *lp = netdev_priv(dev); 895 int i; 896 unsigned long fd_addr; 897 898 if (!lp->fd_buf) { 899 BUG_ON(sizeof(struct FDesc) + 900 sizeof(struct BDesc) * RX_BUF_NUM + 901 sizeof(struct FDesc) * RX_FD_NUM + 902 sizeof(struct TxFD) * TX_FD_NUM > 903 PAGE_SIZE * FD_PAGE_NUM); 904 905 lp->fd_buf = pci_alloc_consistent(lp->pci_dev, 906 PAGE_SIZE * FD_PAGE_NUM, 907 &lp->fd_buf_dma); 908 if (!lp->fd_buf) 909 return -ENOMEM; 910 for (i = 0; i < RX_BUF_NUM; i++) { 911 lp->rx_skbs[i].skb = 912 alloc_rxbuf_skb(dev, lp->pci_dev, 913 &lp->rx_skbs[i].skb_dma); 914 if (!lp->rx_skbs[i].skb) { 915 while (--i >= 0) { 916 free_rxbuf_skb(lp->pci_dev, 917 lp->rx_skbs[i].skb, 918 lp->rx_skbs[i].skb_dma); 919 lp->rx_skbs[i].skb = NULL; 920 } 921 pci_free_consistent(lp->pci_dev, 922 PAGE_SIZE * FD_PAGE_NUM, 923 lp->fd_buf, 924 lp->fd_buf_dma); 925 lp->fd_buf = NULL; 926 return -ENOMEM; 927 } 928 } 929 printk(KERN_DEBUG "%s: FD buf %p DataBuf", 930 dev->name, lp->fd_buf); 931 printk("\n"); 932 } else { 933 for (i = 0; i < FD_PAGE_NUM; i++) 934 clear_page((void *)((unsigned long)lp->fd_buf + 935 i * PAGE_SIZE)); 936 } 937 fd_addr = (unsigned long)lp->fd_buf; 938 939 /* Free Descriptors (for Receive) */ 940 lp->rfd_base = (struct RxFD *)fd_addr; 941 fd_addr += sizeof(struct RxFD) * RX_FD_NUM; 942 for (i = 0; i < RX_FD_NUM; i++) 943 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD); 944 lp->rfd_cur = lp->rfd_base; 945 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1); 946 947 /* Transmit Descriptors */ 948 lp->tfd_base = (struct TxFD *)fd_addr; 949 fd_addr += sizeof(struct TxFD) * TX_FD_NUM; 950 for (i = 0; i < TX_FD_NUM; i++) { 951 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1])); 952 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 953 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0); 954 } 955 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0])); 956 lp->tfd_start = 0; 957 lp->tfd_end = 0; 958 959 /* Buffer List (for Receive) */ 960 lp->fbl_ptr = (struct FrFD *)fd_addr; 961 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr)); 962 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD); 963 /* 964 * move all allocated skbs to head of rx_skbs[] array. 965 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in 966 * tc35815_rx() had failed. 967 */ 968 lp->fbl_count = 0; 969 for (i = 0; i < RX_BUF_NUM; i++) { 970 if (lp->rx_skbs[i].skb) { 971 if (i != lp->fbl_count) { 972 lp->rx_skbs[lp->fbl_count].skb = 973 lp->rx_skbs[i].skb; 974 lp->rx_skbs[lp->fbl_count].skb_dma = 975 lp->rx_skbs[i].skb_dma; 976 } 977 lp->fbl_count++; 978 } 979 } 980 for (i = 0; i < RX_BUF_NUM; i++) { 981 if (i >= lp->fbl_count) { 982 lp->fbl_ptr->bd[i].BuffData = 0; 983 lp->fbl_ptr->bd[i].BDCtl = 0; 984 continue; 985 } 986 lp->fbl_ptr->bd[i].BuffData = 987 cpu_to_le32(lp->rx_skbs[i].skb_dma); 988 /* BDID is index of FrFD.bd[] */ 989 lp->fbl_ptr->bd[i].BDCtl = 990 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | 991 RX_BUF_SIZE); 992 } 993 994 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n", 995 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr); 996 return 0; 997} 998 999static void 1000tc35815_clear_queues(struct net_device *dev) 1001{ 1002 struct tc35815_local *lp = netdev_priv(dev); 1003 int i; 1004 1005 for (i = 0; i < TX_FD_NUM; i++) { 1006 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1007 struct sk_buff *skb = 1008 fdsystem != 0xffffffff ? 1009 lp->tx_skbs[fdsystem].skb : NULL; 1010#ifdef DEBUG 1011 if (lp->tx_skbs[i].skb != skb) { 1012 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1013 panic_queues(dev); 1014 } 1015#else 1016 BUG_ON(lp->tx_skbs[i].skb != skb); 1017#endif 1018 if (skb) { 1019 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1020 lp->tx_skbs[i].skb = NULL; 1021 lp->tx_skbs[i].skb_dma = 0; 1022 dev_kfree_skb_any(skb); 1023 } 1024 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1025 } 1026 1027 tc35815_init_queues(dev); 1028} 1029 1030static void 1031tc35815_free_queues(struct net_device *dev) 1032{ 1033 struct tc35815_local *lp = netdev_priv(dev); 1034 int i; 1035 1036 if (lp->tfd_base) { 1037 for (i = 0; i < TX_FD_NUM; i++) { 1038 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1039 struct sk_buff *skb = 1040 fdsystem != 0xffffffff ? 1041 lp->tx_skbs[fdsystem].skb : NULL; 1042#ifdef DEBUG 1043 if (lp->tx_skbs[i].skb != skb) { 1044 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1045 panic_queues(dev); 1046 } 1047#else 1048 BUG_ON(lp->tx_skbs[i].skb != skb); 1049#endif 1050 if (skb) { 1051 dev_kfree_skb(skb); 1052 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1053 lp->tx_skbs[i].skb = NULL; 1054 lp->tx_skbs[i].skb_dma = 0; 1055 } 1056 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1057 } 1058 } 1059 1060 lp->rfd_base = NULL; 1061 lp->rfd_limit = NULL; 1062 lp->rfd_cur = NULL; 1063 lp->fbl_ptr = NULL; 1064 1065 for (i = 0; i < RX_BUF_NUM; i++) { 1066 if (lp->rx_skbs[i].skb) { 1067 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb, 1068 lp->rx_skbs[i].skb_dma); 1069 lp->rx_skbs[i].skb = NULL; 1070 } 1071 } 1072 if (lp->fd_buf) { 1073 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, 1074 lp->fd_buf, lp->fd_buf_dma); 1075 lp->fd_buf = NULL; 1076 } 1077} 1078 1079static void 1080dump_txfd(struct TxFD *fd) 1081{ 1082 printk("TxFD(%p): %08x %08x %08x %08x\n", fd, 1083 le32_to_cpu(fd->fd.FDNext), 1084 le32_to_cpu(fd->fd.FDSystem), 1085 le32_to_cpu(fd->fd.FDStat), 1086 le32_to_cpu(fd->fd.FDCtl)); 1087 printk("BD: "); 1088 printk(" %08x %08x", 1089 le32_to_cpu(fd->bd.BuffData), 1090 le32_to_cpu(fd->bd.BDCtl)); 1091 printk("\n"); 1092} 1093 1094static int 1095dump_rxfd(struct RxFD *fd) 1096{ 1097 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1098 if (bd_count > 8) 1099 bd_count = 8; 1100 printk("RxFD(%p): %08x %08x %08x %08x\n", fd, 1101 le32_to_cpu(fd->fd.FDNext), 1102 le32_to_cpu(fd->fd.FDSystem), 1103 le32_to_cpu(fd->fd.FDStat), 1104 le32_to_cpu(fd->fd.FDCtl)); 1105 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD) 1106 return 0; 1107 printk("BD: "); 1108 for (i = 0; i < bd_count; i++) 1109 printk(" %08x %08x", 1110 le32_to_cpu(fd->bd[i].BuffData), 1111 le32_to_cpu(fd->bd[i].BDCtl)); 1112 printk("\n"); 1113 return bd_count; 1114} 1115 1116#ifdef DEBUG 1117static void 1118dump_frfd(struct FrFD *fd) 1119{ 1120 int i; 1121 printk("FrFD(%p): %08x %08x %08x %08x\n", fd, 1122 le32_to_cpu(fd->fd.FDNext), 1123 le32_to_cpu(fd->fd.FDSystem), 1124 le32_to_cpu(fd->fd.FDStat), 1125 le32_to_cpu(fd->fd.FDCtl)); 1126 printk("BD: "); 1127 for (i = 0; i < RX_BUF_NUM; i++) 1128 printk(" %08x %08x", 1129 le32_to_cpu(fd->bd[i].BuffData), 1130 le32_to_cpu(fd->bd[i].BDCtl)); 1131 printk("\n"); 1132} 1133 1134static void 1135panic_queues(struct net_device *dev) 1136{ 1137 struct tc35815_local *lp = netdev_priv(dev); 1138 int i; 1139 1140 printk("TxFD base %p, start %u, end %u\n", 1141 lp->tfd_base, lp->tfd_start, lp->tfd_end); 1142 printk("RxFD base %p limit %p cur %p\n", 1143 lp->rfd_base, lp->rfd_limit, lp->rfd_cur); 1144 printk("FrFD %p\n", lp->fbl_ptr); 1145 for (i = 0; i < TX_FD_NUM; i++) 1146 dump_txfd(&lp->tfd_base[i]); 1147 for (i = 0; i < RX_FD_NUM; i++) { 1148 int bd_count = dump_rxfd(&lp->rfd_base[i]); 1149 i += (bd_count + 1) / 2; /* skip BDs */ 1150 } 1151 dump_frfd(lp->fbl_ptr); 1152 panic("%s: Illegal queue state.", dev->name); 1153} 1154#endif 1155 1156static void print_eth(const u8 *add) 1157{ 1158 printk(KERN_DEBUG "print_eth(%p)\n", add); 1159 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n", 1160 add + 6, add, add[12], add[13]); 1161} 1162 1163static int tc35815_tx_full(struct net_device *dev) 1164{ 1165 struct tc35815_local *lp = netdev_priv(dev); 1166 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end; 1167} 1168 1169static void tc35815_restart(struct net_device *dev) 1170{ 1171 struct tc35815_local *lp = netdev_priv(dev); 1172 int ret; 1173 1174 if (lp->phy_dev) { 1175 ret = phy_init_hw(lp->phy_dev); 1176 if (ret) 1177 printk(KERN_ERR "%s: PHY init failed.\n", dev->name); 1178 } 1179 1180 spin_lock_bh(&lp->rx_lock); 1181 spin_lock_irq(&lp->lock); 1182 tc35815_chip_reset(dev); 1183 tc35815_clear_queues(dev); 1184 tc35815_chip_init(dev); 1185 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */ 1186 tc35815_set_multicast_list(dev); 1187 spin_unlock_irq(&lp->lock); 1188 spin_unlock_bh(&lp->rx_lock); 1189 1190 netif_wake_queue(dev); 1191} 1192 1193static void tc35815_restart_work(struct work_struct *work) 1194{ 1195 struct tc35815_local *lp = 1196 container_of(work, struct tc35815_local, restart_work); 1197 struct net_device *dev = lp->dev; 1198 1199 tc35815_restart(dev); 1200} 1201 1202static void tc35815_schedule_restart(struct net_device *dev) 1203{ 1204 struct tc35815_local *lp = netdev_priv(dev); 1205 struct tc35815_regs __iomem *tr = 1206 (struct tc35815_regs __iomem *)dev->base_addr; 1207 unsigned long flags; 1208 1209 /* disable interrupts */ 1210 spin_lock_irqsave(&lp->lock, flags); 1211 tc_writel(0, &tr->Int_En); 1212 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); 1213 schedule_work(&lp->restart_work); 1214 spin_unlock_irqrestore(&lp->lock, flags); 1215} 1216 1217static void tc35815_tx_timeout(struct net_device *dev) 1218{ 1219 struct tc35815_regs __iomem *tr = 1220 (struct tc35815_regs __iomem *)dev->base_addr; 1221 1222 printk(KERN_WARNING "%s: transmit timed out, status %#x\n", 1223 dev->name, tc_readl(&tr->Tx_Stat)); 1224 1225 /* Try to restart the adaptor. */ 1226 tc35815_schedule_restart(dev); 1227 dev->stats.tx_errors++; 1228} 1229 1230/* 1231 * Open/initialize the controller. This is called (in the current kernel) 1232 * sometime after booting when the 'ifconfig' program is run. 1233 * 1234 * This routine should set everything up anew at each open, even 1235 * registers that "should" only need to be set once at boot, so that 1236 * there is non-reboot way to recover if something goes wrong. 1237 */ 1238static int 1239tc35815_open(struct net_device *dev) 1240{ 1241 struct tc35815_local *lp = netdev_priv(dev); 1242 1243 /* 1244 * This is used if the interrupt line can turned off (shared). 1245 * See 3c503.c for an example of selecting the IRQ at config-time. 1246 */ 1247 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED, 1248 dev->name, dev)) 1249 return -EAGAIN; 1250 1251 tc35815_chip_reset(dev); 1252 1253 if (tc35815_init_queues(dev) != 0) { 1254 free_irq(dev->irq, dev); 1255 return -EAGAIN; 1256 } 1257 1258 napi_enable(&lp->napi); 1259 1260 /* Reset the hardware here. Don't forget to set the station address. */ 1261 spin_lock_irq(&lp->lock); 1262 tc35815_chip_init(dev); 1263 spin_unlock_irq(&lp->lock); 1264 1265 netif_carrier_off(dev); 1266 /* schedule a link state check */ 1267 phy_start(lp->phy_dev); 1268 1269 /* We are now ready to accept transmit requeusts from 1270 * the queueing layer of the networking. 1271 */ 1272 netif_start_queue(dev); 1273 1274 return 0; 1275} 1276 1277/* This will only be invoked if your driver is _not_ in XOFF state. 1278 * What this means is that you need not check it, and that this 1279 * invariant will hold if you make sure that the netif_*_queue() 1280 * calls are done at the proper times. 1281 */ 1282static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev) 1283{ 1284 struct tc35815_local *lp = netdev_priv(dev); 1285 struct TxFD *txfd; 1286 unsigned long flags; 1287 1288 /* If some error occurs while trying to transmit this 1289 * packet, you should return '1' from this function. 1290 * In such a case you _may not_ do anything to the 1291 * SKB, it is still owned by the network queueing 1292 * layer when an error is returned. This means you 1293 * may not modify any SKB fields, you may not free 1294 * the SKB, etc. 1295 */ 1296 1297 /* This is the most common case for modern hardware. 1298 * The spinlock protects this code from the TX complete 1299 * hardware interrupt handler. Queue flow control is 1300 * thus managed under this lock as well. 1301 */ 1302 spin_lock_irqsave(&lp->lock, flags); 1303 1304 /* failsafe... (handle txdone now if half of FDs are used) */ 1305 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM > 1306 TX_FD_NUM / 2) 1307 tc35815_txdone(dev); 1308 1309 if (netif_msg_pktdata(lp)) 1310 print_eth(skb->data); 1311#ifdef DEBUG 1312 if (lp->tx_skbs[lp->tfd_start].skb) { 1313 printk("%s: tx_skbs conflict.\n", dev->name); 1314 panic_queues(dev); 1315 } 1316#else 1317 BUG_ON(lp->tx_skbs[lp->tfd_start].skb); 1318#endif 1319 lp->tx_skbs[lp->tfd_start].skb = skb; 1320 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 1321 1322 /*add to ring */ 1323 txfd = &lp->tfd_base[lp->tfd_start]; 1324 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma); 1325 txfd->bd.BDCtl = cpu_to_le32(skb->len); 1326 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start); 1327 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT)); 1328 1329 if (lp->tfd_start == lp->tfd_end) { 1330 struct tc35815_regs __iomem *tr = 1331 (struct tc35815_regs __iomem *)dev->base_addr; 1332 /* Start DMA Transmitter. */ 1333 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1334 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1335 if (netif_msg_tx_queued(lp)) { 1336 printk("%s: starting TxFD.\n", dev->name); 1337 dump_txfd(txfd); 1338 } 1339 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1340 } else { 1341 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL); 1342 if (netif_msg_tx_queued(lp)) { 1343 printk("%s: queueing TxFD.\n", dev->name); 1344 dump_txfd(txfd); 1345 } 1346 } 1347 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM; 1348 1349 /* If we just used up the very last entry in the 1350 * TX ring on this device, tell the queueing 1351 * layer to send no more. 1352 */ 1353 if (tc35815_tx_full(dev)) { 1354 if (netif_msg_tx_queued(lp)) 1355 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name); 1356 netif_stop_queue(dev); 1357 } 1358 1359 /* When the TX completion hw interrupt arrives, this 1360 * is when the transmit statistics are updated. 1361 */ 1362 1363 spin_unlock_irqrestore(&lp->lock, flags); 1364 return NETDEV_TX_OK; 1365} 1366 1367#define FATAL_ERROR_INT \ 1368 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) 1369static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status) 1370{ 1371 static int count; 1372 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):", 1373 dev->name, status); 1374 if (status & Int_IntPCI) 1375 printk(" IntPCI"); 1376 if (status & Int_DmParErr) 1377 printk(" DmParErr"); 1378 if (status & Int_IntNRAbt) 1379 printk(" IntNRAbt"); 1380 printk("\n"); 1381 if (count++ > 100) 1382 panic("%s: Too many fatal errors.", dev->name); 1383 printk(KERN_WARNING "%s: Resetting ...\n", dev->name); 1384 /* Try to restart the adaptor. */ 1385 tc35815_schedule_restart(dev); 1386} 1387 1388static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit) 1389{ 1390 struct tc35815_local *lp = netdev_priv(dev); 1391 int ret = -1; 1392 1393 /* Fatal errors... */ 1394 if (status & FATAL_ERROR_INT) { 1395 tc35815_fatal_error_interrupt(dev, status); 1396 return 0; 1397 } 1398 /* recoverable errors */ 1399 if (status & Int_IntFDAEx) { 1400 if (netif_msg_rx_err(lp)) 1401 dev_warn(&dev->dev, 1402 "Free Descriptor Area Exhausted (%#x).\n", 1403 status); 1404 dev->stats.rx_dropped++; 1405 ret = 0; 1406 } 1407 if (status & Int_IntBLEx) { 1408 if (netif_msg_rx_err(lp)) 1409 dev_warn(&dev->dev, 1410 "Buffer List Exhausted (%#x).\n", 1411 status); 1412 dev->stats.rx_dropped++; 1413 ret = 0; 1414 } 1415 if (status & Int_IntExBD) { 1416 if (netif_msg_rx_err(lp)) 1417 dev_warn(&dev->dev, 1418 "Excessive Buffer Descriptiors (%#x).\n", 1419 status); 1420 dev->stats.rx_length_errors++; 1421 ret = 0; 1422 } 1423 1424 /* normal notification */ 1425 if (status & Int_IntMacRx) { 1426 /* Got a packet(s). */ 1427 ret = tc35815_rx(dev, limit); 1428 lp->lstats.rx_ints++; 1429 } 1430 if (status & Int_IntMacTx) { 1431 /* Transmit complete. */ 1432 lp->lstats.tx_ints++; 1433 spin_lock_irq(&lp->lock); 1434 tc35815_txdone(dev); 1435 spin_unlock_irq(&lp->lock); 1436 if (ret < 0) 1437 ret = 0; 1438 } 1439 return ret; 1440} 1441 1442/* 1443 * The typical workload of the driver: 1444 * Handle the network interface interrupts. 1445 */ 1446static irqreturn_t tc35815_interrupt(int irq, void *dev_id) 1447{ 1448 struct net_device *dev = dev_id; 1449 struct tc35815_local *lp = netdev_priv(dev); 1450 struct tc35815_regs __iomem *tr = 1451 (struct tc35815_regs __iomem *)dev->base_addr; 1452 u32 dmactl = tc_readl(&tr->DMA_Ctl); 1453 1454 if (!(dmactl & DMA_IntMask)) { 1455 /* disable interrupts */ 1456 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); 1457 if (napi_schedule_prep(&lp->napi)) 1458 __napi_schedule(&lp->napi); 1459 else { 1460 printk(KERN_ERR "%s: interrupt taken in poll\n", 1461 dev->name); 1462 BUG(); 1463 } 1464 (void)tc_readl(&tr->Int_Src); /* flush */ 1465 return IRQ_HANDLED; 1466 } 1467 return IRQ_NONE; 1468} 1469 1470#ifdef CONFIG_NET_POLL_CONTROLLER 1471static void tc35815_poll_controller(struct net_device *dev) 1472{ 1473 disable_irq(dev->irq); 1474 tc35815_interrupt(dev->irq, dev); 1475 enable_irq(dev->irq); 1476} 1477#endif 1478 1479/* We have a good packet(s), get it/them out of the buffers. */ 1480static int 1481tc35815_rx(struct net_device *dev, int limit) 1482{ 1483 struct tc35815_local *lp = netdev_priv(dev); 1484 unsigned int fdctl; 1485 int i; 1486 int received = 0; 1487 1488 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) { 1489 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat); 1490 int pkt_len = fdctl & FD_FDLength_MASK; 1491 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1492#ifdef DEBUG 1493 struct RxFD *next_rfd; 1494#endif 1495#if (RX_CTL_CMD & Rx_StripCRC) == 0 1496 pkt_len -= ETH_FCS_LEN; 1497#endif 1498 1499 if (netif_msg_rx_status(lp)) 1500 dump_rxfd(lp->rfd_cur); 1501 if (status & Rx_Good) { 1502 struct sk_buff *skb; 1503 unsigned char *data; 1504 int cur_bd; 1505 1506 if (--limit < 0) 1507 break; 1508 BUG_ON(bd_count > 1); 1509 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl) 1510 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1511#ifdef DEBUG 1512 if (cur_bd >= RX_BUF_NUM) { 1513 printk("%s: invalid BDID.\n", dev->name); 1514 panic_queues(dev); 1515 } 1516 BUG_ON(lp->rx_skbs[cur_bd].skb_dma != 1517 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3)); 1518 if (!lp->rx_skbs[cur_bd].skb) { 1519 printk("%s: NULL skb.\n", dev->name); 1520 panic_queues(dev); 1521 } 1522#else 1523 BUG_ON(cur_bd >= RX_BUF_NUM); 1524#endif 1525 skb = lp->rx_skbs[cur_bd].skb; 1526 prefetch(skb->data); 1527 lp->rx_skbs[cur_bd].skb = NULL; 1528 pci_unmap_single(lp->pci_dev, 1529 lp->rx_skbs[cur_bd].skb_dma, 1530 RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 1531 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN) 1532 memmove(skb->data, skb->data - NET_IP_ALIGN, 1533 pkt_len); 1534 data = skb_put(skb, pkt_len); 1535 if (netif_msg_pktdata(lp)) 1536 print_eth(data); 1537 skb->protocol = eth_type_trans(skb, dev); 1538 netif_receive_skb(skb); 1539 received++; 1540 dev->stats.rx_packets++; 1541 dev->stats.rx_bytes += pkt_len; 1542 } else { 1543 dev->stats.rx_errors++; 1544 if (netif_msg_rx_err(lp)) 1545 dev_info(&dev->dev, "Rx error (status %x)\n", 1546 status & Rx_Stat_Mask); 1547 /* WORKAROUND: LongErr and CRCErr means Overflow. */ 1548 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { 1549 status &= ~(Rx_LongErr|Rx_CRCErr); 1550 status |= Rx_Over; 1551 } 1552 if (status & Rx_LongErr) 1553 dev->stats.rx_length_errors++; 1554 if (status & Rx_Over) 1555 dev->stats.rx_fifo_errors++; 1556 if (status & Rx_CRCErr) 1557 dev->stats.rx_crc_errors++; 1558 if (status & Rx_Align) 1559 dev->stats.rx_frame_errors++; 1560 } 1561 1562 if (bd_count > 0) { 1563 /* put Free Buffer back to controller */ 1564 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl); 1565 unsigned char id = 1566 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1567#ifdef DEBUG 1568 if (id >= RX_BUF_NUM) { 1569 printk("%s: invalid BDID.\n", dev->name); 1570 panic_queues(dev); 1571 } 1572#else 1573 BUG_ON(id >= RX_BUF_NUM); 1574#endif 1575 /* free old buffers */ 1576 lp->fbl_count--; 1577 while (lp->fbl_count < RX_BUF_NUM) 1578 { 1579 unsigned char curid = 1580 (id + 1 + lp->fbl_count) % RX_BUF_NUM; 1581 struct BDesc *bd = &lp->fbl_ptr->bd[curid]; 1582#ifdef DEBUG 1583 bdctl = le32_to_cpu(bd->BDCtl); 1584 if (bdctl & BD_CownsBD) { 1585 printk("%s: Freeing invalid BD.\n", 1586 dev->name); 1587 panic_queues(dev); 1588 } 1589#endif 1590 /* pass BD to controller */ 1591 if (!lp->rx_skbs[curid].skb) { 1592 lp->rx_skbs[curid].skb = 1593 alloc_rxbuf_skb(dev, 1594 lp->pci_dev, 1595 &lp->rx_skbs[curid].skb_dma); 1596 if (!lp->rx_skbs[curid].skb) 1597 break; /* try on next reception */ 1598 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma); 1599 } 1600 /* Note: BDLength was modified by chip. */ 1601 bd->BDCtl = cpu_to_le32(BD_CownsBD | 1602 (curid << BD_RxBDID_SHIFT) | 1603 RX_BUF_SIZE); 1604 lp->fbl_count++; 1605 } 1606 } 1607 1608 /* put RxFD back to controller */ 1609#ifdef DEBUG 1610 next_rfd = fd_bus_to_virt(lp, 1611 le32_to_cpu(lp->rfd_cur->fd.FDNext)); 1612 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) { 1613 printk("%s: RxFD FDNext invalid.\n", dev->name); 1614 panic_queues(dev); 1615 } 1616#endif 1617 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) { 1618 /* pass FD to controller */ 1619#ifdef DEBUG 1620 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); 1621#else 1622 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL); 1623#endif 1624 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD); 1625 lp->rfd_cur++; 1626 } 1627 if (lp->rfd_cur > lp->rfd_limit) 1628 lp->rfd_cur = lp->rfd_base; 1629#ifdef DEBUG 1630 if (lp->rfd_cur != next_rfd) 1631 printk("rfd_cur = %p, next_rfd %p\n", 1632 lp->rfd_cur, next_rfd); 1633#endif 1634 } 1635 1636 return received; 1637} 1638 1639static int tc35815_poll(struct napi_struct *napi, int budget) 1640{ 1641 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi); 1642 struct net_device *dev = lp->dev; 1643 struct tc35815_regs __iomem *tr = 1644 (struct tc35815_regs __iomem *)dev->base_addr; 1645 int received = 0, handled; 1646 u32 status; 1647 1648 if (budget <= 0) 1649 return received; 1650 1651 spin_lock(&lp->rx_lock); 1652 status = tc_readl(&tr->Int_Src); 1653 do { 1654 /* BLEx, FDAEx will be cleared later */ 1655 tc_writel(status & ~(Int_BLEx | Int_FDAEx), 1656 &tr->Int_Src); /* write to clear */ 1657 1658 handled = tc35815_do_interrupt(dev, status, budget - received); 1659 if (status & (Int_BLEx | Int_FDAEx)) 1660 tc_writel(status & (Int_BLEx | Int_FDAEx), 1661 &tr->Int_Src); 1662 if (handled >= 0) { 1663 received += handled; 1664 if (received >= budget) 1665 break; 1666 } 1667 status = tc_readl(&tr->Int_Src); 1668 } while (status); 1669 spin_unlock(&lp->rx_lock); 1670 1671 if (received < budget) { 1672 napi_complete(napi); 1673 /* enable interrupts */ 1674 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); 1675 } 1676 return received; 1677} 1678 1679#define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) 1680 1681static void 1682tc35815_check_tx_stat(struct net_device *dev, int status) 1683{ 1684 struct tc35815_local *lp = netdev_priv(dev); 1685 const char *msg = NULL; 1686 1687 /* count collisions */ 1688 if (status & Tx_ExColl) 1689 dev->stats.collisions += 16; 1690 if (status & Tx_TxColl_MASK) 1691 dev->stats.collisions += status & Tx_TxColl_MASK; 1692 1693 /* TX4939 does not have NCarr */ 1694 if (lp->chiptype == TC35815_TX4939) 1695 status &= ~Tx_NCarr; 1696 /* WORKAROUND: ignore LostCrS in full duplex operation */ 1697 if (!lp->link || lp->duplex == DUPLEX_FULL) 1698 status &= ~Tx_NCarr; 1699 1700 if (!(status & TX_STA_ERR)) { 1701 /* no error. */ 1702 dev->stats.tx_packets++; 1703 return; 1704 } 1705 1706 dev->stats.tx_errors++; 1707 if (status & Tx_ExColl) { 1708 dev->stats.tx_aborted_errors++; 1709 msg = "Excessive Collision."; 1710 } 1711 if (status & Tx_Under) { 1712 dev->stats.tx_fifo_errors++; 1713 msg = "Tx FIFO Underrun."; 1714 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) { 1715 lp->lstats.tx_underrun++; 1716 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) { 1717 struct tc35815_regs __iomem *tr = 1718 (struct tc35815_regs __iomem *)dev->base_addr; 1719 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); 1720 msg = "Tx FIFO Underrun.Change Tx threshold to max."; 1721 } 1722 } 1723 } 1724 if (status & Tx_Defer) { 1725 dev->stats.tx_fifo_errors++; 1726 msg = "Excessive Deferral."; 1727 } 1728 if (status & Tx_NCarr) { 1729 dev->stats.tx_carrier_errors++; 1730 msg = "Lost Carrier Sense."; 1731 } 1732 if (status & Tx_LateColl) { 1733 dev->stats.tx_aborted_errors++; 1734 msg = "Late Collision."; 1735 } 1736 if (status & Tx_TxPar) { 1737 dev->stats.tx_fifo_errors++; 1738 msg = "Transmit Parity Error."; 1739 } 1740 if (status & Tx_SQErr) { 1741 dev->stats.tx_heartbeat_errors++; 1742 msg = "Signal Quality Error."; 1743 } 1744 if (msg && netif_msg_tx_err(lp)) 1745 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status); 1746} 1747 1748/* This handles TX complete events posted by the device 1749 * via interrupts. 1750 */ 1751static void 1752tc35815_txdone(struct net_device *dev) 1753{ 1754 struct tc35815_local *lp = netdev_priv(dev); 1755 struct TxFD *txfd; 1756 unsigned int fdctl; 1757 1758 txfd = &lp->tfd_base[lp->tfd_end]; 1759 while (lp->tfd_start != lp->tfd_end && 1760 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) { 1761 int status = le32_to_cpu(txfd->fd.FDStat); 1762 struct sk_buff *skb; 1763 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext); 1764 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem); 1765 1766 if (netif_msg_tx_done(lp)) { 1767 printk("%s: complete TxFD.\n", dev->name); 1768 dump_txfd(txfd); 1769 } 1770 tc35815_check_tx_stat(dev, status); 1771 1772 skb = fdsystem != 0xffffffff ? 1773 lp->tx_skbs[fdsystem].skb : NULL; 1774#ifdef DEBUG 1775 if (lp->tx_skbs[lp->tfd_end].skb != skb) { 1776 printk("%s: tx_skbs mismatch.\n", dev->name); 1777 panic_queues(dev); 1778 } 1779#else 1780 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb); 1781#endif 1782 if (skb) { 1783 dev->stats.tx_bytes += skb->len; 1784 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE); 1785 lp->tx_skbs[lp->tfd_end].skb = NULL; 1786 lp->tx_skbs[lp->tfd_end].skb_dma = 0; 1787 dev_kfree_skb_any(skb); 1788 } 1789 txfd->fd.FDSystem = cpu_to_le32(0xffffffff); 1790 1791 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM; 1792 txfd = &lp->tfd_base[lp->tfd_end]; 1793#ifdef DEBUG 1794 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) { 1795 printk("%s: TxFD FDNext invalid.\n", dev->name); 1796 panic_queues(dev); 1797 } 1798#endif 1799 if (fdnext & FD_Next_EOL) { 1800 /* DMA Transmitter has been stopping... */ 1801 if (lp->tfd_end != lp->tfd_start) { 1802 struct tc35815_regs __iomem *tr = 1803 (struct tc35815_regs __iomem *)dev->base_addr; 1804 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM; 1805 struct TxFD *txhead = &lp->tfd_base[head]; 1806 int qlen = (lp->tfd_start + TX_FD_NUM 1807 - lp->tfd_end) % TX_FD_NUM; 1808 1809#ifdef DEBUG 1810 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) { 1811 printk("%s: TxFD FDCtl invalid.\n", dev->name); 1812 panic_queues(dev); 1813 } 1814#endif 1815 /* log max queue length */ 1816 if (lp->lstats.max_tx_qlen < qlen) 1817 lp->lstats.max_tx_qlen = qlen; 1818 1819 1820 /* start DMA Transmitter again */ 1821 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1822 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1823 if (netif_msg_tx_queued(lp)) { 1824 printk("%s: start TxFD on queue.\n", 1825 dev->name); 1826 dump_txfd(txfd); 1827 } 1828 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1829 } 1830 break; 1831 } 1832 } 1833 1834 /* If we had stopped the queue due to a "tx full" 1835 * condition, and space has now been made available, 1836 * wake up the queue. 1837 */ 1838 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev)) 1839 netif_wake_queue(dev); 1840} 1841 1842/* The inverse routine to tc35815_open(). */ 1843static int 1844tc35815_close(struct net_device *dev) 1845{ 1846 struct tc35815_local *lp = netdev_priv(dev); 1847 1848 netif_stop_queue(dev); 1849 napi_disable(&lp->napi); 1850 if (lp->phy_dev) 1851 phy_stop(lp->phy_dev); 1852 cancel_work_sync(&lp->restart_work); 1853 1854 /* Flush the Tx and disable Rx here. */ 1855 tc35815_chip_reset(dev); 1856 free_irq(dev->irq, dev); 1857 1858 tc35815_free_queues(dev); 1859 1860 return 0; 1861 1862} 1863 1864/* 1865 * Get the current statistics. 1866 * This may be called with the card open or closed. 1867 */ 1868static struct net_device_stats *tc35815_get_stats(struct net_device *dev) 1869{ 1870 struct tc35815_regs __iomem *tr = 1871 (struct tc35815_regs __iomem *)dev->base_addr; 1872 if (netif_running(dev)) 1873 /* Update the statistics from the device registers. */ 1874 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); 1875 1876 return &dev->stats; 1877} 1878 1879static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr) 1880{ 1881 struct tc35815_local *lp = netdev_priv(dev); 1882 struct tc35815_regs __iomem *tr = 1883 (struct tc35815_regs __iomem *)dev->base_addr; 1884 int cam_index = index * 6; 1885 u32 cam_data; 1886 u32 saved_addr; 1887 1888 saved_addr = tc_readl(&tr->CAM_Adr); 1889 1890 if (netif_msg_hw(lp)) 1891 printk(KERN_DEBUG "%s: CAM %d: %pM\n", 1892 dev->name, index, addr); 1893 if (index & 1) { 1894 /* read modify write */ 1895 tc_writel(cam_index - 2, &tr->CAM_Adr); 1896 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; 1897 cam_data |= addr[0] << 8 | addr[1]; 1898 tc_writel(cam_data, &tr->CAM_Data); 1899 /* write whole word */ 1900 tc_writel(cam_index + 2, &tr->CAM_Adr); 1901 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; 1902 tc_writel(cam_data, &tr->CAM_Data); 1903 } else { 1904 /* write whole word */ 1905 tc_writel(cam_index, &tr->CAM_Adr); 1906 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 1907 tc_writel(cam_data, &tr->CAM_Data); 1908 /* read modify write */ 1909 tc_writel(cam_index + 4, &tr->CAM_Adr); 1910 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; 1911 cam_data |= addr[4] << 24 | (addr[5] << 16); 1912 tc_writel(cam_data, &tr->CAM_Data); 1913 } 1914 1915 tc_writel(saved_addr, &tr->CAM_Adr); 1916} 1917 1918 1919/* 1920 * Set or clear the multicast filter for this adaptor. 1921 * num_addrs == -1 Promiscuous mode, receive all packets 1922 * num_addrs == 0 Normal mode, clear multicast list 1923 * num_addrs > 0 Multicast mode, receive normal and MC packets, 1924 * and do best-effort filtering. 1925 */ 1926static void 1927tc35815_set_multicast_list(struct net_device *dev) 1928{ 1929 struct tc35815_regs __iomem *tr = 1930 (struct tc35815_regs __iomem *)dev->base_addr; 1931 1932 if (dev->flags & IFF_PROMISC) { 1933 /* With some (all?) 100MHalf HUB, controller will hang 1934 * if we enabled promiscuous mode before linkup... */ 1935 struct tc35815_local *lp = netdev_priv(dev); 1936 1937 if (!lp->link) 1938 return; 1939 /* Enable promiscuous mode */ 1940 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); 1941 } else if ((dev->flags & IFF_ALLMULTI) || 1942 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) { 1943 /* CAM 0, 1, 20 are reserved. */ 1944 /* Disable promiscuous mode, use normal mode. */ 1945 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); 1946 } else if (!netdev_mc_empty(dev)) { 1947 struct netdev_hw_addr *ha; 1948 int i; 1949 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE); 1950 1951 tc_writel(0, &tr->CAM_Ctl); 1952 /* Walk the address list, and load the filter */ 1953 i = 0; 1954 netdev_for_each_mc_addr(ha, dev) { 1955 /* entry 0,1 is reserved. */ 1956 tc35815_set_cam_entry(dev, i + 2, ha->addr); 1957 ena_bits |= CAM_Ena_Bit(i + 2); 1958 i++; 1959 } 1960 tc_writel(ena_bits, &tr->CAM_Ena); 1961 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1962 } else { 1963 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 1964 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1965 } 1966} 1967 1968static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1969{ 1970 struct tc35815_local *lp = netdev_priv(dev); 1971 1972 strlcpy(info->driver, MODNAME, sizeof(info->driver)); 1973 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1974 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info)); 1975} 1976 1977static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1978{ 1979 struct tc35815_local *lp = netdev_priv(dev); 1980 1981 if (!lp->phy_dev) 1982 return -ENODEV; 1983 return phy_ethtool_gset(lp->phy_dev, cmd); 1984} 1985 1986static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1987{ 1988 struct tc35815_local *lp = netdev_priv(dev); 1989 1990 if (!lp->phy_dev) 1991 return -ENODEV; 1992 return phy_ethtool_sset(lp->phy_dev, cmd); 1993} 1994 1995static u32 tc35815_get_msglevel(struct net_device *dev) 1996{ 1997 struct tc35815_local *lp = netdev_priv(dev); 1998 return lp->msg_enable; 1999} 2000 2001static void tc35815_set_msglevel(struct net_device *dev, u32 datum) 2002{ 2003 struct tc35815_local *lp = netdev_priv(dev); 2004 lp->msg_enable = datum; 2005} 2006 2007static int tc35815_get_sset_count(struct net_device *dev, int sset) 2008{ 2009 struct tc35815_local *lp = netdev_priv(dev); 2010 2011 switch (sset) { 2012 case ETH_SS_STATS: 2013 return sizeof(lp->lstats) / sizeof(int); 2014 default: 2015 return -EOPNOTSUPP; 2016 } 2017} 2018 2019static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2020{ 2021 struct tc35815_local *lp = netdev_priv(dev); 2022 data[0] = lp->lstats.max_tx_qlen; 2023 data[1] = lp->lstats.tx_ints; 2024 data[2] = lp->lstats.rx_ints; 2025 data[3] = lp->lstats.tx_underrun; 2026} 2027 2028static struct { 2029 const char str[ETH_GSTRING_LEN]; 2030} ethtool_stats_keys[] = { 2031 { "max_tx_qlen" }, 2032 { "tx_ints" }, 2033 { "rx_ints" }, 2034 { "tx_underrun" }, 2035}; 2036 2037static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2038{ 2039 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2040} 2041 2042static const struct ethtool_ops tc35815_ethtool_ops = { 2043 .get_drvinfo = tc35815_get_drvinfo, 2044 .get_settings = tc35815_get_settings, 2045 .set_settings = tc35815_set_settings, 2046 .get_link = ethtool_op_get_link, 2047 .get_msglevel = tc35815_get_msglevel, 2048 .set_msglevel = tc35815_set_msglevel, 2049 .get_strings = tc35815_get_strings, 2050 .get_sset_count = tc35815_get_sset_count, 2051 .get_ethtool_stats = tc35815_get_ethtool_stats, 2052}; 2053 2054static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2055{ 2056 struct tc35815_local *lp = netdev_priv(dev); 2057 2058 if (!netif_running(dev)) 2059 return -EINVAL; 2060 if (!lp->phy_dev) 2061 return -ENODEV; 2062 return phy_mii_ioctl(lp->phy_dev, rq, cmd); 2063} 2064 2065static void tc35815_chip_reset(struct net_device *dev) 2066{ 2067 struct tc35815_regs __iomem *tr = 2068 (struct tc35815_regs __iomem *)dev->base_addr; 2069 int i; 2070 /* reset the controller */ 2071 tc_writel(MAC_Reset, &tr->MAC_Ctl); 2072 udelay(4); /* 3200ns */ 2073 i = 0; 2074 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { 2075 if (i++ > 100) { 2076 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name); 2077 break; 2078 } 2079 mdelay(1); 2080 } 2081 tc_writel(0, &tr->MAC_Ctl); 2082 2083 /* initialize registers to default value */ 2084 tc_writel(0, &tr->DMA_Ctl); 2085 tc_writel(0, &tr->TxThrsh); 2086 tc_writel(0, &tr->TxPollCtr); 2087 tc_writel(0, &tr->RxFragSize); 2088 tc_writel(0, &tr->Int_En); 2089 tc_writel(0, &tr->FDA_Bas); 2090 tc_writel(0, &tr->FDA_Lim); 2091 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ 2092 tc_writel(0, &tr->CAM_Ctl); 2093 tc_writel(0, &tr->Tx_Ctl); 2094 tc_writel(0, &tr->Rx_Ctl); 2095 tc_writel(0, &tr->CAM_Ena); 2096 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ 2097 2098 /* initialize internal SRAM */ 2099 tc_writel(DMA_TestMode, &tr->DMA_Ctl); 2100 for (i = 0; i < 0x1000; i += 4) { 2101 tc_writel(i, &tr->CAM_Adr); 2102 tc_writel(0, &tr->CAM_Data); 2103 } 2104 tc_writel(0, &tr->DMA_Ctl); 2105} 2106 2107static void tc35815_chip_init(struct net_device *dev) 2108{ 2109 struct tc35815_local *lp = netdev_priv(dev); 2110 struct tc35815_regs __iomem *tr = 2111 (struct tc35815_regs __iomem *)dev->base_addr; 2112 unsigned long txctl = TX_CTL_CMD; 2113 2114 /* load station address to CAM */ 2115 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr); 2116 2117 /* Enable CAM (broadcast and unicast) */ 2118 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 2119 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 2120 2121 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */ 2122 if (HAVE_DMA_RXALIGN(lp)) 2123 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); 2124 else 2125 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); 2126 tc_writel(0, &tr->TxPollCtr); /* Batch mode */ 2127 tc_writel(TX_THRESHOLD, &tr->TxThrsh); 2128 tc_writel(INT_EN_CMD, &tr->Int_En); 2129 2130 /* set queues */ 2131 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); 2132 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base, 2133 &tr->FDA_Lim); 2134 /* 2135 * Activation method: 2136 * First, enable the MAC Transmitter and the DMA Receive circuits. 2137 * Then enable the DMA Transmitter and the MAC Receive circuits. 2138 */ 2139 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ 2140 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ 2141 2142 /* start MAC transmitter */ 2143 /* TX4939 does not have EnLCarr */ 2144 if (lp->chiptype == TC35815_TX4939) 2145 txctl &= ~Tx_EnLCarr; 2146 /* WORKAROUND: ignore LostCrS in full duplex operation */ 2147 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL) 2148 txctl &= ~Tx_EnLCarr; 2149 tc_writel(txctl, &tr->Tx_Ctl); 2150} 2151 2152#ifdef CONFIG_PM 2153static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state) 2154{ 2155 struct net_device *dev = pci_get_drvdata(pdev); 2156 struct tc35815_local *lp = netdev_priv(dev); 2157 unsigned long flags; 2158 2159 pci_save_state(pdev); 2160 if (!netif_running(dev)) 2161 return 0; 2162 netif_device_detach(dev); 2163 if (lp->phy_dev) 2164 phy_stop(lp->phy_dev); 2165 spin_lock_irqsave(&lp->lock, flags); 2166 tc35815_chip_reset(dev); 2167 spin_unlock_irqrestore(&lp->lock, flags); 2168 pci_set_power_state(pdev, PCI_D3hot); 2169 return 0; 2170} 2171 2172static int tc35815_resume(struct pci_dev *pdev) 2173{ 2174 struct net_device *dev = pci_get_drvdata(pdev); 2175 struct tc35815_local *lp = netdev_priv(dev); 2176 2177 pci_restore_state(pdev); 2178 if (!netif_running(dev)) 2179 return 0; 2180 pci_set_power_state(pdev, PCI_D0); 2181 tc35815_restart(dev); 2182 netif_carrier_off(dev); 2183 if (lp->phy_dev) 2184 phy_start(lp->phy_dev); 2185 netif_device_attach(dev); 2186 return 0; 2187} 2188#endif /* CONFIG_PM */ 2189 2190static struct pci_driver tc35815_pci_driver = { 2191 .name = MODNAME, 2192 .id_table = tc35815_pci_tbl, 2193 .probe = tc35815_init_one, 2194 .remove = tc35815_remove_one, 2195#ifdef CONFIG_PM 2196 .suspend = tc35815_suspend, 2197 .resume = tc35815_resume, 2198#endif 2199}; 2200 2201module_param_named(speed, options.speed, int, 0); 2202MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps"); 2203module_param_named(duplex, options.duplex, int, 0); 2204MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full"); 2205 2206module_pci_driver(tc35815_pci_driver); 2207MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver"); 2208MODULE_LICENSE("GPL"); 2209