11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/********************************************************************* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Filename: nsc-ircc.h 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Version: 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Description: 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Status: Experimental. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Dag Brattli <dagb@cs.uit.no> 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Created at: Fri Nov 13 14:37:40 1998 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Modified at: Sun Jan 23 17:47:00 2000 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Modified by: Dag Brattli <dagb@cs.uit.no> 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com> 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (c) 1998 Actisys Corp., www.actisys.com 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * All Rights Reserved 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * modify it under the terms of the GNU General Public License as 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation; either version 2 of 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the License, or (at your option) any later version. 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 2296de0e252cedffad61b3cb5e05662c591898e69aJan Engelhardt * Neither Dag Brattli nor University of Tromsø admit liability nor 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * provide warranty for any of this software. This material is 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * provided "AS-IS" and at no charge. 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ********************************************************************/ 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef NSC_IRCC_H 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define NSC_IRCC_H 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/time.h> 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/spinlock.h> 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pm.h> 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/types.h> 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/io.h> 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 381fa98174ba980b2826edd1e4632a17916dfdb4faMatthew Garrett/* Features for chips (set in driver_data) */ 391fa98174ba980b2826edd1e4632a17916dfdb4faMatthew Garrett#define NSC_FORCE_DONGLE_TYPE9 0x00000001 401fa98174ba980b2826edd1e4632a17916dfdb4faMatthew Garrett 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* DMA modes needed */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */ 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */ 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Config registers for the '108 */ 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_108_BAIC 0x00 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_108_CSRT 0x01 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_108_MCTL 0x02 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Config registers for the '338 */ 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_FER 0x00 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_FAR 0x01 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_PTR 0x02 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_PNP0 0x1b 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_PNP1 0x1c 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_338_PNP3 0x4f 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Config registers for the '39x (in the logical device bank) */ 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_LDN 0x07 /* Logical device number (Super I/O bank) */ 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_SIOCF1 0x21 /* SuperI/O Config */ 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_ACT 0x30 /* Device activation */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_BASEH 0x60 /* Device base address (high bits) */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_BASEL 0x61 /* Device base address (low bits) */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_IRQNUM 0x70 /* Interrupt number & wake up enable */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_IRQSEL 0x71 /* Interrupt select (edge/level + polarity) */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_DMA0 0x74 /* DMA 0 configuration */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_DMA1 0x75 /* DMA 1 configuration */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CFG_39X_SPC 0xF0 /* Serial port configuration register */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Flags for configuration register CRF0 */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define APEDCRC 0x02 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ENBNKSEL 0x01 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Set 0 */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXD 0x00 /* Transmit data port */ 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXD 0x00 /* Receive data port */ 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Register 1 */ 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER 0x01 /* Interrupt Enable Register*/ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */ 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_LS_IE 0x04//* Link Status Interrupt */ 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_ETXURI 0x04 /* Tx underrun */ 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_DMA_IE 0x10 /* DMA finished interrupt */ 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_TXEMP_IE 0x20 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_SFIF_IE 0x40 /* Frame status FIFO intr */ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IER_TMR_IE 0x80 /* Timer event */ 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR 0x02 /* (write only) */ 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR_FIFO_EN 0x01 /* Enable FIFO's */ 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR_RXSR 0x02 /* Rx FIFO soft reset */ 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR_TXSR 0x04 /* Tx FIFO soft reset */ 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */ 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR 0x02 /* (read only) */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_RXHDL_EV 0x01 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_TXLDL_EV 0x02 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_LS_EV 0x04 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_DMA_EV 0x10 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_TXEMP_EV 0x20 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_SFIF_EV 0x40 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EIR_TMR_EV 0x80 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LCR 0x03 /* Link control register */ 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LCR_WLS_8 0x03 /* 8 bits */ 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BSR 0x03 /* Bank select register */ 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BSR_BKSE 0x80 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK1 0x80 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK2 0xe0 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK3 0xe4 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK4 0xe8 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK5 0xec 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK6 0xf0 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BANK7 0xf4 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR 0x04 /* Mode Control Register */ 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_MODE_MASK ~(0xd0) 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_UART 0x00 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_RESERVED 0x20 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_SHARP_IR 0x40 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_SIR 0x60 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_MIR 0x80 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_FIR 0xa0 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_CEIR 0xb0 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_IR_PLS 0x10 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_DMA_EN 0x04 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_EN_IRQ 0x08 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MCR_TX_DFR 0x08 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LSR 0x05 /* Link status register */ 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LSR_RXDA 0x01 /* Receiver data available */ 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LSR_TXRDY 0x20 /* Transmitter ready */ 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LSR_TXEMP 0x40 /* Transmitter empty */ 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13825985edcedea6396277003854657b5f3cb31a628Lucas De Marchi#define ASCR 0x07 /* Auxiliary Status and Control Register */ 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */ 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */ 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCR_S_EOT 0x04 /* Set end of transmission */ 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCT_RXBSY 0x20 /* Rx busy */ 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCR_TXUR 0x40 /* Transeiver underrun */ 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ASCR_CTE 0x80 /* Clear timer event */ 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 2 */ 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */ 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ECR1 0x02 /* Extended Control Register 1 */ 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ECR1_EXT_SL 0x01 /* Extended Mode Select */ 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ECR1_DMANF 0x02 /* DMA Fairness */ 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ECR1_DMATH 0x04 /* DMA Threshold */ 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ECR1_DMASWP 0x08 /* DMA Swap */ 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EXCR2 0x04 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */ 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */ 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TXFLV 0x06 /* Tx FIFO level */ 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RXFLV 0x07 /* Rx FIFO level */ 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 3 */ 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MID 0x00 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 4 */ 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TMRL 0x00 /* Timer low byte */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TMRH 0x01 /* Timer high byte */ 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRCR1 0x02 /* Infrared control register 1 */ 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRCR1_TMR_EN 0x01 /* Timer enable */ 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TFRLL 0x04 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define TFRLH 0x05 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RFRLL 0x06 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RFRLH 0x07 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 5 */ 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRCR2 0x04 /* Infrared control register 2 */ 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRCR2_MDRS 0x04 /* MIR data rate select */ 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRCR2_FEND_MD 0x20 /* */ 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST 0x05 /* Frame status FIFO */ 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_ERR_MSK 0x5f 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_LOST_FR 0x40 /* Frame lost */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */ 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_PHY_ERR 0x08 /* Physical layer error */ 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_BAD_CRC 0x04 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */ 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */ 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RFLFL 0x06 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define RFLFH 0x07 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 6 */ 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IR_CFG2 0x00 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IR_CFG2_DIS_CRC 0x02 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Bank 7 */ 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRM_CR 0x07 /* Infrared module control register */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRM_CR_IRX_MSL 0x40 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRM_CR_AF_MNT 0x80 /* Automatic format */ 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* NSC chip information */ 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct nsc_chip { 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds char *name; /* Name of chipset */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int cfg[3]; /* Config registers */ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u_int8_t cid_index; /* Chip identification index reg */ 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u_int8_t cid_value; /* Chip identification expected value */ 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u_int8_t cid_mask; /* Chip identification revision mask */ 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Functions for probing and initializing the specific chip */ 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int (*probe)(struct nsc_chip *chip, chipio_t *info); 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int (*init)(struct nsc_chip *chip, chipio_t *info); 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldstypedef struct nsc_chip nsc_chip_t; 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* For storing entries in the status FIFO */ 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct st_fifo_entry { 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int status; 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int len; 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_TX_WINDOW 7 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MAX_RX_WINDOW 7 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct st_fifo { 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct st_fifo_entry entries[MAX_RX_WINDOW]; 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int pending_bytes; 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int head; 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int tail; 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int len; 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct frame_cb { 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *start; /* Start of frame in DMA mem */ 237efad798b9f01300565f65058b153250cc49d58f2Paulius Zaleckas int len; /* Length of frame in DMA mem */ 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct tx_fifo { 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */ 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int ptr; /* Currently being sent */ 243efad798b9f01300565f65058b153250cc49d58f2Paulius Zaleckas int len; /* Length of queue */ 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int free; /* Next free slot */ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds void *tail; /* Next free start in DMA mem */ 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Private data for each instance */ 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct nsc_ircc_cb { 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct st_fifo st_fifo; /* Info about received frames */ 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct tx_fifo tx_fifo; /* Info about frames to be transmitted */ 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct net_device *netdev; /* Yes! we are some kind of netdevice */ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct irlap_cb *irlap; /* The link layer we are binded to */ 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct qos_info qos; /* QoS capabilities for this device */ 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds chipio_t io; /* IrDA controller information */ 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iobuff_t tx_buff; /* Transmit buffer */ 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds iobuff_t rx_buff; /* Receive buffer */ 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t tx_buff_dma; 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t rx_buff_dma; 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u8 ier; /* Interrupt enable register */ 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timeval stamp; 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct timeval now; 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds spinlock_t lock; /* For serializing operations */ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __u32 new_speed; 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int index; /* Instance index */ 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2743b99b93baba4cbf4fd3d206e65e81a070b21b560Dmitry Torokhov struct platform_device *pldev; 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic inline void switch_bank(int iobase, int bank) 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds outb(bank, iobase+BSR); 2801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* NSC_IRCC_H */ 283