1/********************************************************************* 2 * 3 * Description: Driver for the SMC Infrared Communications Controller 4 * Author: Daniele Peri (peri@csai.unipa.it) 5 * Created at: 6 * Modified at: 7 * Modified by: 8 * 9 * Copyright (c) 2002 Daniele Peri 10 * All Rights Reserved. 11 * Copyright (c) 2002 Jean Tourrilhes 12 * Copyright (c) 2006 Linus Walleij 13 * 14 * 15 * Based on smc-ircc.c: 16 * 17 * Copyright (c) 2001 Stefani Seibold 18 * Copyright (c) 1999-2001 Dag Brattli 19 * Copyright (c) 1998-1999 Thomas Davis, 20 * 21 * and irport.c: 22 * 23 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. 24 * 25 * 26 * This program is free software; you can redistribute it and/or 27 * modify it under the terms of the GNU General Public License as 28 * published by the Free Software Foundation; either version 2 of 29 * the License, or (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, see <http://www.gnu.org/licenses/>. 38 * 39 ********************************************************************/ 40 41#include <linux/module.h> 42#include <linux/kernel.h> 43#include <linux/types.h> 44#include <linux/skbuff.h> 45#include <linux/netdevice.h> 46#include <linux/ioport.h> 47#include <linux/delay.h> 48#include <linux/init.h> 49#include <linux/interrupt.h> 50#include <linux/rtnetlink.h> 51#include <linux/serial_reg.h> 52#include <linux/dma-mapping.h> 53#include <linux/pnp.h> 54#include <linux/platform_device.h> 55#include <linux/gfp.h> 56 57#include <asm/io.h> 58#include <asm/dma.h> 59#include <asm/byteorder.h> 60 61#include <linux/spinlock.h> 62#include <linux/pm.h> 63#ifdef CONFIG_PCI 64#include <linux/pci.h> 65#endif 66 67#include <net/irda/wrapper.h> 68#include <net/irda/irda.h> 69#include <net/irda/irda_device.h> 70 71#include "smsc-ircc2.h" 72#include "smsc-sio.h" 73 74 75MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); 76MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); 77MODULE_LICENSE("GPL"); 78 79static bool smsc_nopnp = true; 80module_param_named(nopnp, smsc_nopnp, bool, 0); 81MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true"); 82 83#define DMA_INVAL 255 84static int ircc_dma = DMA_INVAL; 85module_param(ircc_dma, int, 0); 86MODULE_PARM_DESC(ircc_dma, "DMA channel"); 87 88#define IRQ_INVAL 255 89static int ircc_irq = IRQ_INVAL; 90module_param(ircc_irq, int, 0); 91MODULE_PARM_DESC(ircc_irq, "IRQ line"); 92 93static int ircc_fir; 94module_param(ircc_fir, int, 0); 95MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); 96 97static int ircc_sir; 98module_param(ircc_sir, int, 0); 99MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); 100 101static int ircc_cfg; 102module_param(ircc_cfg, int, 0); 103MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); 104 105static int ircc_transceiver; 106module_param(ircc_transceiver, int, 0); 107MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); 108 109/* Types */ 110 111#ifdef CONFIG_PCI 112struct smsc_ircc_subsystem_configuration { 113 unsigned short vendor; /* PCI vendor ID */ 114 unsigned short device; /* PCI vendor ID */ 115 unsigned short subvendor; /* PCI subsystem vendor ID */ 116 unsigned short subdevice; /* PCI subsystem device ID */ 117 unsigned short sir_io; /* I/O port for SIR */ 118 unsigned short fir_io; /* I/O port for FIR */ 119 unsigned char fir_irq; /* FIR IRQ */ 120 unsigned char fir_dma; /* FIR DMA */ 121 unsigned short cfg_base; /* I/O port for chip configuration */ 122 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ 123 const char *name; /* name shown as info */ 124}; 125#endif 126 127struct smsc_transceiver { 128 char *name; 129 void (*set_for_speed)(int fir_base, u32 speed); 130 int (*probe)(int fir_base); 131}; 132 133struct smsc_chip { 134 char *name; 135 #if 0 136 u8 type; 137 #endif 138 u16 flags; 139 u8 devid; 140 u8 rev; 141}; 142 143struct smsc_chip_address { 144 unsigned int cfg_base; 145 unsigned int type; 146}; 147 148/* Private data for each instance */ 149struct smsc_ircc_cb { 150 struct net_device *netdev; /* Yes! we are some kind of netdevice */ 151 struct irlap_cb *irlap; /* The link layer we are binded to */ 152 153 chipio_t io; /* IrDA controller information */ 154 iobuff_t tx_buff; /* Transmit buffer */ 155 iobuff_t rx_buff; /* Receive buffer */ 156 dma_addr_t tx_buff_dma; 157 dma_addr_t rx_buff_dma; 158 159 struct qos_info qos; /* QoS capabilities for this device */ 160 161 spinlock_t lock; /* For serializing operations */ 162 163 __u32 new_speed; 164 __u32 flags; /* Interface flags */ 165 166 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ 167 int tx_len; /* Number of frames in tx_buff */ 168 169 int transceiver; 170 struct platform_device *pldev; 171}; 172 173/* Constants */ 174 175#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" 176 177#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 178#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 179#define SMSC_IRCC2_C_NET_TIMEOUT 0 180#define SMSC_IRCC2_C_SIR_STOP 0 181 182static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; 183 184/* Prototypes */ 185 186static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); 187static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); 188static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); 189static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); 190static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); 191static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); 192static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); 193static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); 194static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); 195static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb, 196 struct net_device *dev); 197static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb, 198 struct net_device *dev); 199static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); 200static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); 201static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); 202static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); 203static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); 204static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); 205static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); 206#if SMSC_IRCC2_C_SIR_STOP 207static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); 208#endif 209static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); 210static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); 211static int smsc_ircc_net_open(struct net_device *dev); 212static int smsc_ircc_net_close(struct net_device *dev); 213static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 214#if SMSC_IRCC2_C_NET_TIMEOUT 215static void smsc_ircc_timeout(struct net_device *dev); 216#endif 217static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); 218static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); 219static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); 220static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); 221 222/* Probing */ 223static int __init smsc_ircc_look_for_chips(void); 224static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); 225static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 226static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 227static int __init smsc_superio_fdc(unsigned short cfg_base); 228static int __init smsc_superio_lpc(unsigned short cfg_base); 229#ifdef CONFIG_PCI 230static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); 231static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 232static void __init preconfigure_ali_port(struct pci_dev *dev, 233 unsigned short port); 234static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 235static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 236 unsigned short ircc_fir, 237 unsigned short ircc_sir, 238 unsigned char ircc_dma, 239 unsigned char ircc_irq); 240#endif 241 242/* Transceivers specific functions */ 243 244static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); 245static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); 246static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); 247static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); 248static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); 249static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); 250 251/* Power Management */ 252 253static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); 254static int smsc_ircc_resume(struct platform_device *dev); 255 256static struct platform_driver smsc_ircc_driver = { 257 .suspend = smsc_ircc_suspend, 258 .resume = smsc_ircc_resume, 259 .driver = { 260 .name = SMSC_IRCC2_DRIVER_NAME, 261 }, 262}; 263 264/* Transceivers for SMSC-ircc */ 265 266static struct smsc_transceiver smsc_transceivers[] = 267{ 268 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, 269 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, 270 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, 271 { NULL, NULL } 272}; 273#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) 274 275/* SMC SuperIO chipsets definitions */ 276 277#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ 278#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ 279#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ 280#define SIR 0 /* SuperIO Chip has only slow IRDA */ 281#define FIR 4 /* SuperIO Chip has fast IRDA */ 282#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ 283 284static struct smsc_chip __initdata fdc_chips_flat[] = 285{ 286 /* Base address 0x3f0 or 0x370 */ 287 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ 288 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, 289 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, 290 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, 291 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ 292 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, 293 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, 294 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, 295 { NULL } 296}; 297 298static struct smsc_chip __initdata fdc_chips_paged[] = 299{ 300 /* Base address 0x3f0 or 0x370 */ 301 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, 302 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, 303 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, 304 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 305 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, 306 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, 307 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, 308 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, 309 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 310 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, 311 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, 312 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, 313 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, 314 { NULL } 315}; 316 317static struct smsc_chip __initdata lpc_chips_flat[] = 318{ 319 /* Base address 0x2E or 0x4E */ 320 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, 321 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, 322 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, 323 { NULL } 324}; 325 326static struct smsc_chip __initdata lpc_chips_paged[] = 327{ 328 /* Base address 0x2E or 0x4E */ 329 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, 330 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, 331 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 332 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, 333 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 334 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, 335 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, 336 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, 337 { NULL } 338}; 339 340#define SMSCSIO_TYPE_FDC 1 341#define SMSCSIO_TYPE_LPC 2 342#define SMSCSIO_TYPE_FLAT 4 343#define SMSCSIO_TYPE_PAGED 8 344 345static struct smsc_chip_address __initdata possible_addresses[] = 346{ 347 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 348 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 349 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 350 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 351 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 352 { 0, 0 } 353}; 354 355/* Globals */ 356 357static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; 358static unsigned short dev_count; 359 360static inline void register_bank(int iobase, int bank) 361{ 362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), 363 iobase + IRCC_MASTER); 364} 365 366/* PNP hotplug support */ 367static const struct pnp_device_id smsc_ircc_pnp_table[] = { 368 { .id = "SMCf010", .driver_data = 0 }, 369 /* and presumably others */ 370 { } 371}; 372MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); 373 374static int pnp_driver_registered; 375 376#ifdef CONFIG_PNP 377static int smsc_ircc_pnp_probe(struct pnp_dev *dev, 378 const struct pnp_device_id *dev_id) 379{ 380 unsigned int firbase, sirbase; 381 u8 dma, irq; 382 383 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && 384 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0))) 385 return -EINVAL; 386 387 sirbase = pnp_port_start(dev, 0); 388 firbase = pnp_port_start(dev, 1); 389 dma = pnp_dma(dev, 0); 390 irq = pnp_irq(dev, 0); 391 392 if (smsc_ircc_open(firbase, sirbase, dma, irq)) 393 return -ENODEV; 394 395 return 0; 396} 397 398static struct pnp_driver smsc_ircc_pnp_driver = { 399 .name = "smsc-ircc2", 400 .id_table = smsc_ircc_pnp_table, 401 .probe = smsc_ircc_pnp_probe, 402}; 403#else /* CONFIG_PNP */ 404static struct pnp_driver smsc_ircc_pnp_driver; 405#endif 406 407/******************************************************************************* 408 * 409 * 410 * SMSC-ircc stuff 411 * 412 * 413 *******************************************************************************/ 414 415static int __init smsc_ircc_legacy_probe(void) 416{ 417 int ret = 0; 418 419#ifdef CONFIG_PCI 420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { 421 /* Ignore errors from preconfiguration */ 422 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); 423 } 424#endif 425 426 if (ircc_fir > 0 && ircc_sir > 0) { 427 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); 428 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); 429 430 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) 431 ret = -ENODEV; 432 } else { 433 ret = -ENODEV; 434 435 /* try user provided configuration register base address */ 436 if (ircc_cfg > 0) { 437 IRDA_MESSAGE(" Overriding configuration address " 438 "0x%04x\n", ircc_cfg); 439 if (!smsc_superio_fdc(ircc_cfg)) 440 ret = 0; 441 if (!smsc_superio_lpc(ircc_cfg)) 442 ret = 0; 443 } 444 445 if (smsc_ircc_look_for_chips() > 0) 446 ret = 0; 447 } 448 return ret; 449} 450 451/* 452 * Function smsc_ircc_init () 453 * 454 * Initialize chip. Just try to find out how many chips we are dealing with 455 * and where they are 456 */ 457static int __init smsc_ircc_init(void) 458{ 459 int ret; 460 461 IRDA_DEBUG(1, "%s\n", __func__); 462 463 ret = platform_driver_register(&smsc_ircc_driver); 464 if (ret) { 465 IRDA_ERROR("%s, Can't register driver!\n", driver_name); 466 return ret; 467 } 468 469 dev_count = 0; 470 471 if (smsc_nopnp || !pnp_platform_devices || 472 ircc_cfg || ircc_fir || ircc_sir || 473 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) { 474 ret = smsc_ircc_legacy_probe(); 475 } else { 476 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0) 477 pnp_driver_registered = 1; 478 } 479 480 if (ret) { 481 if (pnp_driver_registered) 482 pnp_unregister_driver(&smsc_ircc_pnp_driver); 483 platform_driver_unregister(&smsc_ircc_driver); 484 } 485 486 return ret; 487} 488 489static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb, 490 struct net_device *dev) 491{ 492 struct smsc_ircc_cb *self = netdev_priv(dev); 493 494 if (self->io.speed > 115200) 495 return smsc_ircc_hard_xmit_fir(skb, dev); 496 else 497 return smsc_ircc_hard_xmit_sir(skb, dev); 498} 499 500static const struct net_device_ops smsc_ircc_netdev_ops = { 501 .ndo_open = smsc_ircc_net_open, 502 .ndo_stop = smsc_ircc_net_close, 503 .ndo_do_ioctl = smsc_ircc_net_ioctl, 504 .ndo_start_xmit = smsc_ircc_net_xmit, 505#if SMSC_IRCC2_C_NET_TIMEOUT 506 .ndo_tx_timeout = smsc_ircc_timeout, 507#endif 508}; 509 510/* 511 * Function smsc_ircc_open (firbase, sirbase, dma, irq) 512 * 513 * Try to open driver instance 514 * 515 */ 516static int smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) 517{ 518 struct smsc_ircc_cb *self; 519 struct net_device *dev; 520 int err; 521 522 IRDA_DEBUG(1, "%s\n", __func__); 523 524 err = smsc_ircc_present(fir_base, sir_base); 525 if (err) 526 goto err_out; 527 528 err = -ENOMEM; 529 if (dev_count >= ARRAY_SIZE(dev_self)) { 530 IRDA_WARNING("%s(), too many devices!\n", __func__); 531 goto err_out1; 532 } 533 534 /* 535 * Allocate new instance of the driver 536 */ 537 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); 538 if (!dev) { 539 IRDA_WARNING("%s() can't allocate net device\n", __func__); 540 goto err_out1; 541 } 542 543#if SMSC_IRCC2_C_NET_TIMEOUT 544 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ 545#endif 546 dev->netdev_ops = &smsc_ircc_netdev_ops; 547 548 self = netdev_priv(dev); 549 self->netdev = dev; 550 551 /* Make ifconfig display some details */ 552 dev->base_addr = self->io.fir_base = fir_base; 553 dev->irq = self->io.irq = irq; 554 555 /* Need to store self somewhere */ 556 dev_self[dev_count] = self; 557 spin_lock_init(&self->lock); 558 559 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; 560 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; 561 562 self->rx_buff.head = 563 dma_zalloc_coherent(NULL, self->rx_buff.truesize, 564 &self->rx_buff_dma, GFP_KERNEL); 565 if (self->rx_buff.head == NULL) 566 goto err_out2; 567 568 self->tx_buff.head = 569 dma_zalloc_coherent(NULL, self->tx_buff.truesize, 570 &self->tx_buff_dma, GFP_KERNEL); 571 if (self->tx_buff.head == NULL) 572 goto err_out3; 573 574 self->rx_buff.in_frame = FALSE; 575 self->rx_buff.state = OUTSIDE_FRAME; 576 self->tx_buff.data = self->tx_buff.head; 577 self->rx_buff.data = self->rx_buff.head; 578 579 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); 580 smsc_ircc_setup_qos(self); 581 smsc_ircc_init_chip(self); 582 583 if (ircc_transceiver > 0 && 584 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) 585 self->transceiver = ircc_transceiver; 586 else 587 smsc_ircc_probe_transceiver(self); 588 589 err = register_netdev(self->netdev); 590 if (err) { 591 IRDA_ERROR("%s, Network device registration failed!\n", 592 driver_name); 593 goto err_out4; 594 } 595 596 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, 597 dev_count, NULL, 0); 598 if (IS_ERR(self->pldev)) { 599 err = PTR_ERR(self->pldev); 600 goto err_out5; 601 } 602 platform_set_drvdata(self->pldev, self); 603 604 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); 605 dev_count++; 606 607 return 0; 608 609 err_out5: 610 unregister_netdev(self->netdev); 611 612 err_out4: 613 dma_free_coherent(NULL, self->tx_buff.truesize, 614 self->tx_buff.head, self->tx_buff_dma); 615 err_out3: 616 dma_free_coherent(NULL, self->rx_buff.truesize, 617 self->rx_buff.head, self->rx_buff_dma); 618 err_out2: 619 free_netdev(self->netdev); 620 dev_self[dev_count] = NULL; 621 err_out1: 622 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 623 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 624 err_out: 625 return err; 626} 627 628/* 629 * Function smsc_ircc_present(fir_base, sir_base) 630 * 631 * Check the smsc-ircc chip presence 632 * 633 */ 634static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) 635{ 636 unsigned char low, high, chip, config, dma, irq, version; 637 638 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, 639 driver_name)) { 640 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", 641 __func__, fir_base); 642 goto out1; 643 } 644 645 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, 646 driver_name)) { 647 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", 648 __func__, sir_base); 649 goto out2; 650 } 651 652 register_bank(fir_base, 3); 653 654 high = inb(fir_base + IRCC_ID_HIGH); 655 low = inb(fir_base + IRCC_ID_LOW); 656 chip = inb(fir_base + IRCC_CHIP_ID); 657 version = inb(fir_base + IRCC_VERSION); 658 config = inb(fir_base + IRCC_INTERFACE); 659 dma = config & IRCC_INTERFACE_DMA_MASK; 660 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 661 662 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { 663 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", 664 __func__, fir_base); 665 goto out3; 666 } 667 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " 668 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", 669 chip & 0x0f, version, fir_base, sir_base, dma, irq); 670 671 return 0; 672 673 out3: 674 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 675 out2: 676 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 677 out1: 678 return -ENODEV; 679} 680 681/* 682 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) 683 * 684 * Setup I/O 685 * 686 */ 687static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, 688 unsigned int fir_base, unsigned int sir_base, 689 u8 dma, u8 irq) 690{ 691 unsigned char config, chip_dma, chip_irq; 692 693 register_bank(fir_base, 3); 694 config = inb(fir_base + IRCC_INTERFACE); 695 chip_dma = config & IRCC_INTERFACE_DMA_MASK; 696 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 697 698 self->io.fir_base = fir_base; 699 self->io.sir_base = sir_base; 700 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; 701 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; 702 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; 703 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; 704 705 if (irq != IRQ_INVAL) { 706 if (irq != chip_irq) 707 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", 708 driver_name, chip_irq, irq); 709 self->io.irq = irq; 710 } else 711 self->io.irq = chip_irq; 712 713 if (dma != DMA_INVAL) { 714 if (dma != chip_dma) 715 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", 716 driver_name, chip_dma, dma); 717 self->io.dma = dma; 718 } else 719 self->io.dma = chip_dma; 720 721} 722 723/* 724 * Function smsc_ircc_setup_qos(self) 725 * 726 * Setup qos 727 * 728 */ 729static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) 730{ 731 /* Initialize QoS for this device */ 732 irda_init_max_qos_capabilies(&self->qos); 733 734 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 735 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); 736 737 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; 738 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; 739 irda_qos_bits_to_value(&self->qos); 740} 741 742/* 743 * Function smsc_ircc_init_chip(self) 744 * 745 * Init chip 746 * 747 */ 748static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) 749{ 750 int iobase = self->io.fir_base; 751 752 register_bank(iobase, 0); 753 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 754 outb(0x00, iobase + IRCC_MASTER); 755 756 register_bank(iobase, 1); 757 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), 758 iobase + IRCC_SCE_CFGA); 759 760#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ 761 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 762 iobase + IRCC_SCE_CFGB); 763#else 764 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 765 iobase + IRCC_SCE_CFGB); 766#endif 767 (void) inb(iobase + IRCC_FIFO_THRESHOLD); 768 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); 769 770 register_bank(iobase, 4); 771 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); 772 773 register_bank(iobase, 0); 774 outb(0, iobase + IRCC_LCR_A); 775 776 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 777 778 /* Power on device */ 779 outb(0x00, iobase + IRCC_MASTER); 780} 781 782/* 783 * Function smsc_ircc_net_ioctl (dev, rq, cmd) 784 * 785 * Process IOCTL commands for this device 786 * 787 */ 788static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 789{ 790 struct if_irda_req *irq = (struct if_irda_req *) rq; 791 struct smsc_ircc_cb *self; 792 unsigned long flags; 793 int ret = 0; 794 795 IRDA_ASSERT(dev != NULL, return -1;); 796 797 self = netdev_priv(dev); 798 799 IRDA_ASSERT(self != NULL, return -1;); 800 801 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd); 802 803 switch (cmd) { 804 case SIOCSBANDWIDTH: /* Set bandwidth */ 805 if (!capable(CAP_NET_ADMIN)) 806 ret = -EPERM; 807 else { 808 /* Make sure we are the only one touching 809 * self->io.speed and the hardware - Jean II */ 810 spin_lock_irqsave(&self->lock, flags); 811 smsc_ircc_change_speed(self, irq->ifr_baudrate); 812 spin_unlock_irqrestore(&self->lock, flags); 813 } 814 break; 815 case SIOCSMEDIABUSY: /* Set media busy */ 816 if (!capable(CAP_NET_ADMIN)) { 817 ret = -EPERM; 818 break; 819 } 820 821 irda_device_set_media_busy(self->netdev, TRUE); 822 break; 823 case SIOCGRECEIVING: /* Check if we are receiving right now */ 824 irq->ifr_receiving = smsc_ircc_is_receiving(self); 825 break; 826 #if 0 827 case SIOCSDTRRTS: 828 if (!capable(CAP_NET_ADMIN)) { 829 ret = -EPERM; 830 break; 831 } 832 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts); 833 break; 834 #endif 835 default: 836 ret = -EOPNOTSUPP; 837 } 838 839 return ret; 840} 841 842#if SMSC_IRCC2_C_NET_TIMEOUT 843/* 844 * Function smsc_ircc_timeout (struct net_device *dev) 845 * 846 * The networking timeout management. 847 * 848 */ 849 850static void smsc_ircc_timeout(struct net_device *dev) 851{ 852 struct smsc_ircc_cb *self = netdev_priv(dev); 853 unsigned long flags; 854 855 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", 856 dev->name, self->io.speed); 857 spin_lock_irqsave(&self->lock, flags); 858 smsc_ircc_sir_start(self); 859 smsc_ircc_change_speed(self, self->io.speed); 860 dev->trans_start = jiffies; /* prevent tx timeout */ 861 netif_wake_queue(dev); 862 spin_unlock_irqrestore(&self->lock, flags); 863} 864#endif 865 866/* 867 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) 868 * 869 * Transmits the current frame until FIFO is full, then 870 * waits until the next transmit interrupt, and continues until the 871 * frame is transmitted. 872 */ 873static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb, 874 struct net_device *dev) 875{ 876 struct smsc_ircc_cb *self; 877 unsigned long flags; 878 s32 speed; 879 880 IRDA_DEBUG(1, "%s\n", __func__); 881 882 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;); 883 884 self = netdev_priv(dev); 885 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); 886 887 netif_stop_queue(dev); 888 889 /* Make sure test of self->io.speed & speed change are atomic */ 890 spin_lock_irqsave(&self->lock, flags); 891 892 /* Check if we need to change the speed */ 893 speed = irda_get_next_speed(skb); 894 if (speed != self->io.speed && speed != -1) { 895 /* Check for empty frame */ 896 if (!skb->len) { 897 /* 898 * We send frames one by one in SIR mode (no 899 * pipelining), so at this point, if we were sending 900 * a previous frame, we just received the interrupt 901 * telling us it is finished (UART_IIR_THRI). 902 * Therefore, waiting for the transmitter to really 903 * finish draining the fifo won't take too long. 904 * And the interrupt handler is not expected to run. 905 * - Jean II */ 906 smsc_ircc_sir_wait_hw_transmitter_finish(self); 907 smsc_ircc_change_speed(self, speed); 908 spin_unlock_irqrestore(&self->lock, flags); 909 dev_kfree_skb(skb); 910 return NETDEV_TX_OK; 911 } 912 self->new_speed = speed; 913 } 914 915 /* Init tx buffer */ 916 self->tx_buff.data = self->tx_buff.head; 917 918 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ 919 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 920 self->tx_buff.truesize); 921 922 dev->stats.tx_bytes += self->tx_buff.len; 923 924 /* Turn on transmit finished interrupt. Will fire immediately! */ 925 outb(UART_IER_THRI, self->io.sir_base + UART_IER); 926 927 spin_unlock_irqrestore(&self->lock, flags); 928 929 dev_kfree_skb(skb); 930 931 return NETDEV_TX_OK; 932} 933 934/* 935 * Function smsc_ircc_set_fir_speed (self, baud) 936 * 937 * Change the speed of the device 938 * 939 */ 940static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) 941{ 942 int fir_base, ir_mode, ctrl, fast; 943 944 IRDA_ASSERT(self != NULL, return;); 945 fir_base = self->io.fir_base; 946 947 self->io.speed = speed; 948 949 switch (speed) { 950 default: 951 case 576000: 952 ir_mode = IRCC_CFGA_IRDA_HDLC; 953 ctrl = IRCC_CRC; 954 fast = 0; 955 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__); 956 break; 957 case 1152000: 958 ir_mode = IRCC_CFGA_IRDA_HDLC; 959 ctrl = IRCC_1152 | IRCC_CRC; 960 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; 961 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", 962 __func__); 963 break; 964 case 4000000: 965 ir_mode = IRCC_CFGA_IRDA_4PPM; 966 ctrl = IRCC_CRC; 967 fast = IRCC_LCR_A_FAST; 968 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", 969 __func__); 970 break; 971 } 972 #if 0 973 Now in tranceiver! 974 /* This causes an interrupt */ 975 register_bank(fir_base, 0); 976 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); 977 #endif 978 979 register_bank(fir_base, 1); 980 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); 981 982 register_bank(fir_base, 4); 983 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); 984} 985 986/* 987 * Function smsc_ircc_fir_start(self) 988 * 989 * Change the speed of the device 990 * 991 */ 992static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) 993{ 994 struct net_device *dev; 995 int fir_base; 996 997 IRDA_DEBUG(1, "%s\n", __func__); 998 999 IRDA_ASSERT(self != NULL, return;); 1000 dev = self->netdev; 1001 IRDA_ASSERT(dev != NULL, return;); 1002 1003 fir_base = self->io.fir_base; 1004 1005 /* Reset everything */ 1006 1007 /* Clear FIFO */ 1008 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); 1009 1010 /* Enable interrupt */ 1011 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ 1012 1013 register_bank(fir_base, 1); 1014 1015 /* Select the TX/RX interface */ 1016#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ 1017 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 1018 fir_base + IRCC_SCE_CFGB); 1019#else 1020 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 1021 fir_base + IRCC_SCE_CFGB); 1022#endif 1023 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); 1024 1025 /* Enable SCE interrupts */ 1026 outb(0, fir_base + IRCC_MASTER); 1027 register_bank(fir_base, 0); 1028 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); 1029 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); 1030} 1031 1032/* 1033 * Function smsc_ircc_fir_stop(self, baud) 1034 * 1035 * Change the speed of the device 1036 * 1037 */ 1038static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) 1039{ 1040 int fir_base; 1041 1042 IRDA_DEBUG(1, "%s\n", __func__); 1043 1044 IRDA_ASSERT(self != NULL, return;); 1045 1046 fir_base = self->io.fir_base; 1047 register_bank(fir_base, 0); 1048 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ 1049 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); 1050} 1051 1052 1053/* 1054 * Function smsc_ircc_change_speed(self, baud) 1055 * 1056 * Change the speed of the device 1057 * 1058 * This function *must* be called with spinlock held, because it may 1059 * be called from the irq handler. - Jean II 1060 */ 1061static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) 1062{ 1063 struct net_device *dev; 1064 int last_speed_was_sir; 1065 1066 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed); 1067 1068 IRDA_ASSERT(self != NULL, return;); 1069 dev = self->netdev; 1070 1071 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; 1072 1073 #if 0 1074 /* Temp Hack */ 1075 speed= 1152000; 1076 self->io.speed = speed; 1077 last_speed_was_sir = 0; 1078 smsc_ircc_fir_start(self); 1079 #endif 1080 1081 if (self->io.speed == 0) 1082 smsc_ircc_sir_start(self); 1083 1084 #if 0 1085 if (!last_speed_was_sir) speed = self->io.speed; 1086 #endif 1087 1088 if (self->io.speed != speed) 1089 smsc_ircc_set_transceiver_for_speed(self, speed); 1090 1091 self->io.speed = speed; 1092 1093 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1094 if (!last_speed_was_sir) { 1095 smsc_ircc_fir_stop(self); 1096 smsc_ircc_sir_start(self); 1097 } 1098 smsc_ircc_set_sir_speed(self, speed); 1099 } else { 1100 if (last_speed_was_sir) { 1101 #if SMSC_IRCC2_C_SIR_STOP 1102 smsc_ircc_sir_stop(self); 1103 #endif 1104 smsc_ircc_fir_start(self); 1105 } 1106 smsc_ircc_set_fir_speed(self, speed); 1107 1108 #if 0 1109 self->tx_buff.len = 10; 1110 self->tx_buff.data = self->tx_buff.head; 1111 1112 smsc_ircc_dma_xmit(self, 4000); 1113 #endif 1114 /* Be ready for incoming frames */ 1115 smsc_ircc_dma_receive(self); 1116 } 1117 1118 netif_wake_queue(dev); 1119} 1120 1121/* 1122 * Function smsc_ircc_set_sir_speed (self, speed) 1123 * 1124 * Set speed of IrDA port to specified baudrate 1125 * 1126 */ 1127static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) 1128{ 1129 int iobase; 1130 int fcr; /* FIFO control reg */ 1131 int lcr; /* Line control reg */ 1132 int divisor; 1133 1134 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed); 1135 1136 IRDA_ASSERT(self != NULL, return;); 1137 iobase = self->io.sir_base; 1138 1139 /* Update accounting for new speed */ 1140 self->io.speed = speed; 1141 1142 /* Turn off interrupts */ 1143 outb(0, iobase + UART_IER); 1144 1145 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; 1146 1147 fcr = UART_FCR_ENABLE_FIFO; 1148 1149 /* 1150 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and 1151 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget 1152 * about this timeout since it will always be fast enough. 1153 */ 1154 fcr |= self->io.speed < 38400 ? 1155 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1156 1157 /* IrDA ports use 8N1 */ 1158 lcr = UART_LCR_WLEN8; 1159 1160 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ 1161 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ 1162 outb(divisor >> 8, iobase + UART_DLM); 1163 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ 1164 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ 1165 1166 /* Turn on interrups */ 1167 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); 1168 1169 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed); 1170} 1171 1172 1173/* 1174 * Function smsc_ircc_hard_xmit_fir (skb, dev) 1175 * 1176 * Transmit the frame! 1177 * 1178 */ 1179static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb, 1180 struct net_device *dev) 1181{ 1182 struct smsc_ircc_cb *self; 1183 unsigned long flags; 1184 s32 speed; 1185 int mtt; 1186 1187 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;); 1188 self = netdev_priv(dev); 1189 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); 1190 1191 netif_stop_queue(dev); 1192 1193 /* Make sure test of self->io.speed & speed change are atomic */ 1194 spin_lock_irqsave(&self->lock, flags); 1195 1196 /* Check if we need to change the speed after this frame */ 1197 speed = irda_get_next_speed(skb); 1198 if (speed != self->io.speed && speed != -1) { 1199 /* Check for empty frame */ 1200 if (!skb->len) { 1201 /* Note : you should make sure that speed changes 1202 * are not going to corrupt any outgoing frame. 1203 * Look at nsc-ircc for the gory details - Jean II */ 1204 smsc_ircc_change_speed(self, speed); 1205 spin_unlock_irqrestore(&self->lock, flags); 1206 dev_kfree_skb(skb); 1207 return NETDEV_TX_OK; 1208 } 1209 1210 self->new_speed = speed; 1211 } 1212 1213 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); 1214 1215 self->tx_buff.len = skb->len; 1216 self->tx_buff.data = self->tx_buff.head; 1217 1218 mtt = irda_get_mtt(skb); 1219 if (mtt) { 1220 int bofs; 1221 1222 /* 1223 * Compute how many BOFs (STA or PA's) we need to waste the 1224 * min turn time given the speed of the link. 1225 */ 1226 bofs = mtt * (self->io.speed / 1000) / 8000; 1227 if (bofs > 4095) 1228 bofs = 4095; 1229 1230 smsc_ircc_dma_xmit(self, bofs); 1231 } else { 1232 /* Transmit frame */ 1233 smsc_ircc_dma_xmit(self, 0); 1234 } 1235 1236 spin_unlock_irqrestore(&self->lock, flags); 1237 dev_kfree_skb(skb); 1238 1239 return NETDEV_TX_OK; 1240} 1241 1242/* 1243 * Function smsc_ircc_dma_xmit (self, bofs) 1244 * 1245 * Transmit data using DMA 1246 * 1247 */ 1248static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) 1249{ 1250 int iobase = self->io.fir_base; 1251 u8 ctrl; 1252 1253 IRDA_DEBUG(3, "%s\n", __func__); 1254#if 1 1255 /* Disable Rx */ 1256 register_bank(iobase, 0); 1257 outb(0x00, iobase + IRCC_LCR_B); 1258#endif 1259 register_bank(iobase, 1); 1260 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1261 iobase + IRCC_SCE_CFGB); 1262 1263 self->io.direction = IO_XMIT; 1264 1265 /* Set BOF additional count for generating the min turn time */ 1266 register_bank(iobase, 4); 1267 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); 1268 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; 1269 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); 1270 1271 /* Set max Tx frame size */ 1272 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); 1273 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); 1274 1275 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ 1276 1277 /* Enable burst mode chip Tx DMA */ 1278 register_bank(iobase, 1); 1279 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1280 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1281 1282 /* Setup DMA controller (must be done after enabling chip DMA) */ 1283 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, 1284 DMA_TX_MODE); 1285 1286 /* Enable interrupt */ 1287 1288 register_bank(iobase, 0); 1289 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1290 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1291 1292 /* Enable transmit */ 1293 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); 1294} 1295 1296/* 1297 * Function smsc_ircc_dma_xmit_complete (self) 1298 * 1299 * The transfer of a frame in finished. This function will only be called 1300 * by the interrupt handler 1301 * 1302 */ 1303static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) 1304{ 1305 int iobase = self->io.fir_base; 1306 1307 IRDA_DEBUG(3, "%s\n", __func__); 1308#if 0 1309 /* Disable Tx */ 1310 register_bank(iobase, 0); 1311 outb(0x00, iobase + IRCC_LCR_B); 1312#endif 1313 register_bank(iobase, 1); 1314 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1315 iobase + IRCC_SCE_CFGB); 1316 1317 /* Check for underrun! */ 1318 register_bank(iobase, 0); 1319 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { 1320 self->netdev->stats.tx_errors++; 1321 self->netdev->stats.tx_fifo_errors++; 1322 1323 /* Reset error condition */ 1324 register_bank(iobase, 0); 1325 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); 1326 outb(0x00, iobase + IRCC_MASTER); 1327 } else { 1328 self->netdev->stats.tx_packets++; 1329 self->netdev->stats.tx_bytes += self->tx_buff.len; 1330 } 1331 1332 /* Check if it's time to change the speed */ 1333 if (self->new_speed) { 1334 smsc_ircc_change_speed(self, self->new_speed); 1335 self->new_speed = 0; 1336 } 1337 1338 netif_wake_queue(self->netdev); 1339} 1340 1341/* 1342 * Function smsc_ircc_dma_receive(self) 1343 * 1344 * Get ready for receiving a frame. The device will initiate a DMA 1345 * if it starts to receive a frame. 1346 * 1347 */ 1348static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) 1349{ 1350 int iobase = self->io.fir_base; 1351#if 0 1352 /* Turn off chip DMA */ 1353 register_bank(iobase, 1); 1354 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1355 iobase + IRCC_SCE_CFGB); 1356#endif 1357 1358 /* Disable Tx */ 1359 register_bank(iobase, 0); 1360 outb(0x00, iobase + IRCC_LCR_B); 1361 1362 /* Turn off chip DMA */ 1363 register_bank(iobase, 1); 1364 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1365 iobase + IRCC_SCE_CFGB); 1366 1367 self->io.direction = IO_RECV; 1368 self->rx_buff.data = self->rx_buff.head; 1369 1370 /* Set max Rx frame size */ 1371 register_bank(iobase, 4); 1372 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); 1373 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); 1374 1375 /* Setup DMA controller */ 1376 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, 1377 DMA_RX_MODE); 1378 1379 /* Enable burst mode chip Rx DMA */ 1380 register_bank(iobase, 1); 1381 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1382 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1383 1384 /* Enable interrupt */ 1385 register_bank(iobase, 0); 1386 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1387 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1388 1389 /* Enable receiver */ 1390 register_bank(iobase, 0); 1391 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, 1392 iobase + IRCC_LCR_B); 1393 1394 return 0; 1395} 1396 1397/* 1398 * Function smsc_ircc_dma_receive_complete(self) 1399 * 1400 * Finished with receiving frames 1401 * 1402 */ 1403static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) 1404{ 1405 struct sk_buff *skb; 1406 int len, msgcnt, lsr; 1407 int iobase = self->io.fir_base; 1408 1409 register_bank(iobase, 0); 1410 1411 IRDA_DEBUG(3, "%s\n", __func__); 1412#if 0 1413 /* Disable Rx */ 1414 register_bank(iobase, 0); 1415 outb(0x00, iobase + IRCC_LCR_B); 1416#endif 1417 register_bank(iobase, 0); 1418 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); 1419 lsr= inb(iobase + IRCC_LSR); 1420 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; 1421 1422 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__, 1423 get_dma_residue(self->io.dma)); 1424 1425 len = self->rx_buff.truesize - get_dma_residue(self->io.dma); 1426 1427 /* Look for errors */ 1428 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { 1429 self->netdev->stats.rx_errors++; 1430 if (lsr & IRCC_LSR_FRAME_ERROR) 1431 self->netdev->stats.rx_frame_errors++; 1432 if (lsr & IRCC_LSR_CRC_ERROR) 1433 self->netdev->stats.rx_crc_errors++; 1434 if (lsr & IRCC_LSR_SIZE_ERROR) 1435 self->netdev->stats.rx_length_errors++; 1436 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) 1437 self->netdev->stats.rx_length_errors++; 1438 return; 1439 } 1440 1441 /* Remove CRC */ 1442 len -= self->io.speed < 4000000 ? 2 : 4; 1443 1444 if (len < 2 || len > 2050) { 1445 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len); 1446 return; 1447 } 1448 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len); 1449 1450 skb = dev_alloc_skb(len + 1); 1451 if (!skb) { 1452 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", 1453 __func__); 1454 return; 1455 } 1456 /* Make sure IP header gets aligned */ 1457 skb_reserve(skb, 1); 1458 1459 memcpy(skb_put(skb, len), self->rx_buff.data, len); 1460 self->netdev->stats.rx_packets++; 1461 self->netdev->stats.rx_bytes += len; 1462 1463 skb->dev = self->netdev; 1464 skb_reset_mac_header(skb); 1465 skb->protocol = htons(ETH_P_IRDA); 1466 netif_rx(skb); 1467} 1468 1469/* 1470 * Function smsc_ircc_sir_receive (self) 1471 * 1472 * Receive one frame from the infrared port 1473 * 1474 */ 1475static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) 1476{ 1477 int boguscount = 0; 1478 int iobase; 1479 1480 IRDA_ASSERT(self != NULL, return;); 1481 1482 iobase = self->io.sir_base; 1483 1484 /* 1485 * Receive all characters in Rx FIFO, unwrap and unstuff them. 1486 * async_unwrap_char will deliver all found frames 1487 */ 1488 do { 1489 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff, 1490 inb(iobase + UART_RX)); 1491 1492 /* Make sure we don't stay here to long */ 1493 if (boguscount++ > 32) { 1494 IRDA_DEBUG(2, "%s(), breaking!\n", __func__); 1495 break; 1496 } 1497 } while (inb(iobase + UART_LSR) & UART_LSR_DR); 1498} 1499 1500 1501/* 1502 * Function smsc_ircc_interrupt (irq, dev_id, regs) 1503 * 1504 * An interrupt from the chip has arrived. Time to do some work 1505 * 1506 */ 1507static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id) 1508{ 1509 struct net_device *dev = dev_id; 1510 struct smsc_ircc_cb *self = netdev_priv(dev); 1511 int iobase, iir, lcra, lsr; 1512 irqreturn_t ret = IRQ_NONE; 1513 1514 /* Serialise the interrupt handler in various CPUs, stop Tx path */ 1515 spin_lock(&self->lock); 1516 1517 /* Check if we should use the SIR interrupt handler */ 1518 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1519 ret = smsc_ircc_interrupt_sir(dev); 1520 goto irq_ret_unlock; 1521 } 1522 1523 iobase = self->io.fir_base; 1524 1525 register_bank(iobase, 0); 1526 iir = inb(iobase + IRCC_IIR); 1527 if (iir == 0) 1528 goto irq_ret_unlock; 1529 ret = IRQ_HANDLED; 1530 1531 /* Disable interrupts */ 1532 outb(0, iobase + IRCC_IER); 1533 lcra = inb(iobase + IRCC_LCR_A); 1534 lsr = inb(iobase + IRCC_LSR); 1535 1536 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir); 1537 1538 if (iir & IRCC_IIR_EOM) { 1539 if (self->io.direction == IO_RECV) 1540 smsc_ircc_dma_receive_complete(self); 1541 else 1542 smsc_ircc_dma_xmit_complete(self); 1543 1544 smsc_ircc_dma_receive(self); 1545 } 1546 1547 if (iir & IRCC_IIR_ACTIVE_FRAME) { 1548 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/ 1549 } 1550 1551 /* Enable interrupts again */ 1552 1553 register_bank(iobase, 0); 1554 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1555 1556 irq_ret_unlock: 1557 spin_unlock(&self->lock); 1558 1559 return ret; 1560} 1561 1562/* 1563 * Function irport_interrupt_sir (irq, dev_id) 1564 * 1565 * Interrupt handler for SIR modes 1566 */ 1567static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) 1568{ 1569 struct smsc_ircc_cb *self = netdev_priv(dev); 1570 int boguscount = 0; 1571 int iobase; 1572 int iir, lsr; 1573 1574 /* Already locked coming here in smsc_ircc_interrupt() */ 1575 /*spin_lock(&self->lock);*/ 1576 1577 iobase = self->io.sir_base; 1578 1579 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1580 if (iir == 0) 1581 return IRQ_NONE; 1582 while (iir) { 1583 /* Clear interrupt */ 1584 lsr = inb(iobase + UART_LSR); 1585 1586 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", 1587 __func__, iir, lsr, iobase); 1588 1589 switch (iir) { 1590 case UART_IIR_RLSI: 1591 IRDA_DEBUG(2, "%s(), RLSI\n", __func__); 1592 break; 1593 case UART_IIR_RDI: 1594 /* Receive interrupt */ 1595 smsc_ircc_sir_receive(self); 1596 break; 1597 case UART_IIR_THRI: 1598 if (lsr & UART_LSR_THRE) 1599 /* Transmitter ready for data */ 1600 smsc_ircc_sir_write_wakeup(self); 1601 break; 1602 default: 1603 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", 1604 __func__, iir); 1605 break; 1606 } 1607 1608 /* Make sure we don't stay here to long */ 1609 if (boguscount++ > 100) 1610 break; 1611 1612 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1613 } 1614 /*spin_unlock(&self->lock);*/ 1615 return IRQ_HANDLED; 1616} 1617 1618 1619#if 0 /* unused */ 1620/* 1621 * Function ircc_is_receiving (self) 1622 * 1623 * Return TRUE is we are currently receiving a frame 1624 * 1625 */ 1626static int ircc_is_receiving(struct smsc_ircc_cb *self) 1627{ 1628 int status = FALSE; 1629 /* int iobase; */ 1630 1631 IRDA_DEBUG(1, "%s\n", __func__); 1632 1633 IRDA_ASSERT(self != NULL, return FALSE;); 1634 1635 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__, 1636 get_dma_residue(self->io.dma)); 1637 1638 status = (self->rx_buff.state != OUTSIDE_FRAME); 1639 1640 return status; 1641} 1642#endif /* unused */ 1643 1644static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) 1645{ 1646 int error; 1647 1648 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, 1649 self->netdev->name, self->netdev); 1650 if (error) 1651 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", 1652 __func__, self->io.irq, error); 1653 1654 return error; 1655} 1656 1657static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) 1658{ 1659 unsigned long flags; 1660 1661 spin_lock_irqsave(&self->lock, flags); 1662 1663 self->io.speed = 0; 1664 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 1665 1666 spin_unlock_irqrestore(&self->lock, flags); 1667} 1668 1669static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) 1670{ 1671 int iobase = self->io.fir_base; 1672 unsigned long flags; 1673 1674 spin_lock_irqsave(&self->lock, flags); 1675 1676 register_bank(iobase, 0); 1677 outb(0, iobase + IRCC_IER); 1678 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 1679 outb(0x00, iobase + IRCC_MASTER); 1680 1681 spin_unlock_irqrestore(&self->lock, flags); 1682} 1683 1684 1685/* 1686 * Function smsc_ircc_net_open (dev) 1687 * 1688 * Start the device 1689 * 1690 */ 1691static int smsc_ircc_net_open(struct net_device *dev) 1692{ 1693 struct smsc_ircc_cb *self; 1694 char hwname[16]; 1695 1696 IRDA_DEBUG(1, "%s\n", __func__); 1697 1698 IRDA_ASSERT(dev != NULL, return -1;); 1699 self = netdev_priv(dev); 1700 IRDA_ASSERT(self != NULL, return 0;); 1701 1702 if (self->io.suspended) { 1703 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__); 1704 return -EAGAIN; 1705 } 1706 1707 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, 1708 (void *) dev)) { 1709 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", 1710 __func__, self->io.irq); 1711 return -EAGAIN; 1712 } 1713 1714 smsc_ircc_start_interrupts(self); 1715 1716 /* Give self a hardware name */ 1717 /* It would be cool to offer the chip revision here - Jean II */ 1718 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); 1719 1720 /* 1721 * Open new IrLAP layer instance, now that everything should be 1722 * initialized properly 1723 */ 1724 self->irlap = irlap_open(dev, &self->qos, hwname); 1725 1726 /* 1727 * Always allocate the DMA channel after the IRQ, 1728 * and clean up on failure. 1729 */ 1730 if (request_dma(self->io.dma, dev->name)) { 1731 smsc_ircc_net_close(dev); 1732 1733 IRDA_WARNING("%s(), unable to allocate DMA=%d\n", 1734 __func__, self->io.dma); 1735 return -EAGAIN; 1736 } 1737 1738 netif_start_queue(dev); 1739 1740 return 0; 1741} 1742 1743/* 1744 * Function smsc_ircc_net_close (dev) 1745 * 1746 * Stop the device 1747 * 1748 */ 1749static int smsc_ircc_net_close(struct net_device *dev) 1750{ 1751 struct smsc_ircc_cb *self; 1752 1753 IRDA_DEBUG(1, "%s\n", __func__); 1754 1755 IRDA_ASSERT(dev != NULL, return -1;); 1756 self = netdev_priv(dev); 1757 IRDA_ASSERT(self != NULL, return 0;); 1758 1759 /* Stop device */ 1760 netif_stop_queue(dev); 1761 1762 /* Stop and remove instance of IrLAP */ 1763 if (self->irlap) 1764 irlap_close(self->irlap); 1765 self->irlap = NULL; 1766 1767 smsc_ircc_stop_interrupts(self); 1768 1769 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ 1770 if (!self->io.suspended) 1771 free_irq(self->io.irq, dev); 1772 1773 disable_dma(self->io.dma); 1774 free_dma(self->io.dma); 1775 1776 return 0; 1777} 1778 1779static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) 1780{ 1781 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1782 1783 if (!self->io.suspended) { 1784 IRDA_DEBUG(1, "%s, Suspending\n", driver_name); 1785 1786 rtnl_lock(); 1787 if (netif_running(self->netdev)) { 1788 netif_device_detach(self->netdev); 1789 smsc_ircc_stop_interrupts(self); 1790 free_irq(self->io.irq, self->netdev); 1791 disable_dma(self->io.dma); 1792 } 1793 self->io.suspended = 1; 1794 rtnl_unlock(); 1795 } 1796 1797 return 0; 1798} 1799 1800static int smsc_ircc_resume(struct platform_device *dev) 1801{ 1802 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1803 1804 if (self->io.suspended) { 1805 IRDA_DEBUG(1, "%s, Waking up\n", driver_name); 1806 1807 rtnl_lock(); 1808 smsc_ircc_init_chip(self); 1809 if (netif_running(self->netdev)) { 1810 if (smsc_ircc_request_irq(self)) { 1811 /* 1812 * Don't fail resume process, just kill this 1813 * network interface 1814 */ 1815 unregister_netdevice(self->netdev); 1816 } else { 1817 enable_dma(self->io.dma); 1818 smsc_ircc_start_interrupts(self); 1819 netif_device_attach(self->netdev); 1820 } 1821 } 1822 self->io.suspended = 0; 1823 rtnl_unlock(); 1824 } 1825 return 0; 1826} 1827 1828/* 1829 * Function smsc_ircc_close (self) 1830 * 1831 * Close driver instance 1832 * 1833 */ 1834static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) 1835{ 1836 IRDA_DEBUG(1, "%s\n", __func__); 1837 1838 IRDA_ASSERT(self != NULL, return -1;); 1839 1840 platform_device_unregister(self->pldev); 1841 1842 /* Remove netdevice */ 1843 unregister_netdev(self->netdev); 1844 1845 smsc_ircc_stop_interrupts(self); 1846 1847 /* Release the PORTS that this driver is using */ 1848 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, 1849 self->io.fir_base); 1850 1851 release_region(self->io.fir_base, self->io.fir_ext); 1852 1853 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__, 1854 self->io.sir_base); 1855 1856 release_region(self->io.sir_base, self->io.sir_ext); 1857 1858 if (self->tx_buff.head) 1859 dma_free_coherent(NULL, self->tx_buff.truesize, 1860 self->tx_buff.head, self->tx_buff_dma); 1861 1862 if (self->rx_buff.head) 1863 dma_free_coherent(NULL, self->rx_buff.truesize, 1864 self->rx_buff.head, self->rx_buff_dma); 1865 1866 free_netdev(self->netdev); 1867 1868 return 0; 1869} 1870 1871static void __exit smsc_ircc_cleanup(void) 1872{ 1873 int i; 1874 1875 IRDA_DEBUG(1, "%s\n", __func__); 1876 1877 for (i = 0; i < 2; i++) { 1878 if (dev_self[i]) 1879 smsc_ircc_close(dev_self[i]); 1880 } 1881 1882 if (pnp_driver_registered) 1883 pnp_unregister_driver(&smsc_ircc_pnp_driver); 1884 1885 platform_driver_unregister(&smsc_ircc_driver); 1886} 1887 1888/* 1889 * Start SIR operations 1890 * 1891 * This function *must* be called with spinlock held, because it may 1892 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II 1893 */ 1894static void smsc_ircc_sir_start(struct smsc_ircc_cb *self) 1895{ 1896 struct net_device *dev; 1897 int fir_base, sir_base; 1898 1899 IRDA_DEBUG(3, "%s\n", __func__); 1900 1901 IRDA_ASSERT(self != NULL, return;); 1902 dev = self->netdev; 1903 IRDA_ASSERT(dev != NULL, return;); 1904 1905 fir_base = self->io.fir_base; 1906 sir_base = self->io.sir_base; 1907 1908 /* Reset everything */ 1909 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); 1910 1911 #if SMSC_IRCC2_C_SIR_STOP 1912 /*smsc_ircc_sir_stop(self);*/ 1913 #endif 1914 1915 register_bank(fir_base, 1); 1916 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); 1917 1918 /* Initialize UART */ 1919 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ 1920 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); 1921 1922 /* Turn on interrups */ 1923 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); 1924 1925 IRDA_DEBUG(3, "%s() - exit\n", __func__); 1926 1927 outb(0x00, fir_base + IRCC_MASTER); 1928} 1929 1930#if SMSC_IRCC2_C_SIR_STOP 1931void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) 1932{ 1933 int iobase; 1934 1935 IRDA_DEBUG(3, "%s\n", __func__); 1936 iobase = self->io.sir_base; 1937 1938 /* Reset UART */ 1939 outb(0, iobase + UART_MCR); 1940 1941 /* Turn off interrupts */ 1942 outb(0, iobase + UART_IER); 1943} 1944#endif 1945 1946/* 1947 * Function smsc_sir_write_wakeup (self) 1948 * 1949 * Called by the SIR interrupt handler when there's room for more data. 1950 * If we have more packets to send, we send them here. 1951 * 1952 */ 1953static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) 1954{ 1955 int actual = 0; 1956 int iobase; 1957 int fcr; 1958 1959 IRDA_ASSERT(self != NULL, return;); 1960 1961 IRDA_DEBUG(4, "%s\n", __func__); 1962 1963 iobase = self->io.sir_base; 1964 1965 /* Finished with frame? */ 1966 if (self->tx_buff.len > 0) { 1967 /* Write data left in transmit buffer */ 1968 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, 1969 self->tx_buff.data, self->tx_buff.len); 1970 self->tx_buff.data += actual; 1971 self->tx_buff.len -= actual; 1972 } else { 1973 1974 /*if (self->tx_buff.len ==0) {*/ 1975 1976 /* 1977 * Now serial buffer is almost free & we can start 1978 * transmission of another packet. But first we must check 1979 * if we need to change the speed of the hardware 1980 */ 1981 if (self->new_speed) { 1982 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", 1983 __func__, self->new_speed); 1984 smsc_ircc_sir_wait_hw_transmitter_finish(self); 1985 smsc_ircc_change_speed(self, self->new_speed); 1986 self->new_speed = 0; 1987 } else { 1988 /* Tell network layer that we want more frames */ 1989 netif_wake_queue(self->netdev); 1990 } 1991 self->netdev->stats.tx_packets++; 1992 1993 if (self->io.speed <= 115200) { 1994 /* 1995 * Reset Rx FIFO to make sure that all reflected transmit data 1996 * is discarded. This is needed for half duplex operation 1997 */ 1998 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; 1999 fcr |= self->io.speed < 38400 ? 2000 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 2001 2002 outb(fcr, iobase + UART_FCR); 2003 2004 /* Turn on receive interrupts */ 2005 outb(UART_IER_RDI, iobase + UART_IER); 2006 } 2007 } 2008} 2009 2010/* 2011 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) 2012 * 2013 * Fill Tx FIFO with transmit data 2014 * 2015 */ 2016static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) 2017{ 2018 int actual = 0; 2019 2020 /* Tx FIFO should be empty! */ 2021 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { 2022 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__); 2023 return 0; 2024 } 2025 2026 /* Fill FIFO with current frame */ 2027 while (fifo_size-- > 0 && actual < len) { 2028 /* Transmit next byte */ 2029 outb(buf[actual], iobase + UART_TX); 2030 actual++; 2031 } 2032 return actual; 2033} 2034 2035/* 2036 * Function smsc_ircc_is_receiving (self) 2037 * 2038 * Returns true is we are currently receiving data 2039 * 2040 */ 2041static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) 2042{ 2043 return self->rx_buff.state != OUTSIDE_FRAME; 2044} 2045 2046 2047/* 2048 * Function smsc_ircc_probe_transceiver(self) 2049 * 2050 * Tries to find the used Transceiver 2051 * 2052 */ 2053static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) 2054{ 2055 unsigned int i; 2056 2057 IRDA_ASSERT(self != NULL, return;); 2058 2059 for (i = 0; smsc_transceivers[i].name != NULL; i++) 2060 if (smsc_transceivers[i].probe(self->io.fir_base)) { 2061 IRDA_MESSAGE(" %s transceiver found\n", 2062 smsc_transceivers[i].name); 2063 self->transceiver= i + 1; 2064 return; 2065 } 2066 2067 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", 2068 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); 2069 2070 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; 2071} 2072 2073 2074/* 2075 * Function smsc_ircc_set_transceiver_for_speed(self, speed) 2076 * 2077 * Set the transceiver according to the speed 2078 * 2079 */ 2080static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) 2081{ 2082 unsigned int trx; 2083 2084 trx = self->transceiver; 2085 if (trx > 0) 2086 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); 2087} 2088 2089/* 2090 * Function smsc_ircc_wait_hw_transmitter_finish () 2091 * 2092 * Wait for the real end of HW transmission 2093 * 2094 * The UART is a strict FIFO, and we get called only when we have finished 2095 * pushing data to the FIFO, so the maximum amount of time we must wait 2096 * is only for the FIFO to drain out. 2097 * 2098 * We use a simple calibrated loop. We may need to adjust the loop 2099 * delay (udelay) to balance I/O traffic and latency. And we also need to 2100 * adjust the maximum timeout. 2101 * It would probably be better to wait for the proper interrupt, 2102 * but it doesn't seem to be available. 2103 * 2104 * We can't use jiffies or kernel timers because : 2105 * 1) We are called from the interrupt handler, which disable softirqs, 2106 * so jiffies won't be increased 2107 * 2) Jiffies granularity is usually very coarse (10ms), and we don't 2108 * want to wait that long to detect stuck hardware. 2109 * Jean II 2110 */ 2111 2112static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) 2113{ 2114 int iobase = self->io.sir_base; 2115 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; 2116 2117 /* Calibrated busy loop */ 2118 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) 2119 udelay(1); 2120 2121 if (count < 0) 2122 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__); 2123} 2124 2125 2126/* PROBING 2127 * 2128 * REVISIT we can be told about the device by PNP, and should use that info 2129 * instead of probing hardware and creating a platform_device ... 2130 */ 2131 2132static int __init smsc_ircc_look_for_chips(void) 2133{ 2134 struct smsc_chip_address *address; 2135 char *type; 2136 unsigned int cfg_base, found; 2137 2138 found = 0; 2139 address = possible_addresses; 2140 2141 while (address->cfg_base) { 2142 cfg_base = address->cfg_base; 2143 2144 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/ 2145 2146 if (address->type & SMSCSIO_TYPE_FDC) { 2147 type = "FDC"; 2148 if (address->type & SMSCSIO_TYPE_FLAT) 2149 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) 2150 found++; 2151 2152 if (address->type & SMSCSIO_TYPE_PAGED) 2153 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) 2154 found++; 2155 } 2156 if (address->type & SMSCSIO_TYPE_LPC) { 2157 type = "LPC"; 2158 if (address->type & SMSCSIO_TYPE_FLAT) 2159 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) 2160 found++; 2161 2162 if (address->type & SMSCSIO_TYPE_PAGED) 2163 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) 2164 found++; 2165 } 2166 address++; 2167 } 2168 return found; 2169} 2170 2171/* 2172 * Function smsc_superio_flat (chip, base, type) 2173 * 2174 * Try to get configuration of a smc SuperIO chip with flat register model 2175 * 2176 */ 2177static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) 2178{ 2179 unsigned short firbase, sirbase; 2180 u8 mode, dma, irq; 2181 int ret = -ENODEV; 2182 2183 IRDA_DEBUG(1, "%s\n", __func__); 2184 2185 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) 2186 return ret; 2187 2188 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); 2189 mode = inb(cfgbase + 1); 2190 2191 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/ 2192 2193 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) 2194 IRDA_WARNING("%s(): IrDA not enabled\n", __func__); 2195 2196 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); 2197 sirbase = inb(cfgbase + 1) << 2; 2198 2199 /* FIR iobase */ 2200 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); 2201 firbase = inb(cfgbase + 1) << 3; 2202 2203 /* DMA */ 2204 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); 2205 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; 2206 2207 /* IRQ */ 2208 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); 2209 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2210 2211 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode); 2212 2213 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) 2214 ret = 0; 2215 2216 /* Exit configuration */ 2217 outb(SMSCSIO_CFGEXITKEY, cfgbase); 2218 2219 return ret; 2220} 2221 2222/* 2223 * Function smsc_superio_paged (chip, base, type) 2224 * 2225 * Try to get configuration of a smc SuperIO chip with paged register model 2226 * 2227 */ 2228static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) 2229{ 2230 unsigned short fir_io, sir_io; 2231 int ret = -ENODEV; 2232 2233 IRDA_DEBUG(1, "%s\n", __func__); 2234 2235 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) 2236 return ret; 2237 2238 /* Select logical device (UART2) */ 2239 outb(0x07, cfg_base); 2240 outb(0x05, cfg_base + 1); 2241 2242 /* SIR iobase */ 2243 outb(0x60, cfg_base); 2244 sir_io = inb(cfg_base + 1) << 8; 2245 outb(0x61, cfg_base); 2246 sir_io |= inb(cfg_base + 1); 2247 2248 /* Read FIR base */ 2249 outb(0x62, cfg_base); 2250 fir_io = inb(cfg_base + 1) << 8; 2251 outb(0x63, cfg_base); 2252 fir_io |= inb(cfg_base + 1); 2253 outb(0x2b, cfg_base); /* ??? */ 2254 2255 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) 2256 ret = 0; 2257 2258 /* Exit configuration */ 2259 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2260 2261 return ret; 2262} 2263 2264 2265static int __init smsc_access(unsigned short cfg_base, unsigned char reg) 2266{ 2267 IRDA_DEBUG(1, "%s\n", __func__); 2268 2269 outb(reg, cfg_base); 2270 return inb(cfg_base) != reg ? -1 : 0; 2271} 2272 2273static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) 2274{ 2275 u8 devid, xdevid, rev; 2276 2277 IRDA_DEBUG(1, "%s\n", __func__); 2278 2279 /* Leave configuration */ 2280 2281 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2282 2283 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ 2284 return NULL; 2285 2286 outb(reg, cfg_base); 2287 2288 xdevid = inb(cfg_base + 1); 2289 2290 /* Enter configuration */ 2291 2292 outb(SMSCSIO_CFGACCESSKEY, cfg_base); 2293 2294 #if 0 2295 if (smsc_access(cfg_base,0x55)) /* send second key and check */ 2296 return NULL; 2297 #endif 2298 2299 /* probe device ID */ 2300 2301 if (smsc_access(cfg_base, reg)) 2302 return NULL; 2303 2304 devid = inb(cfg_base + 1); 2305 2306 if (devid == 0 || devid == 0xff) /* typical values for unused port */ 2307 return NULL; 2308 2309 /* probe revision ID */ 2310 2311 if (smsc_access(cfg_base, reg + 1)) 2312 return NULL; 2313 2314 rev = inb(cfg_base + 1); 2315 2316 if (rev >= 128) /* i think this will make no sense */ 2317 return NULL; 2318 2319 if (devid == xdevid) /* protection against false positives */ 2320 return NULL; 2321 2322 /* Check for expected device ID; are there others? */ 2323 2324 while (chip->devid != devid) { 2325 2326 chip++; 2327 2328 if (chip->name == NULL) 2329 return NULL; 2330 } 2331 2332 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", 2333 devid, rev, cfg_base, type, chip->name); 2334 2335 if (chip->rev > rev) { 2336 IRDA_MESSAGE("Revision higher than expected\n"); 2337 return NULL; 2338 } 2339 2340 if (chip->flags & NoIRDA) 2341 IRDA_MESSAGE("chipset does not support IRDA\n"); 2342 2343 return chip; 2344} 2345 2346static int __init smsc_superio_fdc(unsigned short cfg_base) 2347{ 2348 int ret = -1; 2349 2350 if (!request_region(cfg_base, 2, driver_name)) { 2351 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2352 __func__, cfg_base); 2353 } else { 2354 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || 2355 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) 2356 ret = 0; 2357 2358 release_region(cfg_base, 2); 2359 } 2360 2361 return ret; 2362} 2363 2364static int __init smsc_superio_lpc(unsigned short cfg_base) 2365{ 2366 int ret = -1; 2367 2368 if (!request_region(cfg_base, 2, driver_name)) { 2369 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2370 __func__, cfg_base); 2371 } else { 2372 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || 2373 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) 2374 ret = 0; 2375 2376 release_region(cfg_base, 2); 2377 } 2378 return ret; 2379} 2380 2381/* 2382 * Look for some specific subsystem setups that need 2383 * pre-configuration not properly done by the BIOS (especially laptops) 2384 * This code is based in part on smcinit.c, tosh1800-smcinit.c 2385 * and tosh2450-smcinit.c. The table lists the device entries 2386 * for ISA bridges with an LPC (Low Pin Count) controller which 2387 * handles the communication with the SMSC device. After the LPC 2388 * controller is initialized through PCI, the SMSC device is initialized 2389 * through a dedicated port in the ISA port-mapped I/O area, this latter 2390 * area is used to configure the SMSC device with default 2391 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have 2392 * used different sets of parameters and different control port 2393 * addresses making a subsystem device table necessary. 2394 */ 2395#ifdef CONFIG_PCI 2396static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { 2397 /* 2398 * Subsystems needing entries: 2399 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family 2400 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family 2401 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family 2402 */ 2403 { 2404 /* Guessed entry */ 2405 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ 2406 .device = 0x24cc, 2407 .subvendor = 0x103c, 2408 .subdevice = 0x08bc, 2409 .sir_io = 0x02f8, 2410 .fir_io = 0x0130, 2411 .fir_irq = 0x05, 2412 .fir_dma = 0x03, 2413 .cfg_base = 0x004e, 2414 .preconfigure = preconfigure_through_82801, 2415 .name = "HP nx5000 family", 2416 }, 2417 { 2418 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ 2419 .device = 0x24cc, 2420 .subvendor = 0x103c, 2421 .subdevice = 0x088c, 2422 /* Quite certain these are the same for nc8000 as for nc6000 */ 2423 .sir_io = 0x02f8, 2424 .fir_io = 0x0130, 2425 .fir_irq = 0x05, 2426 .fir_dma = 0x03, 2427 .cfg_base = 0x004e, 2428 .preconfigure = preconfigure_through_82801, 2429 .name = "HP nc8000 family", 2430 }, 2431 { 2432 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ 2433 .device = 0x24cc, 2434 .subvendor = 0x103c, 2435 .subdevice = 0x0890, 2436 .sir_io = 0x02f8, 2437 .fir_io = 0x0130, 2438 .fir_irq = 0x05, 2439 .fir_dma = 0x03, 2440 .cfg_base = 0x004e, 2441 .preconfigure = preconfigure_through_82801, 2442 .name = "HP nc6000 family", 2443 }, 2444 { 2445 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */ 2446 .device = 0x24cc, 2447 .subvendor = 0x0e11, 2448 .subdevice = 0x0860, 2449 /* I assume these are the same for x1000 as for the others */ 2450 .sir_io = 0x02e8, 2451 .fir_io = 0x02f8, 2452 .fir_irq = 0x07, 2453 .fir_dma = 0x03, 2454 .cfg_base = 0x002e, 2455 .preconfigure = preconfigure_through_82801, 2456 .name = "Compaq x1000 family", 2457 }, 2458 { 2459 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ 2460 .vendor = PCI_VENDOR_ID_INTEL, 2461 .device = 0x24c0, 2462 .subvendor = 0x1179, 2463 .subdevice = 0xffff, /* 0xffff is "any" */ 2464 .sir_io = 0x03f8, 2465 .fir_io = 0x0130, 2466 .fir_irq = 0x07, 2467 .fir_dma = 0x01, 2468 .cfg_base = 0x002e, 2469 .preconfigure = preconfigure_through_82801, 2470 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", 2471 }, 2472 { 2473 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */ 2474 .device = 0x248c, 2475 .subvendor = 0x1179, 2476 .subdevice = 0xffff, /* 0xffff is "any" */ 2477 .sir_io = 0x03f8, 2478 .fir_io = 0x0130, 2479 .fir_irq = 0x03, 2480 .fir_dma = 0x03, 2481 .cfg_base = 0x002e, 2482 .preconfigure = preconfigure_through_82801, 2483 .name = "Toshiba laptop with Intel 82801CAM ISA bridge", 2484 }, 2485 { 2486 /* 82801DBM (ICH4-M) LPC Interface Bridge */ 2487 .vendor = PCI_VENDOR_ID_INTEL, 2488 .device = 0x24cc, 2489 .subvendor = 0x1179, 2490 .subdevice = 0xffff, /* 0xffff is "any" */ 2491 .sir_io = 0x03f8, 2492 .fir_io = 0x0130, 2493 .fir_irq = 0x03, 2494 .fir_dma = 0x03, 2495 .cfg_base = 0x002e, 2496 .preconfigure = preconfigure_through_82801, 2497 .name = "Toshiba laptop with Intel 8281DBM LPC bridge", 2498 }, 2499 { 2500 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ 2501 .vendor = PCI_VENDOR_ID_AL, 2502 .device = 0x1533, 2503 .subvendor = 0x1179, 2504 .subdevice = 0xffff, /* 0xffff is "any" */ 2505 .sir_io = 0x02e8, 2506 .fir_io = 0x02f8, 2507 .fir_irq = 0x07, 2508 .fir_dma = 0x03, 2509 .cfg_base = 0x002e, 2510 .preconfigure = preconfigure_through_ali, 2511 .name = "Toshiba laptop with ALi ISA bridge", 2512 }, 2513 { } // Terminator 2514}; 2515 2516 2517/* 2518 * This sets up the basic SMSC parameters 2519 * (FIR port, SIR port, FIR DMA, FIR IRQ) 2520 * through the chip configuration port. 2521 */ 2522static int __init preconfigure_smsc_chip(struct 2523 smsc_ircc_subsystem_configuration 2524 *conf) 2525{ 2526 unsigned short iobase = conf->cfg_base; 2527 unsigned char tmpbyte; 2528 2529 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state 2530 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID 2531 tmpbyte = inb(iobase +1); // Read device ID 2532 IRDA_DEBUG(0, 2533 "Detected Chip id: 0x%02x, setting up registers...\n", 2534 tmpbyte); 2535 2536 /* Disable UART1 and set up SIR I/O port */ 2537 outb(0x24, iobase); // select CR24 - UART1 base addr 2538 outb(0x00, iobase + 1); // disable UART1 2539 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr 2540 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 2541 tmpbyte = inb(iobase + 1); 2542 if (tmpbyte != (conf->sir_io >> 2) ) { 2543 IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); 2544 IRDA_WARNING("Try to supply ircc_cfg argument.\n"); 2545 return -ENXIO; 2546 } 2547 2548 /* Set up FIR IRQ channel for UART2 */ 2549 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select 2550 tmpbyte = inb(iobase + 1); 2551 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion 2552 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); 2553 outb(tmpbyte, iobase + 1); 2554 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2555 if (tmpbyte != conf->fir_irq) { 2556 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); 2557 return -ENXIO; 2558 } 2559 2560 /* Set up FIR I/O port */ 2561 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr 2562 outb((conf->fir_io >> 3), iobase + 1); 2563 tmpbyte = inb(iobase + 1); 2564 if (tmpbyte != (conf->fir_io >> 3) ) { 2565 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); 2566 return -ENXIO; 2567 } 2568 2569 /* Set up FIR DMA channel */ 2570 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select 2571 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA 2572 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; 2573 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { 2574 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); 2575 return -ENXIO; 2576 } 2577 2578 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode 2579 tmpbyte = inb(iobase + 1); 2580 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | 2581 SMSCSIOFLAT_UART2MODE_VAL_IRDA; 2582 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed 2583 2584 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel 2585 tmpbyte = inb(iobase + 1); 2586 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down 2587 2588 /* This one was not part of tosh1800 */ 2589 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux 2590 tmpbyte = inb(iobase + 1); 2591 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port 2592 2593 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power 2594 tmpbyte = inb(iobase + 1); 2595 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down 2596 2597 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle 2598 tmpbyte = inb(iobase + 1); 2599 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done 2600 2601 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration 2602 2603 return 0; 2604} 2605 2606/* 82801CAM generic registers */ 2607#define VID 0x00 2608#define DID 0x02 2609#define PIRQ_A_D_ROUT 0x60 2610#define SIRQ_CNTL 0x64 2611#define PIRQ_E_H_ROUT 0x68 2612#define PCI_DMA_C 0x90 2613/* LPC-specific registers */ 2614#define COM_DEC 0xe0 2615#define GEN1_DEC 0xe4 2616#define LPC_EN 0xe6 2617#define GEN2_DEC 0xec 2618/* 2619 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge 2620 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. 2621 * They all work the same way! 2622 */ 2623static int __init preconfigure_through_82801(struct pci_dev *dev, 2624 struct 2625 smsc_ircc_subsystem_configuration 2626 *conf) 2627{ 2628 unsigned short tmpword; 2629 unsigned char tmpbyte; 2630 2631 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); 2632 /* 2633 * Select the range for the COMA COM port (SIR) 2634 * Register COM_DEC: 2635 * Bit 7: reserved 2636 * Bit 6-4, COMB decode range 2637 * Bit 3: reserved 2638 * Bit 2-0, COMA decode range 2639 * 2640 * Decode ranges: 2641 * 000 = 0x3f8-0x3ff (COM1) 2642 * 001 = 0x2f8-0x2ff (COM2) 2643 * 010 = 0x220-0x227 2644 * 011 = 0x228-0x22f 2645 * 100 = 0x238-0x23f 2646 * 101 = 0x2e8-0x2ef (COM4) 2647 * 110 = 0x338-0x33f 2648 * 111 = 0x3e8-0x3ef (COM3) 2649 */ 2650 pci_read_config_byte(dev, COM_DEC, &tmpbyte); 2651 tmpbyte &= 0xf8; /* mask COMA bits */ 2652 switch(conf->sir_io) { 2653 case 0x3f8: 2654 tmpbyte |= 0x00; 2655 break; 2656 case 0x2f8: 2657 tmpbyte |= 0x01; 2658 break; 2659 case 0x220: 2660 tmpbyte |= 0x02; 2661 break; 2662 case 0x228: 2663 tmpbyte |= 0x03; 2664 break; 2665 case 0x238: 2666 tmpbyte |= 0x04; 2667 break; 2668 case 0x2e8: 2669 tmpbyte |= 0x05; 2670 break; 2671 case 0x338: 2672 tmpbyte |= 0x06; 2673 break; 2674 case 0x3e8: 2675 tmpbyte |= 0x07; 2676 break; 2677 default: 2678 tmpbyte |= 0x01; /* COM2 default */ 2679 } 2680 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); 2681 pci_write_config_byte(dev, COM_DEC, tmpbyte); 2682 2683 /* Enable Low Pin Count interface */ 2684 pci_read_config_word(dev, LPC_EN, &tmpword); 2685 /* These seem to be set up at all times, 2686 * just make sure it is properly set. 2687 */ 2688 switch(conf->cfg_base) { 2689 case 0x04e: 2690 tmpword |= 0x2000; 2691 break; 2692 case 0x02e: 2693 tmpword |= 0x1000; 2694 break; 2695 case 0x062: 2696 tmpword |= 0x0800; 2697 break; 2698 case 0x060: 2699 tmpword |= 0x0400; 2700 break; 2701 default: 2702 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", 2703 conf->cfg_base); 2704 break; 2705 } 2706 tmpword &= 0xfffd; /* disable LPC COMB */ 2707 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ 2708 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); 2709 pci_write_config_word(dev, LPC_EN, tmpword); 2710 2711 /* 2712 * Configure LPC DMA channel 2713 * PCI_DMA_C bits: 2714 * Bit 15-14: DMA channel 7 select 2715 * Bit 13-12: DMA channel 6 select 2716 * Bit 11-10: DMA channel 5 select 2717 * Bit 9-8: Reserved 2718 * Bit 7-6: DMA channel 3 select 2719 * Bit 5-4: DMA channel 2 select 2720 * Bit 3-2: DMA channel 1 select 2721 * Bit 1-0: DMA channel 0 select 2722 * 00 = Reserved value 2723 * 01 = PC/PCI DMA 2724 * 10 = Reserved value 2725 * 11 = LPC I/F DMA 2726 */ 2727 pci_read_config_word(dev, PCI_DMA_C, &tmpword); 2728 switch(conf->fir_dma) { 2729 case 0x07: 2730 tmpword |= 0xc000; 2731 break; 2732 case 0x06: 2733 tmpword |= 0x3000; 2734 break; 2735 case 0x05: 2736 tmpword |= 0x0c00; 2737 break; 2738 case 0x03: 2739 tmpword |= 0x00c0; 2740 break; 2741 case 0x02: 2742 tmpword |= 0x0030; 2743 break; 2744 case 0x01: 2745 tmpword |= 0x000c; 2746 break; 2747 case 0x00: 2748 tmpword |= 0x0003; 2749 break; 2750 default: 2751 break; /* do not change settings */ 2752 } 2753 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); 2754 pci_write_config_word(dev, PCI_DMA_C, tmpword); 2755 2756 /* 2757 * GEN2_DEC bits: 2758 * Bit 15-4: Generic I/O range 2759 * Bit 3-1: reserved (read as 0) 2760 * Bit 0: enable GEN2 range on LPC I/F 2761 */ 2762 tmpword = conf->fir_io & 0xfff8; 2763 tmpword |= 0x0001; 2764 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); 2765 pci_write_config_word(dev, GEN2_DEC, tmpword); 2766 2767 /* Pre-configure chip */ 2768 return preconfigure_smsc_chip(conf); 2769} 2770 2771/* 2772 * Pre-configure a certain port on the ALi 1533 bridge. 2773 * This is based on reverse-engineering since ALi does not 2774 * provide any data sheet for the 1533 chip. 2775 */ 2776static void __init preconfigure_ali_port(struct pci_dev *dev, 2777 unsigned short port) 2778{ 2779 unsigned char reg; 2780 /* These bits obviously control the different ports */ 2781 unsigned char mask; 2782 unsigned char tmpbyte; 2783 2784 switch(port) { 2785 case 0x0130: 2786 case 0x0178: 2787 reg = 0xb0; 2788 mask = 0x80; 2789 break; 2790 case 0x03f8: 2791 reg = 0xb4; 2792 mask = 0x80; 2793 break; 2794 case 0x02f8: 2795 reg = 0xb4; 2796 mask = 0x30; 2797 break; 2798 case 0x02e8: 2799 reg = 0xb4; 2800 mask = 0x08; 2801 break; 2802 default: 2803 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); 2804 return; 2805 } 2806 2807 pci_read_config_byte(dev, reg, &tmpbyte); 2808 /* Turn on the right bits */ 2809 tmpbyte |= mask; 2810 pci_write_config_byte(dev, reg, tmpbyte); 2811 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); 2812} 2813 2814static int __init preconfigure_through_ali(struct pci_dev *dev, 2815 struct 2816 smsc_ircc_subsystem_configuration 2817 *conf) 2818{ 2819 /* Configure the two ports on the ALi 1533 */ 2820 preconfigure_ali_port(dev, conf->sir_io); 2821 preconfigure_ali_port(dev, conf->fir_io); 2822 2823 /* Pre-configure chip */ 2824 return preconfigure_smsc_chip(conf); 2825} 2826 2827static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 2828 unsigned short ircc_fir, 2829 unsigned short ircc_sir, 2830 unsigned char ircc_dma, 2831 unsigned char ircc_irq) 2832{ 2833 struct pci_dev *dev = NULL; 2834 unsigned short ss_vendor = 0x0000; 2835 unsigned short ss_device = 0x0000; 2836 int ret = 0; 2837 2838 for_each_pci_dev(dev) { 2839 struct smsc_ircc_subsystem_configuration *conf; 2840 2841 /* 2842 * Cache the subsystem vendor/device: 2843 * some manufacturers fail to set this for all components, 2844 * so we save it in case there is just 0x0000 0x0000 on the 2845 * device we want to check. 2846 */ 2847 if (dev->subsystem_vendor != 0x0000U) { 2848 ss_vendor = dev->subsystem_vendor; 2849 ss_device = dev->subsystem_device; 2850 } 2851 conf = subsystem_configurations; 2852 for( ; conf->subvendor; conf++) { 2853 if(conf->vendor == dev->vendor && 2854 conf->device == dev->device && 2855 conf->subvendor == ss_vendor && 2856 /* Sometimes these are cached values */ 2857 (conf->subdevice == ss_device || 2858 conf->subdevice == 0xffff)) { 2859 struct smsc_ircc_subsystem_configuration 2860 tmpconf; 2861 2862 memcpy(&tmpconf, conf, 2863 sizeof(struct smsc_ircc_subsystem_configuration)); 2864 2865 /* 2866 * Override the default values with anything 2867 * passed in as parameter 2868 */ 2869 if (ircc_cfg != 0) 2870 tmpconf.cfg_base = ircc_cfg; 2871 if (ircc_fir != 0) 2872 tmpconf.fir_io = ircc_fir; 2873 if (ircc_sir != 0) 2874 tmpconf.sir_io = ircc_sir; 2875 if (ircc_dma != DMA_INVAL) 2876 tmpconf.fir_dma = ircc_dma; 2877 if (ircc_irq != IRQ_INVAL) 2878 tmpconf.fir_irq = ircc_irq; 2879 2880 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); 2881 if (conf->preconfigure) 2882 ret = conf->preconfigure(dev, &tmpconf); 2883 else 2884 ret = -ENODEV; 2885 } 2886 } 2887 } 2888 2889 return ret; 2890} 2891#endif // CONFIG_PCI 2892 2893/************************************************ 2894 * 2895 * Transceivers specific functions 2896 * 2897 ************************************************/ 2898 2899 2900/* 2901 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) 2902 * 2903 * Program transceiver through smsc-ircc ATC circuitry 2904 * 2905 */ 2906 2907static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) 2908{ 2909 unsigned long jiffies_now, jiffies_timeout; 2910 u8 val; 2911 2912 jiffies_now = jiffies; 2913 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; 2914 2915 /* ATC */ 2916 register_bank(fir_base, 4); 2917 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, 2918 fir_base + IRCC_ATC); 2919 2920 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && 2921 !time_after(jiffies, jiffies_timeout)) 2922 /* empty */; 2923 2924 if (val) 2925 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__, 2926 inb(fir_base + IRCC_ATC)); 2927} 2928 2929/* 2930 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) 2931 * 2932 * Probe transceiver smsc-ircc ATC circuitry 2933 * 2934 */ 2935 2936static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) 2937{ 2938 return 0; 2939} 2940 2941/* 2942 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) 2943 * 2944 * Set transceiver 2945 * 2946 */ 2947 2948static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) 2949{ 2950 u8 fast_mode; 2951 2952 switch (speed) { 2953 default: 2954 case 576000 : 2955 fast_mode = 0; 2956 break; 2957 case 1152000 : 2958 case 4000000 : 2959 fast_mode = IRCC_LCR_A_FAST; 2960 break; 2961 } 2962 register_bank(fir_base, 0); 2963 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2964} 2965 2966/* 2967 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) 2968 * 2969 * Probe transceiver 2970 * 2971 */ 2972 2973static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) 2974{ 2975 return 0; 2976} 2977 2978/* 2979 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) 2980 * 2981 * Set transceiver 2982 * 2983 */ 2984 2985static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) 2986{ 2987 u8 fast_mode; 2988 2989 switch (speed) { 2990 default: 2991 case 576000 : 2992 fast_mode = 0; 2993 break; 2994 case 1152000 : 2995 case 4000000 : 2996 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; 2997 break; 2998 2999 } 3000 /* This causes an interrupt */ 3001 register_bank(fir_base, 0); 3002 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 3003} 3004 3005/* 3006 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) 3007 * 3008 * Probe transceiver 3009 * 3010 */ 3011 3012static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) 3013{ 3014 return 0; 3015} 3016 3017 3018module_init(smsc_ircc_init); 3019module_exit(smsc_ircc_cleanup); 3020